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Abstract – This paper describes complete design and Digital controller design approaches are briefly reviewed
implementation of a digital controller for a high-frequency in Section III from the standpoint of the target converter
switching power supply. Guidelines for the minimum characteristics and operating modes. A digital controller
required resolution of the analog-to-digital converter, the design example and implementation details are described
pulse-width modulator, and the fixed-point computational in Section IV. Experimental results obtained from the
unit are derived. A design example based on a buck converter
1MHz switching converter with the digital controller are
operating at the switching frequency of 1MHz is presented.
The controller design is based on direct digital design
presented in Section V.
approach and standard root-locus techniques. Experimental
results are shown to validate the design approach and the II. RESOLUTION OF ANALOG-TO-DIGITAL
allocation of resources (resolution) in the implementation. CONVERTER AND DIGITAL PULSE WIDTH
MODULATOR
I. INTRODUCTION
The system in Fig.1 has an analog-to-digital (A/D)
It can be expected that digital controllers will be converter to sample the output voltage, a computational
increasingly used even in low-to-medium power, high- unit to determine the value of the switch duty ratio, and a
frequency switching power supplies where conventional digital pulse-width modulator (DPWM) that outputs a
analog controllers are currently preferred because of cost pulsating waveform that controls the switch(es) in the
and performance reasons [1,2]. converter at the computed duty ratio. The DPWM serves as
This paper addresses practical design and a D/A converter in the control loop. It is of interest to
implementation of a digital controller for a power supply examine the required resolution of A/D and DPWM
that operates at the switching frequency of 1MHz. blocks.
Attention is given to the digital implementation with
limited resources in terms of resolution of A/D and D/A A. Resolution of the A/D converter
(PWM) blocks and the time available to perform the
required computations. To satisfy specifications for the output voltage
Typical system under consideration is shown in Fig.1. regulation, resolution of the A/D converter has to enable
error lower than the allowed variation of the output voltage
∆V0:
+ Load
Switching ∆Vo Vmax V
Vin Vo ⋅ H ≥ n a / d , H = ref
converter Vo 2 a / d ⋅ Vo Vo
- (1)
where:
duty ratio - D Vref - is the reference voltage
Digital Pulse Width Vmax a/d - is the full-range voltage of the analog-to-digital
Modulator converter, assuming unipolar conversion in the range from
H
0 to Vmax a/d
npwm na/d - is the resolution, i.e. the number of output bits of the
A/D converter
na/d H - is the output voltage sensor gain
computational unit
A/D
Rearranging (1) gives the required A/D resolution:
Fig.1. Digital control system for a switching converter
V max a / d Vo
n a / d = int log 2 ⋅ (2)
The required resolution of A/D and PWM units is
V ref ∆Vo
addressed in Section II.
Vref[n] -
D(Z) e-sTpwm Kpwm Gvd(s)
transformation of integral and derivative properties (such
as Pole-Zero Matching or Euler) give more accurate
discrete-time equivalents of the continuous-time model. c[n]
e-sTa/d Ka/d
These methods also give a better transformation of
controller properties if a digital redesign method is applied
ANALOG-TO-DIGITAL
to a PID controller. CONVERTER
Fig.4. Block diagram of the digital control system
The closed-loop reference-to-output discrete-time Using this method, the pole of H(s) caused by low-pass
transfer function C(z) of this system is: filter was mapped to 0.669, zero at s= ∞ was mapped to
z=-1 while the delay was represented according to the rule
C ( z) =
{
D( z ) ⋅ Z K pwm ( s ) ⋅ Gvd ( s ) } 4. Poles of the converter and the gain are not constant
{
1 + D( z ) ⋅ Z K pwm ( s ) ⋅ Gvd ( s ) ⋅ K a / d ( s ) } (7)
values and their position in the z-plane depends on the
operating point. For the two extreme operating points
where Gvd(s) is the control-to-output transfer function of (maximum input voltage/minimum load, and minimum
the buck converter operating in CCM: input voltage/maximum load), the plant transfer function is
given by (12) and (13), respectively:
G do
Gvd ( s ) = (8) 11.76e −3
1+
s
+
s2 H ( s) = ⋅ e − sTs (12)
Qω 0 ω 0 2 s s s 2
1 + 1+
3
+
358e 7.76e 6
150.5e9
For the selected converter components and the range of
operating points, it was found that: Gdo varies from 4V to 7.846e −3
6V, the corner frequency (f0) is 132.7kHz, while the load H ( s) = ⋅ e − sTs (13)
s s s 2
variation causes the Q factor to vary from 2 to 20. 1 + 1+
3
+
358e 7.76e
6
150.5e9
The transfer function of the DPWM is:
1
K pwm ( s) = K pwm ⋅ e − sTpwms , K pwm = (9) For the maximum input voltage and the minimum output
n pwm
2 −1 load current, the discrete-time equivalent is:
In this case, Kpwm is 1/255 and Tpwm is the delay between
the time the DPWM input is updated and the time the 1.141 ⋅ 10−3 ⋅ (z + 1)
H (z ) =
switch duty ratio changes. (
z ⋅ (z − 0.669) z 2 − 1.331z + 0.9793 ) (14)
The transfer function of the A/D is:
When the load is the heaviest and the input voltage has the
K a / d − sTa / d 1− 2 − na / d minimum value, the discrete-time equivalent becomes:
K a / d ( s) = e , Ka / d = (10)
s Vmax a / d
1+
0.761 ⋅ 10−3 ⋅ (z + 1)
ω lp H (z ) =
(
z ⋅ ( z − 0.669) z 2 − 1.22 z + 0.8119 ) (15)
where Ta/d is the delay caused by the conversion time, and
the gain of the A/D converter (Ka/d) is 0.498. The pole at To achieve a controller suitable for implementation, it
fLP =57kHz in the converter characteristic is caused by a was decided to limit the control law to the second order
low-pass filter which is included on the ADMC-401 board. equation. Controller coefficients are determined based on
The discrete-time transfer function H(z) of the analog the poles-zeros cancellation approach: the controller zeroes
plant is: are selected to (approximately) cancel the poles of the
discrete transfer function H(z). The coefficients obtained
{
H (z ) = Z K pwm ( s ) ⋅ Gvd ( s ) ⋅ K a / d ( s ) } (11) for the pole-zero cancellation at the two extreme operating
points are different. As a compromise, the final
In this case, the analog plant consists of the switching coefficients of the digital controller are set between the
converter model, the pulse width modulator, and the values that correspond to the two extreme cases. Finally,
analog-to-digital converter. The pole-zero matched the gain of the controller is found using the root locus
transformation method was applied to obtain H(z). method (with the help of the MATLAB rltool [9]). The
The method is simple to apply and the discrete-time objective was to place the closed-loop system poles inside
model has been shown to reproduce the plant transient the cross section of constant-damping and decrement factor
responses with good accuracy. The second criterion for the areas inside the z-plane, for all operating points [10]. The
selection of this method is its relatively low sensitivity to decrement factor area determines the minimum response
coefficient variations. For the plant in (11), the pole-zero speed, while the constant damping area limits the
matched transformation method is applied as follows [3]: maximum overshoot in the step transient response. The
maximum overshoot was set to 20%, while the minimum
1. If the continuous time plant H(s) has a continuous response speed was set to 50µs.
plant pole at s=-ξp+jωP, then the discrete equivalent The obtained discrete-time control law is given by:
H(z) has a pole at zP=e ξ ω , where Ts is the
(- p+j p)Ts
Limited resolution of the fixed-point computational unit d[n] = d[n-1] + B[n] The new d[n] value
does not allow exact implementation of the control law. formed and available
The closest approximation of the designed controller is
given by:
d[n-1] d[n]
d [n] = d [n − 1] + 49.2(e[n] − 1.3e[n − 1] + 0.81e[n − 2]) (17)
e[n-2] e[n-1]