basics of verilog language

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always- procedural assignment- used to model both sequential and combo model. It
always monitors the signals in its sensitiivty list and runs the commands in its
module whenever the signal changes.
no driver is required, signals inside are to be reg type and can use blocking and
non blocking depending upon the logic.

and - 2 input AND gate primitive, with a instanve name

assign- keyword for continous assignment, needs a driver and has to be a net on
LHS, can have reg or net on RHS, i,e multiple FAN-OUT and they are handled by
resolution table

attritbute - ??

begin - used to start sequrntial flow of commands along with end

buf - primitive gate as a delay or buffer - (f=a)

bufif0 - primitive gate assigns a value 'a' to 'f' if a =0 else 1'bz;

bufif1 - primitive gate assigns a value 'a' to 'f' if a =1 else 1'bz;

case - used to model case statements end with endcase. full case (all combination
with default) or partial case (no default or not all combinations)
parallel case --> if there is only and only one combo possible and it is not
possible to find another combination.
overlapping or non-parallel case --> if in parallel case another combo is possible

casex - treats 0,1,x as dont cares

case z - treats 0,1,x,z as dont cares

cmos - used to model swithces

deassign - procedureal continous assignment - used in case of reg to assign a value

for certain period of time.

default - used in case when none of the combos match

defparam - used to overwrite parameters, parameter themselves are local to module

they are defined in

disable - used to disable a named block and exit it

edge - used to detect edge of a signal like clock

else - used in conjunction with if-else as a loop

end - used to specify the end of a procedural block

endattribute - ??

endcase - used to specify the end of case block

endfunction - used to end the function - function is ued to create a recurring

logic like conversion and calculations
endmodule - used to sepcifiy the end of a module

endprimitive - used to specify the end of a UDP

endspecify - used to specify the end of specific module - used to declare pin-pin
delays or from input to output.

endtable - used in creation of a UDP starts with table and ends with endtable, like
when writing a truth table to create our own UDP

endtask - end the task (subroutines with/withput enhaving the simulation time)

event - used to trigger a named event, then this event is defined in an another
module named with it. (--> is used to trigger and event)
like always @ (posedge clk)

out-->trigger

module trigger;
asdas

endmodule

for - loop iterates a fixed number of time

force - used to force signals to a particulr value used in interactive mode.

forever- it is same as while (1) the loop runs forever, untill stopped from
outside.

fork - sued to model concurrent statements. everything inside it will run with
respect to the current simulation time. unlike
initial block where it sinulation advances in a sequential manner.

module ex;

reg a,b,c;

always @ (s)

fork
#5 a = 1;
#3 b = 0;

join

endmodule
this will result in 3 time units b= 0 and then 5 time units a=1; if it has been
begin-end then the simulation would have been
5 time units a=1 and then 8 time units b = 0; in begin-end the current simulation
time is updated and in fork it is not

function - used to model recurring logic like conversions and calculation. it does
not advance the simulation time.
it cannot call another task but a fucntion. it can take only inputs in its
defination. it returns a single value as output
this value is passed to the respective port or reg. it cannot cintain any delay,
timing.
highz0 - this is the least capactive strength
highz1- this is the least capactive strength

if - used to model conditional logic

ifnone - it is used in specify block to declare the a condition when all other
possible path delays conditions are not met,
it is a default delay value in such a case

initial - procedural assignment used to run the statemtns only once, it runs only
once and once in the entire simulation
used in testbench to initialze the signals. signals in verilog are updated first.

inout- keyword for bi-dir ports (they are always net type whether internal or
external connection).

input - keyword for input port (always a reg type for external connection and wire
type in internal connection)

integer - by default 32 bit used in loops for counting

join - fork-join used to run commands in parallel fashion with respect to a fixed
simulation time

medium - strength level for the driver, medium capacitance like in case of tri

module - defination start of a module or a h/w block inside it the h/w behaviour is
defined

large - strength of a capcacitve driver

macromoudle - same as module used in SV

nand - nand gate primitive 2 input

negedge - transtion from 1->0 or from x,z->0

nmos - nmos switch

nor - 2 input nor gate primitive

not - 1 input not gate primitive

notif0 - conditional assignment where 'a' is assigned to 'f' if !a is 0 (!a?f:1'bz)

notif1 - conditional assignment where 'a' is assigned to 'f' if !a is 1 (!a?f:1'bz)

or - 2 input or gate primitive

output - keyword to declare port as output - default wire can be reg also.
internally - wire or reg....externally always wire (net)

parameter - keyword to edfine constants with a meaningful way

pmos - switch level

posedge - transtion from 0->1 or from 0,x,z->1

primitive - used in UDP creation to define a primitve

pull0 - supply strentg 2nd highest

pull1 - supply strentg 2nd highest

pulldown - switch level strength

pullup- swtich level strength

rcmos - resitive cmos model

real - 32 bit real number like real time-shows the value of current simulation time
in real numbe format

realtime - 32 bit real number like real time-shows the value of current simulation
time in real numbe format

reg - keyword which can store values.

release - release a vlaue which has been force to certain output

repeat - repeat (3) #5 {a,b}={a,b}+1; will repeat this condition 3 times

rnmos - ressitive nmos

rpmos - resistive pmos

rtran - ??

rtanif0-??

rtranif1-??

scalared-??

signed - used to specify number format

small - strength level specification

specify - specify-endspecify block used to assign path delays in case of pin-pin

and input-output and system clock.
$setup,$hold will check for repsective voilations

specparam - used inside the above module for definign the local parameters in the
above modules

strength - driving level

strong0 - driving strength for 0 logic

strong1 - driving strength for 1 logic

supply0 - used to model gnd

supply1 - sued to model Vdd

table - sued in UDP for creating a truth table

task - used to recurring logic, can call another task or module. can contain
delays, timing and events. can take inputs,outputs
and inouts in its defination. can pass output values to the requried ports in
module. can adbanve simulation time.

time - sued as $time - system task to output current simulation time

tran-??

tranif0-??

tranif1-??

tri - keyword for tri state buffer if a else z

tri0 - allows values to pass if contl-0

tri1 - allows values to pass if contl-1

triand - it is tri state and gate

trior- it is a tri state or gate

trireg - it is reg data type variable and is tri stated

unsigned - number radix format

vectored-??

wait - level sensitive timing (delay or event)

wand- wired and logic like in case of 7 segment the diodes anode is kept at wand
since its open collector formation.

weak0 - strength level

weak1 - strength level

while - loop condition

wire - data type net used in contimnous assignment on LHS

wor - wired OR

xnor - 2 input xnor gate

xor - 2 input xor gate