Test: SPARC M7 Processor and Product Overview Assessment

Review your answers, feedback, and question scores below. An asterisk (*) indicates a correct answer.

This 20-question assessment test is one component of the SPARC M7 Servers Support Consultant training. This
assessment will allow you to test your knowledge of the information learned from the SPARC M7 Servers Support
Consultant guided learning path. Passing with a >80% score from this assessment, and passing all required
assessments makes you eligible to become a SPARC M7 Servers Support Consultant.

SPARC M7 Processor Architecture

(Answer all questions in this section)

1. Which statement is true?

Mark for Review
(1) Points

The S4 supports 16 threads per core

The SPARC M7 processor uses the fourth generation CMT Core, referred to as S4
(*)
The SPARC M7 processor uses the fourth generation CMT Core, referred to as S3.

The S3 supports 16 threads per core

Incorrect. Please refer back to the lesson “SPARC M7 Processor Overview.”

2. How does the M7 processor implement SSM within its silicon?

Mark for Review
(1) Points

By improving the crytography performance within the M7 processor chip

By implementing 8 DAX units to function as co-processors (*)

By increasing the size of the instruction pipeline

By implementing increasing the cache size

Correct!

3. How many virtual CPUs can the M7 support considering that each thread can be a
virtual CPU? Mark for Review
(1) Points

32

64

128

256 (*)

Incorrect. Please refer back to the lesson “SPARC M7 Processor Overview.”

 4. Which response is the definition of a DAX?
Mark for Review
(1) Points

(Choose all correct answers)

A co-processor chip that offloads the data compression and decompression

functions from the software threads
A co-processor with the M7 processor that offloads the data compression and
decompression functions from the software threads (*)
A memory control unit within the M7 processor

A memory control unit chip outside of the M7 processor (*)

Incorrect. Please refer back to the lesson “SPARC M7 Processor Overview.”

5. Which two features are part of the SPARC M7 processor’s power management features
? Mark for Review
(1) Points

(Choose all correct answers)

Dynamic Voltage Frequency Scaling (*)

Dynamic memory allocation

Voltage Acclimatization

power gating (*)

Incorrect. Please refer back to the lesson “SPARC M7 Processor Overview.”

Page 1 of 4 Next Summary

Test: SPARC M7 Processor and Product Overview Assessment

Review your answers, feedback, and question scores below. An asterisk (*) indicates a correct answer.

This 20-question assessment test is one component of the SPARC M7 Servers Support Consultant training. This
assessment will allow you to test your knowledge of the information learned from the SPARC M7 Servers Support
Consultant guided learning path. Passing with a >80% score from this assessment, and passing all required
assessments makes you eligible to become a SPARC M7 Servers Support Consultant.

SPARC M7 Processor Architecture

(Answer all questions in this section)
6. Which systems use the SPARC M7 processor?
Mark for Review
(1) Points

(Choose all correct answers)

SPARC M6-32

SPARC T7-2 (*)

Oracle SuperCluster T5-8

SPARC T7-4 (*)

Oracle SuperCluster M7 (*)

Incorrect. Please refer back to the lesson “SPARC M7 Processor Overview.”

7. Which is the function of the Mystic River ASIC?

Mark for Review
(1) Points

Memory Buffer

I/O Hub (*)

Service Processor

Disk Controller

Correct!

8. Which type of DIMMs are supported by the M7 processor?

Mark for Review
(1) Points

DDR5

DDR4 (*)

DDR3
DDR2

Correct!

9. How many layers of cache does the SPARC M7 processor have?

Mark for Review
(1) Points

2
3
 4 (*)

Incorrect. Please refer back to the lesson “SPARC M7 Processor Overview.”

10. Which three statements are true about M7 processors?

Mark for Review
(1) Points

(Choose all correct answers)

Each M7 processor provides coherency links, referred to as CLINKs (*)

CLINKS are used on both the M7 and T7 servers (*)

Level 4 cache is one of the most important processor enhancements

CLINKS provide for inter-processor connections (*)

SSM is also a common features with Intel Processors

Correct!

Previous Page 2 of 4 Next Summary

Test: SPARC M7 Processor and Product Overview Assessment

Review your answers, feedback, and question scores below. An asterisk (*) indicates a correct answer.

This 20-question assessment test is one component of the SPARC M7 Servers Support Consultant training. This
assessment will allow you to test your knowledge of the information learned from the SPARC M7 Servers Support
Consultant guided learning path. Passing with a >80% score from this assessment, and passing all required
assessments makes you eligible to become a SPARC M7 Servers Support Consultant.

SPARC M7 WBT Product Overview

(Answer all questions in this section)

11. Which two responses are true about the SPARC M7-8 Server?
Mark for Review
(1) Points

(Choose all correct answers)

The M7-8 has a maximum of 4 processors

The M7-8 with 2 PDOM is configured as a 2x4 socket arrangement with a

maximum of 8 processors (*)
The M7-8 with 2 PDOM is configured as a 1x8 socket arrangement with a
maximum of 8 processors
The M7-8 with 1 PDOM has cache coherency between all 8 M7 processors (*)
 The M7-8 with 1 PDOM uses the same internal interconnects as that of the M7-8
with 2 PDOM

Correct!

12. Which interconnect is common to the M7-8 and M7-16 configurations?

Mark for Review
(1) Points

II_W_248

II_8_N_RO

II_CMIOU_SP (*)

XI_N_4_T2B_S

Correct!

13. How many DIMM slots are supported on each CMIOU?

Mark for Review
(1) Points

16 (*)

32

64

Correct!

14. What is the Silicon Secured Memory feature?

Mark for Review
(1) Points

A "Software in Silicon" feature where a DAX used to accelerate data

decompression by offloading it from the software threads.
A "Software in Silicon" feature where DAX used to execute the database queries
offloading it from the software threads.
A "Software in Silicon" feature that improves the performance of Java.

A "Software in Silicon" feature that adds a 16 bit application data bits which can
associate the pointer to the object it is pointing to. (*)

Incorrect. Please refer back to the lesson “SPARC M7 Product Overview.”

15. Select the two specifications that correspond to the M7 processor?

Mark for Review
(1) Points

(Choose all correct answers)

 Total of 3 memory controllers

Greater than a 4.0 GHz clock speed (*)

Total of 32 cores (*)

Total of 512KB level 2 data cache per core pair

Total of 4 MB of level 3 cache per each set of 4 cores

Correct!

Previous Page 3 of 4 Next Summary

Test: SPARC M7 Processor and Product Overview Assessment

Review your answers, feedback, and question scores below. An asterisk (*) indicates a correct answer.

This 20-question assessment test is one component of the SPARC M7 Servers Support Consultant training. This
assessment will allow you to test your knowledge of the information learned from the SPARC M7 Servers Support
Consultant guided learning path. Passing with a >80% score from this assessment, and passing all required
assessments makes you eligible to become a SPARC M7 Servers Support Consultant.

SPARC M7 WBT Product Overview

(Answer all questions in this section)

16. Which are the boot options available on the SPARC M7-8 and M7-16 Servers?
Mark for Review
(1) Points

(Choose all correct answers)

Versaboot/eUSB (*)
Internal HBA and HDD

USB port for a flash stick

Aura3 Memory Express (NVMe) controller and a Solid-State Disk (SSD). (*)

16 Gb FC to FC SAN attached Storage using Ganymede-Q or Ganymede-E (*)

Incorrect. Please refer back to the lesson “SPARC M7 Product Overview.”

17. How many CMIOUs are there in a DCU in the M7-16?

Mark for Review
(1) Points

1
2
 3

4 (*)

Correct!

18. Which features of “Software in Silicon” are supported by the SPARC M7 processor?
Mark for Review
(1) Points

(Choose all correct answers)

Database Query Acceleration (*)

Database Decompression (*)

Silicon Secured Memory (*)

scalability links

coherency links

Correct!

19. How many M7 processors are supported on each CMIOU?

Mark for Review
(1) Points

1 (*)

Incorrect. Please refer back to the lesson “SPARC M7 Product Overview.”

20. Which links are connected to the switch units from the CMIOUs on the M7-16?
Mark for Review
(1) Points

coherency

scalability (*)

cache

memory

Incorrect. Please refer back to the lesson “SPARC M7 Product Overview.”

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