library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock is
Port (
Clk : in std_logic;
LED : out STD_LOGIC_VECTOR(6 downto 0);
dp : out STD_LOGIC;
an0 : inout STD_LOGIC;
an1 : inout STD_LOGIC;
an2 : inout STD_LOGIC;
an3 : inout STD_LOGIC;
end clock;

architecture Behavioral of clock is

signal point : std_logic := '0';

signal sec: integer range 0 to 59 := 0;
signal digit1: integer range 0 to 9 := 0;
signal digit2: integer range 0 to 5 := 0;
signal hr: integer range 0 to 23 := 0;
signal pButton, pButton2 : STD_LOGIC := '0';
begin
cycle <= '1' when pulseCnt = 1 else '0';
process (Clk, mButton, mButton2)
begin
if (Clk'event) and (Clk='1') then
if (reset='1') then
sec <= 0;
digit1 <= 0;
digit2 <= 0;
hr <= 0;
pulseCnt <= 0;
end if;
if (mButton/=pButton) then
if (digit1=9) then
if (digit2=5) then
if (hr=23) then
hr<=0;
else
hr<=hr+1;
end if;
digit2<=0;
else
digit2<=digit2+1;
end if;
digit1<=0;
else
digit1<=digit1+1;
end if;
pButton <= mButton;
end if;
if pulseCnt=1 then
if (sec=59) then
if (digit1=9) then
if (digit2=5) then
 if (hr=23) then
hr<=0;
else
hr<=hr+1;
end if;
digit2<=0;
else
digit2<=digit2+1;
end if;

digit1<=0;
else
digit1<=digit1+1;
end if;
sec<=0;
else
sec<=sec+1;
point <= not point;
end if;
end if;
end if;
end process;

end Behavioral;