Motorola - Analog Interface ICs Devices Vol I - Dl128rev6

Volumes
Alphanumeric Index and

II I 1
Cross References
I Amplifiers and Comparators 2
I Power Supply Circuits 3
I Power/Motor Control Circuits 4
II Voltage References 5
II Data Conversion 6
II Interface Circuits 7
II Communication Circuits 8
II Consumer Electronic Circuits 9
II Automotive Electronic Circuits 10
II Other Analog Circuits 11
II I Tape and Reel Options 12
II I Packaging Information 13
II Quality and Reliability Assurance 14
II Applications and Product Literature 15

What's Different
New Additions
CHAPTER 3 CHAPTER 7 MC13283

LM2575 MC1413 MC44007
MC78BC00 MC34156 MC44030/35
MC78FC00 SN75175 MC44306
MC78LC00 MC44353
MC33154 MC44354
CHAPTER 8 MC44355
MC33264
MC13109 MC44461
MC33341
MC13110 MC44462
MC33347
MC13111 MC44463
MC33348
MC13144
MC33363A
MC13159 CHAPTER 10
MC33364
MC33368 MC33143
MC33463 CHAPTER 9 MC33193
MC33464 MC13022 MC33197A
MC33465 MC13029A MC33293
MC33466 MC13081X MCCF33093
MC34065, MC33065 MC13022A MCCF33094
MC34165, MC33165 MC13280AY, MC13281A/B MCCF33095
MC44604 MC13282A
MC44605
Deletes
LM307 MC3372A MC33344

LM248 MC3430 MC34050
MC1411 MC3486 MC34051
MC1412 MC3487 MC44301
MC1472 MC13001X/07X MC44302
MC1748C MC13017 MC44303
MC3361C MC13024 MCT1413
MC3371A MC33292 SN75173
New Product Literature (Referenced)
AN454A AN1044 AN1544

AN829 AN1315 AN1548
AN921 AN1539 AN1575
AN932
Not Recommended For New Designs
AM26LS31 MC3450 MC3485

AM26LS32 MC3453 ULN2068
MC26S10 MC3467 TDA1185A
MC3373 MC3481
MC3448A
3 Ways To Receive
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DL128/D
REV 6
Analog ICs
Device Data Vol. I
This publication presents technical information for the broad line of Analog and Interface Integrated Circuit
products. Complete device specifications are provided in the form of Data Sheets which are categorized by product
type into ten chapters for easy reference. Selector Guides by product family are provided in the beginning of each
chapter to enable quick comparisons of performance characteristics. A Cross Reference chapter lists Motorola
nearest replacement and functional equivalent part numbers for other industry products.
One chapter is devoted showing all of the Tape and Reel Options. All Packaging Information, including
surface mount packages, is provided in another chapter.
Additionally, chapters are provided with information on Quality and Reliability Assurance program concepts,
high–reliability processing, and abstracts of available Applications and Product Literature.
The information in this book has been carefully checked and is believed to be accurate; however, no responsibility
is assumed for inaccuracies.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and
do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer
shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges
that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Series J
First Printing
 Motorola, Inc. 1996
Previous Edition  1995
Printed in U.S.A. ‘‘All Rights Reserved’’
i
Data Classification
Product Preview
This heading on a data sheet indicates that the device is in the formative stages or
in design (under development). The disclaimer at the bottom of the first page reads:
‘‘This document contains information on a product under development. Motorola
reserves the right to change or discontinue this product without notice.’’
Advance Information
This heading on a data sheet indicates that the device is in sampling,
pre–production, or first production stages. The disclaimer at the bottom of the first
page reads: ‘‘This document contains information on a new product. Specifications
and information herein are subject to change without notice.’’
Fully Released
A fully released data sheet contains neither a classification heading nor a disclaimer
at the bottom of the first page. This document contains information on a product in
full production. Guaranteed limits will not be changed without written notice to your
local Motorola Semiconductor Sales Office.
C–QUAM, Designer’s, Easy Switcher, GreenLine, MDTL, MECL, MECL 10,000,

MONOMAX, MOSAIC, MRTL, MTTL, MOSFET, SENSEFET, Sleep–Mode, SMARTMOS,
Switchmode, and ZIP–R–TRIM are trademarks of Motorola Inc.
ii
iii
Alphanumeric Index and
Cross References
In Brief . . .
Motorola Analog and Interface Integrated Circuits cover a
much broader range of products than the traditional op amps/
regulators/consumer–image associated with Analog suppli-
ers. Analog circuit technology currently influences the design
and architecture of equipment for all major markets. As with
other integrated circuit technologies, Analog circuit design
techniques and processes have been continually refined and
updated to meet the needs of these diversified markets.
Operational amplifiers have utilized JFET inputs for
improved performance, plus innovative design and trimming
concepts have evolved for improved high performance and
precision characteristics. In analog power ICs, basic voltage
regulators have been refined to include higher current and
voltage levels, low dropout regulators, and more precise
three–terminal fixed and adjustable voltages. The power area
continues to expand into switching regulators, power supply
control and supervisory circuits, motor controllers, and battery
charging controllers.
Analog designs also offer a wide array of line drivers,
receivers and transceivers for many of the EIA, European,
IEEE and IBM interface standards. Peripheral drivers for a
variety of devices are also offered. In addition to these key
interface functions, hard disk drive read channel circuits,
10BASE–T and Ethernet circuits are also available.
In Data Conversion, a high performance video speed flash
converter is available, as well as a variety of CMOS and
Sigma–Delta converters. Analog circuit technology has also
provided precision low–voltage references for use in Data
Conversion and other low temperature drift applications.
A host of special purpose analog devices have also been
developed. These circuits find applications in telecommunica-
tions, radio, television, automotive, RF communications, and
data transmission. These products have reduced the cost of
RF communications, and have provided capabilities in tele-
communications which make the telephone line convenient
for both voice and data communications. Analog develop-
ments have also reduced the many discrete components
formerly required for consumer functions to a few IC packages
and have made significant contributions to the rapidly growing
market for electronics in automotive applications.
The table of contents provides a perspective of the many
markets served by Analog/Interface ICs and of Motorola’s
involvement in these areas.
MOTOROLA ANALOG IC DEVICE DATA 1–1

Alphanumeric Index
Device Function Page Device Function Page
Number Number
AM26LS30 Dual Differential/Quad Single–Ended Line 7–13 LM2935 Low Dropout Dual Regulator 3–146
Drivers LM3900 Quad Single Supply Operational Amplifier 2–113
AM26LS31# Quad Line Driver with NAND Enabled 7–24 LP2950 Micropower Voltage Regulator 3–150
Three–State Outputs LP2951 Micropower Voltage Regulator 3–150
AM26LS32# Quad EIA–422/423 Line Receiver with 7–24 MC1350 Monolithic IF Amplifier 9–30
Three–State Outputs MC1374 TV Modulator Circuit 9–34
CA3059 Zero Voltage Switches 4–14 MC1377 Color TV RGB to PAL/NTSC Encoder 9–42
CA3146 General Purpose Transistor Array 9–28 MC1378 Color TV Composite Video Overlay 9–58
LF347, B JFET Input Operational Amplifiers 2–11 Synchronizer
LF351 JFET Input Operational Amplifiers 2–11 MC1391 TV Horizontal Processor 9–62
LF353 JFET Input Operational Amplifiers 2–11 MC1403, B Low Voltage Reference 5–9
LF411C Low Offset, Low Drift JFET Input Operational 2–13 MC1404 Voltage References Family 5–13
Amplifiers MC1413, B High Voltage, High Current Darlington 7–30
LF412C Low Offset, Low Drift JFET Input Operational 2–13 Transistor Arrays
Amplifiers MC1416, B High Voltage, High Current Darlington 7–30
LF441C Low Power JFET Input Operational Amplifiers 2–17 Transistor Arrays
LF442C Low Power JFET Input Operational Amplifiers 2–17 MC1436, C High Voltage, Internally Compensated 2–79
LF444C Low Power JFET Input Operational Amplifiers 2–17 Operational Amplifiers
LM11C, CL Precision Operational Amplifiers 2–24 MC1455, B Timing Circuit 11–6
LM201A Operational Amplifiers 2–30 MC1458, C Internally Compensated, High Performance 2–84
LM211 Highly Flexible Voltage Comparator 2–39 Dual Operational Amplifiers
LM224 Quad Low Power Operational Amplifiers 2–45 MC1488 Quad Line Driver 7–33
LM239, A Quad Single Supply Comparators 2–52 MC14C88B Quad Low Power Line Driver 7–44
LM258 Dual Low Power Operational Amplifiers 2–62 MC14C89B, AB Quad Low Power Line Receiver 7–50
LM285 Micropower Voltage Reference Diodes 5–4 MC1489, A Quad Line Receivers 7–39
LM293 Low Offset Voltage Dual Comparators 2–68 MC1490 RF/IF Audio Amplifier 2–92
LM301A Operational Amplifiers 2–30 MC1494 Linear Four–Quadrant Multiplier 11–14
LM308A Precision Operational Amplifier 2–34 MC1495 Wideband Linear Four–Quadrant Multiplier 11–28
LM311 Highly Flexible Voltage Comparator 2–39 MC1496 Balanced Modulatosr/Demodulators 8–45
LM317 Three–Terminal Adjustable Output Positive 3–45 MC1723C Voltage Regulator 3–162
Voltage Regulator MC1741C Internally Compensated, High Performance 2–99
LM317L Three–Terminal Adjustable Output Voltage 3–53 Operational Amplifier
Regulator MC1776C Micropower Programmable Operational 2–104
LM317M Three–Terminal Adjustable Output Positive 3–61 Amplifier
Voltage Regulator MC2833 Low Power FM Transmitter System 8–55
LM323, A Positive Voltage Regulators 3–69 MC3301 Quad Single Supply Operational Amplifier 2–113
LM324, A Quad Low Power Operational Amplifiers 2–45 MC3302 Quad Single Supply Comparators 2–52
LM337 Three–Terminal Adjustable Output Negative 3–75 MC3303 Quad Low Power Operational Amplifier 2–123
Voltage Regulator MC3334 High Energy Ignition Circuit 10–15
LM337M Three–Terminal Adjustable Output Negative 3–82 MC3335 Low Power Dual Conversion FM Receiver 8–62
Voltage Regulator MC3340 Electronic Attenuator 9–66
LM339, A Quad Single Supply Comparators 2–52 MC3346 General Purpose Transistor Array One 9–69
LM340, A Series Three–Terminal Positive Voltage Regulators 3–89 Differentially Connected Pair and Three
LM348 Differential Input Operational Amplifier 2–56 Isolated Transistor Arrays
LM350 Three–Terminal Adjustable Output Positive 3–105 MC3356 Wideband FSK Receiver 8–66
Voltage Regulator MC3357 Low Power FM IF 8–72
LM358 Dual Low Power Operational Amplifier 2–62 MC3358 Dual, Low Power Operational Amplifier 2–137
LM385, B Micropower Voltage Reference Diodes 5–4 MC3359 Dual, Low Power Operational Amplifier 8–76
LM393, A Low Offset Voltage Dual Comparators 2–68 MC3362 Low Power Dual Conversion FM Receiver 8–82
LM833 Dual Low Noise, Audio Amplifier 2–73 MC3363 Low Power Dual Conversion FM Receiver 8–113
LM2575 Easy Switcher 1.0 A Step–Down Voltage 3–113 MC3371 Low Power Narrowband FM IF 8–96
Regulator MC3372 Low Power Narrowband FM IF 8–96
LM2900 Quad Single Supply Operational Amplifier 2–113 MC3373# Remote Control Wideband Amplifier with 9–72
LM2901, V Quad Single Supply Comparator 2–52 Detector
LM2902, V Quad Low Power Operational Amplifier 2–45 MC3374 Low Voltage FM Narrowband Receiver 8–89
LM2903, V Low Offset Voltage Dual Comparator 2–68 MC3392 Low Side Protected Switch 10–19
LM2904, V Dual Low Power Operational Amplifier 2–62 MC3399 Automotive Half–Amp High–Side Switch 10–28
LM2931 Low Dropout Voltage Regulator 3–136 MC3403 Quad Low Power Operational Amplifier 2–123
* = See Communications Device Data (DL136).
# = Not recommended for new designs.
1–2 MOTOROLA ANALOG IC DEVICE DATA

Alphanumeric Index (continued)
Number Number
MC3405 Dual Operational Amplifier and Dual 2–129 MC13111 Universal Cordless Telephone Subsystem IC 8–185
Comparator MC13122 AMAX Stereo Chipset 9–94
MC3418 Continuously Variable Slope Delta * MC13135 FM Communications Receiver 8–214
Modulator/Demodulator MC13136 FM Communications Receiver 8–214
MC3419–IL Telephone Line–Feed Circuit * MC13141 Low Power DC–1.8 GHz LNA and Mixer 8–226
MC3423 Overvoltage Crowbar Sensing Circuit 3–168 MC13142 Low Power DC–1.8 GHz LNA, Mixer and VCO 8–235
MC3425 Power Supply Supervisory/Over and 3–174 MC13143 Ultra Low Power DC–2.4 GHz Linear Mixer 8–245
Undervoltage Protection Circuit MC13144 VHF – 2.0 GHz Low Noise Amplifier with 8–252
MC3448A# Bidirectional Instrumentation Bus (GPIB) 7–58 Programmable Bias
Transceiver MC13150 Narrowband FM Coilless Detector IF 8–258
MC3450# Quad MTTL Compatible Line Receivers 7–64 Subsystem
MC3453# MTTL Compatible Quad Line Driver 7–71 MC13155 Wideband FM IF System 8–275
MC3456 Dual Timing Circuit 11–43 MC13156 Wideband FM IF System 8–290
MC3458 Dual, Low Power Operational Amplifier 2–137 MC13158 Wideband FM IF Subsystem 8–308
MC3467# Triple Wideband Preamplifier with Electronic 7–76 MC13159 Wideband FM IF Amplifier 8–330
Gain Control (EGC) MC13173 Infrared Integrated Transceiver System 8–336
MC3476 Low Cost Programmable Operational Amplifier 2–144 MC13175 UHF FM/AM Transmitter 8–353
MC3479 Stepper Motor Driver 4–19 MC13176 UHF FM/AM Transmitter 8–353
MC3481# Quad Single–Ended Line Driver 7–81 MC13280AY 80/100 MHz Video Processor 9–205
MC3485# Quad Single–Ended Line Driver 7–81 MC13281A, B 80/100 MHz Video Processor 9–205
MC3488A Dual EIA–423/EIA–232D Line Driver 7–86 MC13282A 100 MHz Video Processor with OSD Interface 9–215
MC3518 Continuously Variable Slope Delta * MC13283 130 MHz Video Processor with OSD Interface 9–226
Modulator/Demodulator
MC26S10# Quad Open–Collector Bus Transceiver 7–55
MC4558AC, C Dual Wide Bandwidth Operational Amplifiers 2–149 MC33023 High Speed Single–Ended PWM Controller 3–392
MC4741C Differential Input Operational Amplifier 2–156 MC33025 High Speed Double–Ended PWM Controller 3–408
MC7800 Three–Terminal Positive Voltage Regulators 3–182 MC33030 DC Servo Motor Controller/Driver 4–27
Series
MC33033 Brushless DC Motor Controller 4–41
MC78L00, A Three–Terminal Low Current Positive Voltage 3–197
MC33035 Brushless DC Motor Controller 4–64
Series Regulators
MC33039 Closed–Loop Brushless Motor Adapter 4–87
MC78M00 Three–Terminal Medium Current Positive 3–204
Series Voltage Regulators MC33060A Precision Switchmode Pulse Width Modulator 3–425
Control Circuit
MC78T00 Three–Ampere Positive Voltage Regulators 3–213
Series MC33063A DC–to–DC Converter Control Circuit 3–437
MC78BC00 Micropower Voltage Regulator 3–222 MC33064 Undervoltage Sensing Circuit 3–446
MC78FC00 Micropower Voltage Regulator 3–223 MC33065 High Performance Dual Channel Current Mode 3–451
Controller
MC78LC00 Micropower Voltage Regulator 3–224
MC33065–H, L High Performance Dual Channel Current Mode 3–465
MC7900 Series Three–Terminal Negative Voltage Regulators 3–225
Controllers
MC79L00, A Three–Terminal Low Currect Negative Voltage 3–235
MC33066 High Performance Resonant Mode Controller 3–478
Series Regulators
MC33067 High Performance Resonant Mode Controller 3–486
MC79M00 Three–Terminal Negative Voltage Regulators 3–240
Series MC33071, A High Slew Rate, Wide Bandwidth, Single Supply 2–272
Operational Amplifiers
MC10319 High Speed 8–Bit Analog–to–Digital Flash 6–6
Converter MC33072, A High Slew Rate, Wide Bandwidth, Single Supply 2–272
MC13020 Motorola C–QUAM AM Stereo Decoder 9–66
MC33074, A High Slew Rate, Wide Bandwidth, Single Supply 2–272
MC13022 Advanced Medium Voltage AM Stereo Decoder 9–81
MC13022A Advanced Medium Voltage AM Stereo Decoder 9–86
MC33076 Dual High Output Current, Low Power, Low 2–161
MC13025 Electronically Tuned Radio Front End 9–91 Noise Bipolar Op Amp
MC13027 AMAX Stereo Chipset 9–94 MC33077 Dual, Low Noise Operational Amplifier 2–169
MC13028A Advanced Wide Voltage IF and C–QUAM AM 9–119 MC33078 Dual/Quad Low Noise Operational Amplifier 2–180
Stereo Decoder
MC33079 Dual/Quad Low Noise Operational Amplifier 2–180
MC13029A Advanced Wide Voltage IF and C–QUAM AM 9–137
MC33091A HIgh Side TMOS Driver 10–31
Stereo Decoder with FM Amplifier and
AM/FM Internal Switch MC33092 Alternator Voltage Regulator 10–45
MC13030 Dual Conversion AM Receiver 9–156 MC33095 Integral Alternator Regulator 10–134
MC13055 Wideband FSK Receiver 8–121 MC33102 Sleep–Mode Two–State, Micropower 2–189
Operational Amplifier
MC13060 Mini–Watt Audio Output 9–171
MC13077 Advanced PAL/NTSC Encoder 9–175 MC33110 Low Voltage Compander *
MC13081X Multimode Color Monitor Horizontal, Vertical 9–187 MC33111 Low Voltage Compander with Mute and *
and Video Combination Processor Feedthrough
MC13109 Universal Cordless Telephone Subsystem IC 8–128 MC33120 Subscriber Loop Interface Circuit *
MC13110 Universal Cordless Telephone Subsystem IC 8–154 MC33121 Low Voltage Subscriber Loop Interface Circuit *
with Scrambler MC33128 Power Management Controller 3–244


Number Number
MC33129 High Performance Current Mode Controller 3–499 MC33341 Power Supply/Battery Charger Regulation 3–301
MC33143 Dual High–Side Switch 10–45 Control Circuit
MC33151 High Speed Dual MOSFET Driver 3–514 MC33345 Lithium Battery Protection Circuit for One to 3–316
MC33152 High Speed Dual MOSFET Driver 3–522 Four Cell Battery Packs
MC33153 Single IGBT Gate Driver 3–251 MC33346 Lithium Battery Protection Circuit for Three or 3–328
MC33154 Single IGBT Gate Driver 3–262 Four Cell Battery Packs
MC33160 Microprocessor Voltage Regulator and 3–530 MC33347 Lithium Battery Protection Circuit for One or 3–329
Supervisory Circuit Two Cell Battery Packs
MC33161 Universal Voltage Monitors 3–537 MC33348 Lithium Battery Protection Circuit for One Cell 3–339
Battery Packs
MC33163 Power Switching Regulator 3–550
MC33164 Micropower Undervoltage Sensing Circuit 3–564 MC33362 High Voltage Switching Regulator 3–348
MC33165 Power Switching Regulator 3–570 MC33363 High Voltage Switching Regulator 3–359
MC33166 Power Switching Regulator 3–584 MC33363A High Voltage Switching Regulator 3–370
MC33167 Power Switching Regulator 3–598 MC33364 Critical Conduction SMPS Controller 3–371
MC33169 GaAs Power Amplifier Support IC 3–263 MC33368 High Voltage GreenLine Power Factor 3–372
Controller
MC33171 Low Power, Single Supply Operational Amplifier 2–201
MC33463 Variable Frequency Micropower DC–to–DC 3–384
Converter
MC33464 Micropower Undervoltage Sensing Circuits 3–386
MC33178 High Output Current, Low Power, Low Noise 2–208
MC33465 Micropower Undervoltage Sensing Circuits with 3–388
Bipolar Op Amp
Output Delay
MC33179 High Output Current, Low Power, Low Noise 2–208
MC33466 Fixed Frequency PWM Micropower DC–to–DC 3–390
Bipolar Op Amp
Converter
MC33181 Low Power, High Slew Rate, Wide Bandwidth, 2–299
MC34001, B JFET Input Operational Amplifier 2–265
JFET Input Op Amp
MC34002, B JFET Input Operational Amplifier 2–265
MC33182 Low Power, High Slew Rate, Wide Bandwidth, 2–299
JFET Input Op Amp MC34004, B JFET Input Operational Amplifier 2–265
MC33184 Low Power, High Slew Rate, Wide Bandwidth, 2–299 MC34010 Electronic Telephone Circuit *
JFET Input Op Amp MC34011A Electronic Telephone Circuit *
MC33192 Mi–Bus Interface Stepper Motor Controller 10–60 MC34012 Telephone Tone Ringer *
MC33193 Automotive Direction Indicator 10–71 MC34014 Telephone Speech Network with Dialer *
Interface
MC33197A Automotive Wash Wiper Timer 10–78
MC33199 Automotive ISO 9141 Serial Link Driver 10–83 MC34016 Cordless Universal Telephone Interface *
MC33201 Rail–to–Rail Operational Amplifier 2–218 MC34017 Telephone Tone Ringer *
MC33202 Rail–to–Rail Operational Amplifier 2–218 MC34018 Voice Switched Speakerphone Circuit *
MC33204 Rail–to–Rail Operational Amplifier 2–218 MC34023 High Speed Single–Ended PWM Controller 3–392
MC33206 Rail–to–Rail Operational Amplifier with Enable 2–227 MC34025 High Speed Double–Ended PWM Controller 3–408
Feature MC34055 IEEE 802.3 10BASE–T Transceiver 7–90
MC33207 Rail–to–Rail Operational Amplifier with Enable 2–227 MC34058 Hex EIA–485 Transceiver with Three–State 7–105
Feature Outputs
MC33218A Voice Switched Speakerphone with * MC34059 Hex EIA–485 Transceiver with Three–State 7–105
Microprocessor Interface Outputs
MC33219A Voice Switched Speakerphone * MC34060A Precision Switchmode Pulse Width Modulator 3–425
Control Circuit
MC33261 Power Factor Controller 3–612
MC33262 Power Factor Controller 3–623 MC34063A DC–to–DC Converter Control Circuit 3–437
MC33264 Micropower Voltage Regulators with On/Off 3–273 MC34064 Undervoltage Sensing Circuit 3–446
Control MC34065 High Performance Dual Channel Current Mode 3–451
Controller
MC33267 Low Dropout Regulator 3–280
MC33269 Low Dropout Positive Voltage Regulator 3–285 MC34065–H, L High Performance Dual Channel Current Mode 3–465
Series Controllers
MC33272A Single Supply, High Slew Rate Low Input Offset 2–237 MC34066 High Performance Resonant Mode Controller 3–478
Voltage, Bipolar Op Amp MC34067 High Performance Resonant Mode Controller 3–486
MC33274A Single Supply, High Slew Rate Low Input Offset 2–237 MC34071, A High Slew Rate, Wide Bandwidth, 2–272
Voltage, Bipolar Op Amp Single–Supply Operational Amplifier
MC33282 Low Input Offset, High Slew Rate, Wide 2–246 MC34072, A High Slew Rate, Wide Bandwidth, 2–272
Bandwidth, JFET Input Op Amp Single–Supply Operational Amplifier
MC33284 Low Input Offset, High Slew Rate, Wide 2–246 MC34074, A High Slew Rate, Wide Bandwidth, 2–272
Bandwidth, JFET Input Op Amp Single–Supply Operational Amplifier
MC33293A Quad Low Side Switch 10–94 MC34080 High Slew Rate, Wide Bandwidth, JFET Input 2–288
MC33298 Octal Output Driver 10–109
MC33304 Low Voltage Rail–to–Rail, Sleepmode 2–254 MC34081 High Slew Rate, Wide Bandwidth, JFET Input 2–288
Operational Amplifier Operational Amplifier
MC33340 Battery Fast Charge Controller 3–290 MC34082 High Slew Rate, Wide Bandwidth, JFET Input 2–288

Number Number
MC34083 High Slew Rate, Wide Bandwidth, JFET Input 2–288 MC44603 Mixed Frequency Mode GreenLine PWM 3–667
Operational Amplifier Controller
MC34084 High Slew Rate, Wide Bandwidth, JFET Input 2–288 MC44604 High Safety Standby Ladder Mode GreenLine 3–689
Operational Amplifier PWM Controller
MC34085 High Slew Rate, Wide Bandwidth, JFET Input 2–288 MC44605 High Safety Latched Mode GreenLine PWM 3–690
Operational Amplifier Controller for (Multi) Synchronized
MC34114 Telephone Speech Network with Dialer * Applications
Interface MC44817, B PLL Tuning Circuit with 3–Wire Bus 9–367
MC34115 Continuously Variable Slope Delta * MC44818 PLL Tuning Circuit with I2C Bus 9–374
Modulator/Demodulator MC44824, 25 PLL Tuning Circuit with I2C Bus 9–381
MC34117 Telephone Tone Ringer * MC44826 PLL Tuning Circuit with I2C Bus 9–388
MC34118 Voice Switched Speakerphone Circuit * MC44827 PLL Tuning Circuit with 3–Wire Bus 9–395
MC34119 Low Power Audio Amplifier 9–227 MC44828 PLL Tuning Circuit with I2C Bus 9–396
MC34129 High Performance Current Mode Controller 3–499 MC44829 PLL Tuning Circuit with I2C Bus 9–397
MC34151 High Speed Dual MOSFET Driver 3–514 MC44864 PLL Tuning Circuit with 1.3 GHz Prescaler and 9–405
MC34152 High Speed Dual MOSFET Driver 3–522 D/A Converters for Automatic Tuner
MC34156 28–Channel Inkjet Driver 7–116 Alignment
MC34160 Microprocessor Voltage Regulator and 3–530 MC68160 Enhanced Ethernet Transceiver 7–120
Supervisory Circuit MC75172B Quad EIA–485 Line Driver with Three–State 7–146
MC34161 Universal Voltage Monitor 3–537 Output
MC34163 Power Switching Regulator 3–550 MC75174B Quad EIA–485 Line Driver with Three–State 7–146
Output
MC34164 Micropower Undervoltage Sensing Circuit 3–564
MC34165 Power Switching Regulator 3–570 MC79076 Electronic Ignition Control Chip 10–131
MC34166 Power Switching Regulator 3–584 MCC3334 High Energy Ignition Circuit 10–15
MC34167 Power Switching Regulator 3–598 MCCF3334 High Energy Ignition Circuit 10–15
MC34181 Low Power, High Slew Rate, Wide Bandwidth, 2–299 MCCF33093 Ignition Control Flip–Chip 10–132
JFET Input Op Amp MCCF33094 Ignition Control Flip–Chip 10–133
MC34182 Low Power, High Slew Rate, Wide Bandwidth, 2–299 MCCF33095 Integral Alternator Regulator 10–134
JFET Input Op Amp MCCF79076 electronic Ignition Control Chip 10–131
MC34184 Low Power, High Slew Rate, Wide Bandwidth, 2–299 MCT1458, C Internally Compensated, High Performance 2–89
JFET Input Op Amp Dual Operational Amplifier
MC34216A Programmable Telephone Line Interface Circuit * MCT4558C Dual Wide Bandwidth Operational Amplifier 2–153
with Loudspeaker Amplifier SAA1042 Stepper Motor Driver 4–92
MC34250 5.0 V, 200 M–Bit/Sec PR–IV Hard Disk Drive 7–118 SG3525A Pulse Width Modulator Control Circuit 3–691
Read Channel SG3526 Pulse Width Modulator Control Circuit 3–697
MC34261 Power Factor Controller 3–612 SG3527A Pulse Width Modulator Control Circuit 3–691
MC34262 Power Factor Controller 3–623 SN75175 Quad EIA–485 Line Receiver 7–157
MC34268 SCSI–2 Active Terminator Regulator 3–638 TCA0372 Dual Power Operational Amplifier 2–308
MC34270 Liquid Crystal Display and Backlight Integrated 3–641 TCA3385 Telephone Ring Signal Converter *
Circuit TCA3388 Telephone Speech Network *
MC34271 Liquid Crystal Display and Backlight Integrated 3–641 TCA5600 Universal Microprocessor Power 3–705
Circuit Supply/Controller
MC44002 Chroma 4 Multistandard Video Processor 9–236 TCF5600 Universal Microprocessor Power 3–705
MC44007 Chroma 4 Multistandard Video Processor 9–236 Supply/Controller
MC44011 Bus Controlled Multistandard Video Processor 9–275 TCF6000 Peripheral Clamping Array 10–144
MC44030 Multistandard Video Signal Processor with 9–324 TDA1085C Universal Motor Speed Controller 4–97
Integrated Delay Line TDA1185A# Triac Phase Angle Controller 4–107
MC44035 Multistandard Video Signal Processor with 9–324 TL062 Low Power JFET Input Operational Amplifier 2–312
Integrated Delay Line TL064 Low Power JFET Input Operational Amplifier 2–312
MC44144 Subcarrier Phase–Locked Loop 9–326 TL071C, AC Low Noise JFET Input Operational Amplifier 2–319
MC44145 Pixel Clock Generator/Sync Separator 9–331 TL072C, AC Low Noise JFET Input Operational Amplifier 2–319
MC44353 PLL Tuned UHF Audio/Video Modulator ICs for 9–338 TL074C, AC Low Noise JFET Input Operational Amplifier 2–319
PAL, SECAM and NTSC TV Systems TL081C, AC JFET Input Operational Amplifier 2–325
MC44354 PLL Tuned UHF Audio/Video Modulator ICs for 9–338 TL082C, AC JFET Input Operational Amplifier 2–325
PAL, SECAM and NTSC TV Systems
TL084C, AC JFET Input Operational Amplifier 2–325
MC44355 PLL Tuned UHF Audio/Video Modulator ICs for 9–338 TL431, A, B Programmable Precision References 5–18
PAL, SECAM and NTSC TV Systems Series
MC44461 Picture–in–Picture (PIP) Controller 9–341 TL494 Switchmode Pulse Width Modulation Control 3–716
MC44462 Y–C Picture–in–Picture (PIP) Controller 9–354 Circuit
MC44463 Picture–in–Picture (PIP) Controller 9–360 TL594 Precision Switchmode Pulse Width Modulation 3–726
MC44602 HIgh Performance Current Mode Controller 3–651 Control Circuit

Number Number
TL780 Series Three–Terminal Positive Fixed Voltage 3–736 UC3843A HIgh Performance Current Mode Controller 3–742
Regulator UC3843B HIgh Performance Current Mode Controller 3–755
UAA1016B Zero Voltage Controller 4–116 UC3844 HIgh Performance Current Mode Controller 3–769
UAA1041b Automotive Direction Indicator 10–148 UC3844B HIgh Performance Current Mode Controller 3–782
UAA2016 Zero Voltage Switch Power Controller 4–122 UC3845 HIgh Performance Current Mode Controller 3–769
UC2842A HIgh Performance Current Mode Controller 3–742 UC3845B HIgh Performance Current Mode Controller 3–782
UC2842B HIgh Performance Current Mode Controller 3–755 UC3844B HIgh Performance Current Mode Controller 3–782
UC2843A HIgh Performance Current Mode Controller 3–742 UC3845 HIgh Performance Current Mode Controller 3–769
UC2843B HIgh Performance Current Mode Controller 3–755 UC3845B HIgh Performance Current Mode Controller 3–782
UC2844 HIgh Performance Current Mode Controller 3–769 ULN2068# Quad 1.5 A Sinking High Current Switch 7–162
UC2844B HIgh Performance Current Mode Controller 3–782 ULN2803 Octal High Voltage, High Current Darlington 7–166
UC2845 HIgh Performance Current Mode Controller 3–769 Transistor Array
UC2845B HIgh Performance Current Mode Controller 3–782 ULN2804 Octal High Voltage, High Current Darlington 7–166
UC3842A HIgh Performance Current Mode Controller 3–742 Transistor Array
UC3842B HIgh Performance Current Mode Controller 3–755 µA78S40 Universal Switching Regulator Subsystem 3–796

Cross References
The following table represents a cross reference guide for all number, the Motorola device is a ‘‘form, fit and function’’
Analog devices that are manufactured by Motorola. Where the replacement for the industry part number. However, some
Motorola part number differs from the industry part differences in characteristics and/or specifications may exist.
Industry Motorola Nearest Motorola Similar Industry Motorola Nearest Motorola Similar
Part Number Replacement Replacement Part Number Replacement Replacement
75175 SN75175 CS2845D UC2845BD1
9636AT MC3488AP CS3842AD UC3842BD1
9640PC MC26S10P# CS3843AD UC3843BD1
9667PC MC1413P CS3844D UC3844BD1
9668PC MC1416P CS3845D UC3845BD1
AD589J LM385Z–1.2 DM8822N MC1489AP
AD589K LM385Z–1.2 DS1233M MC34064P–5
AD589L LM385Z–1.2 DS1488N MC1488P
AD589M LM385BZ–1.2 DS1489AN MC1489AP
AM201AD LM201AN DS1489N MC1489P
AM201D LM201AN DS26LS32N AM26LS32P#
AM26LS30P AM26LS30PC DS26S10CN MC26S10P#
AM26LS31CJ AM26LS31PC# DS3650N MC3450P#
AM26LS31CN AM26LS31PC# DS8834N MC8T26AP
AM26LS32ACJ AM26LS32D# DS8835N MC8T26AP
AM26LS32ACN AM26LS32PC# DS9636ACN MC3488AP1
AM26LS32PC AM26LS32PC# ICL741CLNPA MC1741CP1
AM723PC MC1723CP ICL741CLNTY MC1741CP1
AN5150 MC34129P ICL8008CPA LM301AN
CA081AE TL081ACP ICL8008CTY LM301AN
CA081E TL081CP ICL8017CTW LM301AN
CA082AE TL082ACP ICL8017MTW LM301AN
CA082E TL082CP ICL8069CCZR LM385BZ–1.2
CA084AE TL084ACN ICL8069DCZR LM385BZ–1.2
CA084E TL084CN IP33063N MC33063AP1
CA1391E MC1391P IP34060AN MC34060AP
CA1458S MC1458CP1 IP34063N MC34063AP1
CA239AE LM239AN IP3525AN SG3525AN
CA239E LM239N IP3526N SG3526N
CA3026 CA3054 IP3527AN SG3527AN
CA3045F MC3346P LM240LAZ–18 MC78L18ACP
CA3046 MC3346P LM240LAZ–24 MC78L24ACP
CA3054 CA3054 LM240LAZ–5.0 MC78L05ACP
CA3079 CA3079 LM249N MC4741CP
CA3086F MC3346P LM2575 LM2575
CA3136A MC3346P LM258D LM258D
CA3146 MC3346P LM258M LM258D
CA339AE LM339AN LM258N LM258N
CA339E LM339N LM285Z–1.2 LM285Z–1.2
CA723CE MC1723CP LM285Z–2.5 LM285Z–2.5
CA741CS MC1741CP1 LM2901D LM2901D
CS2842AD UC2842BD1 LM2901M LM2901D
CS2843AD UC2843BD1 LM2901N LM2901N
CS2844D UC2844BD1 LM2902D LM2902D

Cross References (continued)
IP494ACJ TL594IN LM2903N LM2903N
IP494ACN TL594CN LM2903P LM2903N
IR3M03A MC34063AP1 LM2904M LM2904D
IR3M03AN MC34063AD LM2904N LM2904N
ITT3710 MC1391P LM2905N MC1455P1
ITT656 MC1413P LM2931AD–5.0 LM2931AD–5.0
L144AP LM324N LM2931AT–5.0 LM2931AT–5.0
L203 MC1413P LM2931AZ–5.0 LM2931AZ–5.0
L387 MC33267T LM2931CD LM2931CD
LF347BN LF347BN LM2931CM LM2931CD
LF347N LF347N LM2931CT LM2931CT
LF351BN MC34001BP LM2931D–5.0 LM2931D–5.0
LF351N LF351N LM2931D LM2931D–5.0
LF353AN MC34002AP LM2931T–5.0 LM2931T–5.0
LF353BN MC34002BP LM2931Z–5.0 LM2931Z–5.0
LF353D LF353D LM2935T LM2935T
LF353N LF353N LM293D LM293D
LF411CD LF411CD LM301AD LM301AD
LF412CD LF412CD LM301AM LM301AD
LF441CD LF441CD LM301AN LM301AN
LF441CN LF441CN LM301AP LM301AN
LF442CD LF442CD LM3045 MC3346P
LF442CN LF442CN LM3046N MC3346P
LF444CD LF444CD LM3054 CA3054
LF444CN LF444CN LM308AD LM308AD
LM11CLN LM11CLN LM308AN LM308AN
LM11CN LM11CN LM308P MC3356P
LM139N MC1391P LM311D LM311D
LM1489AN MC1489AP LM311M LM311D
LM1489N MC1489P LM311N LM311N
LM1496N MC1496P LM311P LM311N
LM1496M MC1496D LM3146A MC3346P
LM1889 MC1374P LM3146 MC3346P
LM1981 MC13020P LM317KC LM317T
LM201AD LM201AD LM317KD LM317T
LM201AN LM201AN LM317LD LM317LD
LM201AP LM201AN LM317LZ LM317LZ
LM211D LM211D LM317MP LM317MT
LM211M LM211D LM317P LM317T
LM224D LM224D LM317T LM317T
LM224M LM224D LM3189 MC3356P
LM224N LM224N LM320LZ–12 MC79L12ACP
LM239AN LM239AN LM320LZ–15 MC79L15ACP
LM239D LM239D LM320LZ–5.0 MC79L05ACP
LM239M LM239D LM320MP–12 MC7912CT
LM239N LM239N LM320MP–15 MC7915CT
LM240LAZ–12 MC78L12ACP LM320MP–18 MC7918CT
LM240LAZ–15 MC78L15ACP LM320MP–24 MC7924CT
LM2902M LM2902D LM340LAZ–5.0 MC78L05ACP
LM2902N LM2902N LM340LAZ–8.0 MC78L08ACP
LM2903D LM2903D LM340T–12 LM340T–12
LM2903M LM2903D LM340T–15 LM340T–15

LM320MP–5.0 MC7905CT LM348D LM348D
LM320MP–5.2 MC7905.2CT LM348M LM348D
LM320MP–6.0 MC7906CT LM349N MC4741CP
LM320MP–8.0 MC7908CT LM350T LM350T
LM320T–12 MC7912CT LM358AN LM358N
LM320T–15 MC7915CT LM358D LM358D
LM320T–5.0 MC7905CT LM358N LM358N
LM320T–5.2 MC7905.2CT LM363AN MC3450P#
LM322N MC1455P1 LM363N MC3450P#
LM323AT LM323AT LM385BZ–1.2 LM385BZ–1.2
LM323T LM323T LM385BZ–2.5 LM385BZ–2.5
LM324AD LM324AD LM385D–1.2 LM385D–1.2
LM324AN LM324AN LM385D–2.5 LM385D–2.5
LM324D LM324D LM385M–1.2 LM385D–1.2
LM324M LM324D LM385M–2.5 LM385D–2.5
LM324N LM324N LM385Z–1.2 LM385Z–1.2
LM337MP LM337MT LM385Z–2.5 LM385Z–2.5
LM337MT LM337MT LM386N MC34119P
LM337T LM337T LM3905N MC1455P1
LM339AD LM339AD LM393AN LM393AN
LM339AM LM339AD LM393D LM393D
LM339AN LM339AN LM393JG LM393N
LM339D LM339D LM393M LM393D
LM339N LM339N LM393N LM393N
LM339P LM339N LM431ACZ TL431ACLP
LM340AT–12 LM340AT–12 LM431ACM TL431ACD
LM340AT–15 LM340AT–15 LM4250CN MC1776CP1
LM340AT–5.0 LM340AT–5.0 LM555CN MC1455P1
LM340KC–12 LM340T–12 LM556CN MC3456P
LM340KC–15 LM340T–15 LM703LN MC1350P
LM340LAZ–12 MC78L12ACP LM723CN MC1723CP
LM340LAZ–18 MC78L18ACP LM741EN MC1741CP1
LM340LAZ–24 MC78L24ACP LM7805CT MC7805CT
LM340T–18 LM340T–18 LM7812CT MC7812CT
LM340T–24 LM340T–24 LM7815CT MC7815CT
LM340T–5.0 LM340T–5.0 LM78L05ACZ MC78L05ACP
LM340T–6.0 LM340T–6.0 LM78L05CZ MC78L05CP
LM340T–8.0 LM340T–8.0 LM78L08ACZ MC78L08ACP
LM341P–12 MC78M12CT LM78L08CZ MC78L08CP
LM341P–15 MC78M15CT LM78L12ACZ MC78L12ACP
LM341P–5.0 MC78M05CT LM78L15CZ MC78L15CP
LM341P–6.0 MC78M06CT LM78L18ACZ MC78L18ACP
LM341P–8.0 MC78M08CT LM78L18CZ MC78L18CP
LM342P–18 MC78M18CT LM78M05CP MC78M05CT
LM342P–24 MC78M24CT LM78M06CP MC78M06CT
LM342P–5.0 MC78M05CT LM78M12CP MC78M12CT
LM342P–6.0 MC78M06CT LM78M15CP MC78M15CT
LM342P–8.0 MC78M08CT LM7905CT MC7905CT

LM7912CT MC7912CT NE550A MC1723CP
LM7915CT MC7915CT NE555D MC1455D
LM79L05ACZ MC79L05ACP NE555V MC1455P1
LM79L12ACZ MC79L12ACP NE556D NE556D
LM79L15ACZ MC78L15ACP NE5561N MC34060AP
LM79M05CP MC79M05CT NE5234D MC33204D
LM79M12CP MC79M12CT NE5234P MC33204P
LM79M15CP MC79M15CT OP–01P MC1436P1
LM833D LM833D RC1458DN MC1458P1
LM833N LM833N RC4136DP MC3403P
LM833P LM833N RC4136N MC3403P
LM837N MC33079P RC4558DN MC4558CP1
LMC6482D MC33202D RC4558P MC4558CP1
LMC6482P MC33202P RC723DB MC1723CP
LMC6484D MC33204D RC741DN MC1741CP1
LMC6484P MC33204P RE5VL47A MC34164P–5
LP2950CZ–3.0 LP2950CZ–3.0 RH5RE30AA–T1 MC78LC30HT1
LP2950ACZ–3.0 LP2950ACZ–3.0 RH5RE50AA–T1 MC78LC50HT1
LP2950ACZ–3.3 LP2950ACZ–3.3 RN5RG30AA–TR MC78BC30NTR
LP2950ACZ–5.0 LP2950ACZ–5.0 RN5RG33AA–TR MC78BC33NTR
LP2951CM LP2951CD RN5RG40AA–TR MC78BC40NTR
LP2951ACM LP2951ACD RN5RG50AA–TR MC78BC50NTR
LP2951CM–3.0 LP2951CD–3.0 RH5RH301A–T1 MC33466H–30JT1
LP2951CM–3.3 LP2951CD–3.3 RH5RH302B–T1 MC33466H–30LT1
LP2951ACM–3.0 LP2951ACD–3.0 RH5RH331A–T1 MC33466H–33JT1
LP2951ACM–3.3 LP2951ACD–3.3 RH5RH332B–T1 MC33466H–33LT1
LP2951CN LP2951CN RH5RH501A–T1 MC33466H–50JT1
LP2951ACN LP2951ACN RH5RH502B–T1 MC33466H–50LT1
LP2951CN–3.0 LP2951CN–3.0 RH5RI301B–T1 MC33463H–30KT1
LP2951CN–3.3 LP2951CN–3.3 RH5RI302B–T1 MC33463H–30LT1
LP2951ACN–3.0 LP2951ACN–3.0 RH5RI331B–T1 MC33463H–33KT1
LP2951ACN–3.3 LP2951ACN–3.3 RH5RI332B–T1 MC33463H–33LT1
LT1083 MC34268DT RH5RI501B–T1 MC33463H–50KT1
LT1431CZ TL431BCLP RH5RI502B–T1 MC33463H–50LT1
LTC699CN8 MC34064D–5 RH5RL30AA–T1 MC78FC30HT1
LTC699IN8 MC33064D–5 RH5RL33AA–T1 MC78FC33HT1
MAX809LCPA MC34064P–5 RH5RL40AA–T1 MC78FC40HT1
MB3759 TL494CN RH5RL50AA–T1 MC78FC50HT1
N5558V MC1458P1 RH5VT09AA–T1 MC33464H–09AT1
N5723A MC1723CP RH5VT20AA–T1 MC33464H–20AT1
N5741A MC1741CP1 RH5VT27AA–T1 MC33464H–27AT1
N5741V MC1741CP1 RH5VT30AA–T1 MC33464H–30AT1
N8T26AB MC8T26AP RH5VT45AA–T1 MC33464H–45AT1
N8T26AN MC8T26AP RH5VT09CA–T1 MC33464H–09CT1
N8T26B MC8T26AP RH5VT20CA–T1 MC33464H–20CT1
N8T26N MC8T26AP RH5VT27CA–T1 MC33464H–27CT1
N8T97B MC8T97P RH5VT30CA–T1 MC33464H–30CT1
N8T97N MC8T97P RH5VT45CA–T1 MC33464H–45CT1
N8T98B MC8T98P RN5RL30AA–TR MC78FC30NTR
N8T98N MC8T98P RN5RL33AA–TR MC78FC33NTR

RN5RL40AA–TR MC78FC40NTR SG723CN MC1723CP
RN5RL50AA–TR MC78FC50NTR SG741CM MC1741CP1
RN5VD09AA–TR MC33465N–09ATR SG777CN LM308AN
RN5VD20AA–TR MC33465N–20ATR SG7805ACP MC7805ACT
RN5VD27AA–TR MC33465N–27ATR SG7805ACR MC7805ACT
RN5VD30AA–TR MC33465N–30ATR SG7805ACT MC7805ACT
RN5VD45AA–TR MC33465N–45ATR SG7805CP MC7805CT
RN5VD09CA–TR MC33465N–09CTR SG7806ACP MC7806ACT
RN5VD20CA–TR MC33465N–20CTR SG7806ACR MC7806ACT
RN5VD27CA–TR MC33465N–27CTR SG7806ACT MC7806ACT
RN5VD30CA–TR MC33465N–30CTR SG7806CP MC7806CT
RN5VD45CA–TR MC33465N–45CTR SG7806CR MC7806CT
RN5VT09AA–TR MC33464N–09ATR SG7808ACP MC7808ACT
RN5VT20AA–TR MC33464N–20ATR SG7808ACT MC7808ACT
RN5VT27AA–T4 MC33464N–27ATR SG7808CP MC7808CT
RN5VT30AA–TR MC33464N–30ATR SG7808CR MC7808CT
RN5VT45AA–TR MC33464N–45ATR SG7812ACP MC7812ACT
RN5VT09CA–TR MC33464N–09CTR SG7812ACR MC7812ACT
RN5VT20CA–TR MC33464N–20CTR SG7812ACT MC7812ACT
RN5VT27CA–TR MC33464N–27CTR SG7812CP MC7812CT
RN5VT30CA–TR MC33464N–30CTR SG7812CR MC7812CT
RN5VT45CA–TR MC33464N–45CTR SG7815ACP MC7815ACT
S–80743AN MC34164P–3 SG7815ACR MC7815ACT
SA555N MC1455BP1 SG7815ACT MC7815ACT
SAA1042 SAA1042V SG7815CP MC7815CT
SG1458M MC1458P1 SG7815CR MC7815CT
SG1496N MC1496P SG7815CT MC7815CT
SG1596J MC1496BP SG7818ACP MC7818ACT
SG201AM LM201AN SG7818ACR MC7818ACT
SG201AN LM201AN SG7818ACT MC7818ACT
SG201M LM201AN SG7818CP MC7818CT
SG201N LM201AN SG7818CR MC7818CT
SG224N LM224N SG7824ACP MC7824ACT
SG300N MC1723CP SG7824ACR MC7824ACT
SG301AM LM301AN SG7824ACT MC7824ACT
SG301AN LM301AN SG7824CP MC7824CT
SG308AM LM308AN SG7824CR MC7824CT
SG3118AM LM308AN SG7905.2CP MC7905.2CT
SG311M LM311N SG7905.2CR MC7905.2CT
SG317P LM317T SG7905.2CT MC7905.2CT
SG317R LM317T SG7905ACP MC7905ACT
SG324N LM324N SG7905ACR MC7905ACT
SG337P LM337T SG7905ACT MC7905ACT
SG337R LM337T SG7905CP MC7905CT
SG3423M MC3423P1 SG7905CR MC7905CT
SG3525AN SG3525AN SG7905CT MC7905CT
SG3526N SG3526N SG7908CP MC7908CT
SG3527AN SG3527AN SG7908CR MC7908CT
SG3561 MC34261P SG7908CT MC7908CT
SG4250CM MC1776CP1 SG7912ACP MC7912ACT
SG555CM MC1455P1 SG7912ACR MC7912ACT
SG556CN MC3456P SG7912ACT MC7912ACT

SG7912CP MC7912CT TA78L008AP MC78L08ACP
SG7912CR MC7912CT TA78L008P MC78L08CP
SG7912CT MC7912CT TA78L012AP MC78L12ACP
SG79015ACP MC7915ACT TA78L012P MC78L12CP
SG7915ACR MC7915ACT TA78L015AP MC78L15ACP
SG7915ACT MC7915ACT TA78L015P MC78L15CP
SG7915CP MC7915CT TA78L018AP MC78L18ACP
SG7915CR MC7915CT TA78L018P MC78L18CP
SG7915CT MC7915CT TA78L024AP MC78L24ACP
SG7918CP MC7918CT TA78L024P MC78L24CP
SN75LBC086 MC34055DW TA78M05P MC78M05CT
SN75121N MC3481/5P# TA78M06P MC78M06CT
SN75126N MC3481/5P# TA78M08P MC78M08CT
SN75150N MC1488P TA78M12P MC78M12CT
SN75154N MC1489P TA78M18P MC78M18CT
SN75174N MC75174BP TA78M20P MC78M20CT
SN75175N SN75175N TA78M24P MC78M24CT
SN75188N MC1488P TA79005P MC7905CT
SN75189AN MC1489AP TA79006P MC7906CT
SN75189N MC1489P TA79008P MC7908CT
SN75468N MC1413P TA79012P MC7912CT
SN76591P MC1391P TA79015P MC7915CT
SN76600P MC1350P TA79018P MC7918CT
SSS201AP LM201AN TA79024P MC7924CT
SSS301AP LM301AN TA79L005P MC79L05CP
TA7504P MC1741CP1 TA79L012P MC79L12P
TA7506P LM301AN TA79L015P MC79L15P
TA75071P MC34001P TA79L018P MC79L18P
TA75072P MC34002P TA79L024P MC79L24P
TA75074F MC34004P TB920 MC1391P
TA75339F LM339D TBA920S MC1391P
TA75339P LM339N TCF5600 TCF5600
TA75358CF LM358D TD62003P/AP MC1413P
TA75358CP LM358N TD62479P MC1374P
TA75393F LM393D TDA1085C TDA1085C
TA75393P LM393N TDA1085 TDA1085C
TA75458F MC1458D TDA1185A TDA1185A#
TA75458P MC1458CP1 TDA4817 MC34261P
TA75558P MC4558CP1 TDC1018 MC10324P
TA7555F MC1455D TDC1048 MC10319P
TA7555P MC1455P1 TK115 MC33264
TA75902F LM324D TL022CP LM358N
TA76494P TL494IN TL044CJ LM324N
TA78005AP MC7805CT TL062ACP TL062ACP
TA78006AP MC7806CT TL062CD TL062CD
TA78008AP MC7808CT TL062CP TL062CP
TA78012AP MC7812CT TL062VP TL062VP
TA78015AP MC7815CT TL064ACD TL064ACD
TA78018AP MC7818CT TL064ACN TL064ACN
TA78024AP MC7824CT TL064CD TL064CD
TA78L005AP MC78L05ACP TL064CN TL064CN
TA78L005P MC78L05CP TL064VN TL064VN

TL071ACD TL071ACD µA4136PC MC4741CP
TL071ACP TL071ACP µA431AWC TL431CP
TL071CD TL071CD µA4558TC MC4558CP1
TL071CP TL071CP µA494PC TL494CN
TL072ACD TL072ACD µA555TC MC1455P1
TL072ACP TL072ACP µA556PC MC3456P
TL072CD TL072CD µA723CN MC1723CP
TL072CP TL072CP µA723PC MC1723CP
TL074ACN TL074ACN µA741CP MC1741CP1
TL074CN TL074CN µA742DC CA3059
TL081ACD TL081ACD µA757DC MC1350P
TL081ACP TL081ACP µA757DM MC1350P
TL081CD TL081CD µA775PC LM339N
TL081CP TL081CP µA776TC MC1776CP1
TL082ACP TL082ACP µA7805CKC MC7805CT
TL082CD TL082CD µA7805UC MC7805CT
TL082CP TL082CP µA7805UV MC7805BT
TL084ACN TL084ACN µA7806CKC MC7806CT
TL084CN TL084CN µA7806UC MC7806CT
TL431CD TL431CD µA7806UV MC7806BT
TL431CLP TL431CLP µA7808CKC MC7808CT
TL431CP TL431CP µA7808UC MC7808CT
TL431ILP TL431ILP µA7808UV MC7808BT
TL431IP TL431IP µA7812CKC MC7812CT
TL494IN TL494IN µA7812UV MC7812BT
TL497CN MC34063AP1 µA7815CKC MC7815CT
TL594IN TL594IN µA7815UV MC7815BT
TL780–05CKC TL780–05CKC µA7818CKC MC7818CT
TL780–12CKC TL780–12CKC µA7818UC MC7818CT
TL780–15CKC TL780–15CKC µA7818UV MC7818BT
TL7805ACKC MC7805ACT µA7824CKC MC7824CT
TLC2272D MC33202D µA7824UC MC7824CT
TLC2272P MC33202P µA7824UV MC7824BT
TLC2274D MC33204D µA78GU1C LM317T
TLC2274P MC33204P µA78GUC LM317T
µA1391PC MC1391P µA78L05ACLP MC78L05ACP
µA1458CP MC1458CP1 µA78L05AWC MC78L05ACP
µA1458CTC MC1458CP1 µA78L05CLP MC78L05CP
µA1458P MC1458P1 µA78L05WC MC78L05CP
µA1458TC MC1458P1 µA78L08ACLP MC78L08ACP
µA2240PC MC1455P1 µA78L08AWC MC78L08ACP
µA301AT LM301AN µA78L08CLP MC78L08CP
µA3026HM CA3054 µA78L12ACLP MC78L12ACP
µA3045 MC3346P µA78L12AWC MC78L12ACP
µA3046DC MC3346P µA78L12CLP MC78L12CP
µA3054DC CA3054 µA78L12WC MC78L12CP
µA311T LM311N µA78L15ACLP MC78L15ACP
µA317UC LM317T µA78L15AWC MC78L15ACP
µA3303P MC3303P µA78L15CLP MC78L15CP
µA3403P MC3403P µA78L15WC MC78L15CP

µA78L18AWC MC78L18ACP µA79M06AUC MC79M06CT
µA78L24AWC MC78L24ACP µA79M06CKC MC79M06CT
µA78M05CKC MC78M05CT µA79M06UC MC79M06CT
µA78M05CKD MC78M05CT µA79M08AUC MC79M08CT
µA78M05UC MC78M05CT µA79M08CKC MC79M08CT
µA78M06CKC MC78M06CT µA79M08UC MC79M08CT
µA78M06CKD MC78M06CT µA79M12AUC MC79M12CT
µA78M06UC MC78M06CT µA79M12CKC MC79M12CT
µA78M08CKC MC78M08CT µA79M18AUC MC79M18CT
µA78M08CKD MC78M08CT µA79M18UC MC79M18CT
µA78M08UC MC78M08CT µA79M24AUC MC79M24CT
µA78M12CKC MC78M12CT µA79M24CKC MC79M24CT
µA78M12CKD MC78M12CT µA79M24UC MC79M24CT
µA78M12UC MC78M12CT µA9636ATC MC3488AP1
µA78M15CKC MC78M15CT UAA1016B UAA1016B
µA78M15CKD MC78M15CT UC2823DW MC33023DW
µA78M15UC MC78M15CT UC2823N MC33023P
µA78M18UC MC78M18CT UC2823Q MC33023FN
µA78M20CKC MC78M20CT UC2825DW MC33025DW
µA78M20CKD MC78M20CT UC2825N MC33025P
µA78M20UC MC78M20CT UC2825Q MC33025FN
µA78M24CKC MC78M24CT UC2842AD UC2842AD
µA78M24CKD MC78M24CT UC2842AN UC2842AN
µA78M24UC MC78M24CT UC2842BD UC2842BD
µA78MGT2C LM317T UC2842BN UC2842BN
µA78MGU1C LM317T UC2842D UC2842AD
µA78MGUC LM317MT UC2842N UC2842AN
µA78S40PC µA78S40PC UC2843AD UC2843AD
µA78S40PV µA78S40PV UC2843AN UC2843AN
µA7905.2CKC MC7905.2CT UC2843BD UC2843BD
µA7905CKC MC7905CT UC2843BN UC2843BN
µA7905UC MC7905CT UC2843D UC2843AD
µA7906CKC MC7906CT UC2843N UC2843AN
µA7906UC MC7906CT UC2844BD UC2844BD
µA7908CKC MC7908CT UC2844BN UC2844BN
µA7912CKC MC7912CT UC2844D UC2844D
µA7912UC MC7912CT UC2844N UC2844N
µA7915CKC MC7915CT UC2845BD UC2845BD
µA7915UC MC7915CT UC2845BN UC2845BN
µA7918CKC MC7918CT UC2845D UC2845D
µA7918UC MC7918CT UC2845N UC2845N
µA7924CKC MC7924CT UC317T LM317T
µA7924UC MC7924CT UC337T LM337T
µA798TC MC3458P1 UC3525AN SG3525AN
µA79L05AWC MC79L05ACP UC3526N SG3526N
µA79L05WC MC79L05CP UC3527AN SG3527AN
µA79L12AWC MC79L12ACP UC3823DW MC34023DW
µA79L12WC MC79L12CP UC3823N MC34023P
µA79L15AWC MC79L15ACP UC3823Q MC34023FN
µA79L15WC MC79L15CP UC3825DW MC34025DW
µA79M05AUC MC79M05CT UC3825N MC34025P
µA79M05CKC MC79M05CT UC3825Q MC34025FN

UC3842AD UC3842AD UC3845N UC3845N
UC3842AN UC3842AN UC494ACN TL594CN
UC3842BD UC3842BD UC494CN TL494CN
UC3842BN UC3842BN UCN5816A MC34142FN
UC3842D UC3842AD ULN2003A MC1413
UC3842N UC3842AN ULN2004A MC1416
UC3843AD UC3843AD ULN2068BB ULN2068B#
UC3843AN UC3843AN ULN2068NE ULN2068B#
UC3843BD UC3843BD ULN2151H MC1741CP1
UC3843BN UC3843BN ULN2151M MC1741CP1
UC3843D UC3843AD ULN2803A ULN2803A
UC3843N UC3843AN ULN2804A ULN2804A
UC3844BD UC3844BD ULN8126A SG3526N
UC3844BN UC3844BN ULS2151M MC1741CP1
UC3844D UC3844D ULX8161M MC34060AP
UC3844N UC3844N UPD6950C MC10319P
UC3845BD UC3845BD UVC3101 MC10319P
UC3845BN UC3845BN XR082CP TL082CP
UC3845D UC3845D XR084CP TL084CN

Amplifiers and Comparators
In Brief . . .
For over two decades, Motorola has continually refined Page
and updated integrated circuit technologies, analog circuit Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
design techniques and processes in response to the needs Single . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
of the marketplace. The enhanced performance of newer Dual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
operational amplifiers and comparators has come through Quad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
innovative application of these technologies, designs and High Frequency Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
processes. Some early designs are still available but are AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
giving way to the new, higher performance operational Miscellaneous Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
amplifier and comparator circuits. Motorola has pioneered in Bipolar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
JFET inputs, low temperature coefficient input stages, Miller CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
loop compensation, all NPN output stages, dual–doublet Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
frequency compensation and analog “in–the–package” Single . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
trimming of resistors to produce superior high performance Dual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
operational amplifiers and comparators, operating in many Quad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
cases from a single supply with low input offset, low noise, Package Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
low power, high output swing, high slew rate and high Device Listing and Related Literature . . . . . . . . . . . . . . . 2–9
gain–bandwidth product at reasonable cost to the customer.
Present day operational amplifiers and comparators find
applications in all market segments including motor controls,
instrumentation, aerospace, automotive, telecommunications,
medical, and consumer products.

Motorola offers a broad line of bipolar operational and quad monolithic devices in a variety of temperature
amplifiers to meet a wide range of applications. From low–cost ranges and package styles. Most devices may be obtained in
industry–standard types to high precision circuits, the span unencapsulated ‘‘chip’’ form as well. For price and delivery
encompasses a large range of performance capabilities. information on chips, please contact your Motorola Sales
These Analog integrated circuits are available as single, dual Representative or Distributor.
Table 1. Single Operational Amplifiers

Supply
BW SR
Voltage
IIB VIO TCVIO IIO Avol (Av = 1) (Av = 1)
(V)
(µA) (mV) (µV/°C)
(µV/ C) (nA) (V/mV) (MHz) (V/µs) Suffix/
Device Max Max Typ Max Min Typ Typ Min Max Description Package
Noncompensated
Commercial Temperature Range (0°C to +70°C)
LM301A 0.25 7.5 10 50 25 1.0 0.5 ±3.0 ±18 General Purpose N/626, D/751
LM308A 7.0 0.5 5.0 1.0 80 1.0 0.3 ±3.0 ±18 Precision N/626, D/751
Industrial Temperature Range (– 25°C to +85°C)
LM201A 0.075 2.0 10 10 50 1.0 0.5 ±3.0 ±22 General Purpose N/626, D/751
Internally Compensated
LF351 200 pA 10 10 100 pA 25 4.0 13 ±5.0 ±18 JFET Input N/626, D/751
LF411C 200 pA 2.0 10 100 pA 25 8.0 25 +5.0 ±22 JFET Input, Low Offset, N/626, D/751
Low Drift
LF441C 100 pA 5.0 10 50 pA 25 2.0 6.0 ±5.0 ±18 Low Power, JFET Input N/626, D/751
LM11C 100 pA 0.6 2.0 10 pA 250 1.0 0.3 ±3.0 ±20 Precision N/626
LM11CL 200 pA 5.0 3.0 25 pA 50 1.0 0.3 ±3.0 ±20 Precision N/626
MC1436, C 0.04 10 12 10 70 1.0 2.0 ±15 ±34 High Voltage P1/626, D/751
MC1741C 0.5 6.0 15 200 20 1.0 0.5 ±3.0 ±18 General Purpose P1/626, D/751
MC1776C 0.003 6.0 15 3.0 100 1.0 0.2 ±1.2 ±18 µPower, Programmable P1/626, D/751
MC3476 0.05 6.0 15 25 50 1.0 0.2 ±1.5 ±18 Low Cost, P1/626
µPower, Programmable
MC34001 200 pA 10 10 100 pA 25 4.0 13 ±5.0 ±18 JFET Input P/626, D/751
MC34001B 200 pA 5.0 10 100 pA 50 4.0 13 ±5.0 ±18 JFET Input P/626, D/751
MC34071 0.5 5.0 10 75 25 4.5 10 +3.0 +44 High Performance P/626, D/751
MC34071A 500 nA 3.0 10 50 50 4.5 10 +3.0 +44 Single Supply P/626, D/751
MC34080B 200 pA 1.0 10 100 pA 25 16 55 ±5.0 ±22 Decompensated P/626, D/751
MC34081B 200 pA 1.0 10 100 pA 25 8.0 30 ±5.0 ±22 High Speed, JFET Input P/626, D/751
MC34181 0.1 nA 2.0 10 0.05 25 4.0 10 ±2.5 ±18 Low Power, JFET Input P/626
TL071AC 200 pA 6.0 10 50 pA 50 4.0 13 ±5.0 ±18 Low Noise, JFET Input P/626, D/751
TL071C 200 pA 10 10 50 pA 25 4.0 13 ±5.0 ±18 Low Noise, JFET Input P/626, D/751
TL081AC 200 pA 6.0 10 100 pA 50 4.0 13 ±5.0 ±18 JFET Input P/626, D/751
TL081C 400 pA 15 10 200 pA 25 4.0 13 ±5.0 ±18 JFET Input P/626, D/751
Automotive Temperature Range (– 40°C to +85°C)
MC33171 0.1 4.5 10 20 50 1.8 2.1 +3.0 +44 Low Power, Single Supply P/626, D/751
MC33181 0.1 nA 2.0 10 0.05 25 4.0 10 ±2.5 ±18 Low Power, JFET Input P/626, D/751
Extended Automotive Temperature Range (– 40°C to +105°C)
MC33201 250 nA 9.0 2.0 100 50 2.2 1.0 ±0.9 ±6.0 Low V Rail–to–Rail P/626, D/751
Military Temperature Range (– 55°C to +125°C)
MC33201 400 nA 9.0 2.0 200 50 2.2 1.0 ±0.9 ±6.0 Low V Rail–to–Rail P/626, D/751

Table 2. Dual Operational Amplifiers
Supply
BW SR
Voltage
(V)
(µA) (mV) (µV/°C)
(µV/ C) (nA) (V/mV) (MHz) (V/µs) Suffix/
LF353 200 pA 10 10 100 pA 25 4.0 13 ±5.0 ±18 JFET Input N/626, D/751
LF412C 200 pA 3.0 10 100 pA 25 4.0 13 +5.0 ±18 JFET Input, Low Offset, N/626, D/751
Low Drift
LF442C 100 pA 5.0 10 50 pA 25 2.0 6.0 ±5.0 ±18 Low Power, JFET Input N/626
LM358 0.25 6.0 7.0 50 25 1.0 0.6 ±1.5 ±18 Single Supply, N/626, D/751
+3.0 +36 Low Power Consumption
LM833 1.0 5.0 2.0 200 31.6 15 7.0 +2.5 ±18 Low Noise, Audio N/626, D/751
MC/MCT1458 0.5 6.0 10 200 20 1.1 0.8 ±3.0 ±18 Dual MC1741 P1/626,
D/751
MC1458C 0.7 10 10 300 20 1.1 0.8 ±3.0 ±18 General Purpose P1/626,
D/751
MC3458 0.5 10 7.0 50 20 1.0 0.6 ±1.5 ±18 Split Supplies, P1/626,
+3.0 +36 Single Supply, D/751
Low Crossover Distortion
MC4558AC 0.5 5.0 10 200 50 2.8 1.6 ±3.0 ±22 High Frequency P1/626
MC/MCT4558C 0.5 6.0 10 200 20 2.8 1.6 ±3.0 ±18 High Frequency P1/626,
D/751
MC34002 100 pA 10 10 100 pA 25 4.0 13 ±5.0 ±18 JFET Input P/626, D/751
MC34002B 100 pA 5.0 10 70 pA 25 4.0 13 ±5.0 ±18 JFET Input P/626, D/751
MC34082 200 pA 3.0 10 100 pA 25 8.0 30 ±5.0 ±22 High Speed, JFET Input P/626
MC34083B 200 pA 3.0 10 100 pA 25 16 55 ±5.0 ±22 Decompensated P/626
TL062AC 200 pA 6.0 10 100 pA 4.0 2.0 6.0 ±2.5 ±18 Low Power, JFET Input P/626, D/751
TL062C 200 pA 15 10 200 pA 4.0 2.0 6.0 ±2.5 ±18 Low Power, JFET Input P/626, D/751
TL072AC 200 pA 6.0 10 50 pA 50 4.0 13 ±5.0 ±18 Low Noise, JFET Input P/626, D/751
TL072C 200 pA 10 10 50 pA 25 4.0 13 ±5.0 ±18 Low Noise, JFET Input P/626, D/751
TL082AC 200 pA 6.0 10 100 pA 50 4.0 13 ±5.0 ±18 JFET Input P/626, D/751
TL082C 400 pA 15 10 200 pA 25 4.0 13 ±5.0 ±18 JFET Input P/626, D/751
LM258 0.15 5.0 10 30 50 1.0 0.6 ±1.5 ±18 Split or Single Supply N/626, D/751
+3.0 +36 Op Amp
MC3358 5.0 8.0 10 75 20 1.0 0.6 ±1.5 ±18 Split or Single Supply P1/626
+3.0 +36
MC33076 0.5 4.0 2.0 70 25 7.4 2.6 ±2.0 ±18 High Output Current P1/626,
P2/648C,
D/751
MC33077 1.0 1.0 2.0 180 150 37 11 ±2.5 ±18 Low Noise P/626, D/751
MC33078 750 nA 2.0 2.0 150 31.6 16 7.0 ±5.0 ±18 Low Noise N/626, D/751
MC33102 P/626, D/751
(Awake) 600 nA 3.0 1.0 60 25 4.6 1.7 ±2.5 ±18 Sleep–Mode
(Sleep) 60 nA 3.0 1.0 6.0 15 0.3 0.1 ±2.5 ±18 Micropower
MC33172 0.10 4.5 10 20 50 1.8 2.1 +3.0 +44 Low Power, Single P/626, D/751
Supply
MC33178 0.5 3.0 2.0 50 50 5.0 2.0 ±2.0 ±18 High Output Current P/626, D/751
MC33272A 650 nA 1.0 0.56 25 nA 31.6 5.5 11.5 ±1.5 ±18 High Performance P/626, D/751
MC33282 100 pA 200 µV 5.0 50 pA 50 30 12 ±2.5 ±18 Low Input, Offset JFET P/626, D/751
TL062V 200 pA 6.0 10 100 pA 4.0 2.0 6.0 ±2.5 ±18 Low Power, JFET Input P/626, D/751

Table 2. Dual Operational Amplifiers (continued)
Supply
BW SR
Voltage
(V)
(µA) (mV) (µV/°C) (nA) (V/mV) (MHz) (V/µs) Suffix/
MC33202 250 nA 11 2.0 100 50 2.2 1.0 ±0.9 ±6.0 Low V Rail–to–Rail P/626, D/751
MC33206 Rail–to–Rail P/646,
with Enable D/751A
LM2904 0.25 10 7.0 50 100 1.0 0.6 ±1.5 ±13 Split or Single Supply N/626, D/751
typ +3.0 +26
TCA0372 500 nA 15 20 50 30 1.1 1.4 +5.0 +36 Power Op Amp, DP2/648,
Single Supply DW/751G
LM2904V 0.25 13 7.0 50 100 1.0 0.6 ±1.5 ±13 Split or Single Supply N/626, D/751
typ +3.0 +26
MC33202 400 pA 11 2.0 200 pA 50 2.2 1.0 ±0.9 ±6.0 Low V Rail–to–Rail P/626, D/751
Table 3. Quad Operational Amplifiers

BW SR Supply
IIB VIO TCVIO IIO Avol (Av = 1) (Av = 1) Voltage
(µA))
(µ ((mV)) (µV/°C))
(µ ((nA)) ((V/mV)) (MHz) (V/µs) (V) Suffix/
LF347 200 pA 10 10 100 pA 25 4.0 13 ±5.0 ±18 JFET Input N/646
LF347B 200 pA 5.0 10 100 pA 50 4.0 13 ±5.0 ±18 JFET Input N/646
LF444C 100 pA 10 10 50 pA 25 2.0 6.0 ±5.0 ±18 Low Power, JFET Input N/646, D/751A
LM324, A 0.25 6.0 7.0 50 25 1.0 0.6 ±1.5 ±16 Low Power N/646, D/751A
+3.0 +32 Consumption
LM348 0.2 6.0 – 50 25 1.0 0.5 ±3.0 ±18 Quad MC1741 D/751A
LM3900 +3.0 +36
MC3403 0.5 10 7.0 50 20 1.0 0.6 ±1.5 ±18 No Crossover P/646, D/751A
+3.0 +36 Distortion
MC4741C 0.5 6.0 15 200 20 1.0 0.5 ±3.0 ±18 Quad MC1741 P/646, D/751A
MC34004 200 pA 10 10 100 pA 25 4.0 13 ±5.0 ±18 JFET Input P/646
MC34004B 200 pA 5.0 10 100 pA 50 4.0 13 ±5.0 ±18 JFET Input P/646
MC34074 0.5 5.0 10 75 25 4.5 10 +3.0 +44 High Performance P/646, D/751A
MC34074A 500 nA 3.0 10 50 50 4.5 10 +3.0 +44 Single Supply P/646, D/751A
MC34084 200 pA 12 10 100 pA 25 8.0 30 ±5.0 ±22 High Speed, JFET Input P/646,
DW/751G
MC34085B 200 pA 12 10 100 pA 25 16 55 ±5.0 ±22 Decompensated P/646,
DW/751G
MC34184 0.1 nA 10 10 0.05 25 4.0 10 ±2.5 ±18 Low Power, JFET Input P/646, D/751A
TL064AC 200 pA 6.0 10 100 pA 4.0 2.0 6.0 ±2.5 ±18 Low Power, JFET Input N/646, D/751A
TL064C 200 pA 15 10 200 pA 4.0 2.0 6.0 ±2.5 ±18 Low Power, JFET Input N/646, D/751A
TL074AC 200 pA 6.0 10 50 pA 50 4.0 13 ±5.0 ±18 Low Noise, JFET Input N/646
TL074C 200 pA 10 10 50 pA 25 4.0 13 ±5.0 ±18 Low Noise, JFET Input N/646
TL084AC 200 pA 6.0 10 100 pA 50 4.0 13 ±5.0 ±18 JFET Input N/646
TL084C 400 pA 15 10 200 pA 25 4.0 13 ±5.0 ±18 JFET Input N/646
LM224, A 0.15 5.0 7.0 30 50 1.0 0.6 ±1.5 ±16 Split Supplies or N/646, D/751A
+3.0 +32 Single Supply
MC3301/ 0.3 – – – 1.0 4.0 0.6 ±2.0 ±15 Norton Input P/646
LM2900 +4.0 +28 N/646
MC3303 0.5 8.0 10 75 20 1.0 0.6 ±1.5 ±18 Differential P/646, D/751A
+3.0 +36 General Purpose

Table 3. Quad Operational Amplifiers (continued)
BW SR Supply
IIB VIO TCVIO IIO Avol (Av = 1) (Av = 1) Voltage
(µA) (mV) (µV/°C) (nA) (V/mV) (MHz) (V/µs) (V) Suffix/
MC33074 0.5 4.5 10 75 25 4.5 10 +3.0 +44 High Performance, P/646, D/751A
Single Supply
MC33074A 500 nA 3.0 10 50 50 4.5 10 +3.0 +44 High Performance P/646, D/751A
MC33079 750 nA 2.5 2.0 150 31.6 9.0 7.0 ±5.0 ±18 Low Noise N/646, D/751A
MC33174 0.1 4.5 10 20 50 1.8 2.1 +3.0 +44 Low Power, Single P/646, D/751A
Supply
MC33179 0.5 3.0 2.0 50 50 5.0 2.0 ±2.0 ±18 High Output Current P/646, D/751A
MC33184 0.1 nA 10 10 0.05 25 4.0 10 ±2.5 ±18 Low Power, JFET Input P/646, D/751A
MC33274A 650 nA 1.0 0.56 25 nA 31.6 5.5 11.5 ±1.5 ±18 High Performance P/646, D/751A
MC33284 100 pA 2.0 5.0 50 pA 50 30 12 ±2.5 ±18 Low Input, Offset JFET P/646, D/751A
TL064V 200 pA 9.0 10 100 pA 4.0 2.0 6.0 ±2.5 ±18 Low Power, JFET Input N/646, D/751A
MC33204 250 nA 13 2.0 100 50 2.2 1.0 ±0.9 ±6.0 Low V Rail–to–Rail P/646, D/751A
MC33207 50 2.2 ±0.9 ±6.0 Rail–to–Rail with Enable P/648, D/751B
MC33304 25 3.0 +1.8 +12 Sleepmode, Rail–to–Rail P/646, D/751A
LM2902 0.5 10 – 50 15 1.0 0.6 ±1.5 ±13 Differential Low Power N/646, D/751A
+3.0 +26
LM2902V 0.5 13 – 50 15 1.0 0.6 ±1.5 ±13 Differential Low Power N/646, D/751A
+3.0 +26
MC33204 400 pA 13 2.0 200 pA 50 2.2 1.0 ±0.9 ±6.0 Low V Rail–to–Rail P/646, D/751A
High Frequency Amplifiers

A variety of high frequency circuits with features ranging Amplifiers. These parts are recommended for applications
from low cost simplicity to multifunction versatility marks up through 70 MHz. The best high frequency performance
Motorola’s line of integrated amplifiers. Devices described may be obtained by using the physically smaller SOIC
here are intended for industrial and communications version (shorter leads) – MC1350D. There are currently no
applications. For devices especially dedicated to consumer other RF ICs like these, because other manufacturers have
products, i.e., TV and entertainment radio. (See the dropped their copies. Applications include variable gain
Consumer Electronics Circuits section.) video and instrumentation amplifiers, IF (Intermediate
Frequency) amplifiers for radio and TV receivers, and
AGC Amplifiers transmitter power output control. Many uses will be found in
medical instrumentation, remote monitoring, video/graphics
MC1490/MC1350 Family Wideband processing, and a variety of communications equipment.
General Purpose Amplifiers The family of parts using the same basic die (identical circuit
with slightly different test parameters) is listed in the
The MC1490 and MC1350 family are basic building
following table.
blocks – AGC (Automatic Gain Controlled) RF/Video
Table 4. High Frequency Amplifier Specifications

Operating AV Bandwidth VCC/VEE
Temperature Range (dB) @ MHz (Vdc)
Suffix/
– 40° to +85°C 0° to +70°C Typical Minimum Maximum Package
– MC1350 50 45 +6.0 +18 P/626, D/751
MC1490 – 50 10 P/626
45 60
35 100

Miscellaneous Amplifiers
Motorola provides several Bipolar and CMOS special range from low power CMOS programmable amplifiers and
purpose amplifiers which fill specific needs. These devices comparators to variable–gain bipolar power amplifiers.
MC3405
Dual Operational Amplifier and Output 1 1 14 Output 4
Dual Voltage Comparator Comp Op
1 Amp 1
2 13
+
This device contains two Differential Input Operational Inputs 1 1 4 Inputs 4
+
3 12
Amplifiers and two Comparators; each set capable of single
supply operation. This operational amplifier–comparator VCC 4 Comp Op 11 VEE/Gnd
circuit will find its applications as a general purpose product for 2 Amp 2
automotive circuits and as an industrial ‘‘building block.’’ 5 + 10
Inputs 2 2 3 Inputs 3
+
6 9
Output 2 7 8 Output 3
Table 5. Bipolar
IIB VIO IIO Avol Response Supply Voltage
(µA) (mV) (nA) (V/mV) (µs) S ffix/
Suffix/
Device Max Max Max Min Typ Single Dual Package
MC3405 0.5 10 50 20 1.3 3.0 to 36 ±1.5 to ±18 P/646
MC14573
Quad Programmable Operational Amplifier
MC14575
Dual Programmable Operational Amplifier and Dual Programmable Comparator
MC14576B/MC14577B
Dual Video Amplifiers
Table 6. CMOS
Quantity Single Supply Dual Supply Suffix/
Function Per Package Voltage Range Voltage Range Frequency Range Device Package
Operational Amplifiers 4 3.0 to 15 V ±1.5 to ±7.5 V DC to 1.0 MHz MC14573 P/648, D/751B
Operational Amplifiers 2 and 2 3.0 to 15 V ±1.5 to ±7.5 V DC to 1.0 MHz MC14575 P/648, D/751B
and Comparators
Video Amplifiers 2 5.0 to 12 V(1) ±2.5 to ±6.0 V(2) Up to 10 MHz MC14576C P/626, F/904
MC14577C
(1) 5.0 to 10 V for surface mount package.
(2) ±2.5 to ±5.0 V for surface mount package.

Comparators
Table 7. Single Comparators
IIB VIO IIO AV IIO Response Supply Temperature
(µA) (mV) (µA) (V/V) (mA) Time Voltage Range S ffix/
Suffix/
Device Max Max Max Typ Min (ns) (V) Description (°C) Package
Bipolar
LM211 0.1 3.0 0.01 200 k 8.0 200 +15, –15 With strobe, will operate –25 to +85 D/751
LM311 0.25 7.5 0.05 from single supply 0 to +70 N/626,
D/751
CMOS
MC14578 1.0 pA 50 – – 1.1 – 3.5 to 14 Requires only 10 µA from –30 to +70 P/648,
single–ended supply D/751B
Table 8. Dual Comparators

Suffix/
Bipolar
LM293 0.25 5.0 0.05 200 k 6.0 1300 ±1.5 to ±18 Designed for single or split –25 to +85 N/626,
LM393 5.0 1300 or su ly operation,
supply o eration, input
in ut 0 to +70 D/751
LM393A 2.0 1300 3.0 to 36 common mode includes 0 to +70
LM2903 70
7.0 1500 ground (negative supply)
su ly) –40 to +105
LM2903V 7.0 1500 –40 to +125
MC3405 0.5 10 0.05 200 k 6.0 1300 ±1.5 to ±7.5 This device contains 2 op 0 to +70 P/646
or am
amps s and 2 comparators
com arators in
3.0 to 15 a single package
CMOS
MC14575 0.001 30 0.0001 2.0 k 3.0 1000 ±1.5 to ±7.5 This device contains 2 op –40 to +85 P/648,
or amps and 2 comparators in D/751B
3.0 to 15 a single package
Table 9. Quad Comparators

Suffix/
Bipolar
LM239 0.25 5.0 0.05 200 k 6.0 1300 ±1.5 to ±18 Designed for single or split –25 to +85 N/646,
LM239A 2.0 200 k or supply operation, input –25 to +85 D/751A
LM339 5.0 200 k 3 0 to 36
3.0 common mode d iincludes
l d 0 to +70
LM339A 2.0 200 k ground
d (negative
( ti supply)l ) 0 to +70
LM2901 7.0 100 k –40 to +85
LM2901V 7.0 100 k –40 to +125
MC3302 0.5 20 0.5 100 k –40 to +85 P/646
MC3431 40 10 1.0 Typ 1.2 k 16 33 +5.0, –5.0 High speed comparator/ 0 to +70 P/648
sense am lifier
amplifier
MC3432 6.0 40
MC3433 10 40
CMOS
MC14574 0.001 30 0.0001 2.0 k 3.0 1000 ±1.5 to ±7.5 Externally programmable –40 to +85 P/648,
or power dissipation with 1 or D/751B
3.0 to 15 2 resistors

Amplifiers and Comparators Package Overview
CASE 626 CASE 646 CASE 648, 648C

N, P, P1 SUFFIX N, P SUFFIX DP2, P, P2 SUFFIX
CASE 751 CASE 751A CASE 751B

D SUFFIX D SUFFIX D SUFFIX
CASE 751G CASE 904

DW SUFFIX F SUFFIX

Device Listing and Related Literature
Amplifiers
Device Function Page
LF347, B, LF351, LF353 JFET Input Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
LF411C, LF412C Low Offset, Low Drift JFET Input Operational Amplifiers . . . . . . . . . . . . . . 2–13
LF441C, LF442C, LF444C Low Power JFET Input Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 2–17
LM11C, CL Precision Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
LM301A, LM201A Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
LM308A Precision Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34
LM324, LM324A, Quad Low Power Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45
LM224, LM2902, V
LM348 Differential Input Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–56
LM358, LM258, LM2904, V Dual Low Power Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–62
LM833 Dual Low Noise, Audio Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–73
MC1436, C High Voltage, Internally Compensated Operational Amplifiers . . . . . . . . . 2–79
MC1458, C Internally Compensated, High Performance Dual Operational
Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–84
MCT1458, C Internally Compensated, High Performance Dual Operational
Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–89
MC1490 RF/IF/Audio Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–92
MC1741C Internally Compensated, High Performance Operational Amplifier . . . . . . 2–99
MC1776C Micropower Programmable Operational Amplifier . . . . . . . . . . . . . . . . . . . . 2–104
MC3301, LM2900, LM3900 Quad Single Supply Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . 2–113
MC3403, MC3303 Quad Low Power Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–123
MC3458, MC3358 Dual, Low Power Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–137
MC3476 Low Cost Programmable Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . 2–144
MC4558AC, MC4558C Dual Wide Bandwidth Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 2–149
MCT4558C Dual Wide Bandwidth Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 2–153
MC4741C Differential Input Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–156
MC33076 Dual High Output Current, Low Power, Low Noise Bipolar
Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–161
MC33077 Dual, Low Noise Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–169
MC33078, MC33079 Dual/Quad Low Noise Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 2–180
MC33102 Sleep–Mode Two–State, Micropower Operational Amplifier . . . . . . . . . . 2–189
MC33171, MC33172, Low Power, Single Supply Operational Amplifiers . . . . . . . . . . . . . . . . . . . . 2–201
MC33174
MC33178, MC33179 High Output Current Low Power, Low Noise Bipolar
Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–208
MC33201, MC33202, Rail–to–Rail Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–218
MC33204
MC33206, MC33207 Rail–to–Rail Operational Amplifiers with Enable Feature . . . . . . . . . . . . . . 2–227
MC33272A, MC33274A Single Supply, High Slew Rate Low Input Offset Voltage, Bipolar
MC33282, MC33284 Low Input Offset, High Slew Rate, Wide Bandwidth, JFET Input
MC33304 Low Voltage Rail–to–Rail SLEEPMODE Operational Amplifier . . . . . . . 2–254
MC34001, B, MC34002, B, JFET Input Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–265
MC34004, B
MC34071, 2, 4, A, High Slew Rate, Wide Bandwidth, Single Supply Operational
MC33071, 2, 4, A Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–272
MC34080 thru MC34085 High Slew Rate, Wide Bandwidth, JFET Input Operational Amplifiers . . . 2–288
MC34181, 2, 4, Low Power, High Slew Rate, Wide Bandwidth, JFET Input
MC33181, 2, 4 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–299

Amplifiers
TCA0372 Dual Power Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–308
TL062, TL064 Low Power JFET Input Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 2–312
TL071C, AC, TL072C, AC, Low Noise, JFET Input Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 2–319
TL074C, AC
TL081C, AC, TL082C, AC, JFET Input Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–325
TL084C, AC
Comparators
LM311, LM211 Highly Flexible Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39
LM339, A, LM239, A, Quad Single Supply Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52
LM2901, V, MC3302
LM393, A, LM293, LM2903, V Low Offset Voltage Dual Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–68
MC3405 Dual Operational Amplifier and Dual Comparator . . . . . . . . . . . . . . . . . . . . 2–129
ADDENDUM
Operational Amplifier Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–331
RELATED APPLICATION NOTES

App Note Title Related Device
AN587 Analysis and Design of the Op Amp Current Source . . . . . . . . . . . . . . . MC1741C

LF347, B
LF351
LF353
JFET Input
FAMILY OF JFET
These low cost JFET input operational amplifiers combine two
state–of–the–art analog technologies on a single monolithic integrated OPERATIONAL AMPLIFIERS
circuit. Each internally compensated operational amplifier has well matched
high voltage JFET input devices for low input offset voltage. The JFET
technology provides wide bandwidths and fast slew rates with low input bias N SUFFIX
currents, input offset currents, and supply currents. PLASTIC PACKAGE
These devices are available in single, dual and quad operational CASE 626
amplifiers which are pin–compatible with the industry standard MC1741, 8
MC1458, and the MC3403/LM324 bipolar devices. 1

D SUFFIX
• Input Offset Voltage of 5.0 mV Max (LF347B) PLASTIC PACKAGE
• Low Input Bias Current: 50 pA 8 CASE 751
(SO–8)
• Low Input Noise Voltage: 16 nV/ ǸHz
1
• Wide Gain Bandwidth: 4.0 MHz PIN CONNECTIONS

• High Slew Rate: 13V/µs Offset Null 1 8 NC
• Low Supply Current: 1.8 mA per Amplifier Invt Input 2 – 7 VCC

LF351
• +
Noninvt Input 3 6 Output (Top View)
High Input Impedance: 1012 Ω
VEE 4 5 Offset Null
• High Common Mode and Supply Voltage Rejection Ratios: 100 dB
Output A 1 8 VCC
2
– 7 Output B LF353
Inputs A
3 A – 6 (Top View)
+ Inputs B
VEE 4 B 5
+
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC +18 V N SUFFIX
VEE –18 PLASTIC PACKAGE
CASE 646
Differential Input Voltage VID ±30 V
14
Input Voltage Range (Note 1) VIDR ±15 V
1
Output Short Circuit Duration (Note 2) tSC Continuous PIN CONNECTIONS
Power Dissipation at TA = +25°C PD 900 mW
Out 1 1 14 Out 4
Derate above TA =+25°C 1/θJA 10 mW/°C
2
– – 13
Operating Ambient Temperature Range TA 0 to +70 °C Inputs 1 Inputs 4
3 1 4 12
Operating Junction Temperature Range TJ 115 °C + +
VCC 4 11 VEE
Storage Temperature Range Tstg – 65 to °C + +
+150 5 10
Inputs 2 Inputs 3
6 2 3 9
NOTES: 1. Unless otherwise specified, the absolute maximum negative input voltage is – –
limited to the negative power supply. Out 2 7 8 Out 3
2. Any amplifier output can be shorted to ground indefinitely. However, if more than
one amplifier output is shorted simultaneously, maximum junction temperature
rating may be exceeded. (Top View)
ORDERING INFORMATION
Operating
Device Function Temperature Range Package
LF351D Single SO–8
LF351N Single Plastic DIP
LF353D Dual SO–8

TA = 0° to +70°C
LF353N Dual Plastic DIP
LF347BN Quad Plastic DIP

LF347N Quad Plastic DIP

LF347, B LF351 LF353
ELECTRICAL CHARACTERISTICS (VCC = +15 VEE = –15 V, TA = 25°C, unless otherwise noted.)
LF347B LF347, LF351, LF353
Characteristic Symbol Min Typ Max Min Typ Max Unit
Input Offset Voltage (RS ≤ 10 k, VCM = 0) VIO mV
TA = +25°C – 1.0 5.0 – 5.0 10
0°C ≤ TA ≤ +70°C – – 8.0 – – 13
Avg. Temperature Coefficient of Input Offset Voltage ∆VIO/∆T µV/°C
RS ≤ 10 k, 0°C ≤ TA ≤ +70°C – 10 – – 10 –
Input Offset Current (VCM = 0, Note 3) IIO
TA = +25°C – 25 100 – 25 100 pA
0°C ≤ TA ≤ +70°C – – 4.0 – – 4.0 nA
Input Bias Current (VCM = 0, Note 3) IIB
TA = +25°C – 50 200 – 50 200 pA
0°C ≤ TA ≤ +70°C – – 8.0 – – 8.0 nA
Input Resistance ri – 1012 – – 1012 – Ω
Common Mode Input Voltage Range VICR ±11 +15 – ±11 +15 – V
–12 –12
Large–Signal Voltage Gain (VO = ±10 V, RL = 2.0 k) AVOL V/mV
TA = +25°C 50 100 – 25 100 –
0°C ≤ TA ≤ +70°C 25 – – 15 – –
Output Voltage Swing (RL = 10 k) VO ±12 ±14 – ±12 ±14 – V
Common Mode Rejection (RS ≤ 10 k) CMR 80 100 – 70 100 – dB
Supply Voltage Rejection (RS ≤ 10 k) PSRR 80 100 – 70 100 – dB
Supply Current ID mA
LF347 – 7.2 11 – 7.2 11
LF351 – – – – 1.8 3.4
LF353 – – – – 3.6 6.5
Short Circuit Current ISC – 25 – – 25 – mA
Slew Rate (AV = +1) SR – 13 – – 13 – V/µs
Gain–Bandwidth Product BWp – 4.0 – – 4.0 – MHz
Equivalent Input Noise Voltage en – 24 – – 24 – nV/ √ Hz
(RS = 100 Ω, f = 1000 Hz)
Equivalent Input Noise Current (f = 1000 Hz) in – 0.01 – – 0.01 – pA/ √ Hz
Channel Separation (LF347, LF353) – – –120 – – –120 – dB
1.0 Hz ≤ f ≤ 20 kHz (Input Referred)
For Typical Characteristic Performance Curves, refer to MC34001, 34002, 34004 data sheet.
NOTE: 3. Input bias currents of JFET input op amps approximately double for every 10°C rise in junction temperature. To maintain junction temperatures as
close to ambient as is possible, pulse techniques are utilized during test.

LF411C
LF412C
Low Offset, Low Drift JFET
Input Operational Amplifiers
Through innovative design concepts and precision matching this SINGLE/DUAL JFET
monolithic high speed JFET input operational amplifier family offers very low OPERATIONAL AMPLIFIERS
input offset voltage as well as low temperature coefficient of input offset
voltage. The amplifier requires less than 3.4 mA per amplifier of supply
current yet exhibits greater than 2.7 MHz of gain bandwidth product and SEMICONDUCTOR
more than 8.0 V/µs slew rate. Through the use of JFET inputs the amplifier TECHNICAL DATA
has very low input bias currents and low input offset currents. The amplifier
utilizes industry standard pinouts which afford the user the opportunity to
directly upgrade circuit performance without the need for redesign.
The LF411C and LF412C are available in the industry standard plastic
8–pin DIP and SO–8 surface mount packages, and specified over the
commercial temperature range.
• Low Input Offset Voltage: 2.0 mV Max (Single) 8
3.0 mV Max (Dual) 1
• Low T.C. of Input Offset Voltage: 10 µV/°C N SUFFIX

• Low Input Offset Current: 20 pA PLASTIC PACKAGE
• Low Input Bias Current: 60 pA
CASE 626

• Low Input Noise Current: 0.01 pA/ ǸHz
• Low Total Harmonic Distortion: 0.05% 8
• Low Supply Current: 2.5 mA 1
• High Input Resistance: 1012 Ω D SUFFIX

• Wide Gain Bandwidth: 8.0 MHz PLASTIC PACKAGE
CASE 751
• High Slew Rate: 25 V/µs (Typ) (SO–8)
• Fast Settling Time: 1.6 µs (to within 0.01%)
• Internally Compensated
PIN CONNECTIONS
LF411C
Offset Null 1 8 NC
ORDERING INFORMATION Invt Input 2 7 VCC
–
Operating Noninvt Input 3 + 6 Output
Device Function Temperature Range Package
VEE 4 5 Offset Null
LF411CD Single SO–8
(Single, Top View)
LF411CN Plastic DIP
TA = 0° to +70°C
LF412CD Dual SO–8
LF412C
LF412CN Plastic DIP
Output 1 1 8 VCC
2 1 7 Output 2
–
Inputs 1 +
3 6
–
2 Inputs 2
+
VEE 4 5
(Dual, Top View)

LF411C LF412C
MAXIMUM RATINGS
Supply Voltages VCC, VEE +18 V
Input Differential Voltage Range (Note 1) VIDR ±30 V
Input Voltage Range (Note 1) VIR ±15 V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Maximum Junction Temperature TJ +150 °C
Operating Ambient Temperature Range TA 0 to 70 °C
Thermal Resistance LF411CN/412CN RθJA 100 °C/W
(Junction–to–Ambient) LF411CD/412CD 180
Storage Temperature Tstg –60 to +150 °C

Maximum Power Dissipation PD (Note 2) mW
NOTES: 1. Input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature
(TJ) is not exceeded.
Representative Schematic Diagram

(Each Amplifier)
Output
VCC
Q2
Q4 Q5
Q3 Q1
Q6
– J1 J2
Inputs
+ Q17
Q20 J3
Q15 Q19 Q23

24
Q14
Q21 Q22 Q24
Q12 Q13 Q16
Q10 Q11 Q8 Q25

Q9
Q7
Q18
Offset
Null
LF411C
Only VEE
Bias Circuitry
Common to All
Amplifiers

LF411C LF412C
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 0° to 70°C, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Input Offset Voltage (RS = 10 k Ω, VCM = 0 V, VO = 0 V) |VIO| mV
LF411 – 0.5 2.0
LF412 – 1.0 3.0
Average Temperature Coefficient of Input Offset Voltage ∆VIO ∆T µV/°C
(RS = 10 k Ω, VCM = 0 V, VO = 0 V) – 10 –
Input Offset Current (VCM = 0 V, VO = 0 V) IIO
LF411 TA = 25°C – 20 100 pA
TA = 0° to 70°C – – 2.0 nA
LF412 TA = 25°C – 25 100 pA
TA = 0° to 70°C – – 2.0 nA
Input Bias Current (VCM = 0 V, VO = 0 V) IIB
LF411 TA = 25°C – 0.6 200 pA
TA = 0° to 70°C – – 4.0 nA
LF412 TA = 25°C – 0.5 200 pA
TA = 0° to 70°C – – 4.0 nA
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 k Ω) AVOL V/mV
LF411 TA = 25°C 25 80 –
TA = 0° to 70°C 15 – –
LF412 TA = 25°C 25 150 –
TA = 0° to 70°C 15 – –
Output Voltage Swing (VID = ±1.0 V, RL = 10 kΩ) V
LF411 VO + +12 +13.9 –
VO – – –14.7 –12
LF412 VO + +12 +14.0 –
VO – – –14.0 –12
Common Mode Input Voltage Range (VO = 0 V) VICR V
LF411 +11 +14 –11
– –14 –
LF412 +11 +15 –11
– –12 –
Common Mode Rejection (VCM = ±11 V, RS ≤ 10 k Ω) CMR dB
LF411 70 90 –
LF412 70 100 –
Power Supply Rejection (Note 3) PSR dB
(VCC VEE = +15 V, –15 V to +5.0 V, –5.0 V)
LF411 70 86 –
LF412 70 100 –
Power Supply Current (VO = 0 V) ID mA
LF411 – 2.5 3.4
LF412 – 2.8 6.8
NOTE: 3. Measured with VCC and VEE simultaneously varied.

LF411C LF412C
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 k Ω, AV = +1.0) SR V/µs
LF411 8.0 25 –
LF412 8.0 13 –
Gain Bandwidth Product GBW MHz
LF411 2.7 8.0 –
LF412 2.7 4.0 –
Channel Separation (f = 1.0 Hz to 20 kHz, LF412) CS – –120 – dB
Differential Input Resistance (VCM = 0 V) Rin – 1012 – kΩ
Equivalent Input Voltage Noise (RS = 100 Ω, f = 1.0 kHz) en nV/ √ Hz
LF411 – 30 –
LF412 – 25 –
Equivalent Input Noise Current (f = 1.0 kHz) in pA/ √ Hz
LF411 – 0.01 –
LF412 – 0.01 –

LF441C
LF442C
Low Power JFET Input LF444C
These JFET input operational amplifiers are designed for low power
applications. They feature high input impedance, low input bias current and
LOW POWER
low input offset current. Advanced design techniques allow for higher slew JFET INPUT
rates, gain bandwidth products and output swing. The LF441C device
provides for the external null adjustment of input offset voltage.
OPERATIONAL AMPLIFIERS
These devices are specified over the commercial temperature range. All SEMICONDUCTOR
are available in plastic dual in–line and SOIC packages.
TECHNICAL DATA
• Low Supply Current: 200 µA/Amplifier
• Low Input Bias Current: 5.0 pA
• High Gain Bandwidth: 2.0 MHz
• High Slew Rate: 6.0 V/µs
• High Input Impedance: 1012 Ω 8
8
1
• Large Output Voltage Swing: ±14 V
1
N SUFFIX D SUFFIX
• Output Short Circuit Protection PLASTIC PACKAGE PLASTIC PACKAGE
CASE 626 CASE 751
(SO–8)
Representative Schematic Diagram PIN CONNECTIONS

(Each Amplifier)
Offset Null 1 8 NC
VCC 2 – 7 VCC
Inputs +
3 6 Output
VEE 4 5
Offset Null
Q7
J1 J2 D2 (Single, Top View)
Inputs R3 R4
Output Output 1 1 8 VCC
+
D1 2
–
1 7 Output 2
C1 Inputs 1 3 + 6
Q3 Q4 2
–
Inputs 2
+ 5
VEE 4
C2
Q1 Q2 Q5 (Dual, Top View)
Q6
R1 R2
R5
VEE
1 * 5 * 14 14
+ 5 1.5 kΩ 1
1
*Null adjustment pins for LF441 only. 1 VEE
100 kΩ N SUFFIX D SUFFIX
PLASTIC PACKAGE PLASTIC PACKAGE
LF441C input offset voltage CASE 646 CASE 751A
null adjust circuit (SO–14)
PIN CONNECTIONS
ORDERING INFORMATION 1 14 Output 4
Output 1
Operating 2
– – 13
Device Function Temperature Range Package Inputs 1 Inputs 4
3 1 4 12
LF441CD Single SO–8 + +
LF441CN Plastic DIP VCC 4 11 VEE
+ +
5 10
LF442CD Dual SO–8
TA = 0° to +70°C Inputs 2 Inputs 3
LF442CN Plastic DIP 6 2 3 9
– –
LF444CD Quad SO–14 Output 2 7 8 Output 3
LF444CN Plastic DIP
(Quad, Top View)

LF441C LF442C LF444C
MAXIMUM RATINGS
Supply Voltage (from VCC to VEE) VS +36 V
Input Voltage Range (Notes 1 and 2) VIR ±15 V
Operating Junction Temperature (Note 3) TJ +150 °C
Storage Temperature Range Tstg –60 to +150 °C
NOTES: 1. Differential voltages are at the noninverting input terminal with respect to the inverting
input terminal.
2. The magnitude of the input voltage must never exceed the magnitude of the supply
or 15 V, whichever is less.
3. Power dissipation must be considered to ensure maximum junction temperature (TJ)
is not exceeded (see Figure 1).
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 0° to 70°C, unless otherwise noted.)
Input Offset Voltage (RS = 10 kΩ, VO = 0 V) VIO mV
Single: TA = +25°C – 3.0 5.0
TA = 0° to +70°C – – 7.5
Dual: TA = +25°C – 3.0 5.0
TA = 0° to +70°C – – 7.5
Quad: TA = +25°C – 3.0 10
TA = 0° to +70°C – – 12
Average Temperature Coefficient of Offset Voltage ∆VIO/∆T – 10 – µV/°C
(RS = 10 kΩ, VO = 0 V)
TA = +25°C – 0.5 50 pA
TA = 0° to +70°C – – 1.5 nA
TA = +25°C – 3.0 100 pA
TA = 0° to +70°C – – 3.0 nA
Common Mode Input Voltage Range (TA = +25°C) VICR – +14.5 +11 V
–11 –12 –
Large Signal Voltage Gain (VO = ±10 V, RL = 10 kΩ) AVOL V/mV

TA = +25°C 25 60 –
TA = 0° to +70°C 15 – –
Output Voltage Swing (RL = 10 kΩ) VO + +12 +14 – V
VO – – –14 –12
Common Mode Rejection (RS ≤ 10 kΩ, VCM = VICR, VO = 0 V) CMR 70 86 – dB

Power Supply Rejection (RS = 100 Ω, VCM = 0 V, VO = 0 V) PSR 70 84 – dB
Power Supply Current (No Load, VO = 0 V) ID µA
Single – 200 250
Dual – 400 500
Quad – 800 1000

AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = +25°C, unless otherwise noted.)
Slew Rate (Vin = –10 V to +10 V, RL = 10 kΩ, CL = 10 pF, AV = +1.0) SR 0.6 6.0 – V/ µs
Settling Time To within 10 mV ts – 1.6 – µs
(AV = –1.0, RL = 10 kΩ, VO = 0 V to +10 V) To within 1.0 mV – 2.2 –
Gain Bandwidth Product (f = 200 kHz) GBW 0.6 2.0 – MHz
Equivalent Input Noise Voltage (RS = 100 Ω, f = 1.0 kHz) en – 47 – nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz) in – 0.01 – pA/ √ Hz
Input Resistance Ri – 1012 – Ω
Channel Separation (f = 1.0 Hz to 20 kHz) CS – 120 – dB
Figure 1. Maximum Power Dissipation versus Figure 2. Input Bias Current versus
Temperature for Package Variations Input Common Mode Voltage
PD, MAXIMUM POWER DISSIPATION (mW)
2400 20
VCC = +15 V
IIB , INPUT BIAS CURRENT (pA)

2000 VEE = –15 V
8 & 14 Pin Plastic 15 TA = 25°C
1600 Package
1200 SO–14
10
SO–8
800
5.0
400
0 0
–55 –40 –20 0 20 40 60 80 100 120 140 160 –10 –5.0 0 5.0 10
TA, AMBIENT TEMPERATURE (°C) VICR, INPUT COMMON MODE VOLTAGE (V)
Figure 3. Input Bias Current versus Temperature Figure 4. Supply Current versus Supply Voltage
ID, SUPPLY CURRENT PER AMPLIFIER ( µA)
1000 300
VCC = +15 V
IIB,INPUT BIAS CURRENT (nA)
100 VEE = –15 V 260

VCM = 0 V
10
220 125°C
25°C
1.0
180
0.1 – 55°C
140
0.01
0.001 100
–55 –25 0 25 50 75 100 125 0 5.0 10 15 20 25
TA, AMBIENT TEMPERATURE (°C) VCC,  VEE, SUPPLY VOLTAGE (V)

Figure 5. Positive Input Common Mode Voltage Figure 6. Negative Input Common Mode Voltage
Range versus Positive Supply Voltage Range versus Negative Supply Voltage
20 –20
+VICR, POSITIVE INPUT COMMON MODE
–VICR,NEGATIVE INPUT COMMON MODE

–55°C ≤ TA ≤ 125°C –55°C ≤ TA ≤ 125°C
VOLTAGE RANGE (V)
15 –15
VOLTAGE RANGE (V)

10 –10
5.0 –5.0
0 0
0 5.0 10 15 20 0 –5.0 –10 –15 –20
VCC, POSITIVE SUPPLY VOLTAGE (V) VEE, NEGATIVE SUPPLY VOLTAGE (V)
Figure 7. Output Voltage versus Output Figure 8. Output Voltage versus

Source Current Output Sink Current
20 –20
VCC = +15 V VCC = +15 V
VEE = –15 V VEE = –15 V
VO, OUTPUT VOLTAGE (V)
15 –15
– 55°C
125°C
– 55°C 25°C
10 –10 125°C 25°C
5.0 –5.0
0
0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
IO, OUTPUT SOURCE CURRENT (mA) –IO, OUTPUT SINK CURRENT (mA)
Figure 9. Output Voltage Swing Figure 10. Output Voltage Swing

versus Supply Voltage versus Load Resistance
40
RL = 10 kΩ 28
VO, OUTPUT VOLTAGE SWING (Vp–p )
35 –55°C ≤ TA ≤ 125°C
26
30
24
25
20 22
15 20
VCC = +15 V
10 18 VEE = –15 V
TA = 25°C
5.0
16
0
0 2.0 4.0 6.0 8.0 10 12 14 16 1.0 k 2.0 k 3.0 k 4.0 k 6.0 k 8.0 k 10 k
VCC,  VEE, SUPPLY VOLTAGE (V) RL, LOAD RESISTANCE (Ω)

Figure 11. Normalized Gain Bandwidth Figure 12. Open Loop Voltage Gain and
Product versus Temperature Phase versus Frequency
GBW, NORMALIZED GAIN BANDWIDTH PRODUCT
1.4
AVOL , OPEN LOOP VOLTAGE GAIN (dB)

VCC = +15 V
φ, EXCESS PHASE (DEGREES)

1.3 VEE = –15 V 20 90
RL = 10 kΩ
1.2 CL = 100 pF Phase
10 135
1.1
1.0 0 180
0.9 VCC = +15 V

VEE = –15 V Gain
–10 225
0.8 RL = 10 kΩ
CL = 100 pF
0.7 –20 TA = 25°C 270
0.6
–75 –50 –25 0 25 50 75 100 125 0.1 1.0 10
TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (MHz)
Figure 14. Total Output Distortion

Figure 13. Slew Rate versus Temperature versus Frequency
8.0 2.5
VCC = +15 V
THD, OUTPUT DISTORTION (%)
VEE = –15 V
SR, SLEW RATE (V/ µs )
2.0 TA = 25°C
7.0
1.5
6.0
1.0
AV = 100
5.0 VCC = +15 V
VEE = –15 V 0.5
RL = 10 kΩ AV = 10
AV = +1.0 0
4.0
–75 –50 –25 0 25 50 75 100 125 10 100 1.0 k 10 k 100 k
TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz)
Figure 15. Output Voltage Swing Figure 16. Open Loop Voltage
versus Frequency Gain versus Frequency
100
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
30
80
20 60
VCC = +15 V 40
VEE = –15 V
10 RL = 10 kΩ VCC = +15 V
AV = +1.0 20 VEE = –15 V
1% THD RL = 10 kΩ
TA = 25°C TA = 25°C
0 0
1.0 k 10 k 100 k 1.0 M 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 17. Common Mode Rejection Figure 18. Power Supply Rejection
versus Frequency versus Frequency
140 140
VCC = +15 V ∆VCC
CMR, COMMON MODE REJECTION (dB)
VEE = –15 V
PSR, POWER SUPPLY REJECTION (dB)

120 120 –
∆VCM ADM ∆VO TA = 25°C ADM ∆VO
+ +
100 100 ∆VEE
( ∆V∆VCMO x ADM )
+PSR
CMR = 20 Log
80 80 –PSR
(∆VCC = ±1.5 V)
(∆VEE=±1.5 V)
60 60
40
VCC = +15 V
VEE = –15 V
40 +PSR = 20 Log ( ∆V∆VO CC
/ADM
)
VCM = 0 V ∆VO /ADM
20 20
∆VCM = ±1.5 V –PSR = 20 Log (
TA = 25°C ∆VEE )
0 0
100 1.0 k 10 k 100 k 1.0 M 100 1.0 k 10 k 100 k 1.0 M
Figure 20. Open Loop Voltage

Figure 19. Input Noise Voltage versus Frequency Gain versus Supply Voltage
70 1.0 M
AVOL, OPEN LOOP VOLTAGE GAIN (V V)
en , INPUT NOISE VOLTAGE ( nV/ √ Hz )
60 RL = 10 kΩ
50
40
100 k
30
25°C
VCC = +15 V 125°C
20
VEE = –15 V
10 VCM = 0 V –55°C
TA = 25°C
0 10 k
10 100 1.0 k 10 k 100 k 0 5.0 10 15 20 25
f, FREQUENCY (Hz) VCC,  VEE , SUPPLY VOLTAGE (V)
Figure 21. Output Impedance versus Frequency Figure 22. Inverter Settling Time
VO, OUTPUT VOLTAGE STEP FROM 0 V (V)
350
VCC = +15 V 10 VCC = +15 V
300 VEE = –15 V VEE = –15 V 10 mV
ZO , OUTPUT IMPEDANCE (Ω )
TA = 25°C TA = 25°C 1.0 mV

250 5.0
200
0
150
AV = 100 AV = 10 AV = 1.0
100 –5.0 1.0 mV
10 mV
50
–10
0
100 1.0k 10k 100k 1.0M 0.1 1.0 10
f, FREQUENCY (Hz) ts, SETTLING TIME (µs)

SMALL SIGNAL RESPONSE

Figure 23. Inverting Figure 24. Noninverting
VCC = +15 V VCC = +15 V

VO , OUTPUT VOLTAGE (50 mV/DIV)

VEE = –15 V VEE = –15 V
RL = 10 kΩ RL = 10 kΩ
CL = 10 pF CL = 10 pF
AV = –1.0 AV = +1.0
TA = 25°C TA = 25°C
0
0
t, TIME (0.5 µs/DIV) t, TIME (0.5 µs/DIV)
LARGE SIGNAL RESPONSE
Figure 25. Inverting Figure 26. Noninverting
VCC = +15 V VCC = +15 V

VO , OUTPUT VOLTAGE (5.0 V/DIV)
VEE = –15 V VEE = –15 V

RL = 10 kΩ RL = 10 kΩ
CL = 10 pF CL = 10 pF
AV = –1.0 AV = +1.0
TA = 25°C TA = 25°C
0 0

LM11C, CL
Precision Operational
Amplifiers
The LM11C is a precision, low drift operational amplifier providing the best PRECISION
features of existing FET and Bipolar op amps. Implementation of super gain OPERATIONAL AMPLIFIERS
transistors allows reduction of input bias currents by an order of magnitude
over earlier devices such as the LM308A. Offset voltage and drift have also
been reduced. Although bandwidth and slew rate are not as great as FET SEMICONDUCTOR
devices, input offset voltage, drift and bias current are inherently lower, TECHNICAL DATA
particularly over temperature. Power consumption is also much lower,
eliminating warm–up stabilization time in critical applications.
Offset balancing is provided, with the range determined by an external low
resistance potentiometer. Compensation is provided internally, but external
compensation can be added for improved stability when driving capacitive
loads.
The precision characteristics of the LM11C make this device ideal for
applications such as charge integrators, analog memories, electrometers,
active filters, light meters and logarithmic amplifiers. 8
• Low Input Offset Voltage: 100 µV 1
• Low Input Bias Current: 17 pA

• Low Input Offset Current: 0.5 pA N SUFFIX
•
PLASTIC PACKAGE
Low Input Offset Voltage Drift: 1.0 µV/°C CASE 626
• Long–Term Stability: 10 µV/year
• High Common Mode Rejection: 130 dB

Balance Compensation PIN CONNECTIONS
VCC
Q9 Q10
7.5 k Balance 1 8 Balance
17.4 k 17.4 k
Q17 Q18 2 – 7 VCC
7.0 k
3.0 pF Inputs +
3 6 Output
VEE 4 5 Compensation
(Top View)
Q7 Q8 Q28
Q5 Q6 1.0 k
80 k 30 1.4 k
– Q1 Q2 Q16 pF Q32
Q3 Q4
Q29 200
Inputs 2.0 k 2.0 k 2.0 k
Q27 Q31 Output
65
+ Q25 Q26 VCC 150
7.0 k
1.0 k 1.0 k
Q11 Q15 47
VCC V
Q30 Q33
Q12 VEE
Q13
Q20 Q21
Q14
Q24 50 k
20 k Operating
6.2 k Q22 Q23 Device Temperature Range Package
362
1.2 k
VEE LM11CN,CLN TA = 0° to +70°C Plastic DIP

LM11C, CL
MAXIMUM RATINGS
Power Supply Voltage VCC to VEE 40 Vdc
Differential Input Current (Note 1) IID ±10 mA
Output Short Circuit Duration (Note 2) tSC Indefinite
Power Dissipation (Note 3) PD 500 mW
Operating Junction Temperature TJ 85 °C
ELECTRICAL CHARACTERISTICS (TJ = 25°C, unless otherwise noted [ Note 4 ] .)

Input Offset Voltage VIO – 0.2 0.6 – 0.5 5.0 mV
Tlow to Thigh – – 0.8 – – 6.0
Input Offset Current IIO – 1.0 10 – 4.0 25 pA
Tlow to Thigh – – 20 – – 50
Input Bias Current IIB – 17 100 – 17 200 pA
Tlow to Thigh – – 150 – – 300
Input Resistance ri – 1011 – – 1011 – Ω
Input Offset Voltage Drift ∆VIO/∆T – 2.0 5.0 – 3.0 – µV/°C
Tlow to Thigh
Input Offset Current Drift ∆IIO/∆T – 10 – – 50 – ƒA/°C
Tlow to Thigh
Input Bias Current Drift ∆IIB/∆T – 0.8 3.0 – 1.4 – pA/°C
Tlow to Thigh
Large Signal Voltage Gain AVOL V/mV
VS = ±15 V, Vout = ±12 V, Iout = ±2.0 mA 100 300 – 25 300 –
Tlow to Thigh (Note 5) 50 – – 15 – –
VS = ±15 V, Vout = ±12 V, Iout = ±0.5 mA 250 1200 – 50 800 –
Tlow to Thigh 100 – – 30 – –
Common Mode Rejection CMR dB
VS = ±15 V, –13 V ≤ VCM ≤ 14 V 110 130 – 96 110 –
VS = ±15 V, –12.5 V ≤ VCM ≤ 14 V, Tlow to Thigh 100 – – 90 – –
Power Supply Rejection PSR dB
±2.5 V ≤ VS ≤ ±20 V 100 118 – 84 100 –
Tlow to Thigh 96 – – 80 – –
Power Supply Current ID – 0.3 0.8 – 0.3 0.8 mA
Tlow to Thigh – – 1.0 – – 1.0
Output Short Circuit Current ISC – ±10 – – ±10 – mA
TJ = 150°C, Output Shorted to Ground
NOTES: 1. The inputs are shunted by back–to–back diodes for over–voltage protection. Excessive current will flow if the input differential voltage is in excess of
1.0 V if no limiting resistance is used. Additionally, a 2.0 kΩ resistance in each input is suggested to prevent possible latch–up initiated by supply
reversals.
2. The output is current limited when shorted to ground or any voltages less than the supplies. Continuous overloads will require package dissipation to
be considered and heatsinking should be provided when necessary.
3. Devices must be derated based on package thermal resistance (see package outline dimensions).
4. These specifications apply for VEE +2.0 V ≤ VCM ≤ VCC –1.0 V (VEE +2.5 V ≤ VCM ≤ VCC –1.0 V for Tlow to Thigh) and ±2.5 V ≤ VS ≤ ±20 V
Tlow to Thigh: 0°C ≤ TJ ≤ +70°C for LM11C and LM11C.
5. Vout = ±11.5 V, all other conditions unchanged.

LM11C, CL
Figure 1. Input Bias Current Figure 2. Input Offset Current

versus Case Temperature versus Case Temperature
50 40
IIO , INPUT OFFSET CURRENT (pA)

40
I IB , INPUT BIAS CURRENT (pA)
30
VCC/VEE = ±2.0 V 30
20 Curve 1, VCC/VEE = ±20 V
10 Curve 2, VCC/VEE = ±2.5 V
0 20
–10
–20 VCC/VEE = ±2.5 V 1
10
–30 2
–40
–50 0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TC, CASE TEMPERATURE (°C) TC, CASE TEMPERATURE (°C)
Figure 3. Temperature Coefficient of Input

Offset Voltage versus Input Offset Voltage Figure 4. Spectral Noise Density
24 200
TC V , TEMPERATURE COEFFICIENT OF
VCC/VEE = ±15 V
VCC/VEE = ±20 V
INPUT OFFSET VOLTAGE ( µV/ ° C)
AV = 10
16 ∆t = 25° to 125°C 160
INPUT NOISE ( nV/ √ Hz )
RS = 100 kΩ
8.0
120
0
80
–8.0
40
–16
IO
–24 0
–6.0 –4.0 –2.0 0 2.0 4.0 6.0 10 100 1.0 k 10 k 100 k
VIO, INPUT OFFSET VOLTAGE (mV) @ 25°C f, FREQUENCY (Hz)
Figure 5. Common Mode Limits Figure 6. Common Mode Rejection and

versus Temperature Slew Limit versus Frequency
CMR, COMMON MODE REJECTION RATIO (dB)
0 140
CMSL, COMMON MODE SLEW LIMIT (Vp-p)
VCC Positive
VCC/VEE = ±15 V 10
120
∆VIO = 100 µV
COMMON MODE LIMITS (V)
CMSL
–1.0 100
CMR
80 1.0
2.0 ±2.5 V ≤ VS ≤ 20 V
∆VIO = 10 µV 60
40 0.1
1.0 Negative
VEE 20
0 0 0.01
–50 0 50 100 150 1.0 10 100 1.0 k 10 k 100 k 1.0 M
T, TEMPERATURE (°C) f, FREQUENCY (Hz)

LM11C, CL
Figure 7. Open Loop Voltage Gain Figure 8. Output Saturation

versus Supply Voltage versus Load Current
140 0
VCC
Vsat , OUTPUT SATURATION VOLTAGE (V)

f ≤ 0.1 Hz
Vsat = 1.5 V
–1.0
130 RL ≥ 2 VS(kΩ)
–2.0 –55°C ≤ TC ≤ 125°C

±2.5 V ≤ VS ≤ ±15 V
120
∆VIO = 10 µV
2.0 ∆VIO = 20 µV (125°C)
110
1.0
VEE
100 0
0 4.0 8.0 12 16 20 0 1.0 2.0 3.0 4.0
VCC/VEE, SUPPLY VOLTAGE (±V) IL, LOAD CURRENT (±mA)
Figure 9. Power Supply Rejection Ratio Figure 10. Supply Current versus
versus Frequency Supply Voltage
120 400
PSR, POWER SUPPLY REJECTIOJN (dB)
100
ID , SUPPLY CURRENT ( µ A)
360
80
1
320
60 2
VEE
3
40 280
VCC 1. TC = 25°C
20 2. TC = 125°C
3. TC = –55°C
240
0
–20 200
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 4.0 8.0 12 16 20
f, FREQUENCY (Hz) VCC/VEE, SUPPLY VOLTAGE (±V)
Figure 11. Open Loop Voltage Gain and Figure 12. Slew Rate versus
Phase versus Frequency External Compensation Capacitor
120 300
0
100
AVOL 30
SR, SLEW RATE (mV/ µ s)
AVOL, VOLTAGE GAIN (dB)
φ, PHASE (DEGREES)
80 100
1
60
2 2
60 φ
90 30
40 1 VCC/VEE = 20 k
120 ±20 V ±
1. CC = 0
20
2. CC = 1000 pF 10 +
150 20 k
VCC/VEE = ±15 V CC
0
RL = 30 kΩ
180
–20 3.0
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k
f, FREQUENCY (Hz) CC, EXTERNAL COMPENSATION CAPACITOR (pF)

LM11C, CL
Figure 13. Closed Loop Output Impedance

versus Frequency
1.0 k
ZO , OUTPUT IMPEDANCE ( Ω )
100
AV = 1000
10
VCC/VEE = ±15 V
Iout = ±1.0 mA
1.0
AV = 1.0
0.1
0.01
10 100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
APPLICATIONS INFORMATION
Due to the extremely low input bias currents of this device, printed circuit boards, sockets and the device package are
it may be tempting to remove the bias current compensation necessary to minimize surface leakage.
resistor normally associated with a summing amplifier When operating in high humidity environments or
configuration. Direct connection of the inputs to a low temperatures near 0°C, a surface coating is suggested to set
impedance source or ground should be avoided when supply up a moisture barrier.
voltages greater than approximately 3.0 V are used. The Leakage effects on printed circuit boards can be reduced
potential problem involves reversal of one supply which can by encircling the inputs (both sides of pc board) with a
cause excessive current to flow in the second supply. conductive guard ring connected to a low impedance
Possible destruction of the IC could result if the second potential nearly the same as that of the inputs.
supply is not current limited to approximately 100 mA or if Guard ring electrical connections for common operational
bypass capacitors greater than 1.0 µF are used in the supply amplifier configurations are illustrated in Figure 14.
bus. Electrostatic shielding is suggested in high impedance
Disconnecting one supply will generally cause reversal circuits.
due to loading of the other supply within the IC and in external Error voltages in external circuitry can be generated by
circuitry. Although the problem can usually be avoided by thermocouple effects. Dissimilar metals along with
placing clamp diodes across the power supplies of each temperature gradients can set up an error voltage ranging in
printed circuit board, a careful design will include sufficient the hundreds of microvolts. Some of the best thermocouples
resistance in the input leads to limit the current to 10 mA if the are junctions of dissimilar metals made up of IC package pins
input leads are pulled to either supply by internal currents. and printed circuit boards. Problems can be avoided by
This precaution is not limited only to the LM11C. keeping low level circuitry away from heat generating
The LM11C is capable of resolving picoampere level elements.
signals. Leakage currents external to the IC can severely The LM11C is internally compensated, but external
impair the performance of the device. It is important that high compensation can be added to improve stability, particularly
quality insulating materials such as teflon be employed. when driving capacitive loads.
Proper cleaning to remove fluxes and other residues from
Figure 14. Guard Ring Electrical Connections for Common Amplifier Configurations
Summing Amp (Inverting) Noninverting Voltage

R1 R1 Follower
R2 R2
Input
Output Output Output

Input Input
R3

LM11C, CL
Figure 15. Input Protection for Figure 16. Input Protection for
Summing (Inverting) Amplifier a Voltage Follower
R3
Input
R1 10 k
Output
R1 Output
Input
10 k
R3 10 k
Input current is limited by R1 when the input

Current is limited by R1 in the event the input exceeds supply voltage, power supply is
is connected to a low impedance source turned off, or output is shorted.
outside the common mode range of the
device. Current is controlled by R2 if one
supply reverses. R1 and R2 do not affect
normal operation.
Figure 17. Cable Bootstrapping and Input Shields

C
R1
Output
Input
Input
Output
C
An input shield bootstrapped in a voltage

follower reduces input capacitance, leakage, In a summing amplifier the input is at virtual
and spurious voltages from cable flexing. A ground. Therefore the shield can be
small capacitor from the input to ground will grounded. A small feedback capacitor will
prevent any instability. insure stability.
Figure 18. Adjusting Input Offset Voltage with Balance Potentiometer

VCC
Minimum
Adjustment Range R
(mV) (Ω)
R
±0.4 1.0 k
±1.0 3.0 k
Output ±2.0 10 k
Inputs
±5.0 100 k
Input offset voltage adjustment range is a function of the Balance

Potentiometer Resistance as indicated by the table above. The
potentiometer is connected between the two ‘‘Balance” pins.

LM301A
LM201A
A general purpose operational amplifier that allows the user to choose the
compensation capacitor best suited to his needs. With proper compensation,
summing amplifier slew rates to 10 V/µs can be obtained. OPERATIONAL AMPLIFIERS
• Low Input Offset Current: 20 nA Maximum Over Temperature Range
SEMICONDUCTOR
• External Frequency Compensation for Flexibility
TECHNICAL DATA
• Class AB Output Provides Excellent Linearity
• Output Short Circuit Protection
• Guaranteed Drift Characteristics
8
1
Figure 1. Standard Figure 2. Double–Ended N SUFFIX

Compensation and Limit Detector PLASTIC PACKAGE
Offset Balancing Circuit VCC CASE 626
VUT
VEE +
Inverting VCC
Input VO
Non– Output
Inverting MZ4622 or Equiv.
VI VEE
Input +
Balance VCC
Freq 3.9 V
Balance Compen 8
1
5.1 MΩ
10 MΩ 30 pF VO D SUFFIX
VLT
PLASTIC PACKAGE
20 k VEE VO = 4.8 V for CASE 751
VLT ≤ VI ≤ VUT (SO–8)
VEE VO = –0.4 V
VI < VLT or VI > VUT
(Pins Not Shown Are Not Connected)
Figure 3. Representative Circuit Schematic

Balance Compensation
VCC PIN CONNECTIONS
Inputs Balance 1 8 Compensation

+ 2 7 VCC
Inputs
500 Output 3 6 Output
25
VEE 4 5 Balance
50
(Top View)
450
Operating
40 k 40 k 80 k
Device Temperature Range Package
LM301AD TA = 0° to +70°C SO–8
5k 20 k 10 k 1.0 k LM301AN Plastic DIP
VEE LM201AD SO–8
250 Balance TA = – 25° to +85°C
LM201AN Plastic DIP

LM301A LM201A
MAXIMUM RATINGS
Value
Rating Symbol LM201A LM301A Unit
Power Supply Voltage VCC, VEE ±22 ±18 Vdc
Input Differential Voltage VID ±30 V
Input Common Mode Range (Note 1) VICR ±15 V
Output Short Circuit Duration tSC Continuous
Power Dissipation (Package Limitation) PD
Plastic Dual–In–Line Package (LM201A/ 625 625 mW
Derate above TA = +25°C 301A) 5.0 5.0 mW/°C
Operating Ambient Temperature Range TA –25 to +85 0 to +70 °C
Storage Temperature Range Tstg – 65 to +150 °C
NOTE: 1. For supply voltages less than ±15 V, the absolute maximum input voltage is equal to the supply voltage.
ELECTRICAL CHARACTERISTICS (TA = +25°C, unless otherwise noted.) Unless otherwise specified, these specifications apply for
supply voltages from ± 5.0 V to ± 20 V for the LM201A, and from ± 5.0 V to ±15 V for the LM301A.
LM201A LM301A
Input Offset Voltage (RS ≤ 50 kΩ) VIO – 0.7 2.0 – 2.0 7.5 mV
Input Offset Current IIO – 1.5 10 – 3.0 50 nA
Input Bias Current IIB – 30 75 – 70 250 nA
Input Resistance ri 1.5 4.0 – 0.5 2.0 – MΩ
Supply Current ICC,IEE mA
VCC/VEE = ± 20 V – 1.8 3.0 – – –
VCC/VEE = ±15 V – – – – 1.8 3.0
Large Signal Voltage Gain AV 50 160 – 25 160 – V/mV
(VCC/VEE = ±15 V, VO = ±10 V, RL > 2.0 kΩ)
The following specifications apply over the operating temperature range.
Input Offset Voltage (RS ≤ 50 kΩ) VIO – – 3.0 – – 10 mV
Input Offset Current IIO – – 20 – – 70 nA
Avg Temperature Coefficient of Input Offset Voltage ∆VIO/∆T – 3.0 15 – 6.0 30 µV/°C
TA(min) ≤ TA ≤ TA (max)
Avg Temperature Coefficient of Input Offset Current ∆IIO/∆T nA/°C
+25°C ≤ TA ≤ TA (max) – 0.01 0.1 – 0.01 0.3
TA(min) ≤ TA ≤ 25°C – 0.02 0.2 – 0.02 0.6
Input Bias Current IIB – – 100 – – 300 nA
Large Signal Voltage Gain AVOL 25 – – 15 – – V/mV
(VCC/VEE = ±15 V, VO = ±10V, RL > 2.0 kΩ)
Input Voltage Range VICR V
VCC/VEE = ± 20 V –15 – +15 – – –
VCC/VEE = ±15 V – – – –12 – +12
Common Mode Rejection (RS ≤ 50 kΩ) CMR 80 96 – 70 90 – dB
Supply Voltage Rejection (RS ≤ 50 kΩ) PSR 80 96 – 70 96 – dB
Output Voltage Swing VO ±12 ±14 – ±12 ±14 – V
(VCC/VEE = ±15 V, RL = ±10 kΩ, RL > 2.0 kΩ) ±10 ±13 – ±10 ±13 –
Supply Currents (TA = TA(max), VCC/VEE = ± 20 V) ICC,IEE – 1.2 2.5 – – – mA

LM301A LM201A
Figure 4. Minimum Input Voltage Range Figure 5. Minimum Output Voltage Swing
20 20
Applicable to the Specified
VOR, OUTPUT VOLTAGE RANGE ( ±V)

VIR , INPUT VOLTAGE RANGE (V)
Operating Temperature Operating Temperature

16 Ranges 16 Ranges
12 12
Positive LM201A
only Minimum LM201A
8.0 8.0 RL = 10 k only
Negative Minimum
4.0 4.0
RL = 2.0 k
0 0
0 5.0 10 15 20 0 5.0 10 15 20
VCC, ( –VEE), SUPPLY VOLTAGE (V) VCC, ( –VEE), SUPPLY VOLTAGE (V)
Figure 6. Minimum Voltage Gain Figure 7. Typical Supply Currents

100 2.5
Operating Temperature I CC , I EE , SUPPLY CURRENTS (mA)
94 Ranges 2.0
A V , VOLTAGE GAIN (dB)
88 1.5
LM201A LM201A
82 only 1.0 only
TA = +25°C
76 0.5
70 0
0 5.0 10 15 20 0 5.0 10 15 20
VCC, ( –VEE), SUPPLY VOLTAGE (V) VCC, ( –VEE), SUPPLY VOLTAGE (V)
Figure 8. Open Loop Frequency Response Figure 9. Large Signal Frequency Response
180
Single–Pole Compensation
160 Single–Pole Compensation

15
140 315
AV , VOLTAGE GAIN (dB)
120 270
100 225 10
C1 = 3.0 pF Phase
80 180 C1 = 3.0 pF
60 135
40 C1 = 30 pF
90 5.0
20 45 C1 = 30 pF
Gain
0 0
–20 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 1.0 k 10 k 100 k 1.0 M 10 M

LM301A LM201A
Figure 10. Voltage Follower Pulse Response Figure 11. Open Loop Frequency Response
10 140
8.0 Single–Pole Compensation Feedforward
120
VIR , VOR, VOLTAGE RANGE ( ±V)
Compensation
6.0
100
A V, VOLTAGE GAIN (dB)

225
4.0
PHASE LAG (DEGREES)

80 180
2.0
Input Phase
0 60 135
Output
–2.0 40 90
–4.0
20 Gain 45
–6.0
0 0
–8.0
–10 –20
0 10 20 30 40 50 60 70 80 90 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
t, TIME (µs) f, FREQUENCY (Hz)
Figure 12. Large Signal Frequency Response Figure 13. Inverter Pulse Response
18 10
Feedforward

8.0 Output
Feedforward Compensation
16 Compensation 6.0
4.0
12 2.0 Input
0
8.0 –2.0
–4.0
4.0 –6.0
–8.0
0 –10
100 k 1.0 M 10 M 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
f, FREQUENCY (Hz) t, TIME (µs)
Figure 14. Single–Pole Compensation Figure 15. Feedforward Compensation

C2
R2
R2
7 VCC
R1 2 7 VCC
R1 2
–VI 6 VI
VO 6
R3 3 3 VO
+VI + 4
8 +
4 VEE
Frequency 1
1 VEE
Compensation R3 C1 Balance
Balance
R1 Cs 1
C1 C1 ≥ 150 pF C2 =
R1 +R2 2πfoR2
Cs = 30 pF fo = 3.0 MHz

LM308A
Precision Operational
Amplifier
The LM308A operational amplifier provides high input impedance, low SUPER GAIN
input offset and temperature drift, and low noise. These characteristics are OPERATIONAL AMPLIFIER
made possible by use of a special Super Beta processing technology. This
amplifier is particularly useful for applications where high accuracy and low
drift performance are essential. In addition high speed performance may be SEMICONDUCTOR
improved by employing feedforward compensation techniques to maximize TECHNICAL DATA
slew rate without compromising other performance criteria.
The LM308A offers extremely low input offset voltage and drift
specifications allowing usage in even the most critical applications without
external offset nulling.
• Operation from a Wide Range of Power Supply Voltages
• Low Input Bias and Offset Currents
• Low Input Offset Voltage and Guaranteed Offset Voltage Drift
8
Performance
1
• High Input Impedance
N SUFFIX
PLASTIC PACKAGE
CASE 626
Frequency Compensation
8
1
Standard Compensation Modified Compensation D SUFFIX

R2 PLASTIC PACKAGE
R2
Inverting R1 CASE 751
Input Inverting R1 (SO–8)
R3 Output Input
Noninverting + Output
Input Compen B Noninverting R3
Cf +
Compen A Input Compen B
100 pF
1
Cf ≥ 30
R2
1+
R1
PIN CONNECTIONS
Compen A 1 8 Compen B
Standard Feedforward Feedforward Compensations for
2 – 7 VCC
Compensation Decoupling Load Capacitance
Inputs +
3 6 Output
RS > 10 k 100 k
10 k 5.0 pF
Input VEE 4 5 NC
Input
10 C2* 10 pF
k (Top View)
0.01 µF 500
Output
Output + Compen B
+ Compen B
3.0 k 3.0 k CL
500 pF
500 pF 10 pF 75 pF to
10 pF ORDERING INFORMATION
Compen A 0.01µF
Compen A
Operating
5 x 105 Device Temperature Range Package
*C2 > pF
R2
LM308AN Plastic DIP
TA = 0° to +70°C
LM308AD SO–8

LM308A
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)

Power Supply Voltage VCC, VEE ±18 Vdc
Input Voltage (See Note 1) VI ±15 V
Input Differential Current ( See Note 2) IID ±10 mA
Output Short Circuit Duration tSC Indefinite
Operating Ambient Temperature Range TA 0 to +70 °C
Junction Temperature TJ +150 °C
NOTES: 1. For supply voltages less than ±15 V, the maximum input voltage is equal to the supply
voltage.
2. The inputs are shunted with back–to–back diodes for overvoltage protection. Therefore,
excessive current will flow if a differential input voltage in excess of 1.0 V is applied
between the inputs, unless some limiting resistance is used.
ELECTRICAL CHARACTERISTICS (Unless otherwise noted these specifications apply for supply voltages of +5.0 V ≤ VCC ≤ +15 V
and –5.0 V ≥ VEE ≥ –15 V, TA = +25°C.)
Input Offset Voltage VIO – 0.3 0.5 mV
Input Offset Current IIO – 0.2 1.0 nA
Input Bias Current IIB – 1.5 7.0 nA
Input Resistance ri 10 40 – MΩ
Power Supply Currents ICC, IEE – ±0.3 ±0.8 mA
(VCC = +15 V, VEE = –15 V)
Large Signal Voltage Gain AVOL 80 300 – V/mV
(VCC = +15 V, VEE = –15 V, VO = ±10 V, RL ≥ 10 kΩ)
The following specifications apply over the operating temperature range.
Input Offset Voltage VIO – – 0.73 mV
Input Offset Current IIO – – 1.5 nA
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T – 1.0 5.0 µV/°C
TA (min) ≤ TA ≤ TA (max)
Average Temperature Coefficient of Input Offset Current ∆IIO/∆T – 2.0 10 pA/°C
Input Bias Current IIB – – 10 nA
Large Signal Voltage Gain AVOL 60 – – V/mV
(VCC +15 V, VEE = –15 V, VO = ±10 V, RL ≥ 10 kΩ)
Input Voltage Range VICR ±14 – – V
(VCC = +15 V, VEE = –15 V)
Common Mode Rejection CMR 96 110 – dB
(RS ≤ 50 kΩ)
Supply Voltage Rejection PSR 96 110 – dB
(RS ≤ 50 kΩ)
Output Voltage Range VOR ±13 ±14 – V
(VCC = +15 V, VEE = –15 V, RL = 10 kΩ)

LM308A
Figure 2. Maximum Equivalent Input Offset

Figure 1. Input Bias and Input Offset Currents Voltage Error versus Input Resistance
2.0 100
EQUIVALENT INPUT OFFSET VOLTAGE (mV)

0.25
I IB , INPUT BIAS CURRENT (nA)
I IO, INPUT OFFSET CURRENT (nA)

1.8
1.6 0.20
1.4
10
1.2 IIO 0.15
1.0
IIB
0.8 0.10
1.0
0.6
0.4 0.05
0.2
0 0 0.1
–60 –40 –20 0 20 40 60 80 100 120 140 100 k 1.0 M 10 M 100 M
T, TEMPERATURE (°C) ri, INPUT RESISTANCE (Ω)
Figure 4. Power Supply Currents versus

Figure 3. Voltage Gain versus Supply Voltages Power Supply Voltages
130 500
IEE , SUPPLY CURRENTS ( µ A)
AVOL , VOLTAGE GAIN (dB)
120 400
TA = 0°C TA = –55°C
110 +25°C 300 0°C
–55°C
+70°C +25°C
100 200
+125°C +70°C
CF = 0 +125°C
90 100
f = 100 Hz
=
I CC
80 0
0 5.0 10 15 20 0 5.0 10 15 20
VCC =  VEE, SUPPLY VOLTAGES (V) VCC =  VEE, SUPPLY VOLTAGES (V)
Figure 5. Open Loop Frequency Response Figure 6. Large Signal Frequency Response
140 20
VOR, OUTPUT VOLTAGE RANGE (± Vp–p)
VCC = +15 V
120 VEE = –15 V
16
AVOL , VOLTAGE GAIN (dB)
100 TA = +25°C
80
CF = 3.0 pF 12
60
40 8.0
CF = 3.0 pF
CF = 30 pF
20
4.0
0 CF = 30 pF
CF = 100 pF
–20 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M 1.0 k 10 k 100 k 1.0 M

LM308A
SUGGESTED DESIGN APPLICATIONS
INPUT GUARDING Even with properly cleaned and coated boards, leakage
Special care must be taken in the assembly of printed currents may cause trouble at +125°C, particularly since the
circuit boards to take full advantage of the low input currents input pins are adjacent to pins that are at supply potentials.
of the LM308A amplifier. Boards must be thoroughly cleaned This leakage can be significantly reduced by using guarding
with alcohol and blown dry with compressed air. After to lower the voltage difference between the inputs and
cleaning, the boards should be coated with epoxy or silicone adjacent metal runs. The guard, which is a conductive ring
rubber to prevent contamination. surrounding the inputs, is connected to a low–impedance
point that is at approximately the same voltage as the inputs.
Leakage currents from high voltage pins are then absorbed
by the guard.
Figure 7. Fast (1) Summing Amplifier with
Low Input Current Figure 8. Sample and Hold
C5 (2) VCC
RS
Input
1.0 M
R1 R4 Input
150 k 0.002 µF
0.002 150 pF Q1
µF 1 Sample
R2 6
2 Output Output
1M Q2
LM308A
3 LM101A (3) 1.0 µF (1)
30 pF
Compen B 1.0 M or equiv
300 pF
(1) Teflon, Polyethylene or Polycarbonate

Dielectric Capacitor
(1) Power Bandwidth: 250 kHz (3) In addition to increasing speed,
Small Signal Bandwidth: the LM101A raises high and low
3.5 MHz frequency gain, increases output
Slew Rate: 10 V/µs drive capability and eliminates
thermal feedback.
6 X 10–8
(2) C5 =
R1
Figure 9. Connection of Input Guards
Inverting Amplifier Follower Noninverting Amplifier
R1 R2 R2
Input R3 (1)
R3 (1)
Output
Output Input Output
R3 (1) R1
C1
C1 C1
Input
R1 R2
(1) Used to compensate for large source resistances. Note: must be an impedance.
R1 +R2

LM308A
Representative Circuit Schematic
Compensation A Compensation B
VCC
3.5 k 5.6 k 7.5 k
15 pF
17.4 k 17.4 k
1.0 k
7.5 k 1.4 k
200
7.0 k VCC Output
65
1.0 k 1.0 k
150
80 k VEE
Inputs 2.0 k 2.0 k
) 20 k
362 1.2 k 50 k
10 k
VEE

LM311
LM211
Highly Flexible Voltage
Comparators
The ability to operate from a single power supply of 5.0 V to 30 V or ±15 V HIGH PERFORMANCE
split supplies, as commonly used with operational amplifiers, makes the VOLTAGE COMPARATORS
LM211/LM311 a truly versatile comparator. Moreover, the inputs of the
device can be isolated from system ground while the output can drive loads
referenced either to ground, the VCC or the VEE supply. This flexibility makes SEMICONDUCTOR
it possible to drive DTL, RTL, TTL, or MOS logic. The output can also switch TECHNICAL DATA
voltages to 50 V at currents to 50 mA. Thus the LM211/LM311 can be used to
drive relays, lamps or solenoids.
8
Typical Comparator Design Configurations
1
Split Power Supply with Offset Balance Single Supply N SUFFIX

VCC PLASTIC PACKAGE
3.0 k VCC
CASE 626
2 8
RL + RL
5.0 k
5 Inputs 7
2 3 Output
6
+ 8 7 –
1
Inputs 3 Output VEE 4 8
– 1
1
4 D SUFFIX
VEE PLASTIC PACKAGE
CASE 751
Ground–Referred Load Load Referred to Negative Supply (SO–8)
VCC VCC
2 8 2 8
+ 7 +
7
Inputs 3 Inputs
3
– 1 Output – 1 Output PIN CONNECTIONS
4 4 RL
RL
Gnd 1 8 VCC
VEE VEE
Input polarity is reversed when Input polarity is reversed when
2
+
7 Output
Inputs
Gnd pin is used as an output. Gnd pin is used as an output. 3 – 6 Balance/Strobe
VEE 4 5 Balance
Load Referred to Positive Supply Strobe Capability
VCC (Top View)
VCC 2 8 RL
+ 7
2 8 Inputs Output
+ RL 3
7 – 1
Inputs ORDERING INFORMATION
3 Output 6
– 4
1 VEE Operating
TTL Strobe
4 Device Temperature Range Package
VEE 1.0 k LM211D TA = 25° to +85°C SO–8
LM311D SO–8
TA = 0° to +70°C
LM311N Plastic DIP

LM311 LM211

Rating Symbol LM211 LM311 Unit
Total Supply Voltage VCC +VEE 36 36 Vdc
Output to Negative Supply Voltage VO –VEE 50 40 Vdc
Ground to Negative Supply Voltage VEE 30 30 Vdc
Input Differential Voltage VID ±30 ±30 Vdc
Input Voltage (Note 2) Vin ±15 ±15 Vdc
Voltage at Strobe Pin – VCC to VCC–5 VCC to VCC–5 Vdc
Power Dissipation and Thermal Characteristics
Plastic DIP PD 625 mW
Derate Above TA = +25°C 1/θJA 5.0 mW/°C
Operating Ambient Temperature Range TA –25 to +85 0 to +70 °C
Operating Junction Temperature TJ(max) +150 +150 °C
Storage Temperature Range Tstg –65 to +150 –65 to +150 °C
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted [Note 1].)
LM211 LM311
Input Offset Voltage (Note 3) VIO mV
RS ≤ 50 kΩ, TA = +25°C – 0.7 3.0 – 2.0 7.5
RS ≤ 50 kΩ, Tlow ≤ TA ≤ Thigh* – – 4.0 – – 10
Input Offset Current (Note 3) TA = +25°C IIO – 1.7 10 – 1.7 50 nA
Tlow ≤ TA ≤ Thigh* – – 20 – – 70
Input Bias Current TA = +25°C IIB – 45 100 – 45 250 nA
Tlow ≤ TA ≤ Thigh* – – 150 – – 300
Voltage Gain AV 40 200 – 40 200 – V/mV
Response Time (Note 4) – 200 – – 200 – ns
Saturation Voltage VOL V
VID ≤ –5.0 mV, IO = 50 mA, TA = 25°C – 0.75 1.5 – – –
VID ≤–10 mV, IO = 50 mA, TA = 25°C – – – – 0.75 1.5
VCC ≥ 4.5 V, VEE = 0, Tlow ≤ TA ≤ Thigh*
VID 6≤6.0 mV, Isink ≤ 8.0 mA – 0.23 0.4 – – –
VID 6≤10 mV, Isink ≤ 8.0 mA – – – – 0.23 0.4
Strobe ”On” Current (Note 5) IS – 3.0 – – 3.0 – mA
Output Leakage Current
VID ≥ 5.0 mV, VO= 35 V, TA = 25°C, Istrobe= 3.0 mA – 0.2 10 – – – nA
VID ≥ 10 mV, VO= 35 V, TA = 25°C, Istrobe= 3.0 mA – – – – 0.2 50 nA
VID ≥ 5.0 mV, VO= 35 V, Tlow ≤ TA ≤ Thigh* – 0.1 0.5 – – – µA
Input Voltage Range (Tlow ≤ TA ≤ Thigh*) VICR –14.5 –14.7 to +13.0 –14.5 –14.7 to +13.0 V
13.8 13.8
Positive Supply Current ICC – +2.4 +6.0 – +2.4 +7.5 mA

Negative Supply Current IEE – –1.3 –5.0 – –1.3 –5.0 mA
* Tlow = –25°C for LM211 Thigh = +85°C for LM211
= 0°C for LM311 = +70°C for LM311
NOTES: 1. Offset voltage, offset current and bias current specifications apply for a supply voltage range from a single 5.0 V supply up to ±15 V supplies.
2. This rating applies for ±15 V supplies. The positive input voltage limit is 30 V above the negative supply. The negative input voltage limit is equal to the
negative supply voltage or 30 V below the positive supply, whichever is less.
3. The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a 1.0 mA load. Thus,
these parameters define an error band and take into account the ”worst case” effects of voltage gain and input impedance.
4. The response time specified is for a 100 mV input step with 5.0 mV overdrive.
5. Do not short the strobe pin to ground; it should be current driven at 3.0 mA to 5.0 mA.

LM311 LM211
Figure 1. Circuit Schematic
8
VCC
1.3 k 1.3 k 800 800
5 300
Balance 3.0 k
Balance/Strobe 100
6 300
5.0 k
3.7 k 3.7 k 7
200 Output
300
250 900
600
800
2 1.3 k
1
Inputs Gnd
1.3 k 5.4 k
730 340
3 4
VEE
Figure 2. Input Bias Current Figure 3. Input Offset Current

versus Temperature versus Temperature
140 5.0
VCC = +15 V VCC = +15 V
I IO , INPUT OFFSET CURRENT (nA)
VEE = –15 V VEE = –15 V

120 4.0
Pins 5 & 6 Tied
to VCC
100 Pins 5 & 6 Tied 3.0
to VCC
80 Normal 2.0
40 1.0 Normal
0 0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
TA, TEMPERATURE (°C) TA, TEMPERATURE (°C)
Figure 4. Input Bias Current versus Figure 5. Common Mode Limits

Differential Input Voltage versus Temperature
140
VCC = +15 V VCC Referred to Supply Voltages
120 VEE = –15 V

COMMON MODE LIMITS (V)
TA = +25°C –0.5
100 –1.0
–1.5
80
60
0.4
40
0.2
20 VEE
0
–16 –12 –8.0 –4.0 0 4.0 8.0 12 16 –55 –25 0 25 50 75 100 125
DIFFERENTIAL INPUT VOLTAGE (V) TA, TEMPERATURE (°C)

LM311 LM211
Figure 6. Response Time for Figure 7. Response Time for

VO , OUTPUT VOLTAGE (V) Various Input Overdrives Various Input Overdrives
VO , OUTPUT VOLTAGE (V)

+5.0 V
5.0 5.0 mV 5.0 5.0 mV Vin * 500 Ω
4.0 +5.0 V 4.0 ) VO

20 mV 2.0 mV
*
3.0 500 Ω 3.0
Vin
2.0
1.0
) VO 2.0
1.0
20 mV
2.0 mV
Vin ,INPUT VOLTAGE (mV)
0 0

VCC = +15 V VCC = +15 V
100 VEE = –15 V 0
VEE = –15 V
50 TA = +25°C –50 TA = +25°C
0 –100
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
tTLH, RESPONSE TIME (µs) tTHL, RESPONSE TIME (µs)
Figure 8. Response Time for Figure 9. Response Time for

Various Input Overdrives Various Input Overdrives
15 15 VCC
10 VCC 10 5.0 mV Vin *
5.0
20 mV 5.0 mV Vin
* 5.0 2.0 mV )
)
VO
0 0
VO 2.0 k
–5.0 –5.0
2.0 k VEE
–10 –10
–15 2.0 mV VEE –15 20 mV

VCC = +15 V
0 100 VEE = –15 V
VCC = +15 V 50 TA = +25°C
–50
VEE = –15 V
–100 TA = +25°C 0
0 1.0 2.0 0 1.0 2.0

tTLH, RESPONSE TIME (µs) tTHL, RESPONSE TIME (µs)
Figure 10. Output Short Circuit Current Figure 11. Output Saturation Voltage
Characteristics and Power Dissipation versus Output Current
OUTPUT SHORT CIRCUIT CURRENT (mA)
150 0.90 0.90

TA = +25°C
V , SATURATION VOLTAGE (V)
0.75
PD , POWER DISSIPATION (W)
125 0.75
100 Power Dissipation 0.60 0.60

TA = –55°C
75 0.45 0.45
Short Circuit Current
50 0.30 0.30
TA = +25°C
OL
25 0.15 0.15 TA = +125°C
0 0 0
0 5.0 10 15 0 8.0 16 24 32 40 48 56
VO, OUTPUT VOLTAGE (V) IO, OUTPUT CURRENT (mA)

LM311 LM211
Figure 12. Output Leakage Current Figure 13. Power Supply Current
versus Temperature versus Supply Voltage
100 3.6
OUTPUT LEAKAGE CURRENT (mA)
TA = +25°C
VCC = +15 V
POWER SUPPLY CURRENT (mA)

3.0
VEE = –15 V
10 Positive Supply – Output Low
2.4
1.0 Output VO = +50 V (LM11/211 only) 1.8

Positive and Negative Power Supply – Output H igh
1.2
0.1
0.6
0.01 0
25 45 65 85 105 125 0 5.0 10 15 20 25 30
TA, TEMPERATURE (°C) VCC–VEE, POWER SUPPLY VOLTAGE (V)
Figure 14. Power Supply Current

versus Temperature
3.0
VCC = +15 V
2.6 VEE = –15 V
SUPPLY CURRENT (mA)
Postive Supply – Output Low
2.2
1.8
Positive and Negative Supply – Output High

1.4
1.0
–55 –25 0 25 50 75 100 125
TA, TEMPERATURE (°C)
Figure 15. Improved Method of Adding

Hysteresis Without Applying Positive Figure 16. Conventional Technique
Feedback to the Inputs for Adding Hysteresis
+15 V +15 V
3.0 k 82 3.0 k 4.7 k

33 k
0.1 µF 5.0 k 0.1 µF 5.0 k
C1
8 0.002 4.7 k 8 C1
2 6 µF 100 3 6
Input + Input +
R1 5 R1 5
C2 LM311 Output C2 LM311 Output
7 7
1 100 1
– –
R2 3 4 R2 2 4
0.1 µF 1.0 M 0.1 µF

–15 V 510 k
–15 V

LM311 LM211
TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS
When a high speed comparator such as the LM211 is used Since feedback to almost any pin of a comparator can
with high speed input signals and low source impedances, result in oscillation, the printed–circuit layout should be
the output response will normally be fast and stable, engineered thoughtfully. Preferably there should be a
providing the power supplies have been bypassed (with 0.1 µF groundplane under the LM211 circuitry (e.g., one side of a
disc capacitors), and that the output signal is routed well double layer printed circuit board). Ground, positive supply or
away from the inputs (Pins 2 and 3) and also away from Pins negative supply foil should extend between the output and
5 and 6. the inputs to act as a guard. The foil connections for the
However, when the input signal is a voltage ramp or a slow inputs should be as small and compact as possible, and
sine wave, or if the signal source impedance is high (1.0 kΩ should be essentially surrounded by ground foil on all sides to
to 100 kΩ), the comparator may burst into oscillation near the guard against capacitive coupling from any fast high–level
crossing–point. This is due to the high gain and wide signals (such as the output). If Pins 5 and 6 are not used, they
bandwidth of comparators like the LM211 series. To avoid should be shorted together. If they are connected to a
oscillation or instability in such a usage, several precautions trim–pot, the trim–pot should be located no more than a few
are recommended, as shown in Figure 15. inches away from the LM211, and a 0.01 µF capacitor should
The trim pins (Pins 5 and 6) act as unwanted auxiliary be installed across Pins 5 and 6. If this capacitor cannot be
inputs. If these pins are not connected to a trim–pot, they used, a shielding printed–circuit foil may be advisable
should be shorted together. If they are connected to a between Pins 6 and 7. The power supply bypass capacitors
trim–pot, a 0.01 µF capacitor (C1) between Pins 5 and 6 will should be located within a couple inches of the LM211.
minimize the susceptibility to AC coupling. A smaller A standard procedure is to add hysteresis to a comparator
capacitor is used if Pin 5 is used for positive feedback as in to prevent oscillation, and to avoid excessive noise on the
Figure 15. For the fastest response time, tie both balance output. In the circuit of Figure 16, the feedback resistor of
pins to VCC. 510 kΩ from the output to the positive input will cause about
Certain sources will produce a cleaner comparator output 3.0 mV of hysteresis. However, if R2 is larger than 100 Ω,
waveform if a 100 pF to 1000 pF capacitor (C2) is connected such as 50 kΩ, it would not be practical to simply increase the
directly across the input pins. When the signal source is value of the positive feedback resistor proportionally above
applied through a resistive network, R1, it is usually 510 kΩ to maintain the same amount of hysteresis.
advantageous to choose R2 of the same value, both for DC When both inputs of the LM211 are connected to active
and for dynamic (AC) considerations. Carbon, tin–oxide, and signals, or if a high–impedance signal is driving the positive
metal–film resistors have all been used with good results in input of the LM211 so that positive feedback would be
comparator input circuitry, but inductive wirewound resistors disruptive, the circuit of Figure 15 is ideal. The positive
should be avoided. feedback is applied to Pin 5 (one of the offset adjustment
When comparator circuits use input resistors (e.g., pins). This will be sufficient to cause 1.0 mV to 2.0 mV
summing resistors), their value and placement are hysteresis and sharp transitions with input triangle waves
particularly important. In all cases the body of the resistor from a few Hz to hundreds of kHz. The positive–feedback
should be close to the device or socket. In other words, there signal across the 82 Ω resistor swings 240 mV below the
should be a very short lead length or printed–circuit foil run positive supply. This signal is centered around the nominal
between comparator and resistor to radiate or pick up voltage at Pin 5, so this feedback does not add to the offset
signals. The same applies to capacitors, pots, etc. For voltage of the comparator. As much as 8.0 mV of offset
example, if R1 = 10 kΩ, as little as 5 inches of lead between voltage can be trimmed out, using the 5.0 kΩ pot and 3.0 kΩ
the resistors and the input pins can result in oscillations that resistor as shown.
are very hard to dampen. Twisting these input leads tightly is
the best alternative to placing resistors close to the
comparator.
Figure 17. Zero–Crossing Detector

Driving CMOS Logic Figure 18. Relay Driver with Strobe Capability
VCC = +15 V VEE VCC1 VCC2
3.0 k VEE
Balance VCC
Adjust +
Output
5.0 k 10 k Inputs LM311
Balance
Balance/Strobe *D1
Input + VCC 2N2222
Output Gnd Q1
Inputs LM311 or Equiv
to CMOS Logic
Gnd *Zener Diode D1
VEE 1.0 k protects the comparator
from inductive kickback
VEE = –15 V and voltage transients
TTL on the VCC2 supply line.
Strobe

LM324, LM324A,
LM224, LM2902,
LM2902V
Quad Low Power
The LM324 series are low–cost, quad operational amplifiers with true QUAD DIFFERENTIAL INPUT
differential inputs. They have several distinct advantages over standard OPERATIONAL AMPLIFIERS
operational amplifier types in single supply applications. The quad amplifier
can operate at supply voltages as low as 3.0 V or as high as 32 V with
quiescent currents about one–fifth of those associated with the MC1741 (on SEMICONDUCTOR
a per amplifier basis). The common mode input range includes the negative TECHNICAL DATA
supply, thereby eliminating the necessity for external biasing components in
many applications. The output voltage range also includes the negative
power supply voltage.
• Short Circuited Protected Outputs
• True Differential Input Stage N SUFFIX
• Single Supply Operation: 3.0 V to 32 V PLASTIC PACKAGE
CASE 646
• Low Input Bias Currents: 100 nA Maximum (LM324A) 14
(LM224, LM324,
• Four Amplifiers Per Package 1 LM2902 Only)
• Common Mode Range Extends to Negative Supply
• Industry Standard Pinouts D SUFFIX
• 14 PLASTIC PACKAGE
ESD Clamps on the Inputs Increase Ruggedness without Affecting CASE 751A
1
Device Operation (SO–14)
PIN CONNECTIONS
Out 1 1 14 Out 4
2
*1 * 13
MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted.)

Inputs 1
3 ) 4
) 12
Inputs 4
LM224 LM2902, VCC 4 11 VEE, Gnd

Rating Symbol LM324, LM324A LM2902V Unit
5
)2 ) 10
Power Supply Voltages Vdc Inputs 2
6
* 3
* 9
Inputs 3
Single Supply VCC 32 26
Split Supplies VCC, VEE ±16 ±13 Out 2 7 8 Out 3
Input Differential VIDR ±32 ±26 Vdc

(Top View)
Voltage Range (See
Note 1)
Input Common Mode VICR –0.3 to 32 –0.3 to 26 Vdc ORDERING INFORMATION
Voltage Range Operating
Output Short Circuit tSC Continuous
Duration LM2902D SO–14
TA = –40° to +105°C
LM2902N Plastic DIP
Junction Temperature TJ 150 °C LM2902VD SO–14
TA = –40° to +125°C
Storage Temperature Tstg –65 to +150 °C LM2902VN Plastic DIP
Range LM224D SO–14
TA = –25° to +85°C
LM224N Plastic DIP
Operating Ambient TA –25 to +85 –40 to +105 °C
Temperature Range 0 to +70 –40 to +125 LM324AD SO–14
LM324AN Plastic DIP
NOTE: 1. Split Power Supplies. TA = 0° to +70°C
LM324D SO–14
LM324N Plastic DIP

LM324, LM324A, LM224, LM2902, LM2902V
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
LM224 LM324A LM324 LM2902 LM2902V
Characteristics Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VIO mV

VCC = 5.0 V to 30 V
(26 V for LM2902,
V), VICR = 0 V to
VCC –1.7 V, VO =
1.4 V, RS = 0 Ω
TA = 25°C – 2.0 5.0 – 2.0 3.0 – 2.0 7.0 – 2.0 7.0 – 2.0 7.0
TA = Thigh(1) – – 7.0 – – 5.0 – – 9.0 – – 10 – – 13
TA = Tlow(1) – – 7.0 – – 5.0 – – 9.0 – – 10 – – 10
Average Temperature ∆VIO/∆T – 7.0 – – 7.0 30 – 7.0 – – 7.0 – – 7.0 – µV/°C

Coefficient of Input
Offset Voltage
TA = Thigh to Tlow(1)
Input Offset Current IIO – 3.0 30 – 5.0 30 – 5.0 50 – 5.0 50 – 5.0 50 nA
TA = Thigh to Tlow(1) – – 100 – – 75 – – 150 – – 200 – – 200
Average Temperature ∆IIO/∆T – 10 – – 10 300 – 10 – – 10 – – 10 – pA/°C

Coefficient of Input
Offset Current
TA = Thigh to Tlow(1)
Input Bias Current IIB – –90 –150 – –45 –100 – –90 –250 – –90 –250 – –90 –250 nA
TA = Thigh to Tlow(1) – – –300 – – –200 – – –500 – – –500 – – –500
Input Common Mode VICR V

Voltage Range(2)
VCC = 30 V (26 V for 0 – 28.3 0 – 28.3 0 – 28.3 0 – 24.3 0 – 24.3
LM2902, V)
VCC = 30 V (26 V for 0 – 28 0 – 28 0 – 28 0 – 24 0 – 24
LM2902, V),
TA = Thigh to Tlow
Differential Input VIDR – – VCC – – VCC – – VCC – – VCC – – VCC V
Voltage Range
Large Signal Open AVOL V/mV

Loop Voltage Gain
RL = 2.0 kΩ, VCC = 50 100 – 25 100 – 25 100 – 25 100 – 25 100 –
15 V, for Large VO 25 – – 15 – – 15 – – 15 – – 15 – –
Swing, TA = Thigh
to Tlow(1)
Channel Separation CS – –120 – – –120 – – –120 – – –120 – – –120 – dB
10 kHz ≤ f ≤ 20 kHz,
Input Referenced
Common Mode CMR 70 85 – 65 70 – 65 70 – 50 70 – 50 70 – dB

Rejection, RS ≤ 10 kΩ
Power Supply PSR 65 100 – 65 100 – 65 100 – 50 100 – 50 100 – dB

Rejection
Output Voltage – High VOH V

Limit (TA = Thigh to
Tlow)(1)
VCC = 5.0 V, RL = 3.3 3.5 – 3.3 3.5 – 3.3 3.5 – 3.3 3.5 – 3.3 3.5 –
2.0 kΩ, TA = 25°C
VCC = 30 V (26 V for 26 – – 26 – – 26 – – 22 – – 22 – –
LM2902, V),
RL = 2.0 kΩ
VCC = 30 V (26 V for 27 28 – 27 28 – 27 28 – 23 24 – 23 24 –
LM2902, V),
RL = 10 kΩ
NOTES: 1. Tlow = –25°C for LM224 Thigh = +85°C for LM224

= 0°C for LM324, A = +70°C for LM324, A
= –40°C for LM2902 = +105°C for LM2902
= –40°C for LM2902V = +125°C for LM2902V
2. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the
common mode voltage range is VCC –1.7 V.

LM324, LM324A, LM224, LM2902, LM2902V
LM224 LM324A LM324 LM2902 LM2902V
Characteristics Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Output Voltage – Low VOL – 5.0 20 – 5.0 20 – 5.0 20 – 5.0 100 – 5.0 100 mV
Limit, VCC = 5.0 V, RL
= 10 kΩ, TA = Thigh to
Tlow(1)
Output Source Current IO + mA

(VID = +1.0 V, VCC =
15 V)
TA = 25°C 20 40 – 20 40 – 20 40 – 20 40 – 20 40 –
TA = Thigh to Tlow(1) 10 20 – 10 20 – 10 20 – 10 20 – 10 20 –
Output Sink Current IO – mA

(VID = –1.0 V, VCC = 10 20 – 10 20 – 10 20 – 10 20 – 10 20 –
15 V) TA = 25°C
TA = Thigh to Tlow(1) 5.0 8.0 – 5.0 8.0 – 5.0 8.0 – 5.0 8.0 – 5.0 8.0 –
(VID = –1.0 V, VO = 12 50 – 12 50 – 12 50 – – – – – – – µA
200 mV, TA = 25°C)
Output Short Circuit to ISC – 40 60 – 40 60 – 40 60 – 40 60 – 40 60 mA

Ground(3)
Power Supply Current ICC mA

(TA = Thigh to Tlow)(1)
VCC = 30 V (26 V for – – 3.0 – 1.4 3.0 – – 3.0 – – 3.0 – – 3.0
LM2902, V),
VO = 0 V, RL = ∞
VCC = 5.0 V, – – 1.2 – 0.7 1.2 – – 1.2 – – 1.2 – – 1.2
VO = 0 V, RL = ∞

= 0°C for LM324, A = +70°C for LM324, A
= –40°C for LM2902 = +105°C for LM2902
= –40°C for LM2902V = +125°C for LM2902V
2. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the
common mode voltage range is VCC –1.7 V.
Representative Circuit Diagram

(One–Fourth of Circuit Shown) Bias Circuitry
Common to Four
Output Amplifiers
VCC
Q15
Q16 Q14 Q22
Q13
40 k
Q19
5.0 pF Q12 Q24

25 Q23
+
Q18 Q20
Inputs
Q11
Q9
– Q17 Q21
Q6 Q7 Q25
Q2 Q5 Q1 2.4 k
Q8 Q10
Q3 Q4 Q26
2.0 k
VEE/Gnd

LM324, LM324A, LM224, LM2902, LM2902V
CIRCUIT DESCRIPTION
The LM324 series is made using four internally Large Signal Voltage Follower Response
compensated, two–stage operational amplifiers. The first
VCC = 15 Vdc
stage of each consists of differential input devices Q20 and RL = 2.0 kΩ
Q18 with input buffer transistors Q21 and Q17 and the TA = 25°C
differential to single ended converter Q3 and Q4. The first
stage performs not only the first stage gain function but also
1.0 V/DIV
performs the level shifting and transconductance reduction
functions. By reducing the transconductance, a smaller
compensation capacitor (only 5.0 pF) can be employed, thus
saving chip area. The transconductance reduction is
accomplished by splitting the collectors of Q20 and Q18.
Another feature of this input stage is that the input common
mode range can include the negative supply or ground, in
5.0 µs/DIV
single supply operation, without saturating either the input
devices or the differential to single–ended converter. The
second stage consists of a standard current source load Each amplifier is biased from an internal–voltage regulator
amplifier stage. which has a low temperature coefficient thus giving each
amplifier good temperature characteristics as well as
excellent power supply rejection.
Single Supply Split Supplies

3.0 V to VCC(max) VCC
VCC
1 1.5 V to VCC(max)
1
2
2
3
3
4 1.5 V to VEE(max)
4
VEE
VEE/Gnd

LM324, LM324A, LM224, LM2902, LM2902V
Figure 1. Input Voltage Range Figure 2. Open Loop Frequency

20 120
18
OPEN LOOP VOLTAGE GAIN (dB)

100 VCC = 15 V
± V , INPUT VOLTAGE (V)
16 VEE = Gnd
A VOL, LARGE–SIGNAL
TA = 25°C
14 80
12
60
10
Negative 40
8.0
Positive
I
6.0 20
4.0
0
2.0
0 –20
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 1.0 10 100 1.0 k 10 k 100 k 1.0 M
± VCC/VEE, POWER SUPPLY VOLTAGES (V) f, FREQUENCY (Hz)
Figure 4. Small–Signal Voltage Follower

Figure 3. Large–Signal Frequency Response Pulse Response (Noninverting)
14 550
VOR , OUTPUT VOLTAGE RANGE (Vpp )
RL = 2.0 kΩ 500
12 VCC = 15 V
VO , OUTPUT VOLTAGE (mV)
VEE = Gnd Input
10 450
Gain = –100
Output
RI = 1.0 kΩ 400
8.0 RF = 100 kΩ
350
6.0
300
4.0 250 VCC = 30 V
VEE = Gnd
2.0 200 TA = 25°C
CL = 50 pF
0 0
1.0 10 100 1000 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
f, FREQUENCY (kHz) t, TIME (µs)
Figure 5. Power Supply Current versus Figure 6. Input Bias Current versus
Power Supply Voltage Power Supply Voltage
2.4
2.1
R
TA = 25°C
ICC , POWER SUPPLY CURRENT (mA)
RL =
90
1.8
1.5
1.2
0.9 80
0.6
0.3
0 70
0 5.0 10 15 20 25 30 35 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
VCC, POWER SUPPLY VOLTAGE (V) VCC, POWER SUPPLY VOLTAGE (V)

LM324, LM324A, LM224, LM2902, LM2902V
Figure 7. Voltage Reference Figure 8. Wien Bridge Oscillator
50 k
R1
VCC 5.0 k
VCC R2
– 10 k VCC
1/4 Vref –
LM324 VO 1/4
LM324 VO
MC1403 +
2.5 V + 1
1 fo = 2 π RC
Vref = VCC
2
For: fo = 1.0 kHz
R1 R = 16 kΩ
VO = 2.5 V 1+ R C
R2 R C = 0.01 µF
C
Figure 9. High Impedance Differential Amplifier Figure 10. Comparator with Hysteresis
+ 1
e1
1/4 CR R R2
LM324 Hysteresis
–
VOH
R1 VO
– Vref +
a R1 1/4
R1 LM324 eo 1/4
LM324
+ Vin – VO
b R1 VOL
1 VinL VinH
–
1/4 CR R1
VinL = (V – V ) + Vref Vref
LM324 R1 + R2 OL ref
e2 + R R1
VinH = (V – V ) + Vref
R1 + R2 OH ref
eo = C (1 + a + b) (e2 – e1) R1
H= (V – V )
R1 + R2 OH OL
Figure 11. Bi–Quad Filter
R
1
fo = 2 π RC
R 100 k
R1 = QR
1
Vin C1 R2 C R1 Vref = VCC
C R2 = 2
– R TBP
1/4
LM324 – 100 k
1/4 – R3 = TN R2
+ LM324 1/4
+ LM324 C1 = 10C
Vref + For: fo = 1.0 kHz

Bandpass Vref For: Q = 10
Vref Output R3 For: TBP = 1
R1 For: TN = 1
R2 – C1
1/4
LM324 Notch Output R = 160 kΩ
+ C = 0.001 µF
R1 = 1.6 MΩ
Vref Where: TBP = Center Frequency Gain R2 = 1.6 MΩ
Where: TN = Passband Notch Gain R3 = 1.6 MΩ

LM324, LM324A, LM224, LM2902, LM2902V
Figure 12. Function Generator Figure 13. Multiple Feedback Bandpass Filter
1 Triangle Wave
Vref = VCC R2 VCC
2 Output
300 k C R3
Vref + R1 C
1/4 R3 Vin – CO
+ 1/4
LM324 1/4 VO
– 75 k LM324
R1 LM324
– Square + CO = 10 C
100 k Wave R2
Vref Output
C Vref 1
Vref = 2 VCC
Rf
R1 + RC R2 R1
f = if R3 = Given: fo = center frequency
4 CRf R1 R2 + R1
A(fo) = gain at center frequency
Choose value fo, C

Q
Then: R3 =
π fo C
R3
R1 =
2 A(fo)
R1 R3
R2 =
4Q2 R1 – R3
Qo fo
For less than 10% error from operational amplifier, < 0.1
BW
where fo and BW are expressed in Hz.
If source impedance varies, filter may be preceded with
voltage follower buffer to stabilize filter parameters.

LM339, LM339A,
LM239, LM239A,
Quad Single Supply
LM2901, M2901V,
Comparators
MC3302
These comparators are designed for use in level detection, low–level
sensing and memory applications in consumer automotive and industrial
electronic applications.
• Single or Split Supply Operation
• Low Input Bias Current: 25 nA (Typ)
•
14
Low Input Offset Current: ±5.0 nA (Typ)
•
1
Low Input Offset Voltage: ±1.0 mV (Typ) LM139A Series
• Input Common Mode Voltage Range to Gnd N, P SUFFIX
•
PLASTIC PACKAGE
Low Output Saturation Voltage: 130 mV (Typ) @ 4.0 mA CASE 646
• TTL and CMOS Compatible
• ESD Clamps on the Inputs Increase Reliability without Affecting Device
Operation
14
MAXIMUM RATINGS 1
Rating Symbol Value Unit D SUFFIX

PLASTIC PACKAGE
Power Supply Voltage VCC Vdc CASE 751A
LM239, A/LM339A/LM2901, V +36 or ±18 (SO–14)
MC3302 +30 or ±15
Input Differential Voltage Range VIDR Vdc
LM239, A/LM339A/LM2901, V 36
MC3302 30 PIN CONNECTIONS
Input Common Mode Voltage Range VICMR –0.3 to VCC Vdc
Output Short Circuit to Ground (Note 1) ISC Continuous Output 2 1 14 Output 3
Power Dissipation @ TA = 25°C PD
Plastic Package 1.0 W
Derate above 25°C 8.0 mW/°C VCC 3 12 Gnd
Junction Temperature TJ 150 °C
– Input 1 4
* ) 11 + Input 4
Operating Ambient Temperature Range
LM239, A
TA
–25 to +85
°C
+ Input 1 5
) 1 4
* 10 – Input 4
MC3302 –40 to +85
LM2901 –40 to +105 – Input 2 6
* ) 9 + Input 3
LM2901V –40 to +125
+ Input 2 7
) 2 3
* 8 – Input 3
LM339, A 0 to +70
(Top View)
NOTE: 1. The maximum output current may be as high as 20 mA, independent of the magnitude of VCC.
Output short circuits to VCC can cause excessive heating and eventual destruction.

VCC + Input – Input Output ORDERING INFORMATION
Operating
LM239D,AD SO–14
TA = 25° to +85°C
LM239N,AN Plastic DIP
LM339D, AD SO–14
TA = 0° to +70°C
LM339N, AN Plastic DIP
LM2901D SO–14
TA = –40° to +105°C
LM2901N Plastic DIP
LM2901VD SO–14
TA = –40° to +125°C
Gnd LM2901VN Plastic DIP
NOTE: Diagram shown is for 1 comparator. MC3302P TA = –40° to +85°C Plastic DIP

LM339, LM339A, LM239, LM239A, LM2901, M2901V, MC3302
ELECTRICAL CHARACTERISTICS (VCC = +5.0 Vdc, TA = +25°C, unless otherwise noted)
LM239A/339A LM239/339 LM2901/2901V MC3302
Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage (Note 4) VIO – ±1.0 ±2.0 – ±2.0 ±5.0 – ±2.0 ±7.0 – ±3.0 ±20 mVdc
Input Bias Current (Notes 4, 5) IIB – 25 250 – 25 250 – 25 250 – 25 500 nA
(Output in Analog Range)
Input Offset Current (Note 4) IIO – ±5.0 ±50 – ±5.0 ±50 – ±5.0 ±50 – ±3.0 ±100 nA
Input Common Mode Voltage Range VICMR 0 – VCC 0 – VCC 0 – VCC 0 – VCC V
–1.5 –1.5 –1.5 –1.5
Supply Current ICC mA
RL = ∞ (For All Comparators) – 0.8 2.0 – 0.8 2.0 – 0.8 2.0 – 0.8 2.0
RL = ∞, VCC = 30 Vdc – 1.0 2.5 – 1.0 2.5 – 1.0 2.5 – 1.0 2.5
Voltage Gain AVOL 50 200 – 50 200 – 25 100 – 25 100 – V/mV
RL ≥ 15 kΩ, VCC = 15 Vdc
Large Signal Response Time – – 300 – – 300 – – 300 – – 300 – ns
VI = TTL Logic Swing,
Vref = 1.4 Vdc, VRL = 5.0 Vdc,
RL = 5.1 kΩ
Response Time (Note 6) – – 1.3 – – 1.3 – – 1.3 – – 1.3 – µs
VRL = 5.0 Vdc, RL = 5.1 kΩ
Output Sink Current ISink 6.0 16 – 6.0 16 – 6.0 16 – 6.0 16 – mA
VI (–) ≥ +1.0 Vdc, VI(+) = 0,
VO ≤ 1.5 Vdc
Saturation Voltage Vsat – 130 400 – 130 400 – 130 400 – 130 500 mV
VI(–) ≥ +1.0 Vdc, VI(+) = 0,
Isink ≤ 4.0 mA
Output Leakage Current IOL – 0.1 – – 0.1 – – 0.1 – – 0.1 – nA
VI(+) ≥ +1.0 Vdc, VI(–) = 0,
VO = +5.0 Vdc
PERFORMANCE CHARACTERISTICS (VCC = +5.0 Vdc, TA = Tlow to Thigh [Note 3])

LM239A/339A LM239/339 LM2901/2901V MC3302
Input Offset Voltage (Note 4) VIO – – ±4.0 – – ±9.0 – – ±15 – – ±40 mVdc
Input Bias Current (Notes 4, 5) IIB – – 400 – – 400 – – 500 – – 1000 nA
(Output in Analog Range)
Input Offset Current (Note 4) IIO – – ±150 – – ±150 – – ±200 – – ±300 nA
Input Common Mode Voltage Range VICMR 0 – VCC 0 – VCC 0 – VCC 0 – VCC V
–2.0 –2.0 –2.0 –2.0
Saturation Voltage Vsat – – 700 – – 700 – – 700 – – 700 mV
VI(–) ≥ +1.0 Vdc, VI(+) = 0,
Isink ≤ 4.0 mA
Output Leakage Current IOL – – 1.0 – – 1.0 – – 1.0 – – 1.0 µA
VI(+) ≥ +1.0 Vdc, VI(–) = 0,
VO = 30 Vdc
Differential Input Voltage VID – – VCC – – VCC – – VCC – – VCC Vdc
All VI ≥ 0 Vdc
NOTES: 3. (LM239/239A) Tlow = –25°C, Thigh = +85°
(LM339/339A) Tlow = 0°C, Thigh = +70°C
(MC3302) Tlow = –40°C, Thigh = +85°C
(LM2901) Tlow = –40°C, Thigh = +105°
]
(LM2901V) Tlow = –40°C, Thigh = +125°C
4. At the output switch point, VO 1.4 Vdc, RS ≤ 100 Ω 5.0 Vdc ≤ VCC ≤ 30 Vdc, with the inputs over the full common mode range
(0 Vdc to VCC –1.5 Vdc).
5. The bias current flows out of the inputs due to the PNP input stage. This current is virtually constant, independent of the output state.
6. The response time specified is for a 100 mV input step with 5.0 mV overdrive. For larger signals, 300 ns is typical.

Figure 2. Inverting Comparator Figure 3. Noninverting Comparator

with Hystersis with Hysteresis
+ VCC + VCC
R3
10 k Rref
10 k
Vin – Vref
Rref VO 10 k
+ VCC +
R1 –
R2 R2 VO
Vref Vin +
1.0 M 10 k
10k R1
[ RVCC+R1R1
Vref R3
Vref =
VCC R1
ref
R3 ] R1 / / Rref / / R2
1.0 M Rref + R1
R1 / / Rref
R2 [ R1 / / Rref
VH = [VO(max) – VO(min)] Amount of Hysteresis VH
R1/ / Rref + R2
R2
R2 ơ Rref / / R1 VH = [(V –V
R2 + R3 O(max) O(min)
]
Typical Characteristics
(VCC = 15 Vdc, TA = +25°C (each comparator) unless otherwise noted.)
Figure 4. Normalized Input Offset Voltage Figure 5. Input Bias Current

1.40 48
NORMALIZED OFFSET VOLTAGE
42
I IB, INPUT BIAS CURRENT (nA)
1.20 36 TA = –55° C
TA = +25° C
30
1.00 24 TA = +125°C
18
0.80 12
6.0
0.60 0
–50 –25 0 25 50 75 100 125 0 4.0 8.0 12 16 20 24 28 32
TA, AMBIENT TEMPERATURE (°C) VCC, POWER SUPPLY VOLTAGE (Vdc)
Figure 6. Output Sink Current versus

Output Saturation Voltage
8.0
7.0
IO, OUTPUT CURRENT (mA)
TA = +25° C
6.0 TA = –55° C
5.0
TA = +125°C
4.0
3.0
2.0
1.0
0
0 100 200 300 400 500
Vsat, OUTPUT SATURATION VOLTAGE (mV)

Figure 7. Driving Logic Figure 8. Squarewave Oscillator
VCC VCC ≥ 4.0 V
10 k
100 k
RS RL
Vin + R1
–
Vref – +
C VO
R1 +
VCC
R2 R3
VCC
330 k 330 k
]
RS = Source Resistance T1
R1 RS R4 330 k T2
T1 = T2 = 0.69 RC
VCC RL
Logic Device (V) kΩ f [ 7.2
C(µF)
CMOS 1/4 MC14001 +15 100
R2 = R3 = R4
TTL 1/4 MC7400 +5.0 10
[
R1 R2 // R3 // R4
These quad comparators feature high gain, wide of positive feedback (< 10 mV) is also recommended. It is
bandwidth characteristics. This gives the device oscillation good design practice to ground all unused input pins.
tendencies if the outputs are capacitively coupled to the Differential input voltages may be larger than supply
inputs via stray capacitance. This oscillation manifests itself voltages without damaging the comparator’s inputs. Voltages
during output transitions (VOL to VOH). To alleviate this more negative than –300 mV should not be used.
situation input resistors < 10 kΩ should be used. The addition
Figure 9. Zero Crossing Detector Figure 10. Zero Crossing Detector

(Single Supply) (Split Supplies)
+15 V Vin(min) ≈ 0.4 V peak for 1% phase distortion (∆Θ).
Vin(min)
Vin
R1 R4 R5
220 k 220 k 10 k
*
8.2 k
Vin VCC Θ
D1
6.8 k
R2 ) VO
* 10 k
VO
Vin + VCC
15 k 10 M
R3
VO Θ
VEE
D1 prevents input from going negative by more than 0.6 V. ∆Θ
VEE
R1 + R2 = R3
R5
R3 ≤ for small error in zero crossing
10

LM348
Differential Input
Operational Amplifier DIFFERENTIAL INPUT
The LM348 is a true quad MC1741. Integrated on a single monolithic chip OPERATIONAL AMPLIFIER
are four independent, low power operational amplifiers which have been
designed to provide operating characteristics identical to those of the
industry standard MC1741, and can be applied with no change in circuit SEMICONDUCTOR
performance. In addition, the total supply current for all four amplifiers is TECHNICAL DATA
comparable to the supply current of a single MC1741. Other features include
input offset currents and input bias currents which are much less than the
MC1741 industry standard.
The LM348 can be used in applications where amplifier matching or high
packing density is important. Other applications include high impedance
buffer amplifiers and active filter amplifiers.
• Each Amplifier is Functionally Equivalent to the MC1741 14
• Low Input Offset and Input Bias Currents 1
• Class AB Output Stage Eliminates Crossover Distortion

• Pin Compatible with MC3403 and LM324
D SUFFIX
• True Differential Inputs PLASTIC PACKAGE
• Internally Frequency Compensated CASE 751A
(SO–14)
• Short Circuit Protection
• Low Power Supply Current (0.6 mA/Amplifier)
PIN CONNECTIONS
Out 1 1 14 Out 4
2
* * 13
Representative Schematic Diagram Inputs 1
3
) 1
)
4
12
Inputs 4
(1/4 of Circuit Shown)
VCC 4 11 VEE
VCC
5
) ) 10
Noninverting
Inputs 2
6
* 2 3
* 9
Inputs 3
Input 4.5 k
25 Out 2 7 8 Out 3
39 k
30 pF
Inverting 7.5 k Output
Input (Top View)
50
10 k 50 k 1.0 k 5.0 k 50 k 50 Operating
VEE Device Temperature Range Package
LM348D TA = 0° to +70°C SO–14

LM348

Power Supply Voltage VCC +18 Vdc
VEE –18

Input Common Mode Voltage VICM ±18 V
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Input Offset Voltage (RS ≤ 10 k) VIO – 1.0 6.0 mV
Input Offset Current IIO – 4.0 50 nA
Input Bias Current IIB – 30 200
Input Resistance ri 0.8 2.5 – MΩ
Common Mode Input Voltage Range VICR ±12 – – V
Large Signal Voltage Gain (RL ≥ 2.0 k, VO = ±10 V) AVOL 25 160 – V/mV
Channel Separation (f = 1.0 Hz to 20 kHz) – – –120 – dB
Common Mode Rejection (RS ≤ 10 k) CMR 70 90 – dB
Supply Voltage Rejection (RS ≤ 10 k) PSR 77 96 –
Output Voltage Swing VO V
(RL ≥ 10 k) ±12 ±13 –
(RL ≥ 2.0 k) ±10 ±12 –
Output Short Circuit Current ISC – 25 – mA
Supply Current (All Amplifiers) ID – 2.4 4.5 mA
Small Signal Bandwidth (AV = 1) BW – 1.0 – MHz
Phase Margin (AV = 1) φm – 60 – Degrees
Slew Rate (AV = 1) SR – 0.5 – V/µs
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = *Thigh to Tlow, unless otherwise noted.)
Input Offset Voltage (RS ≤ 10 kΩ) VIO – – 7.5 mV
Input Offset Current IIO – – 100 nA
Input Bias Current IIB – – 400
Common Mode Input Voltage Range VICR ±12 – – V
Large Signal Voltage Gain (RL ≥ 2 k, VO = ±10 V) AVOL 15 – – V/mV
Supply Voltage Rejection (RS ≤ 10 k) PSR 77 96 –
(RL ≥ 10 k) ±12 ±13 –
(RL ≥ 2 k) ±10 ±12 –
* Thigh = 70°C. Tlow = 0°C.
NOTE: Any of the amplifier outputs can be shorted to ground indefinitely; however, more than one should not be simultaneously shorted or the maximum
junction temperature will be exceeded.

LM348
Figure 1. Power Bandwidth

(Large Signal Swing versus Frequency) Figure 2. Open Loop Frequency Response
28 120
24 100
VO, OUTPUT VOLTAGE (Vpp )
A vol, VOLTAGE GAIN (dB)

20 80
16 60
12 40
Voltage Follower
8.0 THD < 5% 20
4.0 0
0 –20
10 100 1.0 k 10 k 100 k 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
Figure 3. Positive Output Voltage Swing Figure 4. Negative Output Voltage Swing
versus Load Resistance versus Load Resistance
15 –15
14 –14
13 ±15 V Supplies –13
±15 V Supplies
12 –12
11 –11
10 ±12 V –10 ±12 V
9.0 –9.0
8.0 –8.0
7.0 ± 9.0 V –7.0
± 9.0 V
6.0 –6.0
5.0 –5.0
4.0 ± 6.0 V –4.0 ± 6.0 V
3.0 –3.0
2.0 –2.0
1.0 –1.0
100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 k 100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 k
RL, LOAD RESISTANCE (Ω) RL, LOAD RESISTANCE (Ω)
Figure 5. Output Voltage Swing versus

Load Resistance (Single Supply Operation)
28
30 V
26
VO, OUTPUT VOLTAGE SWING (Vpp )
24 27 V
22
20 24 V
18 21 V
16
SUPPLY
14 18 V
12 15 V
10
8.0 12 V
6.0
9.0 V
4.0
2.0 6.0 V
0 5.0 V
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
RL, LOAD RESISTANCE (kW)

LM348
Figure 7. Open Loop Voltage Gain

Figure 6. Noninverting Pulse Response versus Supply Voltage
105
100

95
5.0 V/DIV
Output 90
85
80
Input
75
70
10 µs/DIV 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
VCC, |VEE|, SUPPLY VOLTAGES (V)
50 k
R1
VCC
VCC
R2 5.0 k
– 10 k VCC
1/2 VO Vref –
MC1403 + 1/4 VO
2.5 V + 1
1 fo =
Vref = VCC 2π RC
R1 2
VO = 2.5 V (1 + ) For: fo = 1 kHz
R2
R R C R = 16 kW
C C = 0.01 µF
1
e1 + C R R Hysteresis
R2
1/4
VOH
–
R1 VO
Vref +
a R1 – 1/4
R1 eo VO
1/4 Vin –
+ VOL
Vin L Vin H
b R1
1 Vref
– C R R1
Vin L =
1/4 R1 + R2 (VOL – Vref) + Vref
e2 + R1
R Vin H = (V – V ) + Vref
R1 + R2 OH ref
R1
H=
R1 + R2 (VOH – VOL)
eo = C (1 + a + b) (e2 – e1)

LM348
Figure 12. High Impedance Instrumentation Buffer/Filter
+
1/4
– R4 C1
R1
– R5 R6
1/4 +
VID
C2 1/4
+
–
–
R2
1/4
+ R3
Figure 13. Function Generator
Triangle Wave R2
1 Output
Vref = VCC 300 k
2
Vref + R3
1/4 +
75 k R1 1/4 Square Wave
–
100 k – Output
Vref
C
Rf
R1 + RC R2 R1
f= if R3 =
4 CRf R1 R2 + R1
R 1
fo =
R 100 k 2 π RC
R1 = QR
C1 R2 C
Vin –
C R2 = R1
R TBP
1/4 – 100 k R3 = TN R2
1/4 –
+ C1 = 10C
1/4
+
+ For : fo = 1.0 kHz
Vref
Vref Q = 10
Vref Bandpass R3
R1 Output TBP = 1
R2 TN = 1
– C1
R = 160 kΩ 1/4 Notch Output
C = 0.001 µF Vref = 1 VCC
R1 = 1.6 MΩ 2 + Where: TBP = Center Frequency Gain
R2 = 1.6 MΩ TN = Passband Notch Gain
R3 = 1.6 MΩ Vref

LM348
Figure 15. Absolute Value DVM Front End
0.5 µF
500 k
MSD6150 500 k
–
1
1/4
900 k 1.0 k + 0.5 µF

2 MC1505
+ 1.0 k 1.0 M
MSD6102
1/4 –
47 k Common Mode Adjust
100 k – 1/4 –
VCC 100 k +
+ 1/4 Polarity
–
+
10 M
500 k
Bridge Null Adjust LM348 Quad Op Amp
VEE

LM358, LM258,
LM2904, LM2904V
Dual Low Power

Utilizing the circuit designs perfected for recently introduced Quad
DUAL DIFFERENTIAL INPUT
Operational Amplifiers, these dual operational amplifiers feature 1) low OPERATIONAL AMPLIFIERS
power drain, 2) a common mode input voltage range extending to
ground/VEE, 3) single supply or split supply operation and 4) pinouts
compatible with the popular MC1558 dual operational amplifier. The LM158 SEMICONDUCTOR
series is equivalent to one–half of an LM124. TECHNICAL DATA
These amplifiers have several distinct advantages over standard
operational amplifier types in single supply applications. They can operate at
supply voltages as low as 3.0 V or as high as 32 V, with quiescent currents
about one–fifth of those associated with the MC1741 (on a per amplifier
basis). The common mode input range includes the negative supply, thereby
eliminating the necessity for external biasing components in many
applications. The output voltage range also includes the negative power 8
1
supply voltage.
• Short Circuit Protected Outputs
N SUFFIX
PLASTIC PACKAGE
• True Differential Input Stage CASE 626
• Single Supply Operation: 3.0 V to 32 V
• Low Input Bias Currents 8
• Internally Compensated 1
• Common Mode Range Extends to Negative Supply D SUFFIX

PLASTIC PACKAGE
• Single and Split Supply Operation CASE 751
• Similar Performance to the Popular MC1558 (SO–8)
• ESD Clamps on the Inputs Increase Ruggedness of the Device without

Affecting Operation
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) PIN CONNECTIONS

LM258 LM2904
Rating Symbol LM358 LM2904V Unit
Output A 1 8 VCC
Power Supply Voltages Vdc 2
–
7 Output B
Single Supply VCC 32 26 Inputs A +
3 6
Split Supplies VCC, VEE ±16 ±13 –
+ 5 Inputs B
VEE/Gnd 4
Input Differential Voltage VIDR ±32 ±26 Vdc
Range (Note 1) (Top View)
Input Common Mode Voltage VICR –0.3 to 32 –0.3 to 26 Vdc

Range (Note 2)
Operating
Junction Temperature TJ 150 °C Device Temperature Range Package
Storage Temperature Range Tstg –55 to +125 °C LM2904D SO–8
TA = –40° to +105°C
Operating Ambient Temperature TA °C LM2904N Plastic DIP
Range
LM258 –25 to +85 – LM2904VD SO–8
TA = –40° to +125°C
LM358 0 to +70 – LM2904VN Plastic DIP
LM2904 – –40 to +105
LM2904V – –40 to +125 LM258D SO–8
TA = –25° to +85°C
NOTES: 1. Split Power Supplies. LM258N Plastic DIP
2. For Supply Voltages less than 32 V for the LM258/358 and 26 V for the LM2904, the
absolute maximum input voltage is equal to the supply voltage. LM358D SO–8
TA = 0° to +70°C
LM358N Plastic DIP

LM358, LM258, LM2904, LM2904V
LM258 LM358 LM2904 LM2904V
Input Offset Voltage VIO mV
VCC = 5.0 V to 30 V (26 V for
LM2904, V), VIC = 0 V to VCC –1.7 V,
VO ] 1.4 V, RS = 0 Ω
TA = 25°C – 2.0 5.0 – 2.0 7.0 – 2.0 7.0 – – –
TA = Thigh (Note 1) – – 7.0 – – 9.0 – – 10 – – 13
TA = Tlow (Note 1) – – 2.0 – – 9.0 – – 10 – – 10
Average Temperature Coefficient of Input ∆VIO/∆T – 7.0 – – 7.0 – – 7.0 – – 7.0 – µV/°C
Offset Voltage
TA = Thigh to Tlow (Note 1)
Input Offset Current IIO – 3.0 30 – 5.0 50 – 5.0 50 – 5.0 50 nA
TA = Thigh to Tlow (Note 1) – – 100 – – 150 – 45 200 – 45 200
Input Bias Current IIB – –45 –150 – –45 –250 – –45 –250 – –45 –250
TA = Thigh to Tlow (Note 1) – –50 –300 – –50 –500 – –50 –500 – –50 –500
Average Temperature Coefficient of Input ∆IIO/∆T – 10 – – 10 – – 10 – – 10 – pA/°C
Offset Current
TA = Thigh to Tlow (Note 1)
Input Common Mode Voltage Range VICR V
(Note 2),VCC = 30 V (26 V for LM2904, V) 0 – 28.3 0 – 28.3 0 – 24.3 0 – 24.3
VCC = 30 V (26 V for LM2904, V), 0 – 28 0 – 28 0 – 24 0 – 24
TA = Thigh to Tlow
Differential Input Voltage Range VIDR – – VCC – – VCC – – VCC – – VCC V
Large Signal Open Loop Voltage Gain AVOL V/mV

RL = 2.0 kΩ, VCC = 15 V, For Large VO 50 100 – 25 100 – 25 100 – 25 100 –
Swing,
TA = Thigh to Tlow (Note 1) 25 – – 15 – – 15 – – 15 – –
Channel Separation CS – –120 – – –120 – – –120 – – –120 – dB
1.0 kHz ≤ f ≤ 20 kHz, Input Referenced
Common Mode Rejection CMR 70 85 – 65 70 – 50 70 – 50 70 – dB
RS ≤ 10 kΩ
Power Supply Rejection PSR 65 100 – 65 100 – 50 100 – 50 100 – dB
Output Voltage–High Limit (TA = Thigh to VOH V

Tlow) (Note 1)
VCC = 5.0 V, RL = 2.0 kΩ, TA = 25°C 3.3 3.5 – 3.3 3.5 – 3.3 3.5 – 3.3 3.5 –
VCC = 30 V (26 V for LM2904, V), 26 – – 26 – – 22 – – 22 – –
RL = 2.0 kΩ
VCC = 30 V (26 V for LM2904, V), 27 28 – 27 28 – 23 24 – 23 24 –
RL = 10 kΩ
Output Voltage–Low Limit VOL – 5.0 20 – 5.0 20 – 5.0 20 – 5.0 20 mV
VCC = 5.0 V, RL = 10 kΩ, TA = Thigh to
Tlow (Note 1)
Output Source Current IO + 20 40 – 20 40 – 20 40 – 20 40 – mA
VID = +1.0 V, VCC = 15 V
Output Sink Current IO –
VID = –1.0 V, VCC = 15 V 10 20 – 10 20 – 10 20 – 10 20 – mA
VID = –1.0 V, VO = 200 mV 12 50 – 12 50 – – – – – – – µA
Output Short Circuit to Ground (Note 3) ISC – 40 60 – 40 60 – 40 60 – 40 60 mA
Power Supply Current (TA = Thigh to Tlow) ICC mA

(Note 1)
VCC = 30 V (26 V for LM2904, V), – 1.5 3.0 – 1.5 3.0 – 1.5 3.0 – 1.5 3.0
VO = 0 V, RL = ∞
VCC = 5 V, VO = 0 V, RL = ∞ – 0.7 1.2 – 0.7 1.2 – 0.7 1.2 – 0.7 1.2

= –40°C for LM2904V = +125°C for LM2904V
= –25°C for LM258 = +85°C for LM258
= 0°C for LM358 = +70°C for LM358
2. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common
mode voltage range is VCC –1.7 V.
3. Short circuits from the output to VCC can cause excessive heating and eventual destruction. Destructive dissipation can result from simultaneous shorts
on all amplifiers.

LM358, LM258, LM2904, LM2904V

3.0 V to VCC(max)
VCC VCC
1.5 V to VCC(max)
1 1
2 2
1.5 V to VEE(max)
VEE
VEE/Gnd

(One–Half of Circuit Shown) Bias Circuitry
Common to Both
Output Amplifiers
VCC
Q15
Q16 Q14 Q22
Q13
40 k
Q19
5.0 pF Q12 Q24

25 Q23
Q18 Q20
Inputs
Q11
Q9
Q17 Q21
Q6 Q7 Q25
Q2 Q5 Q1 2.4 k
Q8 Q10
Q3 Q4 Q26
2.0 k
VEE/Gnd
CIRCUIT DESCRIPTION
The LM258 series is made using two internally
compensated, two–stage operational amplifiers. The first
stage of each consists of differential input devices Q20 and Large Signal Voltage
Q18 with input buffer transistors Q21 and Q17 and the Follower Response
differential to single ended converter Q3 and Q4. The first
VCC = 15 Vdc
stage performs not only the first stage gain function but also RL = 2.0 kΩ
performs the level shifting and transconductance reduction TA = 25°C
1.0 V/DIV

second stage consists of a standard current source load
amplifier stage.
5.0 µs/DIV
Each amplifier is biased from an internal–voltage regulator
which has a low temperature coefficient thus giving each
amplifier good temperature characteristics as well as
excellent power supply rejection.

LM358, LM258, LM2904, LM2904V
Figure 1. Input Voltage Range Figure 2. Large–Signal Open Loop Voltage Gain
20 120
AVOL, OPEN LOOP VOLTAGE GAIN (dB)

18
100 VCC = 15 V
VI , INPUT VOLTAGE (V)
16 VEE = Gnd
TA = 25°C
14 80
12
60
10
Negative 40
8.0
Positive
6.0 20
4.0
0
2.0
0 –20
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 1.0 10 100 1.0 k 10 k 100 k 1.0 M
VCC/VEE, POWER SUPPLY VOLTAGES (V) f, FREQUENCY (Hz)
Figure 4. Small Signal Voltage Follower

Figure 3. Large–Signal Frequency Response Pulse Response (Noninverting)
14 550
VCC = 30 V
VOR , OUTPUT VOLTAGE RANGE (Vpp )
RL = 2.0 kΩ VEE = Gnd

12 500
VO , OUTPUT VOLTAGE (mV)
VCC = 15 V TA = 25°C
Input
VEE = Gnd 450 CL = 50 pF
10 Gain = –100
RI = 1.0 kΩ 400
8.0 RF = 100 kΩ Output
350
6.0
300
4.0
250
2.0
200
0 0
1.0 10 100 1000 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
f, FREQUENCY (kHz) t, TIME (ms)
Figure 5. Power Supply Current versus Figure 6. Input Bias Current versus
Power Supply Voltage Supply Voltage
2.4
ICC , POWER SUPPLY CURRENT (mA)
2.1
RL = R
TA = 25°C
90
1.8
1.5
1.2
0.9 80
0.6
0.3
0 70
0 5.0 10 15 20 25 30 35 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
VCC, POWER SUPPLY VOLTAGE (V) VCC, POWER SUPPLY VOLTAGE (V)

LM358, LM258, LM2904, LM2904V

50 k
R1
VCC
VCC 5.0 k
R2 –
10 k VCC
1/2 –
VO Vref 1/2
LM358 VO
MC1403 LM358
+
2.5 V + 1
fo =
1 2 π RC
Vref = VCC
2
For: fo = 1.0 kHz
R1 R = 16 kΩ
VO = 2.5 V (1 + ) R C
R2 R C = 0.01 µF
C
+ 1
e1
1/2 CR R
LM358 R2 Hysteresis
– VOH
R1 VO
– Vref +
a R1 1/2
R1 eo 1/2
LM358 LM358
+ Vin – VO
b R1 VOL
1 VinL VinH
– CR
1/2 R1 Vref
VinL = (V – V )+ V
LM358 R1 + R2 OL ref ref
e2 + R R1
VinH = (V – V ) + Vref
R1 + R2 OH ref
eo = C (1 + a + b) (e2 – e1) R1
H= (VOH – VOL)
R1 + R2

1
R fo = 2 π RC
R 100 k
R1 = QR
1
Vin C1 R2 Vref = VCC
–
C C R2 = R1 2
1/2 R TBP
– 100 k
LM358 1/2 R3 = TN R2
+ –
LM358 1/2 C1 = 10 C
+ LM358
Vref + For: fo = 1.0 kHz
Bandpass Vref Q = 10
Vref R3 TBP = 1
Output
R1 TN = 1
R2 – C1
1/2
LM358 Notch Output R = 160 kΩ
+ C = 0.001 µF
R1 = 1.6 MΩ
Vref Where: TBP = Center Frequency Gain R2 = 1.6 MΩ
TN = Passband Notch Gain R3 = 1.6 MΩ

LM358, LM258, LM2904, LM2904V
1 Triangle Wave
Vref = VCC R2 VCC
2 Output
300 k C R3
Vref + R1 C
1/2 R3 Vin –
+ 1/2
LM358 75 k 1/2 VO
– LM358
R1 100 k LM358 Square
– + CO
Wave R2
CO = 10 C
Vref Output
C Vref 1
Vref = 2 VCC
Rf
R1 + RC R2 R1
f = if, R3 = Given: fo = center frequency
4 CRf R1 R2 + R1
Choose value fo, C

Q
Then: R3 =
π fo C
R3
R1 =
2 A(fo)
R1 R3
R2 =
4Q2 R1 –R3
Qo fo
For less than 10% error from operational amplifier. < 0.1
BW
Where fo and BW are expressed in Hz.
If source impedance varies, filter may be preceded with voltage

follower buffer to stabilize filter parameters.

LM393, LM393A,
LM293, LM2903,
LM2903V
Low Offset Voltage
Dual Comparators SINGLE SUPPLY, LOW POWER
The LM393 series are dual independent precision voltage comparators DUAL COMPARATORS
capable of single or split supply operation. These devices are designed to
permit a common mode range–to–ground level with single supply operation.
Input offset voltage specifications as low as 2.0 mV make this device an SEMICONDUCTOR
excellent selection for many applications in consumer automotive, and TECHNICAL DATA
industrial electronics.
• Wide Single–Supply Range: 2.0 Vdc to 36 Vdc
• Split–Supply Range: ±1.0 Vdc to ±18 Vdc
• Very Low Current Drain Independent of Supply Voltage: 0.4 mA
• Low Input Bias Current: 25 nA
•
8
Low Input Offset Current: 5.0 nA 1
• Low Input Offset Voltage: 2.0 mV (max) LM393A N SUFFIX
5.0 mV (max) LM293/393 PLASTIC PACKAGE
• Input Common Mode Range to Ground Level CASE 626
• Differential Input Voltage Range Equal to Power Supply Voltage

• Output Voltage Compatible with DTL, ECL, TTL, MOS, and CMOS Logic
Levels
•
8
ESD Clamps on the Inputs Increase the Ruggedness of the Device 1
without Affecting Performance
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
Representative Schematic Diagram PIN CONNECTIONS

(Diagram shown is for 1 comparator)
Output A 1 8 VCC
VCC + Input – Input Output 2 7 Output B
–
Inputs A 3
+ 6
–
+ 5 Inputs B
Gnd 4
R2
2.1 k
(Top View)
Q4
R4 Q5 Q6
Q3 Q14
2.0 k
F1
Operating
LM293D TA = –25° to +85°C SO–8
Q10
Q1 Q9 Q16 LM393D SO–8
Q8 Q12 TA = 0° to +70°C
Q2 LM393AN,N Plastic DIP
Q15
Q11 LM2903D SO–8
R1 TA = –40° to +105°C
4.6 k LM2903N Plastic DIP
LM2903VD SO–8
TA = –40° to +105°C
LM2903VN Plastic DIP

LM393, LM393A, LM293, LM2903, LM2903V
MAXIMUM RATINGS
Power Supply Voltage VCC +36 or ±18 Vdc
Input Differential Voltage Range VIDR 36 Vdc
Input Common Mode Voltage Range VICR –0.3 to +36 Vdc
Output Short Circuit–to–Ground ISC Continuous mA
Output Sink Current (Note 1) ISink 20
Power Dissipation @ TA = 25°C PD 570 mW
Derate above 25°C 1/RθJA 5.7 mW/°C
Operating Ambient Temperature Range TA °C
LM293 –25 to +85
LM393, 393A 0 to +70
LM2903 –40 to +105
LM2903V –40 to +125
Maximum Operating Junction Temperature TJ(max) °C
LM393, 393A, 2903, LM2903V 125
LM293 150
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, Tlow ≤ TA ≤ Thigh,* unless otherwise noted.)
LM393A
TA = 25°C – ±1.0 ±2.0
Tlow ≤ TA ≤ Thigh – – 4.0
Input Offset Current IIO nA
TA = 25°C – ±50 ±50
Tlow ≤ TA ≤ Thigh – – ±150
Input Bias Current (Note 3) IIB nA
TA = 25°C – 25 250
Tlow ≤ TA ≤ Thigh – – 400
Input Common Mode Voltage Range (Note 4) VICR V
TA = 25°C 0 – VCC –1.5
Tlow ≤ TA ≤ Thigh 0 – VCC –2.0
Voltage Gain RL ≥ 15 kΩ, VCC = 15 Vdc, TA = 25°C AVOL 50 200 – V/mV
Large Signal Response Time – – 300 – ns
Vin = TTL Logic Swing, Vref = 1.4 Vdc
VRL = 5.0 Vdc, RL = 5.1 kΩ, TA = 25°C
Response Time (Note 5) VRL = 5.0 Vdc, RL = 5.1 kΩ, TA = 25°C tTLH – 1.3 – µs
Input Differential Voltage (Note 6) VID – – VCC V
All Vin ≥ Gnd or V– Supply (if used)
Output Sink Current ISink 6.0 16 – mA

Vin ≥ 1.0 Vdc, Vin+ = 0 Vdc, VO ≤ 1.5 Vdc, TA = 25°C
Output Saturation Voltage VOL mV

Vin ≥ 1.0 Vdc, Vin+ = 0 Vdc, ISink ≤ 4.0 mA, TA = 25°C – 150 400
* Tlow = 0°C, Thigh = +70°C for LM393/393A
NOTES: 1. The maximum output current may be as high as 20 mA, independent of the magnitude of VCC, output short circuits to VCC can cause excessive
]
heating and eventual destruction.
2. At output switch point, VO 1.4 Vdc, RS = 0 Ω with VCC from 5.0 Vdc to 30 Vdc, and over the full input common mode range (0 V to VCC = –1.5 V).
3. Due to the PNP transistor inputs, bias current will flow out of the inputs. This current is essentially constant, independent of the output state, there
fore, no loading changes will exist on the input lines.
4. Input common mode of either input should not be permitted to go more than 0.3 V negative of ground or minus supply. The upper limit of common
mode range is VCC –1.5 V.
5. Response time is specified with a 100 mV step and 5.0 mV of overdrive. With larger magnitudes of overdrive faster response times are obtainable.
6. The comparator will exhibit proper output state if one of the inputs becomes greater than VCC, the other input must remain within the common mode
range. The low input state must not be less than –0.3 V of ground or minus supply.

LM393, LM393A, LM293, LM2903, LM2903V
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, Tlow ≤ TA ≤ Thigh,* unless otherwise noted.)
LM393A
Output Leakage Current IOL µA
Vin– = 0 V, Vin+ ≥ 1.0 Vdc, VO = 5.0 Vdc, TA= 25°C – 0.1 –
Vin– = 0 V, Vin+ ≥ 1.0 Vdc, VO = 30 Vdc, Tlow ≤ TA ≤ Thigh – – 1.0
RL = ∞ Both Comparators, TA = 25°C – 0.4 1.0
RL = ∞ Both Comparators, VCC = 30 V – 1.0 2.5
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, Tlow ≤ TA ≤ Thigh, unless otherwise noted.)
LM392, LM393 LM2903, LM2903V
TA = 25°C – ±1.0 ±5.0 – ±2.0 ±7.0
Tlow ≤ TA ≤ Thigh – – 9.0 – 9.0 15
TA = 25°C – ±5.0 ±50 – ±5.0 ±50
Tlow ≤ TA ≤ Thigh – – ±150 – ±50 ±200
Input Bias Current (Note 3) IIB nA
TA = 25°C – 25 250 – 25 250
Tlow ≤ TA ≤ Thigh – – 400 – 200 500
Input Common Mode Voltage Range (Note 3) VICR V
TA = 25°C 0 – VCC –1.5 0 – VCC –1.5
Tlow ≤ TA ≤ Thigh 0 – VCC –2.0 0 – VCC –2.0
Voltage Gain AVOL 50 200 – 25 200 – V/mV
RL ≥ 15 kΩ, VCC = 15 Vdc, TA = 25°C
Large Signal Response Time – – 300 – – 300 – ns
Vin = TTL Logic Swing, Vref = 1.4 Vdc
VRL = 5.0 Vdc, RL = 5.1 kΩ, TA = 25°C
Response Time (Note 5) tTLH – 1.3 – – 1.5 – µs
VRL = 5.0 Vdc, RL = 5.1 kΩ, TA = 25°C
Input Differential Voltage (Note 6) VID – – VCC – – VCC V
All Vin ≥ Gnd or V– Supply (if used)
Output Sink Current ISink 6.0 16 – 6.0 16 – mA
Vin ≥ 1.0 Vdc, Vin+ = 0 Vdc, VO ≤ 1.5 Vdc TA = 25°C
Output Saturation Voltage VOL mV
Vin ≥ 1.0 Vdc, Vin+ = 0, ISink ≤ 4.0 mA, TA = 25°C – 150 400 – – 400
Tlow ≤ TA ≤ Thigh – – 700 – 200 700
Output Leakage Current IOL nA
Vin– = 0 V, Vin+ ≥ 1.0 Vdc, VO = 5.0 Vdc, TA = 25°C – 0.1 – – 0.1 –
Vin– = 0 V, Vin+ ≥ 1.0 Vdc, VO = 30 Vdc,
Tlow ≤ TA ≤ Thigh – – 1000 – – 1000
RL = ∞ Both Comparators, TA = 25°C – 0.4 1.0 – 0.4 1.0
RL = ∞ Both Comparators, VCC = 30 V – – 2.5 – – 2.5
* Tlow = 0°C, Thigh = +70°C for LM393/393A
LM293 Tlow = –25°C, Thigh = +85°C
LM2903 Tlow = –40°C, Thigh = +105°C
LM2903V Tlow = –40°C, Thigh = +125°C
]
NOTES: 2. At output switch point, VO 1.4 Vdc, RS = 0 Ω with VCC from 5.0 Vdc to 30 Vdc, and over the full input common mode range (0 V to VCC = –1.5 V).
3. Due to the PNP transistor inputs, bias current will flow out of the inputs. This current is essentially constant, independent of the output state, there
fore, no loading changes will exist on the input lines.
5. Response time is specified with a 100 mV step and 5.0 mV of overdrive. With larger magnitudes of overdrive faster response times are obtainable.
6. The comparator will exhibit proper output state if one of the inputs becomes greater than VCC, the other input must remain within the common mode
range. The low input state must not be less than –0.3 V of ground or minus supply.

LM393, LM393A, LM293, LM2903, LM2903V
LM293/393,A LM2903
Figure 1. Input Bias Current versus Figure 2. Input Bias Current versus
80 80
TA = –40° C
IIB , INPUT BIAS CURRENT (nA)
70

70
60 60
TA = –55° C
50 50 TA = 0° C
TA = 0° C
40 40 TA = +25° C
TA = +25° C
30 TA = +70° C 30
TA = +85° C
20 20
TA = +125°C
10 10
0 0
0 5.0 10 15 20 25 30 35 40 0 5.0 10 15 20 25 30 35 40
VCC, SUPPLY VOLTAGE (Vdc) VCC, SUPPLY VOLTAGE (Vdc)
Figure 3. Output Saturation Voltage Figure 4. Output Saturation Voltage

versus Output Sink Current versus Output Sink Current
10 10
Out of Out of
VOL , SATURATION VOLTAGE (Vdc)
VOL , SATURATION VOLTAGE (Vdc)

Saturation Saturation
1.0 1.0
TA = +125°C
TA = +85° C
0.1 0.1
TA = +25° C TA = –55° C TA = +25° C
0.01 0.01
TA = 0° C
TA = –40° C
0.001 0.001
0.01 0.1 1.0 10 100 0.01 0.1 1.0 10 100
ISink, OUTPUT SINK CURRENT (mA) ISink, OUTPUT SINK CURRENT (mA)
Figure 5. Power Supply Current versus Figure 6. Power Supply Current versus
1.0
TA = –55° C TA = –40° C
ICC , SUPPLY CURRENT (mA)
1.2
0.8 TA = 0° C
TA = +25° C TA = 0° C
1.0
TA = +25° C
0.6
TA = +70° C 0.8
0.4 TA = +125°C
TA = +85° C
0.6
0.2
RL = R 0.4
RL = R
0
5.0 10 15 20 25 30 35 40 0 5.0 10 15 20 25 30 35 40
VCC, SUPPLY VOLTAGE (Vdc) VCC, SUPPLY VOLTAGE (Vdc)

LM393, LM393A, LM293, LM2903, LM2903V
These dual comparators feature high gain, wide The addition of positive feedback (< 10 mV) is also
bandwidth characteristics. This gives the device oscillation recommended. It is good design practice to ground all
tendencies if the outputs are capacitively coupled to the unused pins.
inputs via stray capacitance. This oscillation manifests itself Differential input voltages may be larger than supply
during output transitions (VOL to VOH). To alleviate this voltage without damaging the comparator’s inputs. Voltages
situation, input resistors < 10 kΩ should be used. more negative than –0.3 V should not be used.
Figure 7. Zero Crossing Detector Figure 8. Zero Crossing Detector

(Single Supply) (Split Supply)
+15 V
Vin(min)
Vin
R1 R4 R5
220 k 220 k 10 k
*
8.2 k
Vin +VCC Θ
R1
)
6.8 k LM393
D1 R2
*LM393 10 k
15 k 10 M
Vin
) VCC
R3
VO Θ
–VEE
D1 prevents input from going negative by more than 0.6 V. ∆Θ
– VEE
R5
R1 + R2 = R3
Vin(min) [ 0.4 V peak for 1% phase distortion (∆Θ).
R3 ≤ for small error in zero crossing.
10
Figure 9. Free–Running Square–Wave Oscillator Figure 10. Time Delay Generator

1.0 MΩ VCC VCC
VCC
RL t R RL
– 10 k
VCC 0.001 µF LM393 – –
VO LM393 LM393
+ + VC C + VO
51 k
+ Vref
51 k
51 k VCC
‘‘ON’’ for t tO + ∆t
VO where: Vin Vref
0 ∆t = RC ȏ n(
Vref
VCC
) VO
0
t 0
VC Vref
ȏ
0
tO t
Figure 11. Comparator with Hysteresis

VCC
RS = R1 | | R2
RS RL
– (VCC –Vref) R1
Vth1 = Vref +
LM393 R1 + R2 + RL
+
(Vref –VO Low) R1
Vth2 = Vref –
R1 R1 + R2
Vref
R2

LM833
Dual Low Noise,

Audio Amplifier
The LM833 is a standard low–cost monolithic dual general–purpose DUAL OPERATIONAL
operational amplifier employing Bipolar technology with innovative
high–performance concepts for audio systems applications. With high AMPLIFIER
frequency PNP transistors, the LM833 offers low voltage noise
(4.5 nV/ Hz ), 15 MHz gain bandwidth product, 7.0 V/µs slew rate, 0.3 mV SEMICONDUCTOR
input offset voltage with 2.0 µV/°C temperature coefficient of input offset TECHNICAL DATA
voltage. The LM833 output stage exhibits no deadband crossover distortion,
large output voltage swing, excellent phase and gain margins, low open loop
high frequency output impedance and symmetrical source/sink AC
frequency response.
The LM833 is specified over the automotive temperature range and is
available in the plastic DIP and SO–8 packages (P and D suffixes). For an
improved performance dual/quad version, see the MC33079 family.
• Low Voltage Noise: 4.5 nV/ ǸHz 8
1
• High Gain Bandwidth Product: 15 MHz
• High Slew Rate: 7.0 V/µs N SUFFIX
•
PLASTIC PACKAGE
Low Input Offset Voltage: 0.3 mV CASE 626
• Low T.C. of Input Offset Voltage: 2.0 µV/°C
• Low Distortion: 0.002%
• Excellent Frequency Stability
8
• Dual Supply Operation 1
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
PIN CONNECTIONS
Output 1 1 8 VCC
MAXIMUM RATINGS
2 1 7 Output 2
Supply Voltage (VCC to VEE) VS +36 V
Inputs 1
Input Differential Voltage Range (Note 1) VIDR 30 V 3 6
Input Voltage Range (Note 1) VIR ±15 V 2 Inputs 2

VEE 4 5
Output Short Circuit Duration (Note 2) tSC Indefinite
Operating Ambient Temperature Range TA –40 to +85 °C (Top View)
Operating Junction Temperature TJ +150 °C
Maximum Power Dissipation (Notes 2 and 3) PD 500 mW
Operating
NOTES: 1. Either or both input voltages must not exceed the magnitude of VCC or VEE. Device Temperature Range Package
(TJ) is not exceeded (see power dissipation performance characteristic). LM833N Plastic DIP
3. Maximum value at TA ≤ 85°C. TA = – 40° to +85°C
LM833D SO–8

LM833
Input Offset Voltage (RS = 10 Ω, VO = 0 V) VIO – 0.3 5.0 mV
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T – 2.0 – µV/°C
RS = 10 Ω, VO = 0 V, TA = Tlow to Thigh
Input Offset Current (VCM = 0 V, VO = 0 V) IIO – 10 200 nA
Input Bias Current (VCM = 0 V, VO = 0 V) IIB – 300 1000 nA
Common Mode Input Voltage Range VICR – +14 +12 V
–12 –14 –
Large Signal Voltage Gain (RL = 2.0 kΩ, VO = ±10 V AVOL 90 110 – dB
Output Voltage Swing: V
RL = 2.0 kΩ, VID = 1.0 V VO+ 10 13.7 –
RL = 2.0 kΩ, VID = 1.0 V VO– – –14.1 –10
RL = 10 kΩ, VID = 1.0 V VO+ 12 13.9 –
RL = 10 kΩ, VID = 1.0 V VO– – –14.7 –12
Common Mode Rejection (Vin = ±12 V) CMR 80 100 – dB
Power Supply Rejection (VS = 15 V to 5.0 V, –15 V to –5.0 V) PSR 80 115 – dB
Power Supply Current (VO = 0 V, Both Amplifiers) ID – 4.0 8.0 mA
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 kΩ, AV = +1.0) SR 5.0 7.0 – V/µs
Gain Bandwidth Product (f = 100 kHz) GBW 10 15 – MHz
Unity Gain Frequency (Open Loop) fU – 9.0 – MHz
Unity Gain Phase Margin (Open Loop) θm – 60 – Deg
Equivalent Input Noise Voltage (RS = 100 Ω, f = 1.0 kHz) en – 4.5 – nVń ǸHz
Equivalent Input Noise Current (f = 1.0 kHz) in – 0.5 – pAń ǸHz
Power Bandwidth (VO = 27 Vpp, RL = 2.0 kΩ, THD ≤ 1.0%) BWP – 120 – kHz
Distortion (RL = 2.0 kΩ, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0) THD – 0.002 – %
Channel Separation (f = 20 Hz to 20 kHz) CS – –120 – dB
Figure 1. Maximum Power Dissipation

versus Temperature Figure 2. Input Bias Current versus Temperature
PD , MAXIMUM POWER DISSIPATION (mW)
800 1000
VCC = +15 V
800 VEE = –15 V
600 VCM = 0 V
600
400
400
200
200
0 0
–50 0 50 100 150 –55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

LM833
Figure 3. Input Bias Current versus Figure 4. Supply Current versus

Supply Voltage Supply Voltage
800 10
VCC
RL = ∞
IS
TA = 25°C 8.0
IS , SUPPLY CURRENT (mA)

TA = 25°C
600
6.0 VO
+
400 VEE
4.0
200
2.0
0 0
5.0 10 15 20 0 5.0 10 15 20
VCC, |VEE|, SUPPLY VOLTAGE (V) VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 5. DC Voltage Gain Figure 6. DC Voltage Gain versus

versus Temperature Supply Voltage
110 110
VCC = +15 V
VEE = –15 V RL = 2.0 kΩ
AVOL, DC VOLTAGE GAIN (dB)
AVOL, DC VOLTAGE GAIN (dB)

RL = 2.0 kΩ TA = 25°C
105
100
100
90
95
90 80
–55 –25 0 25 50 75 100 125 5.0 10 15 20
TA, AMBIENT TEMPERATURE (°C) VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 7. Open Loop Voltage Gain and Figure 8. Gain Bandwidth Product
Phase versus Frequency versus Temperature
120 0 20
GBW, GAIN BANDWIDTH PRODUCT (MHz)

∅ , EXCESS PHASE (DEGREES)
100
45 15
80
Phase 10
60 90
40 VCC = +15 V VCC = +15 V

VEE = –15 V Gain 135 5.0 VEE = –15 V
RL = 2.0 kΩ f = 100 kHz
20 TA = 25°C
0 180 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M –55 –25 0 25 50 75 100 125
f, FREQUENCY (Hz) TA, AMBIENT TEMPERATURE (°C)

LM833
Figure 9. Gain Bandwidth Product versus

Supply Voltage Figure 10. Slew Rate versus Temperature
30 10
f = 100 kHz
TA = 25°C
SR, SLEW RATE (V/ µs)

8.0 Falling
20
Rising
6.0
10 VCC = +15 V
VEE = –15 V –
Vin + VO
4.0 RL = 2.0 kΩ RL
AV = +1.0
0 2.0
5.0 10 15 20 –55 –25 0 25 50 75 100 125
VCC, |VEE|, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 11. Slew Rate versus Supply Voltage Figure 12. Output Voltage versus Frequency
10 35
RL = 2.0k Ω
AV = +1.0
30
8.0 TA = 25°C Falling
SR, SLEW RATE (V/ µ s)
25
6.0 Rising
20
VCC = +15 V
4.0 15 VEE = –15 V
+ VO
v
– RL = 2.0 kΩ
Vin RL 10 THD 1.0%
2.0 TA = 25°C
5.0
0 0
5.0 10 15 20 10 100 1.0 k 10 k 1.0 M 10 M 100 k
VCC, |VEE|, SUPPLY VOLTAGE (V) f, FREQUENCY (Hz)
Figure 13. Maximum Output Voltage Figure 14. Output Saturation Voltage
versus Supply Voltage versus Temperature
20 15
V sat , OUTPUT SATURATION VOLTAGE |V|
RL = 10 kΩ VO +
15 TA = 25°C +Vsat
10
5.0
–Vsat
14
0
–5.0
–10 VCC = +15 V

VO – VEE = –15 V
–15 RL = 10 kΩ
–20 13
5.0 10 15 20 –55 –25 0 25 50 75 100 125

LM833
Figure 15. Power Supply Rejection Figure 16. Common Mode Rejection
140 160

VCC = +15 V ∆VCC ∆VCM –
120 VEE = –15 V – 140 ADM
TA = 25°C ADM + ∆VO
+ ∆VO
100 ∆VEE 120 ∆VCM
CMR = 20 Log × ADM
∆V0
80 100
–PSR +PSR
60 80 VCC = +15 V
∆VO/ADM VEE = –15 V
40 +PSR = 20 Log ( ∆VCC
) 60 VCM = 0 V
∆VCM = ±1.5 V
∆VO/ADM TA = 25°C
20
–PSR = 20 Log ( ∆VEE
) 40
0 20
100 1.0 k 10 k 100 k 1.0 M 10 M 100 1.0 k 10 k 100 k 1.0 M 10 M
Figure 17. Total Harmonic Distortion Figure 18. Input Referred Noise Voltage
THD, TOTAL HARMONIC DISTORTION (%)
1.0 10
–
VCC = +15 V e n, INPUT NOISE VOLTAGE (nV/√ Hz )
VO VEE = –15 V
+
RL RL = 2.0 kΩ
0.1 TA = 25°C 5.0
VCC = +15 V
VEE = –15 V
0.01 VO = 1.0 Vrms RS = 100 Ω
2.0 TA = 25°C
VO = 3.0 Vrms
0.001 1.0
10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k
Figure 19. Input Referred Noise Current Figure 20. Input Referred Noise Voltage
versus Frequency versus Source Resistance
2.0 100
VCC = +15 V
i n , INPUT NOISE CURRENT (pA/√ Hz )
VCC = +15 V
e n, INPUT NOISE VOLTAGE (nV/√ Hz )
VEE = –15 V VEE = –15 V

TA = 25°C Vn(total) = (inRS)2 +en2 + Ǹ
4KTRS
1.0 TA = 25°C
0.7
10
0.5
0.4
0.3
0.2 1.0
10 100 1.0 k 10 k 100 k 1.0 10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz) RS, SOURCE RESISTANCE (Ω)

LM833
Figure 21. Inverting Amplifier Figure 22. Noninverting Amplifier Slew Rate
VCC = +15 V VCC = +15 V

VEE = –15 V VEE = –15 V

RL = 2.0 kΩ RL = 2.0 kΩ
CL = 0 pF CL = 0 pF
AV = –1.0 AV = +1.0
TA = 25°C TA = 25°C
Figure 23. Noninverting Amplifier Overshoot
VCC = +15 V
VEE = –15 V
RL = 2.0 kΩ
CL = 0 pF
AV = +1.0
TA = 25°C
t, TIME (200 ns/DIV)

MC1436, C
High Voltage, Internally

Compensated Operational
Amplifiers
The MC1436, C was designed for use as a summing amplifier, integrator,
or amplifier with operating characteristics as a function of the external
feedback components. SEMICONDUCTOR
• Output Voltage Swing: TECHNICAL DATA
±22 Vpk(min) (VCC = +28 V, VEE = –28 V)
• Fast Slew Rate: 2.0 V/µs Typ
• Offset Voltage Null Capability
• Input Overvoltage Protection
• AVOL: 500,000 Typ 8
• Characteristics Independent of Power Supply Voltages: 1
(±5.0 Vdc to ±36 Vdc) P1 SUFFIX

PLASTIC PACKAGE
CASE 626
Figure 1. Differential Amplifier with ±20 V

8
Common Mode Input Voltage Range
1
R2
D SUFFIX
100 k
PLASTIC PACKAGE
CASE 751
+28 V (SO–8)
R1
10 k 2
VA – 7
6
MC1436 , C
R3 VO = 10 (VB –VA) PIN CONNECTIONS
470 3
VB + 4
Offset Null 1 8 N.C.
R4 –28 V
4.7 k Inv. Input 2 7 VCC
Noninv. Input 3 6 Output

+
Figure 2. Typical Noninverting X10 Voltage Amplifier VEE 4 5 Offset Null
7 +28 V
VI = 4.4 Vpp (Top View)
3
+
6 VO = 44 Vpp
MC1436 , C
_
2
4 –28 V RL ≥ 5.0 k ORDERING INFORMATION
Operating
9.0 k
1.0 k
MC1436CD,D SO–8
TA = 0° to +70°C
MC1436CP1,P1 Plastic DIP

MC1436, C

Rating Symbol MC1436 MC1436C Unit
Power Supply Voltage VCC +34 +30 Vdc
VEE –34 –30
Input Differential Voltage Range VIDR Note 2 V

Input Common Mode Voltage Range VICR Note 2 V
Output Short Circuit Duration tSC 5.0 sec
(VCC = VEE = 28 Vdc, VO = 0)
Power Dissipation (Package Limitation) PD 680 mW

Derate above TA = +25°C 4.6 mW/°C

MC1436 MC1436C
Input Bias Current IIB nAdc
TA = +25°C – 15 40 – 25 90
TA = Tlow to Thigh (See Note 1) – – 55 – – –
Input Offset Current IIO nAdc
TA = +25°C – 5.0 10 – 10 25
TA = +25°C to Thigh – – 14 – – –
TA = Tlow to +25°C – – 14 – – –
Input Offset Voltage VIO mVdc
TA = +25°C – 5.0 10 – 5.0 12
TA = Tlow to Thigh – – 14 – – –
Differential Input Impedance (Open loop, f ≤ 5.0 Hz) MΩ
Parallel Input Resistance rp – 10 – – 10 – pF
Parallel Input Capacitance Cp – 2.0 – – 2.0 –
Common Mode Input Impedance (f ≤ 5.0 Hz) zic – 250 – – 250 – MΩ
Input Common Mode Voltage Range VICR ± 22 ± 25 – ±18 ± 20 – Vpk
Equivalent Input Noise Voltage en nV/(Hz)1/2
(AV = 100, RS = 10 kΩ, f = 1.0 kHz, BW = 1.0 Hz) – 50 – – 50 –
Common Mode Rejection (DC) CMR 70 110 – 50 90 – dB
Large Signal DC Open Loop Voltage Gain AVOL V/V
(VO = ±10 V, RL = 100 kΩ) TA = +25°C 70,000 500,000 – 50,000 500,000 –
TA = Tlow to Thigh 50,000 – – – – –
(VO = ±10 V, RL = 10 kΩ, TA = +25°C) – 200,000 – – 200,000 –
Power Bandwidth (Voltage Follower) BWp kHz
(AV = 1, RL = 5.0 kΩ, THD ≤ 5%, VO = 40 Vpp) – 23 – – 23 –
Unity Gain Crossover Frequency (Open loop) fc – 1.0 – – 1.0 – MHz
Phase Margin (Open loop, Unity Gain) φm – 50 – – 50 – Degrees
Gain Margin AM – 18 – – 18 – dB
Slew Rate (Unity Gain) SR – 2.0 – – 2.0 – V/µs
Output Impedance (f ≤ 5.0 Hz) zO – 1.0 – – 1.0 – kΩ
Short Circuit Output Current ISC – ±17 – – ±19 – mAdc
NOTES: 1. Tlow = 0°C for MC1436,C Thigh = +70°C for MC1436,C
2. Either or both input voltages must not exceed the magnitude of VCC or VEE + 3.0 V.

MC1436, C
MC1436 MC1436C
Output Voltage Range (RL = 5.0 kΩ) VO Vpk
VCC = +28 Vdc, VEE = –28 Vdc ± 20 ± 22 – ± 20 ± 22 –
VCC = +36 Vdc, VEE = –36 Vdc – – – – – –
Power Supply Rejection µV/V
VEE = Constant, Rs ≤ 10 kΩ PSR + – 35 200 – 50 –
VCC = Constant, Rs ≤ 10 kΩ PSR – – 35 200 – 50 –
Power Supply Current (See Note 2) ICC – 2.6 5.0 – 2.6 5.0 mAdc
IEE – 2.6 5.0 – 2.6 5.0
DC Quiescent Power Consumption (VO = 0) PC – 146 280 – 146 280 mW

NOTES: 2. VCC = VEE = 5.0 Vdc to 30 Vdc for MC1436
VCC = VEE = 5.0 Vdc to 28 Vdc for MC1436C
Figure 3. Low–Drift Sample and Hold Figure 4. Power Bandwidth
+28 V 70
60 +28 V
VO, OUTPUT VOLTAGE (V p–p )

7 2 7
2 50
6
– 3 VO
Switch 6
MC1436 *eo 40 4 10 k
3 –28 V
ei + 5 30
1
10 k 20
1.0 µF 4
Polycarbonate
Sample *Drift due to bias current 10
–28 V is typically 8.0 mV s
Command
0
4.0 6.0 8.0 10 20 40 60 80 100 200 400
f, FREQUENCY (kHz)
Figure 5. Peak Output Voltage Swing versus

Power Supply Voltage Figure 6. Open Loop Frequency Response
35 140
TA = 25° C 120
VO , OUTPUT VOLTAGE SWING (Vpk )
30
, VOLTAGE GAIN (dB)
25 100
80
20 RL = 5.0 kΩ
60
15
40
10
VOL
20
A
5.0 0
0 –20
0 10 20 30 40 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
VCC/VEE, POWER SUPPLY VOLTAGE (Vdc) f, FREQUENCY (kHz)

MC1436, C
Figure 7. Output Short Circuit Current Figure 8. Input Bias Current

I SC , OUTPUT SHORT CIRCUIT CURRENT (mAdc) versus Temperature versus Temperature
IIB , INPUT BIAS CURRENT (NORMALIZED)

32 3.2
28 2.8
24 2.4
Source
20 2.0
16 1.6
Sink
12 1.2
8.0 0.8
4.0 0.4
0 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Figure 9. Inverting Feedback Model Figure 10. Noninverting Feedback Model
Z2 1 +Z2/Z1 Z2
zo = zo
zi
Z1
(–)
2 Ao ( ω ) 2
+ (–) zo
Iin
V1 zi zo VO zo If : Ao ( ω ) ∞ Z1 + zi + zo 6
+ EX
EX VO Z2 – Ao ( ω ) EX VO IO
– IO
Vin (+) Ao ( ω ) EX 6 =– (+) –
– RL Vi Z1 zi RL
V2 3 If : R3 Ơ Z1 3
Z1
R3 Z3
zi Ii Ao ( ω ) Z 1
Vin zi = , zi Very High
1 +Z2/Z1
1 +Z2/Z1 VO
zo = zo = 1 +Z2/Z1, when AO (ω) ∞
Ao (ω ) Vi
³
³∞
Zo 0
Ao (ω)
Figure 11. Audio Amplifier

100 k
Current Drain,
VCC = +30 Vdc
ID 100 mAdc @
50 µF 1.0 k R1 = 51 Ω
D1 , D2 , D3 = 1N4001
+ 2N3716
+ Common
1.0 k or Equiv
10 µF Heat Sink
7 51 R1 D1
2N3766
10 k 2 of Equiv RL
– D2 0.24
6
0.5 µF MC1536
3 D3 VO = 48 Vpp
+ 2N3740
Vi or Equiv 0.24 PO = 72 W (rms) @ RL = 4.0 Ω
10 k 4 PO = 36 W (rms) @ RL = 8.0 Ω
1.0 k 10 µF 0.1 µF
1.0 k
10 µF 4.7
2N3791
or Equiv
VEE = –30 Vdc

MC1436, C
Figure 12. Voltage Controlled Current Source or Transconductance Amplifier

with 0 V to 40 V Compliance
R2
100 k
R1 +50 V
100 k 2 7
–Vi –
6
MC1436,C
IO I
3 = = 2.0 mA/V
Vi RTC
+ RTC
4 R3 510
–6.0 V 100 k R1RTC (R3 +R4)
ZO =
R1 (RTC +R3) – R2 R4
R4
100 k
Figure 13. Representative Schematic Diagram

VCC
7
6.0 k 1.5 k 1.0 k 12 k 1.2 k 28 k
28 k 15 k
500 500
200
1.5 k 1.5 k
2
In- 26
put – 4.7 k Output
+
Input 6
3 22
3.5 k
35 pF
5.0 k
500
77 k 1.0 k 39 k 1.0 k 7.7 k 7.0 k 7.0 k 39 k 39 k 50
1 5
Offset Adjust
Figure 14. Equivalent Circuit

VCC
7
Inverting
2
–
Vi – AV +
Zin in 6
Rout VO
3 +
Noninverting
1 10 k 5
4
Offset Adjust
VEE

MC1458, C
Internally Compensated,
High Performance DUAL
Dual Operational Amplifiers (DUAL MC1741)
The MC1458, C was designed for use as a summing amplifier, integrator, SEMICONDUCTOR
or amplifier with operating characteristics as a function of the external TECHNICAL DATA
feedback components.
• No Frequency Compensation Required
• Wide Common Mode and Differential Voltage Ranges
• Low Power Consumption
• No Latch–Up
8
1
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
VEE –18 8
1
D SUFFIX
Input Common Mode Voltage (Note 1) VICM ±15 V
PLASTIC PACKAGE
Output Short Circuit Duration (Note 2) tSC Continuous CASE 751
(SO–8)
NOTES: 1. For supply voltages less than ±15 V, the absolute maximum
input voltage is equal to the supply voltage. PIN CONNECTIONS
2. Supply voltage equal to or less than 15 V.
Output A 1 8 VCC
2
–
A 7 Output B
Inputs
3 + B– 6
A Inputs
+ B
VEE 4 5
VCC
(Top View)
4.5 k
Noninverting 25
Input 39 k
30 pF 7.5 k
Output
Inverting
Input
50
Operating
50 k 50 Device Temperature Range Package
1.0 k 50 k 1.0 k
VEE
MC1458CD, D SO–8
TA = 0° to +70°C
MC1458CP1, P1 Plastic DIP

MC1458, C
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted. (Note 3))
MC1458 MC1458C
Input Offset Voltage (RS ≤ 10 k) VIO – 2.0 6.0 – 2.0 1.0 mV
Input Offset Current IIO – 20 200 – 20 300 nA
Input Bias Current IIB – 80 500 – 80 700 nA
Input Resistance ri 0.3 2.0 – – 2.0 – MΩ
Input Capacitance Ci – 1.4 – – 1.4 – pF
Offset Voltage Adjustment Range VIOR – ±15 – – ±15 – mV
Common Mode Input Voltage Range VICR ±12 ±13 – ±11 ±13 – V
(VO = ±10 V, RL = 2.0 k) 20 200 – – – –
(VO = ±10 V, RL = 10 k) – – – 20 200 –
Output Resistance ro – 75 – – 75 – Ω
Common Mode Rejection (RS ≤ 10 k) CMR 70 90 – 60 90 – dB
Supply Voltage Rejection (RS ≤ 10 k) PSR – 30 150 – 30 – µV/V
(RS ≤ 10 k) ±12 ±14 – ±11 ±14 –
(RS ≤ 2.0 k) ±10 ±13 – ± 9.0 ±13 –
Output Short Circuit Current ISC – 20 – – 20 – mA
Supply Currents (Both Amplifiers) ID – 2.3 5.6 – 2.3 8.0 mA
Power Consumption PC – 70 170 – 70 240 mW
Transient Response (Unity Gain)
(VI = 20 mV, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Rise Time tTLH – 0.3 – – 0.3 – µs
(VI = 20 mV, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Overshoot os – 15 – – 15 – %
(VI = 10 V, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Slew Rate SR – 0.5 – – 0.5 – V/µs
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Thigh to Tlow, unless otherwise noted. (Note 3))*
MC1458 MC1458C
Input Offset Voltage (RS ≤ 10 kΩ) VIO – – 7.5 – – 12 mV
Input Offset Current (TA = 0° to +70°C) IIO – – 300 – – 400 nA
Input Bias Current (TA = 0° to +70°C) IIB – – 800 – – 1000 nA
(Rs ≤ 10 k) ±12 ±14 – – – –
(Rs ≤ 2 k) ±10 ±13 – ± 9.0 ±13 –
(VO = ±10 V, RL = 2 k) 15 – – – – –
(VO = ±10 V, RL = 10 k) – – – 15 – –
*Tlow = 0°C for MC1458, C Thigh = +70°C for MC1458, C
NOTE: 3. Input pins of an unused amplifier must be grounded for split supply operation or biased at least 3.0 V above VEE for single supply operation.

MC1458, C
Figure 1. Burst Noise versus Source Resistance Figure 2. RMS Noise versus Source Resistance
1000 100
BW = 1.0 Hz to 1.0 kHz

en, INPUT NOISE (peak) (µV)
en, INPUT NOISE (peak) (µV)

100 10
10 1.0
0 0.1
10 100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 10 k 100 k 1.0 M
RS, SOURCE RESISTANCE (Ω) RS, SOURCE RESISTANCE (Ω)
Figure 3. Output Noise versus Source Resistance Figure 4. Spectral Noise Density
10 140
120
en, OUTPUT NOISE (rms mV)
en, INPUT NOISE ( nV/ √ Hz )

AV = 1000 AV = 10, RS = 100 kΩ
100
1.0
100 80
10 60
0.1 1.0 40
20
0 0
10 100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k
RS, SOURCE RESISTANCE (Ω) f, FREQUENCY (Hz)
Figure 5. Burst Noise Test Circuit
Positive
100 k Threshold +
Voltage
–
– To Pass / Fail
100 k X 500 X2 Indicator
+
1.0 k –
100 k Low Pass Filter
Under Test 1.0 Hz to 1.0 kHz +
Negative
Threshold
Voltage
Unlike conventional peak reading or RMS meters, this system The test time employed is 10 sec and the 20 µV peak limit
was especially designed to provide the quick response time refers to the operational amplifier input thus eliminating errors
essential to burst (popcorn) noise testing. in the closed loop gain factor of the operational amplifier .

MC1458, C

28 120
24 100
A VOL , VOLTAGE GAIN (dB)

20 80
16 60
12 40
(Voltage Follower)
8.0 20
THD < 5%
4.0 0
0 –20
10 100 1.0 k 10 k 100 k 10 10 100 1.0 k 10 k 100 k 1.0 M 10 M
15 –15
VO , OUTPUT VOLTAGE SWING (V)
VO , OUTPUT VOLTAGE SWING (V)

±15 V Supplies
11 –11
±12 V
9.0 –9.0 ±12 V
7.0 ± 9.0 V –7.0

± 9.0 V
5.0 –5.0
± 6.0 V
3.0 –3.0 ± 6.0 V
1.0 –1.0
100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 k 100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 k

Load Resistance (Single Supply Operation) Figure 11. Single Supply Inverting Amplifier
28 +30 V Supply
100 µF 10 k
1.0 k
24 +27 V
+24 V VCC
20
Vin
+21 V
16
+18 V
200 k 50 k 2 7
12 100 µF
+15 V –
50 k +
8.0 +12 V MC1558
200 k 3 4 RL
4.0 +9.0 V
+6.0 V
+5.0 V
0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
RL, LOAD RESISTANCE (kΩ)

MC1458, C
Figure 12. Noninverting Pulse Response
Output
5.0 V/DIV
Input
10 µs/DIV
Figure 13. Transient Response Test Circuit Figure 14. Unused OpAmp
To Scope
(Input)
– To Scope –
(Output)
+ +
RL CL

versus Supply Voltage
105
100
95
90
85
80
75
70
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20

MCT1458, C
High Performance Dual
DUAL
The MCT1458, C was designed for use as a summing amplifier, OPERATIONAL AMPLIFIER
integrator, or amplifier with operating characteristics as a function of the
external feedback components. (DUAL MC1741)
• No Frequency Compensation Required SEMICONDUCTOR
• Short Circuit Protection TECHNICAL DATA
• No Latch–Up
This MCT–prefixed device is intended to be a possible replacement for the similar

device with the MC–prefix. Because the MCT device originates from different
source material, there may be subtle differences in typical parameter values or
8
characteristic curves. Due to the diversity of potential applications, Motorola can not
assure identical performance in all circuits. Motorola recommends that the 1
customer qualify the MCT–prefixed device in each potential application.
P1 SUFFIX
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) PLASTIC PACKAGE
CASE 626
VEE –18
Input Differential Voltage VID ± 30 V 8

1
Output Short Circuit Duration (Note 2) tSC Continuous D SUFFIX
PLASTIC PACKAGE
Operating Ambient Temperature Range TA 0 to +70 °C CASE 751
(SO–8)
NOTES: 1. For supply voltages less than ±15 V, the absolute maximum input voltage is equal to
the supply voltage.
2. Supply voltage equal to or less than 15 V. PIN CONNECTIONS

Output A 1 8 VCC
VCC A
2 7 Output B
To Other –
Amplifier Inputs A + B
25Ω 3 6
+In –In 30pF –
Out Inputs B
50kΩ 30Ω 20kΩ +
VEE 4 5
(Top View)
To Other
Amplifier
1.0kΩ
1.0kΩ
5.0kΩ
50kΩ
50kΩ
50kΩ
50Ω
VEE Operating
This device contains 46 active transistors.
MCT1458CD, D SO–8
CAUTION: These devices do not have internal ESD protection circuitry and are rated TA = 0° to +70°C
MCT1458CP1, P1 Plastic
as CLASS 1 devices per the ESD test method in Mil–Std–833D. They should be handled
using standard ESD prevention methods to avoid damage to the device.

MCT1458, C
MCT1458 MCT1458C
Input Offset Voltage (RS ≤ 10 k) VIO — 2.0 6.0 — 2.0 10 mV
Input Offset Current IIO — 20 200 — 20 300 nA
Input Bias Current IIB — 80 500 — 80 700 nA
Input Resistance ri 0.3 2.0 — — 2.0 — MΩ
Input Capacitance Ci — 6.0 — — 6.0 — pF
Common Mode Input Voltage Range VICR ±12 ±13 — ±11 ±13 — V
(VO = ±10 V, RL = 2.0 k) 20 200 — — — —
(VO = ±10 V, RL = 10 k) — — — 20 200 —
Output Resistance ro — 75 — — 75 — Ω
Common Mode Rejection (RS ≤ 10 k) CMR 70 90 — 60 90 — dB
Supply Voltage Rejection (RS ≤ 10 k) PSR — 30 150 — 30 — µV/V
(RS ≤ 10 k) ±12 ±14 — ±11 ±14 —
(RS ≤ 2.0 k) ±10 ±13 — ±9.0 ±13 —
Output Short Circuit Current ISC — 20 — — 20 — mA
Supply Currents (Both Amplifiers) ID — 2.3 5.6 — 2.3 8.0 mA
Power Consumption PC — 70 170 — 70 240 mW
(VI = 20 mV, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Rise Time tTLH — 0.9 — — 0.9 — µs
(VI = 20 mV, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Overshoot os — 15 — — 15 — %
(VI = 10 V, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Slew Rate SR — 0.8 — — 0.8 — V/µs
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Thigh to Tlow, unless otherwise noted.)
MCT1458 MCT1458C
Input Offset Voltage (Rs ≤ 10 kΩ) VIO — — 7.5 — — 12 mV
(TA = 0° to +70°C) — — 300 — — 400
Input Bias Current IIB nA

(TA = 0° to +70°C) — — 800 — — 1000

(Rs ≤ 10 k) ±12 ±14 — — — —
(Rs ≤ 2 k) ±10 ±13 — ±9.0 ±13 —
(VO = ±10 V, RL = 2 k) 15 — — — — —
(VO = ±10 V, RL = 10 k) — — — 15 — —

MCT1458, C
Figure 1. Power Bandwidth Figure 2. Maximum Output Voltage Swing

(Large Signal Swing versus Frequency) versus Load Resistance
VO , MAXIMUM OUTPUT VOLTAGE SWING (V pp)

28 32
VCC = +15 V TA = +25°C
VEE = –15 V 28 VS = ±15 V
24
24
20
20
16 VS = ±12 V
16
12
12
8.0
8.0
4.0 4.0
0 0
10 100 1.0 k 10 k 100 k 100 1.0 k 10 k 50 k
f, FREQUENCY (Hz) RL, LOAD RESISTANCE (Ω)
Figure 3. Input Offset Current Figure 4. Input Offset Current

100 30
VCC = +15 V TA = +25°C
IIO , INPUT OFFSET CURRENT (nA)
IIO , INPUT OFFSET CURRENT (nA)

VEE = –15 V
25
80
20
60
15
40
10
20
5.0
0 0
– 40 – 20 0 20 40 60 80 0 2.0 4.0 6.0 8.0 10 12 14 16 18
TA, AMBIENT TEMPERATURE (°C) VCC, VEE, SUPPLY VOLTAGE (V)
Figure 5. Open Loop Voltage Gain Figure 6. Voltage Gain and Phase
versus Supply Voltage versus Frequency
105 50 80
VCC = +5.0 V
40 VEE = – 5.0 V 100
100
30 120
φ, PHASE (DEGREES)
2A 1A
95 20 140
90 10 160
0 2B 180
85 –10 200
1B
80 – 20 1A) Phase CL = 0 pF 220
– 30 2A) Phase CL = 200 pF 240
75 1B) Gain CL = 0 pF
– 40 2B) Gain CL = 200 pF 260
70 – 50 280
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 1.0 k 10 k 100 k 1.0 M 10 M
VCC, |VEE|, SUPPLY VOLTAGES (V) f, FREQUENCY (Hz)

MC1490
RF/IF/Audio Amplifier
The MC1490 is an integrated circuit featuring wide–range AGC for use in

RF/IF amplifiers and audio amplifiers over the temperature range, –40° to
+85°C.
WIDEBAND AMPLIFIER
• High Power Gain: 50 dB Typ at 10 MHz WITH AGC
45 dB Typ at 60 MHz
35 dB Typ at 100 MHz
SEMICONDUCTOR
• Wide Range AGC: 60 dB Min, DC to 60 MHz TECHNICAL DATA
• 6.0 V to 15 V Operation, Single Polarity Supply
• See MC1350D for Surface Mount

8
AGC Supply VAGC VCC Vdc 1
Input Differential Voltage VID 5.0 Vdc

P SUFFIX
Operating Temperature Range TA –40 to +85 °C PLASTIC PACKAGE
Storage Temperature Range Tstg –65 to +150 °C CASE 626
Operating PIN CONNECTIONS
MC1490P TA = – 40° to +85°C Plastic Output Output

1 8 (+)
(–)
VCC 2 7 Substrate
Ground
– +
Representative Schematic Diagram 3 6 Noninverting
GND
Input
2 VCC
Inverting 4 5 AGC
1.5 k Input Input
VAGC 70 (Top View)
5.5 k 12.1 k
5
470 470
8 (+)
SCATTERING PARAMETERS
Outputs (VCC = +12 Vdc, TA = +25°C, Zo = 50 Ω)
2.0 k
(–)
1 f = MHz
Typ
4
(–) 45 Parameter Symbol 30 60 Unit
Inputs
(+) 66 1.4 k
Input
6 2.8 k 200 200 2.8 k Reflection |S11| 0.95 0.93 –
5.0 k 5.0 k Coefficient θ11 –7.3 –16 deg
5.6 k Output
1.9k Reflection |S22| 0.99 0.98 –
1.1 k 1.1 k 8.4 k Coefficient θ22 –3.0 –5.5 deg
200
3 Forward
Substrate 7 Transmission |S21| 16.8 14.7 –
Coefficient θ21 128 64.3 deg
Reverse
Transmission S12 0.00048 0.00092 –
Pins 3 and 7 should both be connected to circuit ground. Coefficient θ12 84.9 79.2 deg

MC1490
ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, f = 60 MHz, BW = 1.0 MHz, TA = 25°C)

Characteristic Figure Symbol Min Typ Max Unit
Power Supply Current Drain – ICC – – 17 mA
AGC Range (AGC) 5.0 V Min to 7.0 V Max 19 MAGC –60 – – dB
Output Stage Current (Sum of Pins 1 and 8) – IO 4.0 – 7.5 mA
Single–Ended Power Gain RS = RL = 50 Ω 19 GP 40 – – dB
Noise Figure RS = 50 Ohms 19 NF – 6.0 – dB
Power Dissipation – PD – 168 204 mW
Figure 1. Unneutralized Power Gain versus Figure 2. Voltage Gain versus Frequency
Frequency (Tuned Amplifier, See Figure 19) (Video Amplifier, See Figure 20)
70 50
AC , SINGLE–ENDED VOLTAGE GAIN (dB)

RL = 1.0 k VCC = 12 Vdc
VCC = 12 Vdc
60
G P , UNNEUTRALIZED GAIN (dB)
(SINGLE–ENDED OUTPUT)
40
50
40 30
RL = 100 Ω
30
20
20
10
10 RL = 10 Ω
0 0
10 20 50 100 200 0.1 1.0 10 100 1000
f, FREQUENCY (MHZ) f, FREQUENCY (MHZ)
Figure 3. Dynamic Range: Output Voltage versus Figure 4. Voltage Gain versus Frequency
Input Voltage (Video Amplifier, See Figure 20) (Video Amplifier, See Figure 20)
10 50
VCC = 12 Vdc VCC = 6.3 Vdc
V O, OUTPUT VOLTAGE (V RMS)
5.0
AV , SINGLE VOLTAGE GAIN (dB)
V5(AGC) = 0 V 40
f = 1.0 MHz RL = 1.0 kΩ
1.0
30
0.5
RL = 1.0 k
100 Ω
20
0.1
0.05 100 Ω
10
10 Ω
0.01 0
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 0.3 0.5 1.0 3.0 5.0 10 30 50 100 300
en, INPUT VOLTAGE (mVRMS) f, FREQUENCY (MHZ)

MC1490
Figure 5. Voltage Gain and Supply Current versus Figure 6. Typical Gain Reduction
Supply Voltage (Video Amplifier, See Figure 20) versus AGC Voltage
45 24 0
AV, SINGLE–ENDED VOLTAGE GAIN (dB)
f = 1.0 MHz 10
40 21 VR(AGC)
Rl = 1.0 Ω AV 5
GR , GAIN REDUCTION (dB)

I C , SUPPLY CURRENT (mAdc)
MC1490P
35 18 20 RAGC
30 15 30
RAGC = 100 kΩ
25 12 40
ICC
20 9.0 50
15 6.0 60
RAGC = 0 Ω RAGC = 5.6 kΩ
10 3.0 70
5.0 0 80
0 2.0 4.0 6.0 8.0 10 12 14 16 0 3.0 6.0 9.0 12 15 18 21 24 27 30
VCC, SUPPLY VOLTAGE (V) VR(AGC), AGC VOLTAGE (Vdc)
Figure 7. Typical Gain Reduction Figure 8. Fixed Tuned Power Gain Reduction versus
versus AGC Current Temperature (See Test Circuit, Figure 19)
0 50
10 40
GR , GAIN REDUCTION (dB)
20 100 < RAGC < 100 k

30
G p ,POWER GAIN (dB)
0°C
30
20 +25°C
40
10 +75°C
50 –55°C
0 VCC = 12 Vdc
60
f = 60 MHz
70 –10 RAGC = 5.6 kΩ
+125°C
80 –20
–40 –20 0 20 40 60 80 100 120 140 160 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0
IAGC AGC CURRENT (µA) VR(AGC), AGC VOLTAGE (Vdc)
Figure 9. Power Gain versus Supply Voltage

(See Test Circuit, Figure 19) Figure 10. Noise Figure versus Frequency
80 10
70 9.0
f = 60 MHz 8.0
NF, NOISE FIGURE (dB)
60
Gp , POWER GAIN (dB)
7.0
50 6.0
40 GP 5.0
4.0 RS Optimized
30 for minimum NF
3.0
20
2.0
10 1.0
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 15 20 25 30 35 40 50 60 70 80 90 100 150
VCC, POWER SUPPLY VOLTAGE (V) f, FREQUENCY (MHz)

MC1490
Figure 11. Noise Figure versus Figure 12. Noise Figure versus
Source Resistance AGC Gain Reduction
20 40
18 f = 30 MHz
VCC = 12 Vdc 35
16 BW = 1.0 MHz
30
NF, NOISE FIGURE (dB)
NOISE FIGURE (dB)

14
f = 105 MHz 25
12
10 f = 60 MHz 20
8.0 15
f = 30 MHz Test circuit has tuned input
6.0
10 providing a source resistance
4.0 optimized for best noise figure.
2.0 5
0 0
100 200 400 600 1.0 k 2.0 k 4.0 k 10 k 0 –10 –20 –30 –40 –50 –60 –70 –80
RS, SOURCE RESISTANCE (Ω) GR, GAIN REDUCTION (dB)
Figure 13. Harmonic Distortion versus AGC Gain

Reduction for AM Carrier (For Test Circuit, See Figure 14)
40
f = 10.7 MHz
HARMONIC DISTORTION IN DETECTED
35 Modulation: 90 % AM, fm = 1.0 kHz

Load at Pin 8 = 2.0 kΩ 760 mVpp
30 EO = peak–to–peak envelope of
MODULATION (%)
modulated 10.7 MHz carrier at Pin 8

25
20
EO = 2400 mVpp 240 mVpp
15
10
5.0
0
0 10 20 30 40 50 60 70 80
GR, GAIN REDUCTION (dB)
Figure 14. 10.7 MHz Amplifier Gain ] 55 dB, BW ] 100 kHz

7
0.002
36 pF
6 8
50 Ω Load
5.6 k 5
VAGC MC1490P L2
4 1
10.7 MHz
(50 Ω Source) 82 pF 3
RFC
+12 Vdc
L1
2
0.002 0.002
50–150 pF
L1 = 24 turns, #22 AWG wire L2 = 20 turns, #22 AWG wire

on a T12–44 micro metal on a T12–44 micro metal
Toroid core (–124 pF) Toroid core (–100 pF)

MC1490
Figure 15. S11 and S22, Input and Output Figure 16. S11 and S22, Input and Output
Reflection Coefficient Reflection Coefficient
Figure 17. S21, Forward Transmission Figure 18. S12, Reverse Transmission
Coefficient (Gain) Coefficient (Feedback)
80 MHz
70 MHz
10 100 MHz
120 MHz
5.0
60 MHz 150 MHz
50 MHz
200 MHz
5.0
40 MHz
10
30 MHz 15
20 MHz
10 MHz

MC1490
Figure 19. 60 MHz Power Gain Test Circuit Figure 20. Video Amplifier
0.0001 0.001
C3 µF
µF 1.0 µF
Shield 7
7 C4 10 k eo
Output 6
6 VR(AGC) 8
C2 (50 Ω) 5.6 k RL
8 VR(AGC) MC1490P
VAGC 1.0 µF 5 1
L1 MC1490P L2 ei 2
5 4 1.0 µF
Input 1 3
(50 Ω) 4 3 2 0.001 µF
C1
RAGC
+12 Vdc +12 Vdc
0.001 µF 0.001 µF
VR(AGC)
L1 = 7 turns, #20 AWG wire, 5/16″ Dia.,5/8″ long
L2 = 6 turns, #14 AWG wire, 9/16″ Dia.,3/4″ long
C1,C2,C3 = (1–30) pF
C4 = (1–10) pF
Figure 21. 30 MHz Amplifier

(Power Gain = 50 dB, BW 1.0 MHz) [ Figure 22. 100 MHz Mixer
0.002 µF
VAGC 6.0 V (1 – 10) pF
7 Input from
6 T1 7 (1 – 30) pF
local oscillator 100 5 8
8 IF Output
5 (70 MHz)
(1 – 30) pF L1 MC1490P C2 RL = 50 Ω (1 – 10) pF
6 (30 MHz)
VAGC 1 Signal Input MC1490P L2
Input
(50 Ω) (100 MHz)
38 pF 4 3 2 1 – 10 pF L1 4
10 µH 1
5.6 k 0.002 µF (1 – 30) pF 3 2 +12 Vdc
+12 Vdc 0.002 µF
VR(AGC) 0.002 µF 10 µH
L1 = 12 turns, #22 AWG wire on a Toroid core, L1 = 5 turns, #16 AWG wire, 1/4″, ID Dia., 5/8″ long
(T37–6 micro metal or equiv). L2 = 16 turns, #20 AWG wire on a Toroid core, (T44–6).
T1: Primary = 17 turns, #20 AWG wire on a Toroid core, (T44–6).
Secondary = 2 turns, #20 AWG wire.
Figure 23. Two–Stage 60 MHz IF Amplifier (Power Gain [ 80 dB, BW [ 1.5 MHz)
10 k
VR(AGC)
5.1 k (1–10) pF
7 Shield 7 Shield
Input
24 pF
4 T1 0.002 µF 4 T2 Output
8 8
(50 Ω) (50 Ω)
5 5
200 µH MC1490P 1.0 k MC1490P
6 6
1 (1–10) pF 39 pF 1 (1–10) pF
2 2
(1–10) pF 3
3 RFC 0.002 µF RFC
0.002 µF
10 µH 0.001 µF
+12 Vdc
T1: Primary Winding = 15 turns, #22 AWG wire, 1/4″ ID Air Core T2: Primary Winding = 10 turns, #22 AWG wire, 1/4″ ID Air Core
[ [
Secondary Winding = 4 turns, #22 AWG wire, Secondary Winding = 2 turns, #22 AWG wire,
Coefficient of Coupling 1.0 Coefficient of Coupling 1.0

MC1490
DESCRIPTION OF SPEECH COMPRESSOR Table 1. Distortion versus Frequency
The amplifier drives the base of a PNP transistor operating Distortion Distortion
Freq ency
Frequency
common–emitter with a voltage gain of approximately 20. 10 mV ei 100 mV ei 10 mV ei 100 mV ei
The control R1 varies the quiescent Q point of this transistor
so that varying amounts of signal exceed the level Vr. Diode 100 Hz 3.5% 12% 15% 27%
D1 rectifies the positive peaks of Q1’s output only when these
]
300 Hz 2% 10% 6% 20%
peaks are greater than Vr 7.0 V. The resulting output is
1.0 kHz 1.5% 8% 3% 9%
filtered by Cx, Rx.
Rx controls the charging time constant or attack time. Cx is 10 kHz 1.5% 8% 1% 3%
involved in both charge and discharge. R2 (the 150 kΩ and 100 kHz 1.5% 8% 1% 3%
input resistance of the emitter–follower Q2) controls the
decay time. Making the decay long and attack short is Notes 1 and 2 Notes 3 and 4
accomplished by making Rx small and R2 large. (A Notes: (1) Decay = 300 ms (3) Decay = 20 ms
Darlington emitter–follower may be needed if extremely slow Attack = 20 ms Attack = 3.0 ms
decay times are required.) (2) Cx = 7.5 µF (4) Cx = 0.68 µF
The emitter–follower Q2 drives the AGC Pin 5 of the Rx = 0 (Short) Rx = 1.5 kΩ
MC1490P and reduces the gain. R3 controls the slope of
signal compression.
Figure 24. Speech Compressor

+12 V 25 µF
0.001
1.0 k
1.0 k
2 10 µF
5 1 Output
15 µF 10 µF
4 8
Input MC1490P
6
3
15 µF 7 +12 V +12 V
R3 220 2.2 k
15 k +12 V
R2 Q1
Q2 2N3906
Vr
2N3904 Rx D1 33 k
4.7 k 150 k Cx 6.8 k R1

100 k

MC1741C
High Performance
Operational Amplifier OPERATIONAL
AMPLIFIER
The MC1741C was designed for use as a summing amplifier, integrator,
or amplifier with operating characteristics as a function of the external
feedback components. SEMICONDUCTOR
• No Frequency Compensation Required TECHNICAL DATA
• Offset Voltage Null Capability
• No Latch Up 8
1
P1 SUFFIX
PLASTIC PACKAGE
MAXIMUM RATINGS CASE 626
Power Supply Voltage VCC, VEE ±18 Vdc
Input Common Mode Voltage (Note 1) VICM ±15 V 8
1
Output Short Circuit Duration (Note 2) tSC Continuous D SUFFIX
PLASTIC PACKAGE
CASE 751
Storage Temperature Range Tstg –55 to +125 °C (SO–8)
NOTES: 1. For supply voltages less than +15 V, the absolute maximum input voltage is
equal to the supply voltage.
2. Supply voltage equal to or less than 15 V.
PIN CONNECTIONS
Offset Null 1 8 N.C.
Equivalent Circuit Schematic Inv. Input 2 7 VCC

(1/4 of Circuit Shown) Noninv. Input 3
+ 6 Output
VCC VEE 4 5 Offset Null
G
Noninverting
Input (Top View)
4.5 k
39 k 25
Inverting
Input 30 pF 7.5 k
Output
50 ORDERING INFORMATION
Offset Operating
Null 50 k 50 Device Alternate Temperature Range Package
1.0 k 50 k 1.0 k 5.0 k
VEE MC1741CD – SO–8
TA = 0° to +70°C Plastic DIP
MC1741CP1 LM741CN
µA741TC

MC1741C
Input Offset Current IIO – 20 200 nA
Input Bias Current IIB – 80 500 nA
Input Capacitance Ci – 1.4 – pF
Offset Voltage Adjustment Range VIOR – ±15 – mV
Common Mode Input Voltage Range VICR ±12 ±13 – V
Large Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) AVOL 20 200 – V/mV
Output Resistance ro – 75 – Ω
Supply Voltage Rejection (RS ≤ 10 k) PSR 75 – – dB
(RL ≥ 10 k) ±12 ±14 –
(RL ≥ 2.0 k) ±10 ±13 –
Supply Current ID – 1.7 2.8 mA
Power Consumption PC – 50 85 mW
Transient Response (Unity Gain, Noninverting)
(VI = 20 mV, RL ≥ 2.0 k, CL ≤ 100 pF) Rise Time tTLH – 0.3 – µs
(VI = 20 mV, RL ≥ 2.0 k, CL ≤ 100 pF) Overshoot os – 15 – %
(VI = 10 V, RL ≥ 2.0 k, CL ≤ 100 pF) Slew Rate SR – 0.5 – V/µs
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh, unless otherwise noted.)*
Input Offset Current (TA = 0° to +70°C ) IIO – – 300 nA
Input Bias Current (TA = 0° to +70°C ) IIB – – 800 nA
Supply Voltage Rejection (RS ≤ 10 k) PSR 75 – – dB
Output Voltage Swing (RL ≥ 2.0 k) VO ±10 ±13 – V
Large Signal Voltage Gain (RL ≥ 2.0 k, VO = ±10 V) AVOL 15 – – V/mV
* Tlow = 0°C Thigh = 70°C

MC1741C
1000 100

en, INPUT NOISE (µVpk)
en, INPUT NOISE (µVpk)

100 10
10 1.0
0 0.1
10 100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 10 k 100 k 1.0 M
10 14.0
en, OUTPUT NOISE (mVrms)
12.0
AV = 1000 e n, INPUT NOISE ( nV/ √ Hz ) AV = 10, RS = 100 k Ω
10.0
1.0
100 8.0
10 6.0
0.1
4.0
1.0
2.0
0.01 0
10 100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k
Positive
100 k Threshold +
Voltage
–
– To Pass / Fail
100 k x500 x2 Indicator
+
1.0 k +
100 k Low Pass
Under Test Filter –
1.0 Hz to 1.0 kHz
Negative
Threshold
Voltage
Unlike conventional peak reading or RMS meters, this system was The test time employed is 10 sec and the 20 mV peak limit
especially designed to provide the quick response time essential refers to the operational amplifier input thus eliminating errors
to burst (popcorn) noise testing. in the closed loop gain factor of the operational amplifier.

MC1741C

28 120
24 100
Avol , VOLTAGE GAIN (dB)

20 80
16 60
12 40
(Voltage Follower)
8.0 20
THD < 5%
4.0 0
0 –20
10 100 1.0 k 10 k 100 k 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
15 –15

±15 V Supplies
11 –11
±12 V
9.0 –9.0 ±12 V
7.0 ±9.0 V –7.0

±9.0 V
5.0 –5.0
±6.0 V
3.0 –3.0 ±6.0 V
1.0 –1.0
100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 k 100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 k

Load Resistance (Single Supply Operation) Figure 11. Single Supply Inverting Amplifier
28 30 V Supply
26 100 µF
1.0 k 10 k
24 27 V
22
24 V VCC
20
18 21 V Vin
16
18 V
14
200 k 50 k 2 7
12 100 µF
10 15 V –
50 k +
8.0 12 V MC1741
6.0 200 k 3 4 RL
4.0 9.0 V
2.0 6.0 V
5.0 V
0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
RL, LOAD RESISTANCE (kΩ)

MC1741C
Figure 12. Noninverting Pulse Response
Output
5.0 V/DIV
Input
10 µs/DIV
Figure 13. Transient Response Test Circuit
To Scope
(Input)
– To Scope
+ (Output)
RL CL

versus Supply Voltage
105
100
AV, VOLTAGE GAIN (dB)
95
90
85
80
75
70
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20

MC1776C
Micropower Programmable
This extremely versatile operational amplifier features low power PROGRAMMABLE
consumption and high input impedance. In addition, the quiescent currents OPERATIONAL AMPLIFIER
within the device may be programmed by the choice of an external resistor
value or current source applied to the Iset input. This allows the amplifier’s
characteristics to be optimized for input current and power consumption SEMICONDUCTOR
despite wide variations in operating power supply voltages. TECHNICAL DATA
• ±1.2 V to ±18 V Operation
• Wide Programming Range
• Offset Null Capability
• Low Input Bias Currents
• Short Circuit Protection 8
1
P1 SUFFIX
PLASTIC PACKAGE
Resistive Programming CASE 626
(See Figure 1)
Rset to Ground Rset to Negative Supply

(Recommended for supply voltage
less than ± 6.0 V) 8
7 VCC 7 VCC 1
2 2
– – D SUFFIX
6 6 PLASTIC PACKAGE
3 3 CASE 751
+ +
(SO–8)
8 8
4 Rset 4 Rset
VCC – 0.6
Iset = VCC – 0.6 – VEE
VEE VEE Iset =
Rset
Rset
Typical Rset Values Typical Rset Values
VCC, VEE Iset = 1.5 µA Iset = 15 µA VCC, VEE Iset = 1.5 µA Iset = 15 µA PIN CONNECTIONS
± 6.0 V 3.6 MΩ 360 kΩ ± 1.5 V 1.6 MΩ 160 kΩ
± 10 V 6.2 MΩ 620 kΩ ± 3.0 V 3.6 MΩ 360 kΩ
± 12 V 7.5 MΩ 750 kΩ ± 6.0 V 7.5 MΩ 750 kΩ
± 15 V 10 MΩ 1.0 MΩ ± 15 V 20 MΩ 2.0 MΩ Offset Null 1 8 Iset
Invert 2 – 7 VCC
Input
Noninvert + Output
Active Programming 3 6
FET Current Source Bipolar Current Source VEE 4 5 Offset Null
7 (Top View)
7 VCC 2
2 –
– 6
6
3
3 +
+ 4 VEE
4 VEE 8 Q
8 ORDERING INFORMATION
VG VB
Operating
R
VEE MC1776CD SO–8
Pins not shown are not connected. TA = 0° to +70°C
MC1776CP1 Plastic DIP

MC1776C

Power Supply Voltages VCC,VEE ±18 Vdc
Differential Input Voltage VID ±30 Vdc
Common Mode Input Voltage VICM Vdc
VCC and |VEE| 15 Vt VCC,VEE
VCC and |VEE| 15 Vw ±15
Offset Null to VEE Voltage Voff–VEE ±0.5 Vdc
Programming Current Iset 500 µA
Programming Voltage Vset (VCC –2.0 V) Vdc
(Voltage from Iset Terminal to Ground) to VCC
Operating Temperature Range TA 0 to +70 °C
NOTE 1. May be to ground or either supply voltage. Rating applies up to a case temperature of +125°C
or ambient temperature of +70°C and Iset ≤ 30 µA.

8 Iset 7
VCC
–
2 50
Inputs
3
+ 2.0 k 100
30 pF 100 6
Output
100
1
50
Offset Null
5
10 k 10 k
4
VEE
Voltage Offset Null Circuit Transient Response Test Circuit
2 7 VCC
7 VCC –
2 – 6
6 VO
3
+
3 + 5 4
1 RL
100 k Vin 8 CL
8 4
VEE Rset
Rset
Pins not shown are
VEE not connected.

MC1776C
ELECTRICAL CHARACTERISTICS (VCC = +3.0 V, VEE = –3.0 V, Iset = 1.5 µA, TA = +25°C, unless otherwise noted.*)
Input Offset Voltage (RS ≤ 10 kΩ) VIO mV
TA = +25°C – 2.0 6.0
Tlow* ≤ TA ≤ Thigh* – – 7.5
Offset Voltage Adjustment Range VIOR – 9.0 – mV
TA = +25°C – 0.7 6.0
TA = Thigh – – 6.0
TA = Tlow – – 10
TA = +25°C – 2.0 10
TA = Thigh – – 10
TA = Tlow – – 20
Input Resistance ri – 50 – MΩ
Input Capacitance ci – 2.0 – pF
Input Voltage Range VID V
Tlow ≤ TA ≤ Thigh +1.0 – –
Large Signal Voltage Gain AVOL V/V
RL ≥ 75 kΩ, VO = ±1.0 V, TA = +25°C 25 k 200 k –
RL ≥ 75 kΩ, VO = ±1.0 V, Tlow ≤ TA ≤ Thigh 25 k – –
RL ≥ 75 kΩ, Tlow ≤ TA ≤ Thigh ±2.0 ±2.4 –
Output Resistance ro – 5.0 – kΩ
Output Short Circuit Current ISC – 3.0 – mA
RS ≤ 10 kΩ, Tlow ≤ TA ≤ Thigh 70 86 –
Supply Voltage Rejection Ratio PSRR µV/V
RS ≤ 10 kΩ, Tlow ≤ TA ≤ Thigh – 25 200
Supply Current ICC, IEE µA
TA = +25°C – 13 20
Power Dissipation PD µW
TA = +25°C – 78 120
Vin = 20 mV, RL ≥ 5.0 kΩ, CL = 100 pF
Rise Time tTLH – 3.0 – µs
Overshoot os – 0 – %
Slew Rate (RL ≥ 5.0 kΩ) SR – 0.03 – V/µs
*Tlow = 0°C Thigh = +70°C

MC1776C
ELECTRICAL CHARACTERISTICS (VCC = +3.0 V, VEE = –3.0 V, Iset = 15 µA, TA = +25°C, unless otherwise noted.*)
TA = +25°C – 2.0 6.0
Offset Voltage Adjustment Range VIOR – 18 – mV
TA = +25°C – 2.0 25
TA = Tlow – – 40
TA = +25°C – 15 50
TA = Tlow – – 100
Input Resistance ri – 5.0 – MΩ
Tlow ≤ TA ≤ Thigh ±1.0 – –
RL ≥ 5.0 kΩ, VO = ±1.0 V, TA = +25°C 25 k 200 k –
RL ≥ 5.0 kΩ, VO = ±1.0 V, Tlow ≤ TA ≤ Thigh 25 k – –
RL ≥ 5.0 kΩ, Tlow ≤ TA ≤ Thigh ±2.0 ±2.1 –
TA = +25°C – 130 170
TA = +25°C – 780 1020
Vin = 20 mV, RL ≥ 5.0 kΩ, CL = 100 pF
Overshoot os – 5.0 – %

MC1776C
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, Iset = 1.5 µA, TA = +25°C, unless otherwise noted.*)
TA = +25°C – 2.0 6.0
Offset Voltage Adjustment Range VIOR – 9.0 – mV
TA = +25°C – 0.7 6.0
TA = Thigh – – 6.0
TA = Tlow – – 10
TA = +25°C – 2.0 10
TA = Tlow – – 20
Input Resistance ri – 50 – MΩ
Tlow ≤ TA ≤ Thigh ±10 – –
RL ≥ 75 kΩ, VO = ±10 V, TA = +25°C 50 k 400 k –
RL ≥ 75 kΩ, VO = ±10 V, Tlow ≤ TA ≤ Thigh 50 k – –
RL ≥ 75 kΩ, TA = +25°C ±12 ±14 –
RL ≥ 75 kΩ, Tlow ≤ TA ≤ Thigh ±10 – –
TA = +25°C – 20 30
Power Dissipation PD mW
TA = +25°C – 780 0.9
Vin = 20 mV, RL ≥ 5.0 kΩ, CL = 100 pF

MC1776C
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, Iset = 15 µA, TA = +25°C, unless otherwise noted.*)
TA = +25°C – 2.0 6.0
TA = +25°C – 2.0 25
TA = Tlow – – 40
TA = +25°C – 15 50
TA = Tlow – – 100
Tlow ≤ TA ≤ Thigh ±10 – –
RL ≥ 5.0 kΩ, VO = ±10 V, TA = +25°C 50 k 400 k –
RL ≥ 75 kΩ, VO = ±10 V, Tlow ≤ TA ≤ Thigh 50 k – –
RL ≥ 5.0 kΩ, TA = +25°C ±10 ±13 –
RL ≥ 75 kΩ, Tlow ≤ TA ≤ Thigh ±10 – –
TA = +25°C – 160 190
TA = +25°C – – 5.7
Vin = 20 mV, RL ≥ 5.0 kΩ, CL = 100 pF

MC1776C
Figure 2. Positive Standby Supply Current

Figure 1. Set Current versus Set Resistor versus Set Current
POSITIVE STANDBY SUPPLY CURRENT ( µA)

100 M 1000
VCC = +15 V +3.0 V ≤ VCC ≤ +18 V
VEE = –15 V –3.0 V ≥ VEE ≥ –18 V
R set , SET RESISTOR ( Ω )
10 M Rset to VEE
VCC = +15 V 100
VEE = –15 V
VCC = +3.0 V Rset to GND
VEE = –3.0 V
1.0 M Rset to VEE 10
VCC = +3.0 V
100 k VEE = –3.0 V 1.0
Rset to GND
10 k 0.1
0.1 1.0 10 100 0.01 0.1 1.0 10 100
Iset, SET CURRENT (µA) Iset, SET CURRENT (µA)
Figure 3. Open Loop Gain versus Set Current Figure 4. Input Bias Current versus Set Current
107 100
VCC = +15 V
A VOL, OPEN LOOP GAIN (V/M)

VEE = –15 V
RL = 75 k
106 10 +3.0 V ≤ VCC ≤ +18 V
–3.0 V ≥ VEE ≥ –18 V
VCC = +3.0 V
VEE = –3.0 V
105
1.0
104 0.1
0.1 1.0 10 100 0.01 0.1 1.0 10 100
Figure 5. Input Bias Current Figure 6. Gain Bandwidth Product

versus Ambient Temperature versus Set Current
30 10 M
GBW, GAIN BANDWIDTH PRODUCT (Hz)
+3.0 V ≤ VCC ≤ +18 V

–3.0 V ≥ VEE ≥ –18 V
24
1.0 M
VCC = +15 V
18 VEE = –15 V VCC = +3.0 V
100 k VEE = –3.0 V
Iset = 1.5 µA
12
10 k
6.0 Iset = 1.5 µA
0 1.0 k
–60 –40 –20 0 20 40 60 80 100 120 140 0.1 1.0 10 100
T, TEMPERATURE (°C) Iset, SET CURRENT (µA)

MC1776C
Figure 7. Output Voltage Swing Figure 8. Supply Current

versus Load Resistance versus Ambient Temperature
30 150
VCC = +15 V
V O(pp), PEAK–TO–PEAK OUTPUT
VEE = –15 V
24 Iset = 15 µA
I S , SUPPLY CURRENT ( µA)

VCC = +15 V 120
VOLTAGE SWING (V)
VEE = –15 V
Iset = 15 µA
Iset = 1.5 µA
18 90 Iset = 1.5 µA VCC = +3.0 V
VCC = +15 V VEE = –3.0 V
VEE = –15 V
Iset = 1.5 µA
12 VCC = +3.0 V 60 VCC = +3.0 V
Iset = 1.5 µA
VEE = –3.0 V VEE = –3.0 V
VCC = +15 V
1.5 µA ≤ Iset ≤ 15 µA
6.0 30 VEE = –15 V
0 0
1.0 k 10 k 100 k 1.0 M –60 –40 –20 0 20 40 60 80 100 120 140
RL, LOAD RESISTANCE (Ω) T, AMBIENT TEMPERATURE (°C)
Figure 9. Output Voltage Swing Figure 10. Slew Rate

versus Supply Voltage versus Set Current
40 10
36
VO,OUTPUT VOLTAGE SWING (V)
32
SR, SLEW RATE (Vµ s)
1.0
28
Iset = 15 µA
1.5 µA ≤ Iset ≤ 15 mA RL = 5.0 k
24
RL = 75 k
20 0.1 VCC = +15 V
VEE = –15 V
16 Iset = 1.5 µA
12 RL = 5.0 k
0.01 VCC = +3.0 V
8.0 VEE = –3.0 V
4.0
0 0.001
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0.01 0.1 1.0 10 100
VCC, (VEE), SUPPLY VOLTAGES (V) Iset, SET CURRENT (µA)
Figure 11. Input Noise Voltage Figure 12. Optimum Source Resistance for
versus Set Current Minimum Noise versus Set Current
10–13 100
V(RMS), MEAN SQUARE VOLTAGE(V 2/Hz)
OPTIMUM SOURCE RESISTANCE (M Ω )
10–14
10
f = 1.0 kHz
∆1 = Hz
10–15 +3.0 V ≤ VCC ≤ +18 V
–3.0 V ≥ VEE ≥ –18 V
1.0
10–16
10–17 0.1
0.01 0.1 1.0 10 100 0.01 0.1 1.0 10 100

MC1776C
Figure 13. Wien Bridge Oscillator Figure 15. Multiple Feedback Bandpass Filter
(1.0 kHz)
22 k
+15 V
C R5
200 k +15 V R1 2 7
Input –
10 k 7 C 6
2 MC1776C
–
6 3 Output
MC1776C R2 + 8
3 VO
+ 8 4 2.0 M
4 Rset
for a 1.0 kHz filter R1 = 160 k –15 V
–15 V with Q = 10 R2 = 820
and A (fo) = 1 R5 = 300 k
C = 0.01 µF
R C
C R
1
fo = (for fo = 1.0 kHz)
2π RC
Figure 16. Gated Amplifier
R= 16 kΩ
C = 0.01 µF
1M
+15 V
10 k 2 7
–
6
MC1776C Output
Figure 14. Multiple Feedback Bandpass Filter 3
Input +
4
–15 V
10 k 8
VCC VCC
C R5
C 2.7 M 15 V
R1 2 7
Vin – 270 k
6 10 k
MC1776C Gate Q
R2 3 VO
+
8 5.6 k
4
Rset
VEE
For a given: Choose a value for C, then
fo = center frequency Figure 17. High Input Impedance Amplifier
Q
A (fo) = Gain at center frequency R5 =
Q = quality factor πfoC 10 k
50 M
R5
R1 = +15 V
2A (fo)
500 k 2 90 k
– 7
R1,R5
R2 = 6
4Q2 R1–R5 Input Output
MC1776C
500 k 3
To obtain less than 10% error from the operational amplifier: +
4
QO fo 8
≤ 0.1 –15 V
GBW 50 M
30 M
where fo and GBW are expressed in Hz. GBW is available from
Figure 6 as a function of Set Current, Iset.

MC3301, LM2900,
LM3900
Quad Single Supply

QUAD
These internally compensated Norton operational amplifiers are designed
specifically for single positive power supply applications found in industrial
control systems and automotive electronics. Each device contains four SEMICONDUCTOR
independent amplifiers – making it ideal for applications such as active TECHNICAL DATA
filters, multi–channel amplifiers, tachometers, oscillators and other similar
usage.
• Single Supply Operation
• Wide Unity Gain Bandwidth: 4.0 MHz Typical
N, P SUFFIX
• Low Input Bias Current: 50 nA Typical PLASTIC PACKAGE
•
14 CASE 646
High Open Loop Gain: 1000 V/V Minimum
1
• Large Output Voltage Swing: (VCC – 1) Vpp
D SUFFIX
PLASTIC PACKAGE
14
CASE 751A 1
MAXIMUM RATINGS (SO–14)
LM2900/
Rating Symbol LM3900 MC3301 Unit
Supply Voltage VCC +32 +28 V
Input Current Iin 5.0 mA PIN CONNECTIONS

(Iin+ or Iin–)
Output Current IO 50 mA
Power Dissipation (TA = +25°C) PD 625 mW Input 1 1 14 VCC

Derate above TA = +25°C 1/RθJA 5.0 mW/°C Noninv
Input 2 2 13 Input 3
Ambient Temperature Range TA °C
LM2900 –40 to +85 –40 to +85
Noninv
Inv 3 – + + –
LM3900 0 to +70 12 Input 4
Input 2 2 4
Storage Temperature Range Tstg –65 to +150 °C 2 4 11 Inv
Input 4
Out
1 5 10 4
1 3
Out
Inv – + + –
6 9 3
Input 1
Gnd 7 8 Inv
Input 3
(Top View)
Operating
LM3900D SO–14
TA = 0° to +70°C
LM3900N
Plastic DIP
LM2900N
TA = – 40° to +85°C
MC3301P

MC3301, LM2900, LM3900
ELECTRICAL CHARACTERISTICS (VCC = +15 Vdc, RL = 5.0 kΩ. TA = +25°C [each amplifier], unless otherwise noted.)
LM2900 LM3900 MC3301
Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Unit
Open Loop Voltage Gain AVOL V/mV

f = 100 Hz, RL = 5.0 k 1.2 2.0 – 1.2 2.0 – 1.2 2.0 –
TA = Tlow to Thigh (Notes 1, 2) – – – – – – – – –
Input Resistance (Inverting Input) ri – 1.0 – – 1.0 – – 1.0 – MΩ
Output Resistance ro – 8.0 – – 8.0 – – 8.0 – kΩ
Input Bias Current (Inverting Input) IIB – 50 200 – 50 200 – 50 300 nA

TA = Tlow to Thigh (Note 1) – – – – – – – – –
Slew Rate (CL = 100 pF, RL = 2.0 k) SR V/µs
Positive Output Swing – 0.5 – – 0.5 – – 0.5 –
Negative Output Swing – 20 – – 20 – – 20 –
Unity Gain Bandwidth BW – 4.0 – – 4.0 – – 4.0 – MHz
Output Voltage Swing (Note 7) V

VCC = +15 V, RL = 2.0 k
Vout High (Iin– = 0, Iin += 0) VOH 13.5 14.2 – 13.5 14.2 – 13.5 14.2 –
Vout Low (Iin– = 10 µA, Iin += 0) VOL – 0.03 0.2 – 0.03 0.2 – 0.03 0.2
VCC = Maximum Rating, RL = ∞
Vout High (Iin– = 0, Iin += 0) VOH – 29.5 – – 29.5 – – 25.5 –
Output Current mA
Source ISource 6.0 10 – 6.0 10 – 5.0 10 5.0
Sink (Note 3) ISink 0.5 0.87 – 0.5 0.87 – 0.5 0.87 0.5
Low Level Output Current IOL – 5.0 – – 5.0 – – 5.0 –
Iin– = 5.0 µA, VOL = 1.0 V
Supply Current (All Four Amplifiers) mA
Noninverting Inputs Open IDO – 6.9 10 – 6.9 10 – 6.9 10
Noninverting Inputs Grounded IDG – 7.8 14 – 7.8 14 – 7.8 14
Power Supply Rejection (f = 100 Hz) PSR – 55 – – 55 – – 55 – dB
Mirror Gain (TA = Tlow to Thigh; Notes 1, 4) Ai µA

Iin += 20 µA 0.90 1.0 1.1 0.90 1.0 1.1 0.90 1.0 1.1
Iin += 200 µA 0.90 1.0 1.1 0.90 1.0 1.1 0.90 1.0 1.1
∆ Mirror Gain (TA = Tlow to Thigh; Notes 1, 4) ∆Ai – 2.0 5.0 – 2.0 5.0 – 2.0 5.0 %
20 µA ≤ Iin + ≤ 200 µA
Mirror Current (TA = Tlow to Thigh; Notes 1, 5) – 10 500 – 10 500 – 10 500 µA
Negative Input Current (Note 6) – 1.0 – – 1.0 – – 1.0 – mA
NOTES: 1. Tlow = –40°C for LM2900, MC3301 Thigh = +85°C for LM2900, MC3301
= 0°C for LM3900 = +70°C for LM3900
2. Open loop voltage gain is defined as voltage gain from the inverting input to the output.
3. Sink current is specified for analog operation. When the device is used as a comparator (non–analog operation) where the inverting input is
overdriven, the sink current (low level output current) capability is typically 5.0 mA.
4. This specification indicates the current gain of the current mirror which is used as the noninverting input.
5. Input VBE match between the noninverting and inverting inputs occurs for a mirror current (noninverting input current) of approximately 10 µA.
6. Clamp transistors are included to prevent the input voltages from swinging below ground more than approximately –0.3 V. The negative input
currents that may result from large signal overdrive with capacitive input coupling must be limited externally to values of approximately 1.0 mA. If
more than one of the input terminals are simultaneously driven negative, maximum currents are reduced. Common mode biasing can be used to
prevent negative input voltages.
7. When used as a noninverting amplifier, the minimum output voltage is the VBE of the inverting input transistor.

MC3301, LM2900, LM3900
Figure 1. Open Loop Voltage Gain Figure 2. Open Loop Voltage Gain
versus Frequency versus Supply Voltage
70 2500
OPEN LOOP VOLTAGE GAIN (V/V)

60
2000
50
40 1500
30 1000
20
500
10
0 0
100 1.0 k 10 k 100 k 1.0 M 10 M 0 3.0 6.0 9.0 12 15 18 21 24 27 30
FREQUENCY (Hz) SUPPLY VOLTAGE (Vdc)
Figure 3. Output Resistance Figure 4. Supply Current versus

versus Frequency Supply Voltage
10 k 10
I DO , I DG , SUPPLY CURRENT (mAdc)
(Noninverting Inputs Grounded)
8.0
OUTPUT RESISTANCE ( Ω )
IDG
IDO
6.0
(Noninverting Inputs Open)
1.0 k
4.0
2.0
100 0
0.5 k 1.0 k 5.0 k 10 k 50 k 100 k 500 k 1.0 M 5.0 M 0 3.0 6.0 9.0 12 15 18 21 24 27 30
FREQUENCY SUPPLY VOLTAGE (Vdc)
Figure 5. Analog Source Current Figure 6. Analog Sink Current

versus Supply Voltage versus Supply Voltage
20 1000
OUTPUT SOURCE CURRENT (mAdc)
OUTPUT SINK CURRENT ( µA)
16 800
12 600
VOL = 0.4 Vdc
VOH = 0.4 Vdc
8.0 400
4.0 200
0 0
0 3.0 6.0 9.0 12 15 18 21 24 27 30 0 3.0 6.0 9.0 12 15 18 21 24 27 30
SUPPLY VOLTAGE (Vdc) SUPPLY VOLTAGE (Vdc)

MC3301, LM2900, LM3900
OPERATION AND APPLICATIONS
Basic Amplifier
The basic amplifier is the common emitter stage shown in The sink of the device can be forced to exceed the specified
Figures 7 and 8. The active load I1 is buffered from the input level by keeping the output DC voltage above 1.0 V [
transistor by a PNP transistor, Q4, and from the output by an resulting in an increase in the distortion appearing at the
NPN transistor, Q2. Q2 is biased Class A by the current output. Closed loop stability is maintained by an on–the–chip
source I2. The magnitude of I2 (specified Isink) is a limiting 3–pF capacitor shown in Figure 10 on the following page. No
factor in capacitively coupled analog operation at the output. external compensation is required.
Figure 7. Block Diagram
VCC
14
3 – 6 – 8 – 11 –
#1 4 #2 5 #3 9 #4 10
Gnd 2 + 1 + 13 + 12 +
7
Operational Operational Operational Operational
Biasing Circuitry Amplifier # 1 Amplifier # 2 Amplifier # 3 Amplifier # 4
VCC 3 4 6 5 8 9 11
14
Q6 Q5 Q5 Q5 Q5
Q2 Q2 Q2
10k C1 C1 C1 C1 Q2
Q7 Q4
3.0 pF 3.0 pF Q4 3.0 pF Q4 3.0 pF Q4
Q8 10
3.5 k Q1 Q1 Q1 Q1
Q3 Q3 Q3 Q3
Q9
CR2 CR1 CR1 CR1 CR1
Q11 560 Q10 Q10 Q10
CR3 Q10
CR4 CR5
2 1 13 12
7
Gnd Multiple emitter (8) transistor – one emitter connected to each input.
A noninverting input obtained by adding a current mirror as collector current is approximately equal to Iin+ also. In
shown in Figure 9. Essentially all current which enters the operation this current flows through an external feedback
noninverting input, Iin+, flows through the diode CR1. The resistor which generates the output voltage signal. For
voltage drop across CR1 corresponds to this input current inverting applications, the noninverting input is often used to
magnitude and this same voltage is applied to a matched set the DC quiescent level at the output. Techniques for doing
device, Q3. Thus Q3 is biased to conduct an emitter current this are discussed in the “Normal Design Procedure” section.
equal to Iin+. Since the alpha current gain of Q3 1, its [
Figure 8. A Basic Gain Stage Figure 9. Obtaining A Noninverting Input

VCC
VCC
I1
I1
Iin – Q2
Q2
Q1 Output
( –)
( –) Q1 Output Iin + I2
Inputs
Input Q3 Iin +
I2 ( +)
CR1

MC3301, LM2900, LM3900
Biasing Circuitry
The circuitry common to all four amplifiers is shown in loading. The voltage across resistor R2 is the sum of the
Figure 11. The purpose of this circuitry is to provide biasing voltage drops across CR2, CR3 and CR4, minus the VBE
voltage for the PNP and NPN current sources used in the drops of transistor Q9 and diode CR5; thus the current set is
amplifiers. established by CR5 in all the NPN current sources (Q10,
The voltage drops across diodes CR2, CR3 and CR4 are etc.). This technique results in current source magnitudes
used as references. The voltage across resistor R1 is the which are relatively independent of the supply voltage. Q11
sum of the drops across CR4 and CR3 minus the VBE of Q8. (Figure 7) provides circuit protection from signals that are
The PNP current sources (Q5, etc.) are set to the magnitude negative with respect to ground.
VBE/R1 by transistor Q6. Transistor Q7 reduces base current
Figure 10. A Basic Operational Amplifier Figure 11. Biasing Circuitry
VCC VCC
Q5
Q6
VBE
10 k
R1
Q2 Q7
(–) Q4
Q1 Output Q9
3.0 pF
Inputs CR2 VBE
R2 VBE/R2
Q3 Q8 560 R2
( +) CR3 Q10
CR1 R1 3.5 k CR5
CR4
NORMAL DESIGN PROCEDURE

1. Output Q–Point Biasing
A. A number of techniques may be devised to bias the Choosing the feedback resistor (Rf) to be equal to
quiescent output voltage to an acceptable level. 1/2 Rr will now bias the amplifier output DC level to
However, in terms of loop gain considerations it is approximately VCC/2. This allows the maximum
usually desirable to use the noninverting input to dynamic range of the output voltage.
effect the biasing, as shown in Figures 12 and 13.
The high impedance of the collector of the C. Reference Voltage other than VCC (see Figure 14)
noninverting ‘‘current mirror’’ transistor helps to The biasing resistor (Rr) may be returned to a
achieve the maximum loop gain for any particular voltage(Vr) other than VCC. By setting Rf = Rr, (still
configuration. It is desirable that the noninverting keeping Iin +between 10 µA and 200 µA) the output
input current be in the 10 µA to 200 µA range. DC level will be equal to Vr. The expression for
determining VOdc is:
B. VCC Reference Voltage (see Figures 12 and 13)
(Ai)(Vr)(Rf) R
The noninverting input is normally returned to the VOdc = + (1 – f Ai ) φ
VCC voltage (which should be well filtered) through Rr Rr
a resistor (Rr) allowing the input current, (Iin+) to be
where φ is the VBE drop of the input transistors
within the range of 10 µA to 200 µA.
(approximately 0.6 Vdc @ +25°C and assumed
equal). Ai is the current mirror gain.

MC3301, LM2900, LM3900
Figure 12. Inverting Amplifier Figure 13. Noninverting Amplifier
^
Rf Rf Rf (Rf)(Aj)
510 k AV = – AV = 1
Ri 510 k
26
%
Ri +
for 1 Ri lin +(mA)
VCC +15 V ωC
0.1 µF VCC +15 V
Vin – 1.0 µF –
BW = 250 kHz
Ri VO 0.1 µF lin + +
VO
C 51 k + +
Vin + +5.0 µF
Ri
Rr 10 k 510 k Rr 10 k
1.0 M 1.0 M
+15 V AV = 10 BW = 150 kHz +15 V
2. Gain Determination The lower corner frequency is determined by the

A. Inverting Amplifier coupling capacitors to the input and load resistors.
The amplifier is normally used in the inverting mode. The upper corner frequency will usually be
The input may be capacitively coupled to avoid determined by the amplifier internal compensation.
upsetting the DC bias and the output is normally The amplifier unity gain bandwidth is typically
capacitively coupled to eliminate the DC voltage 400 kHz with 20 dB of closed loop gain or 40 kHz
across the load. Note that when the output is with 40 dB of closed loop gain. The exception to this
capacitively coupled to the load, the value of Isink occurs at low gains where the input resistor
becomes a limitation with respect to the load driving selected is large. The pole formed by the amplifier
capabilities of the device if it is direct coupled. In this input capacitance, stray capacitance and the input
configuration, the AC gain is determined by the ratio resistor may occur before the closed loop gain
of Rf to Ri, in the same manner as for a conventional intercepts the open loop response curve. The
operational amplifier: inverting input capacity is typically 3.0 pF.
R
AV = Rf
i
Figure 14. Inverting Amplifier with Figure 15. Inverting Amplifier with
Arbitrary Reference AV = 100 and Vr = VCC
Rf 510 k
VCC +15 V
0.1 µF
C* Ri
Vin – Vin – 0.1 µF
5.1 k VO
VO
+ +
10 k
1.0 M
Rr lin +
Vr
+15 V fL = 300 Hz, fH = 50 kHz
Vr
AV = 100
*Select for low frequency response.

MC3301, LM2900, LM3900
B. Noninverting Amplifier (Rf)(Ai)

These devices may be used in the noninverting mode Av=
26
(see Figure 13). The amplifier gain in this configuration is Ri +
subject to the current mirror gain. In addition, the Iin +(mA)
resistance of the input diode must be included in the The bandwidth of the noninverting configuration for a
value of the input resistor. This resistance is given Rf value is essentially independent of the gain
26 chosen. For Rf = 510 kΩ the bandwidth will be in excess
approximately Ω, where Iin+is input current in
Iin + of 200 kHz for noninverting of 1, 10, or 100. This is a
milliamperes. The noninverting AC gain expression is result of the loop gain remaining constant for these gains
given by: since the the input resistor is effectively isolated from the
feedback loop.
Figure 16. Tachometer Circuit
VCC = +12 V
Magnetic Pickup
Hysteresis Amplifier 130 Monostable Multivibrator Pulse Averaging
100 k C1
0.1 µF
MSD6100 R1
or equiv R2 6.1 V 100 k 100 k
10 k R1
Magnetic – Power –
1.0 M
Pickup – 4.7 k
Amp 1 Supply Amp 2 – VO Amp 4 Output
+ (nonregulated) + C1 Amp 3 +
R1 0.01 µF 500 k
MSD6100 1.0 M 0.01 µF +
RY
or equiv
10 k
Hysteresis Voltage for Switching Timing Interval: t [ 0.7 R1 C1 Vpp ^ (VO –0.6) Ai t
AiR2 RYC1
VH = R1 (VCC – 1.6)
Figure 17. Voltage Regulator Figure 18. Logic ‘‘OR’’ Gate
VCC
Z1 150 k
R2 VCC = +15 Vdc –
75 k f
A +
75 k
B
– 75 k
Q1 C
+ f=A+B+C
R1
VO
VO = VZ1 +0.6 (1 +
R2
) – VBE
R1 Q1
Note: For positive TC zeners R2 and R1 can be

selected to give TC output.

MC3301, LM2900, LM3900
Figure 19. Logic ‘‘NAND’’ Gate (Large Fan–In) Figure 20. Logic ‘‘NOR’’ Gate
VCC = +15 Vdc
75 k
A A –
f
75 k 75 k +
B B
C – 75 k
f C f = A +B +C +D
+ 150 k
D 75 k
E D
150 k VCC = +15 Vdc
f = A +B +C +D
f=ABCD•E
VCC
Figure 21. R–S Flip–Flop Figure 22. Astable Multivibrator
VCC VCC VCC = +15 Vdc

0.1 µF
100 k 100 k 100 k
– – 51 k
Q Q 1.0 M
+ + –
51 k 1.0 M VO
+
22 k 22 k
Reset Set
Figure 23. Positive–Edge Differentiator Figure 24. Negative–Edge Differentiator
Output Rise Time ≈ 0.22 ms 0.001 µF

Input Change Time Constant ≈ 1.0 ms
0.001 µF 100 k
∆Vin
100 k –
0.002 µF 51 k VO
∆Vin +
–
0.002 µF
VO 150 k
+
51 k
VCC = +15 Vdc
VO(dc) ≈ 7.0 Vdc

Output Rise Time ≈ 0.22 ms
Input Change Time Constant ≈ 1.0 ms

MC3301, LM2900, LM3900
Figure 25. Amplifier and Driver for a 50 Ω Line

510 k
+15 V
2N4401
51 k or equiv
Vin –
0.1 µF
+
10 20 µF
1N914 +
VO
or equiv
1.2 M 10
1N914
or equiv 2N4403 50
or equiv
AV = 10 5.6 k
VO = 6.0 V(p–p)
+15 V
Figure 26. Basic Bandpass and Notch Filter

R
R1
BP C 390 k
R1
C × 10 TBP
C R 6 390 k 8
Vin – 4 – 5 –
R2 3 9
1 13
+ + +
TBP = Center Frequency Gain 2
TN = Passband Notch Gain 14
2(R | | QR) Ir R×2 390 k
1
w0 = VCC
RC
R1 = QR TN R2
R1 2(R1 | | R3)
R1 R2 R3
R2 =
TBP 10 Notch
11
R3 = TN R2
C1
12 7
Figure 27. Bandpass and Notch Filter
62 k
0.005 µF
0.005 µF 100 k
300 k
6 8
– – –
3 4 62 k 5 100 k 9
Amp 1 Amp 2 Amp 3
2 1 13
+ + +
BP
100 k 120 k 100 k VCC (Pin 14) = +12 V
300 k Ground – Pin 7
VCC VCC 300 k VCC Center Frequency 500 Hz
300 k Q=5
Bandpass Gain = 1
11
–
0.1 µF 300 k 10 Bandpass Output Pin 4
Amp 4 Notch Notch Output Pin 10
300 k 12
Vin VCC +

MC3301, LM2900, LM3900
Figure 28. Voltage Regulator
1N3824
V
4.3 V Z or equiv
VCC VO = VZ +0.6 Vdc

1.0 Ω/16 W NOTES: 1. R is used to bias the zener.
2. If the zener TC is positive, and equal in
magnitude to the negative TC of the input
– 0.1 µF to the operational amplifier (≈2.0 mV/°C),
the output is zero–TC. A 7.0 V zener will
100 give approximately zero–TC.
+
MJE800 VO
10 R
or equiv 5.0 V at 4.0 A
Figure 29. Zero Crossing Detector
VCC = +15 V
1.0 M 1.0 M
Input 0V
510 k 510 k
– Output
Magnetic
Pickup 510 k Output 0V
510 k
+

MC3403
Quad Low Power MC3303
The MC3403 is a low cost, quad operational amplifier with true differential
inputs. The device has electrical characteristics similar to the popular
MC1741C. However, the MC3403 has several distinct advantages over QUAD DIFFERENTIAL INPUT
standard operational amplifier types in single supply applications. The quad OPERATIONAL AMPLIFIERS
amplifier can operate at supply voltages as low as 3.0 V or as high as 36 V
with quiescent currents about one third of those associated with the
MC1741C (on a per amplifier basis). The common mode input range SEMICONDUCTOR
includes the negative supply, thereby eliminating the necessity for external TECHNICAL DATA
biasing components in many applications. The output voltage range also
includes the negative power supply voltage.
• Short Circuit Protected Outputs
• Class AB Output Stage for Minimal Crossover Distortion
• True Differential Input Stage 14
1
• Single Supply Operation: 3.0 V to 36 V D SUFFIX
• Split Supply Operation: ±1.5 V to ±18 V PLASTIC PACKAGE
CASE 751A
• Low Input Bias Currents: 500 nA Max (SO–14)
• Four Amplifiers Per Package
• Similar Performance to Popular MC1741C 14
• Industry Standard Pinouts 1
• ESD Diodes Added for Increased Ruggedness P SUFFIX

PLASTIC PACKAGE
Single Supply Split Supplies CASE 646
3.0 V to 36 V VCC VCC
1 1 1.5 V to 18 V
PIN CONNECTIONS
2 2
3 3
Out 1 1 14 Out 4
1.5 V to 18 V
4 4
2 – – 13
VEE, Gnd VEE Inputs 1 1 3 Inputs 4
3 + + 12
MAXIMUM RATINGS VCC 4 11 VEE/Gnd

5 + 10
Power Supply Voltages Vdc Inputs 2 2 4 + Inputs 3
Single Supply VCC 36 – –
6 9
Split Supplies VCC, VEE ±18
Out 2 7 8 Out 3
Input Differential Voltage Range (Note 1) VIDR ±36 Vdc
Input Common Mode Voltage Range VICR ±18 Vdc (Top View)
(Notes 1, 2)

Operating Ambient Temperature Range TA °C
MC3303 –40 to +85 Operating
MC3403 0 to +70 Device Temperature Range Package
Junction Temperature TJ 150 °C MC3303D SO–14

MC3303P TA = – 40° to +85°C Plastic DIP
NOTES: 1. Split power supplies.
SO–14
2. For supply voltages less than ±18 V, the absolute maximum input voltage is equal MC3403D
to the supply voltage. TA = 0° to +70°C Plastic DIP
MC3403P

MC3403 MC3303
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V for MC3403; VCC = +14 V, VEE = Gnd for MC3303
TA = 25°C, unless otherwise noted.)
MC3403 MC3303
Input Offset Voltage VIO – 2.0 10 – 2.0 8.0 mV
TA = Thigh to Tlow (Note 1) – – 12 – – 10
TA = Thigh to Tlow – – 200 – – 250
VO = ±10 V, RL = 2.0 kΩ 20 200 – 20 200 –
TA = Thigh to Tlow 15 – – 15 – –
Input Bias Current IIB – –200 –500 – –200 –500 nA
TA = Thigh to Tlow – – –800 – – –1000
Output Impedance f = 20 Hz zo – 75 – – 75 – Ω
Input Impedance f = 20 Hz zi 0.3 1.0 – 0.3 1.0 – MΩ
Output Voltage Range VO V
RL = 10 kΩ ±12 ±13.5 – 12 12.5 –
RL = 2.0 kΩ ±10 ±13 – 10 12 –
RL = 2.0 kΩ, TA = Thigh to Tlow ±10 – – 10 – –
Input Common Mode Voltage Range VICR +13 V +13 V – +12 V +12.5 V – V
–VEE –VEE –VEE –VEE
Common Mode Rejection RS ≤ 10 k Ω CMR 70 90 – 70 90 – dB

Power Supply Current (VO = 0) RL = ∞ ICC, IEE – 2.8 7.0 – 2.8 7.0 mA
Individual Output Short–Circuit Current (Note 2) ISC ±10 ±20 ±45 ±10 ±30 ±45 mA
Positive Power Supply Rejection Ratio PSRR+ – 30 150 – 30 150 µV/V
Negative Power Supply Rejection Ratio PSRR– – 30 150 – 30 150 µV/V
Average Temperature Coefficient of Input ∆IIO/∆T – 50 – – 50 – pA/°C
Offset Current
TA = Thigh to Tlow
Average Temperature Coefficient of Input ∆VIO/∆T – 10 – – 10 – µV/°C
Offset Voltage
TA = Thigh to Tlow
Power Bandwidth BWp – 9.0 – – 9.0 – kHz
AV = 1, RL = 10 kΩ, VO = 20 V(p–p), THD = 5%
Small–Signal Bandwidth BW – 1.0 – – 1.0 – MHz

AV = 1, RL = 10 kΩ, VO = 50 mV
Slew Rate AV = 1, Vi = –10 V to +10 V SR – 0.6 – – 0.6 – V/µs

Rise Time AV = 1, RL = 10 kΩ, VO = 50 mV tTLH – 0.35 – – 0.35 – µs
Fall Time AV = 1, RL = 10 kΩ, VO = 50 mV tTLH – 0.35 – – 0.35 – µs
Overshoot AV = 1, RL = 10 kΩ, VO = 50 mV os – 20 – – 20 – %
Phase Margin AV = 1, RL = 2.0 kΩ, VO = 200 pF φm – 60 – – 60 – Degrees
Crossover Distortion – – 1.0 – – 1.0 – %
(Vin = 30 mVpp,Vout= 2.0 Vpp, f = 10 kHz)
NOTES: 1. Thigh = +70°C for MC3403, +85°C for MC3303

Tlow = 0°C for MC3403, –40°C for MC3303
2. Not to exceed maximum package power dissipation.

MC3403 MC3303
MC3403 MC3303
Input Offset Voltage VIO – 2.0 10 – – 10 mV
Input Offset Current IIO – 30 50 – – 75 nA
Input Bias Current IIB – –200 –500 – – –500 nA
Large Signal Open Loop Voltage Gain AVOL 10 200 – 10 200 – V/mV
RL = 2.0 kΩ
Power Supply Rejection Ratio PSRR – – 150 – – 150 µV/V

Output Voltage Range (Note 3) VOR Vpp
RL = 10 kΩ, VCC = 5.0 V 3.3 3.5 – 3.3 3.5 –
RL = 10 kΩ, 5.0 ≤ VCC ≤ 30 V VCC–2.0 VCC–1.7 – VCC–2.0 VCC–1.7 –
Power Supply Current ICC – 2.5 7.0 – 2.5 7.0 mA
Channel Separation CS – –120 – – –120 – dB
f = 1.0 kHz to 20 kHz
(Input Referenced)
NOTES: 3. Output will swing to ground with a 10 kΩ pull down resistor.

Bias Circuitry
Common to Four
Output Amplifiers
VCC
Q19 Q18 Q27
Q20 Q17
Q16
Q23
40 k
5.0 pF Q29
31k Q28
Q1
+ Q15
Q22 Q24
2.0 k Q13
Inputs 25
Q9
37 k Q11
– Q21 Q25 Q12
Q6 Q30
Q2 Q5 2.4 k
Q7 Q10
Q3 Q4 60 k Q8
VEE (Gnd)

MC3403 MC3303
CIRCUIT DESCRIPTION
Inverter Pulse Response stage performs not only the first stage gain function but also
5.0 V/DIV

amplifier stage.
The output stage is unique because it allows the output to
swing to ground in single supply operation and yet does not
20 µs/DIV exhibit any crossover distortion in split supply operation. This
The MC3403/3303 is made using four internally is possible because Class AB operation is utilized.
compensated, two–stage operational amplifiers. The first Each amplifier is biased from an internal voltage regulator
stage of each consists of differential input device Q24 and which has a low temperature coefficient, thus giving each
Q22 with input buffer transistors Q25 and Q21 and the amplifier good temperature characteristics as well as
differential to single ended converter Q3 and Q4. The first excellent power supply rejection.
Figure 1. Sine Wave Response Figure 2. Open Loop Frequency Response
120
AV = 100 VCC = 15 V
VEE = –15 V
0.5 V/DIV
100
TA = 25°C
A VOL , LARGE SIGNAL
80
60
40
20
50 mV/DIV
*Note Class A B output stage produces distortion less sinewave. –20

1.0 10 100 1.0 k 10 k 100 k 1.0 M
50 µs/DIV f, FREQUENCY (Hz)

MC3403 MC3303
Figure 3. Power Bandwidth Figure 4. Output Swing versus Supply Voltage

30
TA = 25°C
30
VO, OUTPUT VOLTAGE RANGE (V pp)

25 +15 V
–
20 VO
+
–15 V 10 k
20
15
10
5.0 10
TA = 25°C
0
–5.0 0
1.0 k 10 k 100 k 1.0 M 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
f, FREQUENCY (Hz) VCC AND (VEE), POWER SUPPLY VOLTAGES (V)
Figure 5. Input Bias Current Figure 6. Input Bias Current

300 VCC = 15 V
VEE = –15 V
TA = 25°C 170
200
160
100
150
–75 –55 –35 –15 5.0 25 45 65 85 105 125 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
T, TEMPERATURE (°C) VCC AND (VEE), POWER SUPPLY VOLTAGES (V)

VCC 50 k
1N914
VCC
10 k 5.0 k
R2 – 1N914
1/2 VCC
MC3403 VO 10 k
+ Vref –
1/2
MC3403 VO
+
10 k
R1 R1 1 fo = 1
Vref = V 2πRC
VO = R1 +R2 2 CC
R C For: fo = 1.0 kHz
1 R C R = 16 kΩ
VO = V
2 CC C = 0.01 µF

MC3403 MC3303
1 Hysteresis
e1 – R R2
C R
1/2 VOH
MC3403
+ R1
Vref – VO
1/2
MC3403 VO
a R1 –
R1 1/2 Vin + VOL
MC3403 eo
VinL VinH
+ R1
b R1 1 VinL = (VOL –Vref) +Vref Vref
R R1 +R2
– 1/2 C
MC3403 R1
VinH = (VOH –Vref) +Vref
e2 + R1 +R2
R
R1
eo = C (1 +a +b) (e2 –e1) Vh = (VOH –VOL)
R1 +R2
R fo = 1
R 2πRC
100 k
C R1 = QR 1
C Vref = V
C1 R2 2 CC
Vin – R2 = R1
1/2 TBP R = 160 kΩ
– 100 k
MC3403 1/2 R3 = TNR2 C = 0.001 µF
–
+ MC3403 1/2 C1 = 10 C R1 = 1.6 MΩ
+ MC3403 R2 = 1.6 MΩ
Vref + R3 = 1.6 MΩ
Vref
Vref Bandpass R3
Output
R1
R2
– C1
1/2
MC3403 Notch Output
For: fo = 1.0 kHz Where: TBP = center frequency gain
Q = 10 TN = passband notch gain +
TBP =1 Vref
TN =1
1
Vref = V VCC
2 CC
R2 C R3
Triangle Wave R1 C
Vref Output 300 k Vin – CO
+ 1/2
1/2 R3 MC3403 VO
MC3403 + Square Wave
75 k 1/2 + CO = 10 C
– Output R2
R1 MC3403
100 k –
Vref Vref 1
Vref = V
C 2 CC
Given: fo = center frequency
Rf
R1 +RC R2 R1
f= if R3 = Choose value fo, C
4 CRf R1 R2 +R1
Then: R3 = Q R1 = R3 R2 = R1 R5
π fo C 2 A(fo) 4Q2 R1 –R5
Oo fo
For less than 10% error from operational amplifier < 0.1
BW
where fo and BW are expressed in Hz.


MC3405
Dual Operational Amplifier

and Dual Comparator DUAL OPERATIONAL
AMPLIFIER / DUAL
The MC3405 contains two differential–input operational amplifiers and VOLTAGE COMPARATOR
two comparators, each set capable of single supply operation. This
operational amplifier–comparator circuit fulfills its applications as a general
SEMICONDUCTOR
purpose product for automotive and consumer circuits as well as an
TECHNICAL DATA
industrial building block.
The MC3405 is specified over the commercial operating temperature
range of 0° to +70°C.
• Operational Amplifier Equivalent in Performance to MC3403
• Comparator Similar in Performance to LM339
• Single Supply Operation: 3.0 V to 36 V
• Split Supply Operation: ±1.5 V to ±18 V
• Low Supply Current Drain
• Operational Amplifier is Internally Frequency Compensated 14
• Comparator TTL and CMOS Compatible 1
P SUFFIX
PLASTIC PACKAGE
CASE 646
PIN CONNECTIONS
Out 1 1 14 Out 4
Comp Op
2
1 Amp 1 13
+ –
– +
3 12
VCC 4 11 VEE/Gnd
Comp Op
2 Amp 2
5 10
+ +
2 3
Inputs 2 – – Inputs 3
6 9
Single Supply Split Supplies Out 2 7 8 Out 3

3.0 V to 36 V VCC VCC
(Top View)
1 1 1.5 V to 18 V
2 2
3 3
1.5 V to 18 V ORDERING INFORMATION
4 4
Operating
VEE, Gnd VEE
MC3405P TA = 0° to +70°C Plastic DIP

MC3405
OPERATIONAL AMPLIFIER SECTION
MAXIMUM RATINGS
Power Supply Voltage – Single Supply VCC 36 Vdc
Power Supply Voltage – Split Supplies VCC, VEE ±18
Input Differential Voltage Range VIDR ±36 Vdc

Input Common Mode Voltage Range VICR ±18 Vdc
Operating Junction Temperature Range TJ 150 °C
Input Offset Voltage VIO – 2.0 10 mV
Input Bias Current IIB – –200 –500 nA
Large–Signal, Open Loop Voltage Gain (RL = 2.0 kΩ) AVOL 20 200 – V/mV
Power Supply Rejection PSR – – 150 µV/V
(RL = 10 kΩ, VCC = 5.0 V) 3.3 3.5 –
(RL = 10 kΩ, 5.0 V ≤ VCC ≤ 30 V) VCC – 2.0 VCC –1.7 –
Power Supply Current (Notes 2 and 3) ICC – 2.5 7.0 mA
Channel Separation, f = 1.0 kHz to 20 kHz (Input Referenced) – – –120 – dB
(TA = Tlow + Thigh) (Note 4) – – 12
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T – 15 – µV/°C
Input Offset Current IIO – – 50 nA
(TA = Tlow to Thigh) (Note 4) – – 200
(TA = Tlow to Thigh) (Note 4) – – –800
Input Common Mode Voltage Range VICR +13 –VEE – – Vdc
Large Signal, Open Loop Voltage Gain AVOL V/mV
(VO = ±10 V, RL = 2.0 kΩ) 20 200 –
(TA = Tlow to Thigh) (Note 4) 15 100 –
Power Supply Rejection Ratio PSRR – 30 150 µV/V
Output Voltage VO Vdc
(RL = 10 kΩ) ±12 ±13.5 –
(RL = 2.0 kΩ) ±10 ±13 –
(RL = 2.0 kΩ, TA = Tlow to Thigh) (Note 4) ±10 – –
Output Short Circuit Current ISC ±10 ±20 ±45 mA
Power Supply Current (Notes 2 and 3) ICC, IEE – 2.8 7.0 mA
Phase Margin φm – 60 – Degrees
Small–Signal Bandwidth (AV = 1, RL = 10 kΩ, VO = 50 mV) BW – 1.0 – MHz
NOTES: 1. Output will swing to ground.
3. For operational amplifier and comparator.
4. Tlow = 0°C, Thigh = +70°C

MC3405
Power Bandwidth (AV = 1, RL = 2.0 kΩ, VO = 20 Vpp, THD = 5%) BWp – 9.0 – kHz
Rise Time/Fall Time tTLH, tTHL – 0.35 – µs
Overshoot (AV = 1, RL = 10 kΩ, VO = 50 mV) os – 20 – %
Slew Rate SR – 0.6 – V/µs
COMPARATOR SECTION
MAXIMUM RATINGS
Power Supply Voltage – Single Supply VCC 36 Vdc
Power Supply Voltage – Split Supplies VCC, VEE ±18
Input Common Mode Voltage Range VICR –0.3 to +36 Vdc
Sink Current ISink 20 mA
Operating Junction Temperature Range TJ 150 °C
(TA = Tlow to Thigh) (Notes 1 and 2) – – 12
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T – 15 – µV/°C
(TA = Tlow to Thigh) (Note 1) – – –800
Input Common Mode Voltage Range VICR 0 VCC –1.5 VCC –1.7 Vpp
(TA = Tlow to Thigh) (Note 1) 0 VCC –1.7 VCC –2.0
Input Differential Voltage VID – – 36 V
(All Vin ≥ 0 Vdc)
Large–Signal, Open Loop Voltage Gain (RL = 15 kΩ) AVOL – 200 – V/mV
Output Sink Current (–Vin ≥ 1.0 Vdc, +Vin= 0, VO ≤ 1.5 V) ISink 6.0 16 – mA
Low Level Output Voltage VOL µA
(+Vin= 0 V, –Vin= 1.0 V, ISink = 4.0 mA) – 350 500
Output Leakage Current IOL µA
(+Vin ≥ 1.0 Vdc, –Vin= 0, VO = 5.0 Vdc) – 0.1 1.0
(TA = Tlow to Thigh) (Note 1) – 0.1 1.0
Large–Signal Response – – 300 – ns
Response Time (Note 3) (VRL = 5.0 Vdc, RL = 5.1 kΩ) – – 1.3 – µs
^
NOTES: 1. Tlow = 0°C, Thigh = +70°C
2. VO 1.4 V, RS = 0 Ω with VCC from 5.0 Vdc to 30 Vdc, and over the input common mode range 0 to VCC –1.7 V.
3. The response time specified is for a 100 mV input step with 5.0 mV overdrive. For larger signals 300 ns is typical.

2–132

(+) Output (+) (–)

10,12 8,14 2, 6 3, 5 VCC
4
Q23 Q20 Q31 Q32

Q19 Q29
Q18 Q17
Q16
(–) Q24 Q22
Q25 Q21 Q26 Q30
9, 13 Q15 Q27 Q33
31.2 k 25
Output
Q13 1,7
5.0 pF 30 34.4 k
MC3405
pF Q36
Q12 Q42 Q34
Q7 Q11 Q37
Q35
Q43 Q38
Q28
Q39
Q2 Q6
Q9
Q5 Q27 Q8 Q10 Q14

MOTOROLA ANALOG IC DEVICE DATA
Q4
Q3
Operational Amplifier Side Q40

Q1 Q41
2.0 k 2.4 k 700
11
Bias Circuitry Common Comparator Side VEE/Gnd
to All Op Amps and
Comparators
MC3405
OPERATIONAL AMPLIFIER SECTION

120
AV = 100 VCC = 15 V
VEE = –15 V
0.5 V/DIV

100
TA = 25°C

80
60
40
20
50 mV/DIV

1.0 10 100 1.0 k 10 k 100 k 1.0 M

30
TA = 25°C
VO, OUTPUT VOLTAGE RANGE (Vpp )
30
25 +15 V
–
20 VO
+
–15 V 10 k
15 20
10
5.0 10
TA = 25°C
0
–5.0 0
1.0 k 10 k 100 k 1.0 M
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
f, FREQUENCY (Hz)
VCC AND |VEE|, POWER SUPPLY VOLTAGES (V)

300 VCC = 15 V
VEE = –15 V
TA = 25°C 170
200
160
100
150
–75 –55 –35 –15 5.0 25 45 65 85 105 125 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
T, TEMPERATURE (°C) VCC AND |VEE|, POWER SUPPLY VOLTAGES (V)

MC3405
COMPARATOR SECTION
Figure 7. Normalized Input Offset Voltage Figure 8. Input Bias Current
1.40 200

VCC = +15 V
1.20
INPUT OFFSET VOLTAGE
VEE = Gnd
NORMALIZED TO 25 C
160
°
TA = –55°C
1.00
120 TA = +25°C
0.80
80 TA = +125°C
0.60 VEE = Gnd
Slope Can Be Either Polarity.
0.40 40
–60 –40 –20 0 20 40 60 80 100 120 140 2.0 6.0 10 14 18 22 26 30
TA, AMBIENT TEMPERATURE (°C) VCC, POSITIVE SUPPLY VOLTAGE (V)
Figure 10. Output Sink Current versus

Figure 9. Normalized Input Offset Current Output Voltage
2.20 7.0
TA = +25°C
ISink , OUTPUT SINK CURRENT (mA)

6.0
1.80
INPUT OFFSET VOLTAGE
NORMALIZED TO 25 C
TA = –55°C
°
5.0
1.40
VCC = +15 V 4.0
VEE = Gnd
1.00 3.0
TA = +125°C
2.0
0.60 VCC = +15 V
Slope Can Be Either Polarity. 1.0 VEE = Gnd
0.20 0
–60 –40 –20 0 20 40 60 80 100 120 140 0 200 400 600 800 1000
TA, AMBIENT TEMPERATURE (°C) VOL, OUTPUT VOLTAGE (mV)
Figure 11. Pulse Width Modulator Schematic and Waveforms
1.0 M VCC VSW (a) Oscillator Square Wave Output

VCC
10 k 2 5.0 k 4 5.0 k
VC +
3 Comp 1 + 7
VCC – 1 6 Comp 2 Vout
– VEE
5 11 Time
5.0 k
VEE (b) Triangle Wave and Control Voltage
vt
10 VTH
+ 8 300 k VC
Amp 2 vt
– R1 VTL
9 Time
C 150 k 12
+ 14
R2 Amp 1 VSW (c) Output Pulses
– Vout
13 VCC
5.0 k Rf
VEE 1 VEE
VTH = V (1 + R2/R1) + VEE VS = VCC – VEE Time
2 S
1 1 Vc – VTL
VTL = V (1 – R2/R1) + VEE Pulse Width = when: VTL < VC < VTH
2 S f VTH – VTL
R1
Oscillator Frequency f = Vc – VTL
4RfCR2
Duty Cycle in % = (100)
VTH – VTL

MC3405
Figure 12. Window Comparator
VCC VO
10 k
VCC 13
10 k 13 ∆V
∆V – 14 5 4 3.0 k
∆V
Adjust 12 Amp 1 – 7
+ 6 Comp 2
+ Vin
10 k 11
10 k
10 k VEE
3
9 – 1
VCC vO
10 k – 8 2 Comp
+
1
–13
10 Amp 2
+ VC
VC Adjust
Vin
VEE
Figure 13. Squelch Circuit for AM or FM

C3
VCC
R2
C1 C2 13
Vin – 14 3 2.7 k
12 Amp 1 – 1 10
+ 2 Comp 1 + 8
R1 + 2.7 k 9 Amp 2 VAO
C4 R3 –
High Pass Filter VCC

100 k
High Pass Filter
Given: Ao, Q, ωo = 2πfo Rf
Choose: C = C1 = C2, a convenient value Squelch Ri
Threshold Adj
Calculate: R2 = Q (2Ao + 1)
ωoC VAi
R3C4 > 5 Tin Switched Audio Stage
C3 = C Where : Tin is the period of Vin
Ao Q = Quality Factor Gain of Audio Stage
Ao R
R1 = Ao = High Frequency Gain ACI = f
QωoC(2Ao + 1) ωo = Break Frequency Ri
Figure 14. High/Low Limit Alarm
VCC
10 k VC
10 k R6 VCC
R4 12
+ 14
10 k 13 Amp 1 Oscillator
VCC – 0
R5 VIL VIH Vi
R1 VCC Rf 33 k R3
1.0 k 3 VIL = VCC
R1 + R2 + R3
– 1 10
2 Comp 1 2.0 k + 8
+ 9 Amp 2 VO VIH = VCC R2 + R3
– R1 + R2 + R3
Vi R2 0.01 µF Oscillator
5 2.0 k C
– 7 If R4 = R5 = R6
1.0 k 6 Comp 2
+ VC f = 0.72/RfC
Hi/Low As shown, f = 2.2 kHz
R3 Limit Detector VO will oscillate if VIH < Vi, or VIL > Vi
VO will be low if VIL < Vi < VIH

MC3405
Figure 15. Zero Crossing Detector with Temperature Sensor
VCC
10 k 2 Zero Crossing Detector 12
VCC + Vt = (VBE of Q1) R4 + R5
+ 14
3 Comp 1 VO R5
Vin – 1 VCC 13 Amp 1
1N914 + –
R1 2VBE
R2 VD R6 10 k 13 >
– 1.0 M VEE R5
+ 6 + Temp R8 10
10 k
VD Comp 2 7 Adjust R1 and R2 control the switching
1N914 + 8
– 5 voltage of the zero crossing detector
VEE –
10 k
VCC 9 Amp 2
10 k –
R7 ±VS = ±VD R1 + R2
13 R3 R2
vt
+VS
R4 0
–VS
Q1
R5 Temperature Sensor
vo Time
VCC
TA < TSet
VEE
Figure 16. LSTTL to CMOS Interface with Hysteresis Figure 17. NOR Gate
+ 5.0 V + 15 V VCC
27 k
3.0 k *
– A
Comp *
+ B 10 k 3.0 k*
C +
50 k D Comp * G
2.4 k
–
LSTTL Level Shift CMOS

VIL = 1.17 V 10 k 10 k
VIH = 1.80 V
* The same configuration may be used with an op amp if G=A+B+C+D

the 3.0 k resistor is removed.
* The same configuration may be used with an
op amp if the 3.0 k resistor is removed.

MC3458
MC3358
Dual, Low Power
Utilizing the circuit designs perfected for the quad operational amplifiers, DUAL DIFFERENTIAL
these dual operational amplifiers feature: 1) low power drain, 2) a common INPUT
mode input voltage range extending to ground/VEE, and 3) Single Supply or
Split Supply operation. OPERATIONAL AMPLIFIERS
These amplifiers have several distinct advantages over standard
operational amplifier types in single supply applications. They can operate at SEMICONDUCTOR
supply voltages as low as 3.0 V or as high as 36 V with quiescent currents TECHNICAL DATA
about one–fifth of those associated with the MC1741C (on a per amplifier
basis). The common mode input range includes the negative supply, thereby
eliminating the necessity for external biasing components in many
applications. The output voltage range also includes the negative power
supply voltage.
• Short Circuit Protected Outputs 8
• True Differential Input Stage 1
• Single Supply Operation: 3.0 V to 36 V P1 SUFFIX

• Low Input Bias Currents PLASTIC PACKAGE
CASE 626
• Common Mode Range Extends to Negative Supply
• Class AB Output Stage for Minimum Crossover Distortion
• Single and Split Supply Operations Available 8
• Similar Performance to the Popular MC1458 1
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
PIN CONNECTIONS
MAXIMUM RATINGS
Output A 1 8 VCC
Power Supply Voltages Vdc 2
–
7 Output B
Single Supply VCC 36 Inputs A +
3 6
Split Supplies VCC, VEE ±18 – Inputs B
+
VEE/Gnd 4 5
Input Differential Voltage Range (1) VIDR ±30 Vdc
Input Common Mode Voltage Range (2) VICR ±15 Vdc
(Top View)
Operating Ambient Temperature Range TA °C ORDERING INFORMATION
MC3458 0 to +70
Operating
MC3358 –40 to +85
NOTES: 1. Split Power Supplies.
2. For supply voltages less than ±18 V, the absolute maximum input voltage is equal MC3358P1 TA = –40° to +85°C Plastic DIP
to the supply voltage. SO–8
MC3458D
TA = 0° to +70°C
MC3458P1 Plastic DIP

MC3458 MC3358
ELECTRICAL CHARACTERISTICS (For MC3458, VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
(For MC3358, VCC = +14 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
MC3458 MC3358
Input Offset Voltage VIO – 2.0 10 – 2.0 8.0 mV
TA = Thigh to Tlow (Note 1) – – 12 – – 10
TA = Thigh to Tlow – – 200 – – 250
VO = ±10 V, RL = 2.0 kΩ, 20 200 – 20 200 –
TA = Thigh to Tlow 15 – – 15 – –
Input Bias Current IIB – –200 –500 – –200 –500 nA
TA = Thigh to Tlow – – –800 – – –1000
Output Impedance, f = 20 Hz zO – 75 – – 75 – Ω
Input Impedance, f = 20 Hz zI 0.3 1.0 – 0.3 1.0 – MΩ
Output Voltage Range VOR V
RL = 10 kΩ ±12 ±13.5 – 12 12.5 –
RL = 2.0 kΩ ±10 ±13 – 10 12 –
RL = 2.0 kΩ, TA = Thigh to Tlow ±10 – – 10 – –
Input Common Mode Voltage Range VICR +13 +13.5 – +13 +13.5 – V
–VEE –VEE –VEE –VEE
Common Mode Rejection Ratio, RS ≤ 10 kΩ CMR 70 90 – 70 90 – dB

Power Supply Current (VO = 0) RL = ∞ ICC, IEE – 1.6 3.7 – 1.6 3.7 mA
Individual Output Short Circuit Current (Note 2) ISC ±10 ±20 ±45 ±10 ±30 ±45 mA
Positive Power Supply Rejection Ratio PSRR+ – 30 150 – 30 150 µV/V
Negative Power Supply Rejection Ratio PSRR– – 30 150 – – – µV/V
Average Temperature Coefficient of Input ∆IIO/∆T – 50 – – 50 – pA/°C
Offset Current, TA = Thigh to Tlow
Average Temperature Coefficient of Input ∆VIO/∆T – 10 – – 10 – µV/°C
Offset Current, TA = Thigh to Tlow
Power Bandwidth BWp – 9.0 – – 9.0 – kHz
AV = 1, RL = 2.0 kΩ, VO = 20 Vpp, THD = 5%
Small Signal Bandwidth BW – 1.0 – – 1.0 – MHz
AV = 1, RL = 10 kΩ, VO = 50 mV
Slew Rate SR – 0.6 – – 0.6 – V/µs
AV = 1, VI = –10 V to +10 V
Rise Time tTLH – 0.35 – – 0.35 – µs
AV = 1, RL = 10 kΩ, VO = 50 mV
Fall Time tTHL – 0.35 – – 0.35 – µs
AV = 1, RL = 10 kΩ, VO = 50 mV
Overshoot os – 20 – – 20 – %
AV = 1, RL = 10 kΩ, VO = 50 mV
Phase Margin φm – 60 – – 60 – Degrees
AV = 1, RL = 2.0 kΩ, CL = 200 pF
Crossover Distortion – – 1.0 – – 1.0 – %
(Vin = 30 mVpp, Vout = 2.0 Vpp, f = 10 kHz)
NOTES: 1. Thigh = 70°C for MC3458, 85°C for MC3358
Tlow = 0°C for MC3458, –40°C for MC3358

MC3458 MC3358
MC3458 MC3358
Input Offset Voltage VIO – 2.0 5.0 – 2.0 10 mV
Input Offset Current IIO – 30 50 – – 75 nA
Input Bias Current IIB – –200 –500 – – –500 nA
Large Signal Open Loop Voltage Gain AVOL 20 200 – 20 200 – V/mV
RL = 2.0 kΩ,
Power Supply Rejection Ratio PSRR – – 150 – – 150 µV/V
RL = 10 kΩ, VCC = 5.0 V 3.3 3.5 – 3.3 3.5 –
RL = 10 kΩ, 5.0 V ≤ VCC ≤ 30 V – VCC – – VCC –
–1.7 –1.7
Power Supply Current ICC – 2.5 7.0 – 2.5 4.0 mA
Channel Separation CS – –120 – – –120 – dB
f = 1.0 kHz to 20 kHz (Input Referenced)
NOTE: 3. Output will swing to ground with a 10 kΩ pull down resistor.

MC3458 MC3358

Bias Circuitry
Common to Both
Output Amplifiers
VCC
Q19 Q18 Q27
Q20 Q17
Q16
Q23
40 k
5.0 pF Q29
31 k Q28
Q1
Q15
+
Q22 Q24
2.0 k Q13 25
Inputs
Q9
37k Q11
Q21 Q25 Q12
– Q6 Q30
2.4 k
Q2 Q5 Q10
Q7
Q3 Q4 60 k Q8
VEE (Gnd)
Inverter Pulse Response differential to single ended converter Q3 and Q4. The first
stage performs not only the first stage gain function but also
5 V/DIV
Another feature of this input stage is that the input Common

Mode range can include the negative supply or ground, in
amplifier stage.
The output stage is unique because it allows the output to
20 µs/DIV swing to ground in single supply operation and yet does not
exhibit any crossover distortion in split supply operation. This
is possible because Class AB operation is utilized.
CIRCUIT DESCRIPTION Each amplifier is biased from an internal voltage regulator
The MC3458/3358 is made using two internally which has a low temperature coefficient thus giving each
compensated, two–stage operational amplifiers. The first amplifier good temperature characteristics as well as
stage of each consists of differential input devices Q24 and excellent power supply rejection.
Q22 with input buffer transistors Q25 and Q21 and the

MC3458 MC3358

120
AV = 100 VCC = +15 V
VEE = –15 V

0.5 V/DIV
100
TA = 25°C

80
60
40
20
50 mV/DIV

1.0 10 100 1.0 k 10 k 100 k 1.0 M

30
30 TA = 25°C
VO, OUTPUT VOLTAGE RANGE (V pp)
25 +15 V
–
20 VO
+
–15 V 10 k
20
15
10
5.0 10
TA = 25°C
0
–5.0 0
1.0 k 10 k 100 k 1.0 M 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
f, FREQUENCY (Hz) VCC AND (VEE), POWER SUPPLY VOLTAGES (V)

300 VCC = +15 V

VEE = –15 V
TA = 25°C 170
200
160
100
150
–75 –55 –35 –15 5.0 25 45 65 85 105 125 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
T, TEMPERATURE (°C) VCC AND (VEE), POWER SUPPLY VOLTAGES (V)

MC3458 MC3358

VCC 50 k
VCC
10 k 5.0 k
R2 –
1/2 VCC
MC3458 VO 10 k
+ Vret –
1/2
MC3458 VO
+ fo = 1
10 k 2πRC
R1
VO =
R1 Vref = 1 VCC
R1 +R2 2 For: fo
R = 1.0 kHz
C R
1 R C
VO = V = 16 kΩ
2 CC
C
= 0.01 µF
Figure 9. High Impedance Differential Amplifier Figure 10. Comparator with

Hysteresis
1 Hysteresis
e1 + R R2
C R
1/2 VOH
MC3458
– R1
Vret + VO
1/2
MC3458 VO
a R1 –
R1 1/2 Vin – VOL
MC3458 eo
VinL VinH
+
b R1 VinL = R1 (VOL – Vref) +Vref Vref
1 R1 +R2
R
– 1/2 C
MC3458 VinH = R1 (VOH – Vref) +Vref
e2 + R1 +R2
R
Vh = R1 (VOH – VOL)
R1 +R2
eo = C (1 +a +b) (e2 –e1)
R
R
100 k fo = 1
2πRC
C1 C C
R2 R1 = QR 1
Vref = V
Vin – 2 CC
1/2
– R2 = R1
MC3458 1/2 100 k TBP R = 160 kΩ
–
+ MC3458 1/2 R3 = TN R2 C = 0.001 µF
+ MC3458 C1 = 10 C R1 = 1.6 MΩ
Vref + R2 = 1.6 MΩ
R3 = 1.6 MΩ
Vref For: fo = 1.0 kHz
Vref Bandpass R3 Q = 10
Output TBP = 1
R1
R2 TN = 1
– C1
1/2
MC3458 Notch Output
Where: TBP = center frequency gain +
TN = passband notch gain
Vref

MC3458 MC3358
Figure 12. Function Generator
Vref = 1 VCC Triangle Wave R2

2
Output 300 k
Vref + R3
1/2
MC3458 +
75 k 1/2 Square Wave
– R1 MC3458 Output
100 k –
Vref
C
Rf
R1 +RC
f= if, R3 = R2 R1
4 CRf R1 R2 +R1
Figure 13. Multiple Feedback Bandpass Filter
VCC
C R3
R1 C
Vin –
1/2
MC3458 VO
+ CO
R2
CO = 10 C
Vref Vref = 1 VCC

2
Given: fo = center frequency

Choose value fo, C.
Then: R3 = Q R1 = R3 R2 = R1 R5
π fo C 2 A(fo) 4Q2 R1 – R3
Qo fo
For less than 10% error from operational amplifier < 0.1
BW
where, fo and BW are expressed in Hz.

MC3476
Low Cost Programmable
The MC3476 is a low cost selection of the popular industry standard LOW COST PROGRAMMABLE
MC1776 programmable operational amplifier. This extremely versatile OPERATIONAL AMPLIFIER
operational amplifier features low power consumption and high input
impedance. In addition, the quiescent currents within the device may be
programmed by the choice of an external resistor value or current source SEMICONDUCTOR
applied to the Iset input. This allows the amplifier’s characteristics to be TECHNICAL DATA
optimized for input current and power consumption despite wide variations in
operating power supply voltages.
• ±6.0 V to ±18 V Operation
• Wide Programming Range
• Offset Null Capability
• Low Input Bias Currents
•
8
Short Circuit Protection 1
Resistive Programming P1 SUFFIX

(See Figure 1) PLASTIC PACKAGE
CASE 626
Rset to Ground Rset to Negative Supply
(Recommended for supply voltage
less than ±6.0 V)
7 VCC 7 VCC
2 2
– –
6 6
3 3
+ +
8 8 PIN CONNECTIONS
4 Rset 4 Rset
VCC – 0.6
Iset = VCC – 0.6 – VEE
VEE VEE Iset =
Rset Offset Null 1 8 Iset
Rset
Invert 2 – 7 VCC
Typical Rset Values Typical Rset Values Input
Noninvert 3 + 6 Output
VCC, VEE Iset = 1.5 µA Iset = 15 µA VCC, VEE Iset = 1.5 µA Iset = 15 µA
±6.0 V 3.6 MΩ 360 kΩ +1.5 V 1.6 MΩ 160 kΩ VEE 4 5 Offset Null
±10 V 6.2 MΩ 620 kΩ +3.0 V 3.6 MΩ 360 kΩ
±12 V 7.5 MΩ 750 kΩ +6.0 V 7.5 MΩ 750 kΩ
±15 V 10 MΩ 1.0 MΩ +15 V 20 MΩ 2.0 MΩ (Top View)
Active Programming
FET Current Source Bipolar Current Source
7
7 VCC 2
2 –
– 6
6
3
3 +
+ 4 VEE
4 VEE 8 Q
8
VG VB
VEE
R Operating
Pins not shown are not connected.
MC3476P1 TA = 0° to +70°C Plastic DIP

MC3476

Power Supply Voltages VCC, VEE ±18 Vdc
Input Common Mode Voltage Range VICR VCC, VEE Vdc
Offset Null to VEE Voltage Voff – VEE ±0.5 Vdc
Programming Current Iset 200 µA
Programming Voltage Vset (VCC – 0.6 V) Vdc
(Voltage from Iset Terminal to Ground) to VCC
Storage Temperature Range Tstg – 55 ot +125 °C
NOTES: 1. Short circuit to ground with Iset v 15 µA. Rating applies up to ambient temperature of +70°C.
8 Iset 7
VCC
2 – 50
Inputs
3
+
2.0 k
100
30 pF 100 6
Output
100
1
50
Offset Null
5
10 k 10 k
4
VEE
Voltage Offset Null Circuit Transient Response Test Circuit
2 7 VCC
7 VCC
– 6
2 –
6 VO
3
+
3 + 5
1 4
8 100 k 8 CL RL
4 Vin
VEE
Rset Rset Pins not shown are
not connected.
VEE

MC3476
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = – 15 V, Iset = 15 µA, TA = +25°C, unless otherwise noted).
Input Offset voltage (RS ≤ 10 kΩ) VIO mV
TA = +25°C – 2.0 6.0
0°C ≤ TA ≤ +70°C – – 7.5
TA = +25°C – 20 25
TA = +70°C – – 25
TA = 0°C – – 40
TA = +25°C – 15 50
TA = +70°C – – 50
TA = 0°C – – 100
Input Common Mode Voltage Gain VICR ±10 – – V
0°C ≤ TA ≤ +70°C
RL ≥ 10 kΩ, VO = ±10 V, TA = +25°C 50 k 400 k –
RL ≥ 10 kΩ, VO = ±10 V, 0°C ≤ TA ≤ +70°C 25 k – –
Output Voltage Range VOR V
RL ≥ 10 kΩ, TA = +25°C ±12 ±13 –
RL ≥ 10 kΩ, 0°C ≤ TA ≤ +70°C ±12 – –
RS ≤ 10 kΩ, 0°C ≤ TA ≤ +70°C
Supply Voltage Rejection Ratio PSRR – 25 200 µV/V
RS ≤ 10 kΩ, 0°C ≤ TA ≤ +70°C
TA = +25°C – 160 200
0°C ≤ TA ≤ +70°C – – 225
Power Dissipation PD mW
TA = +25°C – 4.8 6.0
0°C ≤ TA ≤ +70°C – – 6.75
Vin = 20 mV, RL w
10 kΩ, CL = 100 pF
Slew Rate (RL ≥ 10 kΩ) SR – 0.8 – V/µs

MC3476
Figure 2. Positive Standby Supply Current

Figure 1. Set Current versus Set Resistor versus Set Current
POSITIVE STANDBY SUPPLY CURRENT ( µA)

100 M 1000
VCC = +15 V +6.0 V ≤ VCC ≤ +15 V
VEE = –15 V –6.0 V ≥ VEE ≥ –15 V
R set , SET RESISTOR ( Ω )
Rset to VEE
10 M VCC = +15 V 100
VEE = –15 V
Rset to GND
1.0 M 10
100 k 1.0
10 k 0.1
0.1 1.0 10 100 0.01 0.1 1.0 10 100
Figure 3. Open Loop versus Set Current Figure 4. Input Bias Current versus Set Current
107 100
VCC = +15 V
A VOL , OPEN LOOP GAIN (V/V)
+6.0 V ≤ VCC ≤ +15 V

VEE = – 15 V
RL = 10 k –6.0 V ≥ VEE ≥ –15 V
106 10
105
1.0
104 0.1
0.1 1.0 10 100 0.01 0.1 1.0 10 100
Figure 5. Slew Rate Figure 6. Gain Bandwidth Product

versus Set Current versus Set Current
10 10M
GBW, GAIN BANDWIDTH PRODUCT (Hz)
VCC = +15 V
1.0 1.0M VEE = –15 V
SR, SLEW RATE (V/µ s)
VCC = +15 V
VEE = –15 V
0.1 100k
0.01 10k
0.001 1.0k
0.01 0.1 1.0 10 100 0.1 1.0 10 100

MC3476

versus Load Resistance versus Supply Voltage
30 40
V O(pp) , PEAK–TO–PEAK OUTPUT
36
VO,OUTPUT VOLTAGE SWING (V)

24 32
VOLTAGE SWING (V)
28
18 24 Iset = 1.5 µA
RL = 5.0 k
20
12 16
VCC = +15 V 12
6.0 VEE = –15 V 8.0
Iset = 15 µA
4.0
0 0
1.0 k 10 k 100 k 1.0 M 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
RL, LOAD RESISTANCE (Ω) VCC, |VEE|, SUPPLY VOLTAGES (V)

MC4558AC
MC4558C
Dual Wide Bandwidth
The MC4558AC, C combine all the outstanding features of the MC1458 DUAL WIDE BANDWIDTH
and, in addition offer three times the unity gain bandwidth of the industry OPERATIONAL AMPLIFIERS
standard.
• 2.5 MHz Unity Gain Bandwidth Guaranteed (MC4558AC)
SEMICONDUCTOR
• 2.0 MHz Unity Gain Bandwidth Guaranteed (MC4558C)
TECHNICAL DATA
• Gain and Phase Match between Amplifiers
8
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) 1
Rating Symbol MC4558AC MC4558C Unit P1 SUFFIX

PLASTIC PACKAGE
Power Supply Voltage VCC +22 +18 Vdc CASE 626
VEE –22 –18

Input Common Mode Voltage VICM ±15 V 8
(Note 1) 1

(Note 2) D SUFFIX
PLASTIC PACKAGE
Ambient Temperature Range TA 0 to +70 °C CASE 751
(SO–8)
NOTES: 1. For supply voltages less than ±15 V, the absolute maximum input voltage is equal
to the supply voltage.
2. Short circuit may be to ground or either supply.
PIN CONNECTIONS
Representative Schematic Diagram Output A 1 8 VCC

2 A 7 Output B
–
2.9 k Inputs A + B
VCC 3 6
–
+
Inputs B
VEE 4 5
Inverting
Input – 620
150 (Top View)
Input +
Noninverting
25
Output
25
10 pF ORDERING INFORMATION
Operating
5.0 k 53 5.0 k 680 1.84 k 20 k 50 k
pF
VEE MC4558CD SO–8
TA = 0° to +70°C
MC4558ACP1,CP1 Plastic DIP

MC4558AC MC4558C
FREQUENCY CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C)

MC4558AC MC4558C
Characteristic Symbol Unit
Min Typ Max Min Typ Max
Unity Gain Bandwidth BW 2.5 2.8 – 2.0 2.8 – MHz
ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)

Input Offset Voltage (RS ≤ 10 kΩ) VIO – 1.0 5.0 – 2.0 6.0 mV
Input Bias Current (Note 1) IIB – 80 500 – 80 500 nA
Input Resistance ri 0.3 2.0 – 0.3 2.0 – MΩ
Input Capacitance Ci – 1.4 – – 1.4 – pF
Common Mode Input Voltage Range VICR ±12 ±13 – ±12 ±13 – V
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kΩ) AVOL 50 200 – 20 200 – V/mV
Output Resistance ro – 75 – – 75 – Ω
Common Mode Rejection (RS ≤ 10 kΩ) CMR 70 90 – 70 90 – dB
Supply Voltage Rejection Ratio (RS ≤ 10 kΩ) PSRR – 30 150 – 30 150 µV/V
(RL ≥ 10 kΩ) ±12 ±14 – ±12 ±14 –
(RL ≥ 2.0 kΩ) ±10 ±13 – ±10 ±13 –
Output Short Circuit Current ISC 10 20 40 10 20 40 mA
Supply Currents (Both Amplifiers) ID – 2.3 5.0 – 2.3 5.6 mA
Power Consumption (Both Amplifiers) PC – 70 150 – 70 170 mW
(VI = 20 mV, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Rise Time tTLH – 0.3 – – 0.3 – µs
(VI = 20 mV, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Overshoot os – 15 – – 15 – %
(VI = 10 V, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Slew Rate SR 1.5 1.6 – 1.0 1.6 – V/µs
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Thigh to Tlow, unless otherwise noted. See Note 2.)
Input Offset Voltage (RS ≤ 10 kΩ) VIO – 1.0 6.0 – – 7.5 mV
(TA = Thigh) – 7.0 200 – – –
(TA = Tlow) – 85 500 – – –
(TA = 0° to +70°C) – – – – – 300
(TA = Thigh) – 30 500 – – –
(TA = Tlow) – 300 1500 – – –
(TA = 0° to +70°C) – – – – – 800
Common Mode Input Voltage Range VICR ±12 ±13 – – – – V
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kΩ) AVOL 25 – – 15 – – V/mV
Common Mode Rejection (RS ≤ 10 kΩ) CMR 70 90 – – – – dB
Supply Voltage Rejection Ratio (RS ≤ 10 kΩ) PSRR – 30 150 – – – µV/V
(RL ≥ 10 kΩ) ±12 ±14 – ±12 ±14 –
(RL ≥ 2.0 kΩ) ±10 ±13 – ±10 ±13 –
Supply Currents (Both Amplifiers) ID mA
(TA = Thigh) – – 4.5 – – 5.0
(TA = Tlow) – – 6.0 – – 6.7
Power Consumption (Both Amplifiers) PC mW
(TA = Thigh) – – 135 – – 150
(TA = Tlow) – – 180 – – 200
NOTES: 1. IIB is out of the amplifier due to PNP input transistors.
2. Thigh = +70°C, Tlow = 0°C.

MC4558AC MC4558C
1000 100
e n, INPUT NOISE (Peak) ( µ V)

en,INPUT NOISE (Peak) (µV)

100 10
10 1.0
0 0.1
10 100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 10 k 100 k 1.0 M
10 140
en, OUTPUT NOISE (RMS) (mV)
120
AV = 1000 e n, INPUT NOISE ( nV/ √ Hz ) AV = 10, RS = 100 k Ω
100
1.0
100 80
10 60
0.1 1.0 40
20
0.01 0
10 100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k
Positive
100 k Threshold +
Voltage
–
– To Pass / Fail
100 k X 500 X2 Indicator
+
1.0 k –
100 k Low Pass Filter
Under Test 1.0 Hz to 1.0 kHz +
Negative
Threshold
Voltage
Unlike conventional peak reading or RMS meters, this system was The test time employed is 10 sec and the 20 µV peak limit
especially designed to provide the quick response time essential refers to the operational amplifier input thus eliminating errors
to burst (popcorn) noise testing. in the closed loop gain factor of the operational amplifier.

MC4558AC MC4558C
Figure 6. Open Loop Frequency Response Figure 7. Phase Margin versus Frequency
180
PHASE MARGIN (DEGREES)

140 160
A VOL , VOLTAGE GAIN (dB)
120 140
100 120
80 100
60 80
Unity
40 60 Gain
20 40
0 20
–20 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
15 15
±15 V Supplies ±15 V Supplies
VO,OUTPUT VOLTAGE (Vpeak )
13 13
±12 V ±12 V
11 11
9.0 9.0
±9.0 V ±9.0 V
7.0 7.0
±6.0 V ±6.0 V
5.0 5.0
3.0 3.0
±3.0 V ±3.0 V
1.0 1.0
100 500 1.0 k 2.0 k 10 k 20 k 50 k 100 k 100 500 1.0 k 2.0 k 10 k 20 k 50 k 100 k

(Large Signal Swing versus Frequency) Figure 11. Transient Response Test Circuit
28
24 To Scope
(Input)
– To Scope
20
(Output)
+
16 RL CL
12
8.0 Voltage Follower

THD < 5% VI
4.0
0
10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)

MCT4558C
Dual Wide Bandwidth
The MCT4558C combines all of the outstanding features of the MC1458
and, in addition, offers three times the unity gain bandwidth of the industry DUAL WIDE BANDWIDTH
standard. OPERATIONAL AMPLIFIER
• 2.0 MHz Unity Gain Bandwidth Guaranteed
SEMICONDUCTOR
• Short Circuit Protection TECHNICAL DATA
• Gain and Phase Match Between Amplifiers
This MCT–prefixed device is intended to be a possible replacement for the similar

device with the MC–prefix. Because the MCT device originates from different
source material, there may be subtle differences in typical parameter values or
characteristic curves. Due to the diversity of potential applications, Motorola can not
assure identical performance in all circuits. Motorola recommends that the 8
customer qualify the MCT–prefixed device in each potential application. 1
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) P1 SUFFIX

PLASTIC PACKAGE
Rating Symbol Value Unit CASE 626
Power Supply Voltages VCC +18 Vdc
VEE –18
Input Differential Voltage VID ± 30 V

8
1
Output Short Circuit Duration (Note 2) tSC Continuous
D SUFFIX
Ambient Temperature Range TA 0 to +70 °C PLASTIC PACKAGE
Storage Temperature Range Tstg – 55 to +125 °C CASE 751
(SO–8)
NOTES: 1. For supply voltages less than ±15 V, the absolute maximum input voltage is equal to
the supply voltage.
2. Short circuit may be to ground or either supply.
PIN CONNECTIONS
Output A 1 8 VCC
VCC
A
2 7 Output B
–
Inputs A + B
3 6
–
Inputs B
–In A Out A Out B –In A +
VEE 4 5
+In A +In A
(Top View)
VEE
This device contains 29 active transistors. Operating
CAUTION: These devices do not have internal ESD protection circuitry and are rated
as CLASS 1 devices per the ESD test method in Mil–Std–833D. They should be handled MCT4558CD SO–8
TA = 0° to +70°C
using standard ESD prevention methods to avoid damage to the device. MCT4558CPI Plastic DIP

MCT4558C
FREQUENCY CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C)

Unity Gain Bandwidth BW 2.0 2.8 — MHz
ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)

Input Offset Voltage VIO — 2.0 6.0 mV
(RS ≤ 10 kΩ)
Input Offset Current IIO — 20 200 nA
Input Bias Current (Note 1) IIB — 80 500 nA
Common Mode Input Voltage Range VICR ±12 ±13 — V
Large Signal Voltage Gain AVOL 20 200 — V/mV
(VO = ±10 V, RL = 2.0 kΩ)
Common Mode Rejection CMR 70 90 — dB
(RS ≤ 10 kΩ)
Supply Voltage Rejection Ratio PSRR — 30 150 µV/V
(RS ≤ 10 kΩ)
Output Voltage Swing VO
(RL ≥ 10 kΩ) ±12 ±14 — V
(RL ≥ 2.0 kΩ) ±10 ±13 —
Output Short Circuit Current ISC 10 20 75 mA
Supply Currents (Both Amplifiers) ID — 4.0 5.6 mA
Power Consumption (Both Amplifiers) PC — 70 170 mW
(VI = 20 mV, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Rise Time tTLH — 0.3 — µs
(VI = 20 mV, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Overshoot os — 15 — %
(VI = 10 V, RL ≥ 2.0 kΩ, CL ≤ 100 pF) Slew Rate SR 1.0 1.8 — V/µs
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Thigh to Tlow, [Note 2] unless otherwise noted.)
Input Offset Voltage VIO — — 7.5 mV
(RS ≤ 10 kΩ)
Input Offset Current IIO — — 300 nA
(TA = 0° to +70°C)
Input Bias Current IIB — — 800 nA
(TA = 0° to +70°C)
Large Signal Voltage Gain AVOL 15 — — V/mV
(VO = ±10 V, RL = 2.0 kΩ)
(RL ≥ 10 kΩ) ±12 ±14 —
(RL ≥ 2.0 kΩ) ±10 ±13 —
Supply Currents (Both Amplifiers) ID mA
(TA = Thigh) — — 5.0
(TA = Tlow) — — 6.7
Power Consumption (Both Amplifiers) PC mW
(TA = Thigh) — — 150
(TA = Tlow) — — 200
NOTES: 1. IIB is out of the amplifier due to PNP input transistors.
2. Tlow = 0°C Thigh = +70°C

MCT4558C
Figure 1. Power Bandwidth Figure 2. Maximum Output Voltage Swing

(Large Signal Swing versus Frequency) versus Load Resistance
VO , MAXIMUM OUTPUT VOLTAGE SWING (V pp)

28 32
VCC = +15 V
24 VCC = +15 V
VEE = –15 V
VEE = –15 V 28 TA = +25°C

20
16 24
12
20
8.0
16
4.0
0 12
10 100 1.0 k 10 k 100 k 1.0 M 0.1 0.3 0.5 1.0 3.0 5.0 10
f, FREQUENCY (Hz) RL, LOAD RESISTANCE (kΩ)
Figure 3. Equivalent Input Noise Voltage Figure 4. Input Bias Current

versus Frequency versus Ambient Temperature
1000
en , EQUIVALENT INPUT NOISE VOLTAGE
VCC = +15 V 80 VCC = +15 V

500
VEE = –15 V VEE = –15 V
300 TA = +25°C 70 TA = +25°C
RS = 50 Ω
100 60
( nV/ √ Hz )
50 50
30
40
10
30
5.0
20
1.0 3.0 10 30 100 300 1000 – 40 – 30 – 20 0 20 40 60 80 100
Figure 5. Voltage Gain and Phase

versus Frequency Figure 6. Transient Response Test Circuit
50 80
VCC = +5.0 V
40 100
VEE = – 5.0 V
30 120 To Scope
– To Scope
φ, PHASE (DEGREES)
20 2A 1A 140 (Input) (Output)

+
10 160 RL CL
0 1B 180
–10 200
– 20 2B 220
1A) Phase CL = 0 pF VI
– 30 2A) Phase CL = 200 pF 240
1B) Gain CL = 0 pF
– 40 260
2B) Gain CL = 200 pF
– 50 280
10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)

MC4741C
Differential Input
The MC4741C is a true quad MC1741. Integrated on a single monolithic DIFFERENTIAL INPUT
chip are four independent, low power operational amplifiers which have been OPERATIONAL AMPLIFIER
designed to provide operating characteristics identical to those of the (QUAD MC1741)
industry standard MC1741, and can be applied with no change in circuit
performance. SEMICONDUCTOR
The MC4741C can be used in applications where amplifier matching or TECHNICAL DATA
high packing density is important. Other applications include high
impedance buffer amplifiers and active filter amplifiers.
• Each Amplifier is Functionally Equivalent to the MC1741
• Class AB Output Stage Eliminates Crossover Distortion
• True Differential Inputs
•
14
Internally Frequency Compensated
•
1
Short Circuit Protection
P SUFFIX
• Low Power Supply Current (0.6 mA/Amplifier) PLASTIC PACKAGE
CASE 646
14
1
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
PIN CONNECTIONS
Out 1 1 14 Out 4
2
* * 13
Inputs 1
3
) 1 4
) 12
Inputs 4

(1/4 of Circuit Shown) VCC 4 11 VEE
VCC 5
) ) 10
Noninverting
G Inputs 2
6
* 2 3
* 9
Inputs 3
Input
4.5 k Out 2 7 8 Out 3
39 k 25
Inverting
Input 30 pF 7. 5k (Top View)
Output
50
Offset ORDERING INFORMATION
Null 50 k 50 Operating
1.0 k 50 k 1.0 k 5.0 k
MC4741CD SO–14
TA = 0° to +70°C
MC4741CP Plastic DIP

MC4741C

VEE –18
Input Common Mode Voltage VICM ±18 V
High Impedance Instrumentation Buffer/Filter
+
1/4
MC4741C
– C1
R4
R1
– R5 56
1/4
+
MC4741C 1/4
VID
+ C2 MC4741C
–
– R2
1/4
MC4741C
+
R3

MC4741C
Input Bias Current IIB – 80 500 nA
Offset Voltage Adjustment Range VIOR – ±15 – mV
Common Mode Input Voltage Range VICR ±12 ±13 – V
Large Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) Av 20 200 – V/mV
Output Resistance ro – 75 – Ω
Supply Voltage Rejection Ratio (RS ≤ 10 k) PSRR – 30 150 µV/V
(RL ≥ 10 k) ±12 ±14 –
(RL ≥ 2 k) ±10 ±13 –
Supply Current – (All Amplifiers) ID – 3.5 7.0 mA
Power Consumption (All Amplifiers) PC – 105 210 mW
Transient Response (Unity Gain – Non–Inverting)
(VI = 20 mV, RL ≥ 2 kΩ, CL ≤ 100 pF) Rise Time tTLH – 0.3 – µs
(VI = 20 mV, RL ≥ 2 kΩ, CL ≤ 100 pF) Overshoot os – 15 – %
(VI = 10 V, RL ≥ 2 kΩ, CL ≤ 100 pF) Slew Rate SR – 0.5 – V/µs
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = * Thigh to Tlow, unless otherwise noted.)
Input Offset Current (TA = 0° to + 70°C) IIO – – 300 nA
Input Bias Current (TA = 0° to + 70°C) IIB – – 800 nA
Large Signal Voltage Gain (RL ≥ 2k, VOUT = ±10 V) AV 15 – – V/mV
Output Voltage Swing (RL ≥ 2 k) VO ±10 ±13 – V
* Thigh = 70°C Tlow = –0°C

MC4741C

28
120
24 100
A VOL, VOLTAGE GAIN (dB)

20 80
16 60
12 40
8.0 Voltage Follower

THD < 5% 20
4.0 0
0
–20
10 100 1.0 k 10 k 100 k 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
15 –15
14 –14
13 ±15 V Supplies –13 ±15 V Supplies
12 –12
11 –11
10 ±12 V –10 ±12 V
9.0 –9.0
8.0 –8.0
7.0 ±9.0 V –7.0
6.0 –6.0 ±9.0 V
5.0 –5.0
4.0 ±6.0 V –4.0 ±6.0 V
3.0 –3.0
2.0 –2.0
1.0 –1.0
100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 k 100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 k

Load Resistance (Single Supply Operation) Figure 6. Noninverting Pulse Response
28 30 V Supply
26
VO , OUTPUT VOLTAGE SWING (V pp )
24 27 V
22
20 24 V
18 21 V
16
5.0 V/DIV
Output
14 18 V
12
10 15 V
8.0 12 V
6.0
9.0 V Input
4.0
2.0 6.0 V
0 5.0 V
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 10 µs/DIV
RL, LOAD RESISTANCE (kW)

MC4741C
R 1
fo =
R 2πRC
100 k
C R1 = QR 1
C Vref = V
C1 R2 2 CC
Vin – R2 = R1
1/4 TBP R = 160 kΩ
– 100 k
MC4741C 1/4 C = 0.001 µF
– R3 = TNR2
+ MC4741C 1/4 C1 = 10 C R1 = 1.6 MΩ
+ MC4741C R2 = 1.6 MΩ
Vref + R3 = 1.6 MΩ
Vref
Vref Bandpass R3
Output
R1
R2
– C1
1/4
MC4741C Notch Output
For: fo = 1.0 kHz Where: TBP = center frequency gain
Q = 10 TN = passband notch gain +
TBP = 1 Vref
TN = 1

versus Supply Voltage Figure 9. Transient Response Test Circuit
105
100
To Scope
95 (Input)
–
90 To Scope
+ (Output)
85 RL CL
80
75
70
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
Figure 10. Absolute Value DVM Front End

0.5 µF
500 k
MSD6150 500 k
– 1
1/4
MC4741C
1.0 k + MC1505
2
900 k
+ 1.0 k MSD6102 1.0 M

1/4
– 1/4 47 k Common Mode Adjust
MC4741C
MC4741C
–
100 k – 1/4 +
VCC 1.0 k + MC4741C Polarity
–
+
1.0 M
MC4741 Quad Op Amp
500 k
Bridge Null Adjust
VEE

MC33076
Dual High Output Current,

DUAL HIGH OUTPUT
Low Power, Low Noise CURRENT OPERATIONAL
Bipolar Operational Amplifier AMPLIFIER
The MC33076 operational amplifier employs bipolar technology with SEMICONDUCTOR
innovative high performance concepts for audio and industrial applications. TECHNICAL DATA
This device uses high frequency PNP input transistors to improve frequency
response. In addition, the amplifier provides high output current drive
capability while minimizing the drain current. The all NPN output stage
exhibits no deadband crossover distortion, large output voltage swing,
excellent phase and gain margins, low open loop high frequency output 8
impedance and symmetrical source and sink AC frequency performance. 1
8
1
The MC33076 is tested over the automotive temperature range and is
available in an 8–pin SOIC package (D suffix) and in both the standard 8 pin D SUFFIX P1 SUFFIX
DIP and 16–pin DIP packages for high power applications. PLASTIC PACKAGE PLASTIC PACKAGE
• 100 Ω Output Drive Capability
CASE 751 CASE 626
(SO–8)
• Large Output Voltage Swing
• Low Total Harmonic Distortion PIN CONNECTIONS
Output 1 1 8 VCC
2 7 Output 2
• Dual Supply Operation: ±2.0 V to ±18 V Inputs 1
–
+1
• High Output Current: ISC = 250 mA typ
3 – 6
2 + Inputs 2
• Similar Performance to MC33178 VEE 4 5
(8 Pin Pkg, Top View)
P2 SUFFIX
Equivalent Circuit Schematic PLASTIC PACKAGE
(Each Amplifier) 16 CASE 648C
1 DIP (12+2+2)
VCC
PIN CONNECTIONS
1 – 16 Output 1
Inputs 1
Iref 2 + 1 15 NC
NC 3 14 VCC
Iref
4 13
VEE VEE
5 12
Vin– Vin+ CC NC 6 11 NC
Vout
7 + 10 NC
Inputs 2
CM 8 – 2 9 Output 2
(16 Pin Pkg, Top View)
Operating
VEE MC33076D SO–8
MC33076P1 TA = – 40° to + 85°C Plastic DIP
MC33076P2 Power Plastic

MC33076
MAXIMUM RATINGS
Power Supply Voltage (Note 2) VCC to +36 V
VEE
Input Differential Voltage Range VIDR (Note 1) V

Input Voltage Range VIR (Note 1) V
Output Short Circuit Duration (Note 2) tSC 5.0 sec
NOTES: 1. Either or both input voltages should not exceed VCC or VEE.
is not exceeded (see power dissipation performance characteristic, Figure 1).
See applications section for further information.
DC ELECTRICAL CHARACTERICISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Input Offset Voltage (RS = 50 Ω, VCM = 0 V) 2 |VIO| mV
(VS = ±2.5 V to ±15 V)
TA = +25°C — 0.5 4.0
TA = –40° to +85°C — 0.5 5.0
Input Offset Voltage Temperature Coefficient ∆VIO/∆T µV/°C
(RS = 50 Ω, VCM = 0 V)
TA = –40° to +85°C — 2.0 —
Input Bias Current (VCM = 0 V) 3, 4 IIB nA
TA = +25°C — 100 500
TA = –40° to +85°C — — 600
Input Offset Current (VCM = 0 V) |IIO| nA
TA = +25°C — 5.0 70
TA = –40° to +85°C — — 100
Common Mode Input Voltage Range 5 VICR –13 –14 V
+14 13
Large Signal Voltage Gain (VO = –10 V to +10 V) 6 AVOL kV/V

(TA = +25°C)
RL = 100 Ω 25 — —
RL = 600 Ω 50 200 —
(TA = –40° to +85°C)
RL = 600 Ω 25 — —
Output Voltage Swing (VID = ±1.0 V) 7, 8, 9 V
(VCC = +15 V, VEE = –15 V)
RL = 100 Ω VO+ 10 +11.7 —
RL = 100 Ω VO– — –11.7 –10
RL = 600 Ω VO+ 13 +13.8 —
RL = 600 Ω VO– — –13.8 –13
(VCC = +2.5 V, VEE = –2.5 V)
RL = 100 Ω VO+ 1.2 +1.66 —
RL = 100 Ω VO– — –1.74 –1.2
Common Mode Rejection (Vin = ±13 V) 10 CMR 80 116 — dB
Power Supply Rejection 11 PSR dB
(VCC/VEE = +15 V/–15 V, +5.0 V/–15 V, +15 V/–5.0 V) 80 120 —

MC33076
DC ELECTRICAL CHARACTERICISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Output Short Circuit Current (VID = ±1.0 V Output to Gnd) 12, 13 ISC mA
(VCC = +15 V, VEE = –15 V)
Source 190 +250 —
Sink — –280 –215
(VCC = +2.5 V, VEE = –2.5 V)
Source 63 +94 —
Sink — –80 –46
Power Supply Current per Amplifier (VO = 0 V) 14 ID mA
(VS = ±2.5 V to ±15 V)
TA = +25°C — 2.2 2.8
TA = –40° to +85°C — — 3.3
AC ELECTRICAL CHARACTERICISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Slew Rate (Vin = –10 V to +10 V, RL = 100 Ω, CL = 100 pF, AV = +1) 15 SR 1.2 2.6 — V/µs
Gain Bandwidth Product (f = 20 kHz) 16 GBW 4.0 7.4 — MHz
Unity Gain Frequency (Open Loop) (RL = 600 Ω, CL = 0 pF) — fU — 3.5 — MHz
Gain Margin (RL = 600 Ω, CL = 0 pF) 19, 20 Am — 15 — dB
Phase Margin (RL = 600 Ω, CL = 0 pF) 19, 20 ∅m — 52 — Deg
Channel Separation (f = 100 Hz to 20 kHz) 21 CS — –120 — dB
Power Bandwidth (VO = 20 Vpp, RL = 600 Ω, THD ≤ 1%) — BWp — 32 — kHz
Total Harmonic Distortion (RL = 600 Ω, VO = 2.0 Vpp, AV = +1) 22 THD %
f = 1.0 kHz — 0.0027 —
f = 10 kHz — 0.011 —
f = 20 kHz — 0.022 —
Open Loop Output Impedance (VO = 0 V, f = 2.5 MHz, AV = 10) 23 |ZO| — 75 — Ω
Differential Input Resistance (VCM = 0 V) — Rin — 200 — kΩ
Differential Input Capacitance (VCM = 0 V) — Cin — 10 — pF
Equivalent Input Noise Voltage (RS = 100 Ω) 24 en nV/√Hz
f = 10 Hz — 7.5
f = 1.0 kHz — 5.0 —
Equivalent Input Noise Current — in pA/√Hz
f = 10 Hz — 0.33 —
f = 1.0 kHz — 0.15 —

MC33076
Figure 1. Maximum Power Dissipation Figure 2. Distribution of Input

versus Temperature Offset Voltage
4000 25
PD , MAXIMUM POWER DISSIPATION (mW)
180 amplifiers tested
PERCENTAGE OF AMPLIFIERS (%)

See Application Section
3500 for Further Information from 3 wafer lots
20 VCC = ±15 V
3000 TA = 25°C
MC33076P2 (Plastic DIP package)
2500 15
2000
MC33076P1
1500 10
1000
5
500 MC33076D
0 0
–60 –30 0 30 60 90 120 150 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
TA, AMBIENT TEMPERATURE (°C) VIO, INPUT OFFSET VOLTAGE (mV)
Figure 3. Input Bias Current versus Figure 4. Input Bias Current

Common Mode Voltage versus Temperature
250 150
VCC = +15 V
225 VEE = –15 V 137

TA = 25°C
200 125
175 112
150 100
VCC = +15 V
125 88 VEE = –15 V
VCM = 0 V
100 75
–15 –10 –5.0 0 5.0 10 15 –55 –25 5.0 35 65 95 125
VCM, COMMON MODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 5. Input Common Mode Voltage Figure 6. Open Loop Voltage Gain
Range versus Temperature versus Temperature
VCC 120
VCC–0.25 VCC = + 5.0 V to +18 V

VEE = – 5.0 V to –18 V 115
VCC–0.50 ∆VIO = 5.0 mV RL = 2.0 kΩ
110
VCC–0.75
VCC–1.0 105
100
VEE+0.25 VCC = +15 V RL = 100 Ω
VEE = –15 V
95
VEE+0.125 f = 10 Hz
∆VO = –10 to +10 V
VEE 90
–55 –25 5.0 35 65 95 125 –55 –25 5.0 35 65 95 125
TA, TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

MC33076
Figure 7. Output Voltage Swing Figure 8. Maximum Peak–to–Peak Output

versus Supply Voltage Voltage Swing versus Load Resistance
40 30
VO , OUTPUT VOLTAGE SWING (Vpp)

TA = 25°C
35 VS = ±15 V
25 f = 1.0 kHz
30 RL = 10 kΩ
TA = 25°C 20
25
20 RL = 100 Ω 15
15
10
10
5.0 VS = ± 5.0 V
5.0
0 0
0 5.0 10 15 20 25 10 100 1.0 k 10 k
VCC, |VEE|, SUPPLY VOLTAGE (V) RL, LOAD RESISTANCE TO GROUND (Ω)
Figure 9. Output Voltage Figure 10. Common Mode Rejection

versus Frequency versus Frequency Over Temperature
25 100

20 80
15 60
VCC = +15 V
10 VEE = –15 V 40 VCC = +15 V
RL = 100 Ω VEE = –15 V
AV = +1.0 VCM = 0 V
5.0 THD = ≤ 1.0% 20 ∆VCM = ±1.5 V
TA = 25°C TA = – 55° to +125°C
0 0
100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k 1.0 M
Figure 11. Power Supply Rejection Figure 12. Output Short Circuit Current
versus Frequency Over Temperature versus Output Voltage
|I SC |, OUTPUT SHORT CIRCUIT CURRENT (mA)
100 300
80 250
+PSR 200 Sink

60
Source
150
40 –PSR
VCC = +15 V 100
VEE = –15 V
20 ∆VCC = ±1.5 V VCC = +15 V
50 VEE = –15 V
TA = – 55° to +125°C
VID = ±1.0 V
0 0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 3.0 6.0 9.0 12 15
f, FREQUENCY (Hz) |VO|, OUTPUT VOLTAGE (V)

MC33076
Figure 13. Output Short Circuit Current Figure 14. Supply Current versus
versus Temperature Supply Voltage with No Load
320 5.0
I D, SUPPLY CURRENT/AMPLIFIER (mA)

300 TA = +125°C
4.0
Sink
280
3.0 TA = + 25°C
260
240 Source 2.0

VCC = +15 V TA = – 55°C
220
VEE = –15 V
200 VID = ±1.0 V 1.0
RL < 10 Ω
180 0
–55 –25 5.0 35 65 95 125 0 3.0 6.0 9.0 12 15 18
TA, AMBIENT TEMPERATURE (°C) VCC |VEE|, SUPPLY VOLTAGE (V)


3.0 8.5
2.5 8.0
SR, SLEW RATE (V/µS)
2.0 7.5
1.5 7.0
1.0
∆Vin +– 6.5 VCC = +15 V
100Ω 100pF VEE = –15 V
VCC = +15 V f = 100 Hz
0.5 VEE = –15 V 6.0 RL = 100 Ω
∆Vin = 20 Vpp CL = 0 pF
0 5.5
–55 –25 5.0 35 65 95 125 –55 –25 5.0 35 65 95 125
Figure 17. Voltage Gain and Phase Figure 18. Voltage Gain and Phase
50 80 50 80
∅ , EXCESS PHASE (DEGREES)

∅, EXCESS PHASE (DEGREES)
1
30 A 120 30 120
2
A
10 160 10 160
2 1
B B
–10 200 –10 1B 1 200
1A) Phase, (R = 100 Ω) A
1A) Phase, VS = ±18 V
2A) Phase, VS = ±1.5 V 2A) Phase, (R = 100 Ω, C = 300 pF) 2B
–30 –30 240
1B) Gain, VS = ±18 V
240 1B) Gain, (R = 100 Ω)
2B) Gain, VS = ±1.5 V 2B) Gain, (R = 100 Ω, C = 300 pF) 2
–50 280 –50 A 280
100 k 1.0 M 10 M 30 M 100 k 1.0 M 10 M 30 M
f, FREQUENCY (Hz) f, FREQEUNCY (Hz)

MC33076
Figure 19. Phase Margin and Gain Margin Figure 20. Open Loop Gain Margin and Phase
versus Differential Source Resistance Margin versus Output Load Capacitance
20 50 60 16
VCC = +15 V
A m , OPEN LOOP GAIN MARGIN (dB)

VCC = +15 V 14
VEE = –15 V
∅ m, PHASE MARGIN (DEGREES)

50 VEE = –15 V
16 RT = R1 + R2 40 VO = 0 V
A m , GAIN MARGIN (dB)
VO = 0 V 12
TA = 25°C 40
12 Gain Margin 30 10
30 8.0
8.0 20 Phase Margin
6.0
20
Phase Margin 4.0
4.0 10 Gain Margin
10
2.0
0 0 0 0
0 2.0 k 4.0 k 6.0 k 8.0 k 10 k 12 k 0 400 800 1200 1600 2000
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω) CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 21. Channel Separation Figure 22. Total Harmonic Distortion

140 3.0

VCC = +15 V
CS, CHANNEL SEPARATION (dB)
130 2.5 VEE = –15 V

RL = 100 Ω
120 VO = 2.0 Vpp
2.0 TA = 25°C
110
1.5
100
Drive Channel 1.0 AV = +10
90 VCC = +15 V AV = +1000
VEE = –15 V 0.5
80 RL = 100 Ω AV = +100
TA = 25°C AV = +1
70 0
100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k
Figure 23. Output Impedance Figure 24. Input Referred Noise Voltage
e n , INPUT REFERRED NOISE VOLTAGE (NV/ √Hz)
100 20
VCC = +15 V VCC = +15 V
VEE = –15 V VEE = –15 V +
80 VCM = 0 V 16 – VO
TA = 25°C
VO = 0 V
TA = 25°C
60 12 Input Noise Voltage
Test Circuit
40 8.0
AV = 1000
20 4.0
AV = 100
AV = 10
AV = 1.0
0 0
10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k

MC33076
Figure 25. Percent Overshoot Figure 26. PC Board Heatsink Example

versus Load Capacitance
100
VCC = +15 V
VEE = –15 V
os, PERCENT OVERSHOOT (%)
80 TA = 25°C
Copper Copper
Pad Pad
60
RL = 2.0 kΩ
40
RL = 100 Ω
20
0
10 100 1000 10 k
CL, LOAD CAPACITANCE (pF)
The MC33076 dual operational amplifier is available in the typically, in still air. The junction–to–ambient thermal
standard 8–pin plastic dual–in–line (DIP) and surface mount resistance (RθJA) can be decreased further by using a copper
packages, and also in a 16–pin batwing power package. To padb on the printed circuit board (as shown in Figure 26) to
enhance the power dissipation capability of the power draw the heat away from the package. Care must be taken
package, Pins 4, 5, 12, and 13 are tied together on the not to exceed the maximum junction temperature or damage
leadframe, giving it an ambient thermal resistance of 52°C/W to the device may occur.

MC33077
Dual, Low Noise
The MC33077 is a precision high quality, high frequency, low noise
monolithic dual operational amplifier employing innovative bipolar design
techniques. Precision matching coupled with a unique analog resistor trim DUAL, LOW NOISE
technique is used to obtain low input offset voltages. Dual–doublet frequency OPERATIONAL AMPLIFIER
compensation techniques are used to enhance the gain bandwidth product
of the amplifier. In addition, the MC33077 offers low input noise voltage, low
temperature coefficient of input offset voltage, high slew rate, high AC and SEMICONDUCTOR
DC open loop voltage gain and low supply current drain. The all NPN TECHNICAL DATA
transistor output stage exhibits no deadband cross–over distortion, large
output voltage swing, excellent phase and gain margins, low open loop
output impedance and symmetrical source and sink AC frequency
performance.
The MC33077 is tested over the automotive temperature range and is
available in plastic DIP and SO–8 packages (P and D suffixes).
• Low Voltage Noise: 4.4 nV/ ǸHz @ 1.0 kHz 8
1
• Low Input Offset Voltage: 0.2 mV
P SUFFIX
• Low TC of Input Offset Voltage: 2.0 µV/°C PLASTIC PACKAGE
• High Gain Bandwidth Product: 37 MHz @ 100 kHz CASE 626
• High AC Voltage Gain: 370 @ 100 kHz

High AC Voltage Gain: 1850 @ 20 kHz
• Unity Gain Stable: with Capacitance Loads to 500 pF
• High Slew Rate: 11 V/µs 8
•
1
Low Total Harmonic Distortion: 0.007%
• Large Output Voltage Swing: +14 V to –14.7 V D SUFFIX
PLASTIC PACKAGE
• High DC Open Loop Voltage Gain: 400 k (112 dB) CASE 751
• High Common Mode Rejection: 107 dB (SO–8)
• Low Power Supply Drain Current: 3.5 mA

• Dual Supply Operation: ±2.5 V to ±18 V
PIN CONNECTIONS
Representative Schematic Diagram (Each Amplifier)
VCC Output 1 1 8 VCC

R1 R6 R8 R11 R16
Q1 Q17 –
Q8
Q13 2 1 7 Output 2
D3 Q19 +
Bias Network
C3 Q11 Inputs 1
C1
R3 R9 Q14 3 6
Z1 Q21 –
D4 D6
J1 Q6 2 Inputs 2
VEE 4 + 5
R13
Neg Q7 Q9 Pos Q16 R17 R18 Vout
C6 (Dual, Top View)
Q2 R14
Q12 D7 R19
Q4 Q10
R5 C2
C7
D1 Q22 ORDERING INFORMATION
C8
Operating
Q1 Q5 R4 R7 R10 R12 Q20 R20 Device Temperature Range Package
D5
R2 R15 MC33077D SO–8
D2 TA = – 40° to +85°C
MC33077P Plastic DIP
VEE

MC33077
MAXIMUM RATINGS
NOTES: 1. Either or both input voltages should not exceed VCC or VEE (See Applications Information).
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not
exceeded (See power dissipation performance characteristic, Figure 1).
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (RS = 10 Ω, VCM = 0 V, VO = 0 V) |VIO| mV
TA = +25°C — 0.13 1.0
TA = –40° to +85°C — — 1.5
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T — 2.0 — µV/°C
RS = 10 Ω, VCM = 0 V, VO = 0 V, TA = –40° to +85°C
Input Bias Current (VCM = 0 V, VO = 0 V) IIB nA

TA = +25°C — 280 1000
TA = –40° to +85°C — — 1200
Input Offset Current (VCM = 0 V, VO = 0 V) IIO nA
TA = +25°C — 15 180
TA = –40° to +85°C — — 240
Common Mode Input Voltage Range (∆VIO ,= 5.0 mV, VO = 0 V) VICR ±13.5 ±14 — V
Large Signal Voltage Gain (VO = ±1.0 V, RL = 2.0 kΩ) AVOL V/V
TA = +25°C 150 k 400 k —
TA = –40° to +85°C 125 k — —
Output Voltage Swing (VID = ±1.0 V) V
RL = 2.0 kΩ VO+ +13.0 +13.6 —
RL = 2.0 kΩ VO – — –14.1 –13.5
RL = 10 kΩ VO+ +13.4 +14.0 —
RL = 10 kΩ VO – — –14.7 –14.3
Common Mode Rejection (Vin = ±13 V) CMR 85 107 — dB
Power Supply Rejection (Note 3) PSR 80 90 — dB
VCC/VEE = +15 V/ –15 V to +5.0 V/ –5.0 V
Output Short Circuit Current (VID = ±1.0 V, Output to Ground) ISC mA

Source +10 +26 +60
Sink –20 –33 +60
Power Supply Current (VO = 0 V, All Amplifiers) ID mA
TA = +25°C — 3.5 4.5
TA = –40° to +85°C — — 4.8
NOTE: 3. Measured with VCC and VEE simultaneously varied.

MC33077
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 100 pF, AV = +1.0) SR 8.0 11 — V/µs
Gain Bandwidth Product (f = 100 kHz) GBW 25 37 — MHz
AC Voltage Gain (RL = 2.0 kΩ, VO = 0 V) AVO V/V
f = 100 kHz — 370 —
f = 20 kHz — 1850 —
Unity Gain Frequency (Open Loop) fU — 7.5 — MHz
Gain Margin (RL = 2.0 kΩ, CL = 10 pF) Am — 10 — dB
Phase Margin (RL = 2.0 kΩ, CL = 10 pF) ∅m — 55 — Degrees
Channel Separation (f = 20 Hz to 20 kHz, RL = 2.0 kΩ, VO = 10 Vpp) CS — –120 — dB

Power Bandwidth (VO = 27p–p, RL = 2.0 kΩ, THD ≤ 1%) BWp — 200 — kHz
Distortion (RL = 2.0 kΩ) THD %
AV = +1.0, f = 20 Hz to 20 kHz
VO = 3.0 Vrms — 0.007 —
AV = 2000, f = 20 kHz
VO = 2.0 Vpp — 0.215 —
VO = 10 Vpp — 0.242 —
AV = 4000, f = 100 kHz
VO = 2.0 Vpp — 0.3.19 —
VO = 10 Vpp — 0.316 —
Open Loop Output Impedance (VO = 0 V, f = fU) |ZO| — 36 — Ω
Differential Input Resistance (VCM = 0 V) Rin — 270 — kΩ
Differential Input Capacitance (VCM = 0 V) Cin — 15 — pF
Equivalent Input Noise Voltage (RS = 100 Ω) en nV/ √ Hz
f = 10 Hz — 6.7 —
f = 1.0 kHz — 4.4 —
Equivalent Input Noise Current (f = 1.0 kHz) in pA/ √ Hz
f = 10 Hz — 1.3 —
f = 1.0 kHz — 0.6 —
Figure 1. Maximum Power Dissipation Figure 2. Input Bias Current

PD(MAX) , MAXIMUM POWER DISSIPATION (mW)
2400 800
VCM = 0 V
2000 TA = 25°C
600
1600
MC33077P
1200 400
800
MC33077D 200
400
0 0
–60 –40 –20 0 20 40 60 80 100 120 140 160 180 0 2.5 5.0 7.5 10 12.5 15 17.5 20

MC33077
Figure 3. Input Bias Current Figure 4. Input Offset Voltage

1000 1.0
V IO , INPUT OFFSET VOLTAGE (mV)

VCC = +15 V
VEE = –15 V
800 VCM = 0 V
0.5
600
0
400 VCC = +15 V
VEE = –15 V
–0.5 RS = 10 Ω
200 VCM = 0 V
AV = +1.0
0 –1.0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
Figure 5. Input Bias Current versus Figure 6. Input Common Mode Voltage Range
V ICR , INPUT COMMON MODE VOTAGE RANGE (V)
600 VCC 0.0
VCC –0.5 +VCM
500 VCC = +15 V

VEE = –15 V VCC –1.0
400 TA = 25°C
VCC –1.5 VCC = +3.0 V to +15 V
Input VEE = –3.0 V to –15 V
300 Voltage ∆ VIO = 5.0 mV
Range VO = 0 V
VEE +1.5
200
VEE +1.0
100 VEE +0.5 –VCM
0 VEE +0.0
–15 –10 –5.0 0 5.0 10 15 –55 –25 0 25 50 75 100 125
Figure 7. Output Saturation Voltage versus Figure 8. Output Short Circuit Current
Load Resistance to Ground versus Temperature
VCC 0 50
V sat , OUTPUT SATURATION VOLTAGE (V)
VCC = +15 V
VCC –2 VEE = –15 V
–55°C VID = ±1.0 V
40 RL < 100 Ω
VCC –4 25°C Sink
125°C VCC = +15 V
VEE = –15 V 30
Source
125°C
VEE +4
25°C
20
VEE +2 –55°C
VEE 0 10
0 0.5 1.0 1.5 2.0 2.5 3.0 –55 –25 0 25 50 75 100 125
RL, LOAD RESISTANCE TO GROUND (kΩ) TA, AMBIENT TEMPERATURE (°C)

MC33077
Figure 9. Supply Current Figure 10. Common Mode Rejection

versus Temperature versus Frequency
5.0 120

–
100 ∆ VCM ADM ∆ VO
I CC , SUPPLY CURRENT (mA)
4.0 +
±15 V
80 ∆ VCM
±5.0 V CMR = 20Log × ADM
3.0 ∆ VO
60
2.0 VCC = +15 V
VCM = 0 V 40 VEE = –15 V
RL = ∞ VCM = 0 V
1.0 VO = 0 V 20 ∆ VCM = ±1.5 V
TA = 25°C
0 0
–55 –25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M 10 M
Figure 11. Power Supply Rejection Figure 12. Gain Bandwidth Product
120 48
∆VO/ADM ∆VO/ADM RL = 10 kΩ
+PSR = 20Log –PSR = 20Log

∆ VCC ∆ VEE CL = 0 pF
100 44 f = 100 kHz
TA = 25°C
+PSR
80 40
–PSR
60 36
40 VCC 32
–
VCC = +15 V ADM ∆ VO
20 VEE = –15 V + 28
TA = 25°C VEE
0 24
100 1.0 k 10 k 100 k 1.0 M 0 5 10 15 20
f, FREQUENCY (Hz) VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 13. Gain Bandwidth Product Figure 14. Maximum Output Voltage
50 20
TA = 25°C RL = 10 kΩ
VCC = +15 V
15
46 VEE = –15 V
Vp + RL = 2.0 kΩ
VO,OUTPUT VOLTAGE (Vp )
f = 100 kHz 10
RL = 10 kΩ
42 CL = 0 pF 5.0
38 0
–5.0
34 Vp –
–10
30 RL = 2.0 kΩ
–15
RL = 10 kΩ
26 –20
–55 –25 0 25 50 75 100 125 0 5.0 10 15 20

MC33077
Figure 15. Output Voltage Figure 16. Open Loop Voltage Gain
AVOL , OPEN LOOP VOLTAGE GAIN (X1000 V/V)

30 1200
RL = 2.0 kΩ
25 1000 f = 10 Hz
∆ VO = 2/3 (VCC –VEE)

TA = 25°C
20 800
15 600
VCC = +15 V
10 VEE = –15 V 400
RL = 2.0 kΩ
AV =+1.0
5.0 THD ≤ 1.0% 200
TA = 25°C
0 0
100 1.0 k 10 k 100 k 1.0 M 0 5.0 10 15 20
Figure 17. Open Loop Voltage Gain Figure 18. Output Impedance
A VOL , OPEN LOOP VOLTAGE GAIN (X1000 V/V)
600 80
VCC = +15 V VCC = +15 V
70
| Z O |, OUTPUT IMPEDANCE ( Ω )
550 VEE = –15 V VEE = –15 V
RL = 2.0 kΩ 60 VO = 0 V
f = 10 Hz TA = 25°C
500 ∆ VO = –10 V to +10 V 50
450 40
30
400 AV = 10
20 AV = 1000
350 AV = 100
10
AV = 1.0
300 0
–55 –25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M 10 M

160 1.0
Drive Channel VCC = +15 V VO = 2.0 Vpp

–
150 VCC = +15 V VEE = –15 V TA = 25°C

∆Vin ∆VO
+ VEE = –15 V AV = +1000
RL = 2.0 kΩ AV = +100
140 Measurement Channel ∆VOD = 20 Vpp 0.1
TA = 25°C AV = +10
130
100 kΩ 2.0 kΩ
120 0.01 RA –
+ VO AV = +1.0
Vin
110 ∆VOD
CS = 20 Log
∆Vin
100 0.001
10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k

MC33077
Figure 21. Total Harmonic Distortion Figure 22. Total Harmonic Distortion
versus Frequency versus Output Voltage
1.0 1.0

VCC = +15 V 100 kΩ 2.0 kΩ VCC = +15 V 100 kΩ 2.0 kΩ
VEE = –15 V VEE = –15 V
RA – 0.5 RA –
V0 = –10 Vpp VO f = 20 kHz VO
TA = 25°C Vin + TA = 25°C Vin +
0.1 0.1
AV = +1000
AV = +1000
AV = +100 0.05
AV = +100
0.01 AV = +10 0.01 AV = +10
AV = +1.0
0.005
AV = +1.0
0.001 0.001
10 100 1.0 k 10 k 100 k 0 2.0 4.0 6.0 8.0 10 12
f, FREQUENCY (Hz) VO, OUTPUT VOLTAGE (Vpp)
Figure 23. Slew Rate versus Supply Voltage Figure 24. Slew Rate versus Temperature
16 40
Vin = 2/3 (VCC –VEE) VCC = +15 V –
TA = 25°C VEE = –15 V VO
∆Vin +
12 30 ∆Vin = 20 V
2.0 kΩ 100 pF
8.0 20
–
VO
∆Vin +
4.0 10
2.0 kΩ 100 pF
0 0
0 2.5 5.0 7.5 10 12.5 15 17.5 20 –55 –25 0 25 50 75 100 125
Figure 25. Voltage Gain and Phase Figure 26. Open Loop Gain Margin and Phase
versus Frequency Margin versus Output Load Capacitance
180 0 14 0
A VOL , OPEN–LOOP VOLTAGE GAIN (dB)
VCC = +15 V 125°C –

φm , PHASE MARGIN (DEGREES)
VEE = –15 V 12 VO 10
φ , EXCESS PHASE (DEGREES)
140 40 Vin +
Phase RL = 2.0 kΩ 2.0 kΩ
25°C CL
TA = 25°C 10 20
100 80
Gain
8.0 30
60 120 –55°C Phase
6.0 40
20 160 Gain
4.0 125°C 50
–20 200 2.0 VCC = +15 V

60
–55°C 25°C VEE = –15 V
VO = 0 V 70
–60 240 0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M 1.0 10 100 1000
f, FREQUENCY (Hz) CL, OUTPUT LOAD CAPACITANCE (pF)

MC33077
Figure 27. Phase Margin versus Figure 28. Overshoot versus

Output Voltage Output Load Capacitance
70 100
VCC = +15 V
φ m , PHASE MARGIN (DEGREES)
60 – VEE = –15 V
CL = 0 pF VO
80 ∆Vin + ∆Vin = 100 mV
CL = 100 pF
os, OVERSHOOT (%)

50 2.0 kΩ 100 pF
40 60
VCC = +15 V CL = 300 pF
30 VEE = –15 V
TA = 25°C 40
CL = 500 pF
20
–
Vin + VO 20
10 CL
2.0kΩ 125°C and 25°C
–55°C
0 0
–10 –5.0 0 5.0 10 1 10 100 1000
VO, OUTPUT VOLTAGE (V) CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 29. Input Referred Noise Voltage Figure 30. Total Input Referred Noise Voltage
e n , INPUT REFERRED NOISE VOLTAGE ( nV/ √ Hz )
VV n , TOTAL REFERRED NOISE VOLTAGE (nV/ √ Hz )

and Current versus Frequency versus Source Resistant
i n ,INPUT REFERRED NOISE CURRENT (pA)
100 10 1000
VCC = +15 V VCC = +15 V f = 1.0 kHz
Ǹ
50 VEE = –15 V 5.0 VEE = –15 V TA = 25°C
30
TA = 25°C
3.0
Vn (total) =
(inRs)2 ) en2 ) 4KTRS
20 2.0 100
10 1.0
Current
5.0 0.5 10
3.0 Voltage 0.3
2.0 0.2
1.0 0.1 1.0

1.0 10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k 1.0 M
Figure 31. Phase Margin and Gain Margin

versus Differential Source Resistance Figure 32. Inverting Amplifer Slew Rate
14 0
VCC = +15 V
Gain
12 10 VEE = –15 V
φ m ,PHASE MARGIN (DEGREES)
AV = –1.0
Am , GAIN MARGIN (dB)
R
10 1 – 20 RL = 2.0 kΩ
Vin VO
+ CL = 100 pF
8.0 R2 30 TA = 25°C
Phase
6.0 40
VCC = +15 V
4.0 VEE = –15 V 50
RT = R1 + R2
2.0 VO = 0 V 60
TA = 25°C
0 70
1.0 10 100 1.0 k 10 k t, TIME (2.0 µs/DIV)
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)

MC33077
Figure 33. Noninverting Amplifier Slew Rate Figure 34. Noninverting Amplifier Overshoot

VCC = +15 V
VEE = –15 V
AV = +1.0 CL = 100 pF
RL = 2.0 kΩ
CL = 100 pF
TA = 25°C
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 kΩ
TA = 25°C
CL = 0 pF
t, TIME (2.0 µs/DIV) t, TIME (200 ns/DIV)
Figure 35. Low Frequency Noise Voltage

versus Time
e n , INPUT NOISE VOLTAGE (100nV/DIV)
VCC = +15 V
VEE = –15 V
BW = 0.1 Hz to 10 Hz
TA = 25°C
See Noise Circuit
(Figure 36)
t, TIME (1.0 sec/DIV)

MC33077
The MC33077 is designed primarily for its low noise, low With the all NPN output stage, there is minimal swing loss
offset voltage, high gain bandwidth product and large output to the supply rails, producing superior output swing, no
swing characteristics. Its outstanding high frequency crossover distortion and improved output phase symmetry
gain/phase performance make it a very attractive amplifier for with output voltage excursions (output phase symmetry
high quality preamps, instrumentation amps, active filters being the amplifiers ability to maintain a constant phase
and other applications requiring precision quality relation independent of its output voltage swing). Output
characteristics. phase symmetry degradation in the more conventional PNP
The MC33077 utilizes high frequency lateral PNP input and NPN transistor output stage was primarily due to the
transistors in a low noise bipolar differential stage driving a inherent cut–off frequency mismatch of the PNP and NPN
compensated Miller integration amplifier. Dual–doublet transistors used (typically 10 MHz and 300 MHz,
frequency compensation techniques are used to enhance the respectively), causing considerable phase change to occur
gain bandwidth product. The output stage uses an all NPN as the output voltage changes. By eliminating the PNP in the
transistor design which provides greater output voltage swing output, such phase change has been avoided and a very
and improved frequency performance over more significant improvement in output phase symmetry as well as
conventional stages by using both PNP and NPN transistors output swing has been accomplished.
(Class AB). This combination produces an amplifier with The output swing improvement is most noticeable when
superior characteristics. operation is with lower supply voltages (typically 30% with
Through precision component matching and innovative ± 5.0 V supplies). With a 10 k load, the output of the amplifier
current mirror design, a lower than normal temperature can typically swing to within 1.0 V of the positive rail (VCC),
coefficient of input offset voltage (2.0 µV/°C as opposed to 10 and to within 0.3 V of the negative rail (VEE), producing a 28.7
µV/°C), as well as low input offset voltage, is accomplished. Vpp signal from ±15 V supplies. Output voltage swing can be
The minimum common mode input range is from 1.5 V further improved by using an output pull–up resistor
below the positive rail (VCC) to 1.5 V above the negative rail referenced to the VCC. Where output signals are referenced
(VEE). The inputs will typically common mode to within 1.0 V to the positive supply rail, the pull–up resistor will pull the
of both negative and positive rails though degradation in output to VCC during the positive swing, and during the
offset voltage and gain will be experienced as the common negative swing, the NPN output transistor collector will pull
mode voltage nears either supply rail. In practice, though not the output very near VEE. This configuration will produce the
recommended, the input voltage may exceed VCC by maximum attainable output signal from given supply
approximately 30 V and decrease below the VEE by voltages. The value of load resistance used should be much
approximately 0.6 V without causing permanent damage to less than any feedback resistance to avoid excess loading
the device. If the input voltage on either or both inputs is less and allow easy pull–up of the output.
than approximately 0.6 V, excessive current may flow, if not Output impedance of the amplifier is typically less than
limited, causing permanent damage to the device. 50 Ω at frequencies less than the unity gain crossover
The amplifier will not latch with input source currents up to frequency (see Figure 18). The amplifier is unity gain stable
20 mA, though in practice, source currents should be limited with output capacitance loads up to 500 pF at full output
to 5.0 mA to avoid any parametric damage to the device. If swing over the –55° to +125°C temperature range. Output
both inputs exceed VCC, the output will be in the high state phase symmetry is excellent with typically 4°C total phase
and phase reversal may occur. No phase reversal will occur change over a 20 V output excursion at 25°C with a 2.0 kΩ
if the voltage on one input is within the common mode range and 100 pF load. With a 2.0 kΩ resistive load and no
and the voltage on the other input exceeds VCC. Phase capacitance loading, the total phase change is approximately
reversal may occur if the input voltage on either or both inputs one degree for the same 20 V output excursion. With a
is less than 1.0 V above the negative rail. Phase reversal will 2.0 kΩ and 500 pF load at 125°C, the total phase change is
be experienced if the voltage on either or both inputs is less typically only 10°C for a 20 V output excursion (see Figure
than VEE. 27).
Through the use of dual–doublet frequency compensation As with all amplifiers, care should be exercised to insure
techniques, the gain bandwidth product has been greatly that one does not create a pole at the input of the amplifier
enhanced over other amplifiers using the conventional single which is near the closed loop corner frequency. This
pole compensation. The phase and gain error of the amplifier becomes a greater concern when using high frequency
remains low to higher frequencies for fixed amplifier gain amplifiers since it is very easy to create such a pole with
configurations. relatively small values of resistance on the inputs. If this does

MC33077
occur, the amplifier’s phase will degrade severely causing the decoupled with adequate capacitance as close as possible to
amplifier to become unstable. Effective source resistances, the device supply pin.
acting in conjunction with the input capacitance of the In addition to amplifier stability considerations, input
amplifier, should be kept to a minimum to avoid creating such source resistance values should be low to take full advantage
a pole at the input (see Figure 31). There is minimal effect on of the low noise characteristics of the amplifier. Thermal
stability where the created input pole is much greater than the noise (Johnson Noise) of a resistor is generated by
closed loop corner frequency. Where amplifier stability is thermally–charged carriers randomly moving within the
affected as a result of a negative feedback resistor in resistor creating a voltage. The rms thermal noise voltage in
conjunction with the amplifier’s input capacitance, creating a a resistor can be calculated from:
pole near the closed loop corner frequency, lead capacitor
Enr = / 4k TR × BW
compensation techniques (lead capacitor in parallel with the
feedback resistor) can be employed to improve stability. The where:
feedback resistor and lead capacitor RC time constant k = Boltzmann’s Constant (1.38 × 10–23 joules/k)
should be larger than that of the uncompensated input pole T = Kelvin temperature
frequency. Having a high resistance connected to the R = Resistance in ohms
noninverting input of the amplifier can create a like instability BW = Upper and lower frequency limit in Hertz.
problem. Compensation for this condition can be
By way of reference, a 1.0 kΩ resistor at 25°C will produce
accomplished by adding a lead capacitor in parallel with the
a 4.0 nV/ √ Hz of rms noise voltage. If this resistor is
noninverting input resistor of such a value as to make the RC
connected to the input of the amplifier, the noise voltage will
time constant larger than the RC time constant of the
be gained–up in accordance to the amplifier’s gain
uncompensated input resistor acting in conjunction with the
configuration. For this reason, the selection of input source
amplifiers input capacitance.
resistance for low noise circuit applications warrants serious
For optimum frequency performance and stability, careful
consideration. The total noise of the amplifier, as referred to
component placement and printed circuit board layout should
be exercised. For example, long unshielded input or output its inputs, is typically only 4.4 nV/ √ Hz at 1.0 kHz.
leads may result in unwanted input output coupling. In order The output of any one amplifier is current limited and thus
to reduce the input capacitance, the body of resistors protected from a direct short to ground, However, under such
connected to the input pins should be physically close to the conditions, it is important not to allow the amplifier to exceed
input pins. This not only minimizes the input pole creation for the maximum junction temperature rating. Typically for ±15 V
optimum frequency response, but also minimizes extraneous supplies, any one output can be shorted continuously to
signal “pickup” at this node. Power supplies should be ground without exceeding the temperature rating.
Figure 36. Voltage Noise Test Circuit

(0.1 Hz to 10 Hzp–p)
0.1 µF
100 kΩ
10 Ω
–
2.0 kΩ
D.U.T. + 22 µF
1/2 4.3 kΩ
+ 4.7 µF MC33077 Scope
– ×1
Rin = 1.0 MΩ
100 kΩ
Voltage Gain = 50,000 2.2 µF
24.3 kΩ 110 kΩ
0.1 µF
Note: All capacitors are non–polarized.

MC33078
MC33079
Dual/Quad Low Noise

DUAL/QUAD
The MC33078/9 series is a family of high quality monolithic amplifiers
employing Bipolar technology with innovative high performance concepts for
LOW NOISE
quality audio and data signal processing applications. This family OPERATIONAL AMPLIFIERS
incorporates the use of high frequency PNP input transistors to produce
amplifiers exhibiting low input voltage noise with high gain bandwidth
product and slew rate. The all NPN output stage exhibits no deadband
DUAL
crossover distortion, large output voltage swing, excellent phase and gain
margins, low open loop high frequency output impedance and symmetrical
source and sink AC frequency performance. 8
8
1
The MC33078/9 family offers both dual and quad amplifier versions, 1
tested over the automotive temperature range and available in the plastic P SUFFIX D SUFFIX
DIP and SOIC packages (P and D suffixes). PLASTIC PACKAGE PLASTIC PACKAGE
CASE 626 CASE 751
• Dual Supply Operation: ± 5.0 V to ± 18 V
Ǹ
(SO–8)
• Low Voltage Noise: 4.5 nV/ Hz PIN CONNECTIONS
• Low Input Offset Voltage: 0.15 mV
• Low T.C. of Input Offset Voltage: 2.0 µV/°C Output 1 1 8 VCC
• Low Total Harmonic Distortion: 0.002% 2

–
1 7 Output 2
• High Gain Bandwidth Product: 16 MHz Inputs 1
+

3
–
6
Inputs 2
• High Open Loop AC Gain: 800 @ 20 kHz VEE 4
2
+ 5
• Excellent Frequency Stability
(Dual, Top View)
• Large Output Voltage Swing: +14.1 V/ –14.6 V
• ESD Diodes Provided on the Inputs QUAD
14
14
1
1
D SUFFIX
P SUFFIX
Representative Schematic Diagram PLASTIC PACKAGE
PLASTIC PACKAGE
CASE 751A
(Each Amplifier) CASE 646
(SO–14)
PIN CONNECTIONS
VCC
R2 Output 1 1 14 Output 4
D1
Q4 2
*1 * 13
Q9 Inputs 1
3 ) 4
) 12 Inputs 4
Q3 Q5 D3 Q11 4 11
VCC VEE
R7
) 10
Neg Pos C2 5
)2 *9
J1 Amplifier
Q3 Inputs 2 6 * 3 Inputs 3
Biasing Q8 D4 C3 R9 7 8
Output 2 Output 3
Q6 Vout
Q12 (Quad, Top View)
Q2 D2 Q10
R6 ORDERING INFORMATION
R4
Z1 Q1 Q7 Operating
R1 C1 R3 Q5 Device Temperature Range Package
VEE MC33078D SO–8
TA = – 40° to +85°C
MC33079D SO–14

MC33078 MC33079
MAXIMUM RATINGS
Storage Temperature Tstg – 60 to +150 °C
NOTES: 1. Either or both input voltages must not exceed the magnitude of VCC or VEE.
(TJ) is not exceeded (see Figure 1).
Input Offset Voltage (RS = 10 Ω, VCM = 0 V, VO = 0 V) |VIO| mV
(MC33078) TA = +25°C — 0.15 2.0
TA = –40° to +85°C — — 3.0
(MC33079) TA = +25°C — 0.15 2.5
TA = –40° to +85°C — — 3.5
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T — 2.0 — µV/°C
RS = 10 Ω, VCM = 0 V, VO = 0 V, TA = Tlow to Thigh

TA = +25°C — 300 750
TA = –40° to +85°C — — 800
Input Offset Current (VCM = 0 V, VO = 0 V) IIO nA
TA = +25°C — 25 150
TA = –40° to +85°C — — 175
Common Mode Input Voltage Range (∆VIO = 5.0 mV, VO = 0 V) VICR ±13 ±14 — V
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kΩ) AVOL dB
TA = +25°C 90 110 —
TA = –40° to +85°C 85 — —
Output Voltage Swing (VID = ±1.0V) V
RL = 600 Ω VO + — +10.7 —
RL = 600 Ω VO – — –11.9 —
RL = 2.0 kΩ VO + +13.2 +13.8 —
RL = 2.0 kΩ VO – — –13.7 –13.2
RL = 10 kΩ VO + +13.5 +14.1 —
RL = 10 kΩ VO – — –14.6 –14
Common Mode Rejection (Vin = ±13V) CMR 80 100 — dB
Power Supply Rejection (Note 3) PSR 80 105 — dB
VCC/VEE = +15 V/ –15 V to +5.0 V/ –5.0 V
Output Short Circuit Current (VID = 1.0 V, Output to Ground) ISC mA

Source +15 +29 —
Sink –20 –37 —
Power Supply Current (VO = 0 V, All Amplifiers) ID mA
(MC33078) TA = +25°C — 4.1 5.0
(MC33078) TA = –40° to +85°C — — 5.5
(MC33079) TA = +25°C — 8.4 10
(MC33079) TA = –40° to +85°C — — 11
NOTE: 3. Measured with VCC and VEE differentially varied simultaneously.

MC33078 MC33079
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 100 pF AV = +1.0) SR 5.0 7.0 — V/µs
Gain Bandwidth Product (f = 100 kHz) GBW 10 16 — MHz
Gain Margin (RL = 2.0 kΩ) CL = 0 pF Am — –11 — dB
CL = 100 pF — – 6.0
Phase Margin (RL = 2.0 kΩ) CL = 0 pF φm — 55 — Degree

CL = 100 pF — 40 s
Channel Separation (f = 20 Hz to 20 kHz) CS — –120 — dB

Power Bandwidth (VO = 27 Vpp, RL = 2.0 kΩ, THD ≤ 1.0%) BWp — 120 — kHz
Distortion (RL = 2.0 kΩ, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0) THD — 0.002 — %
Open Loop Output Impedance (VO = 0 V, f = 9.0 MHz) |ZO| — 37 — Ω
Differential Input Resistance (VCM = 0 V) RIN — 175 — kΩ
Differential Input Capacitance (VCM = 0 V) CIN — 12 — pF
Equivalent Input Noise Voltage (RS = 100 Ω, f = 1.0 kHz) en — 4.5 — nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz) in — 0.5 — pA/ √ Hz
Figure 1. Maximum Power Dissipation Figure 2. Input Bias Current versus

P D , MAXIMUM POWER DISSIPATION (mW)
2400 800
VCM = 0 V
2000
MC33078P & MC33079P TA = 25°C

600
1600
MC33079D
1200 400
800
200
400 MC33078D
0 0
–55 –40 –20 0 20 40 60 80 100 120 140 160 5.0 10 15 20
TA, AMBIENT TEMPERATURE (°C) VCC, | VEE |, SUPPLY VOLTAGE (V)
Figure 3. Input Bias Current versus Temperature Figure 4. Input Offset Voltage versus Temperature
1000 2.0
VCC = +15 V
VCC = +15 V VEE = –15 V
V IO, INPUT OFFSET VOLTAGE (mV)
VEE = –15 V RS = 10 Ω Unit 1

800
VCM = 0 V 1.0 VCM = 0 V
AV = +1
600
Unit 2
0
400
Unit 3
–1.0
200
0 –2.0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125

MC33078 MC33079
Figure 5. Input Bias Current versus Figure 6. Input Common Mode Voltage
Common Mode Voltage Range versus Temperature
V ICR , INPUT COMMON MODE VOLTAGE RANGE (V)

600 VCC –0
VCC = +15 V
VEE = –15 V VCC –0.5 +VCM
500 TA = 25°C VCC = +3.0 V to +15 V

VCC –1.0 VEE = –3.0 V to –15 V
400 ∆VIO = 5.0 mV
VCC –1.5
VO = 0 V
Voltage
300 Range
VEE +1.5
200
VEE +1.0
100 –VCM
VEE +0.5
0 VEE +0
–15 –10 – 5.0 0 5.0 10 15 – 55 – 25 0 25 50 75 100 125
Figure 7. Output Saturation Voltage versus Figure 8. Output Short Circuit Current
Load Resistance to Ground versus Temperature
| I SC |, OUTPUT SHORT CIRCUIT CURRENT (mA)

50
VCC –1.0 VCC = +15 V

–55°C Sink
VCC = +15 V VEE = –15 V
VCC –3.0 25°C VEE = –15 V 40 RL < 100 Ω
VID = 1.0 V
VCC –5.0 125°C Source
30
125°C
VEE +5.0 25°C
20
VEE +3.0
–55°C
VEE +1.0 10
0 1.0 2.0 3.0 4.0 – 55 – 25 0 25 50 75 100 125
RL, LOAD RESISTANCE TO GROUND (kΩ) TA, AMBIENT TEMPERATURE (°C)
Figure 10. Common Mode Rejection

Figure 9. Supply Current versus Temperature versus Frequency
10 160
VCM = 0 V –
±15 V ±10 V RL = ∞ 140 ∆ VCM ADM ∆ VO
8.0 VO = 0 V +
±5.0 V VCM
120
CMR = 20Log × ADM
6.0 VO
MC33079 100
±15 V ±10 V MC33078 VCC = +15 V

4.0 80
VEE = –15 V
±5.0 V VCM = 0 V
60
∆VCM = ±1.5 V
2.0 Supply Voltages TA = 25°C
40
0 20
– 55 – 25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M 10 M

MC33078 MC33079
Figure 11. Power Supply Rejection Figure 12. Gain Bandwidth Product
140 30
∆VO/ADM ∆VO/ADM
GWB, GAIN BANDWIDTH PRODUCT (MHz)

+PSR = 20Log –PSR = 20Log RL = 10 kΩ

120 ∆VCC ∆VCC
CL = 0 pF
+PSR ∆VCC f = 100 kHz
20
100 – TA = 25°C
ADM ∆VO
+
80
–PSR VEE
60 10
40
VCC = +15 V
20 VEE = –15 V
TA = 25°C
0 0
100 1.0 k 10 k 100 k 1.0 M 10 M 5.0 10 15 20
f, FREQUENCY (Hz) VCC |VEE| , SUPPLY VOLTAGE (V)
Figure 13. Gain Bandwidth Product Figure 14. Maximum Output Voltage
20 20
GWB, GAIN BANDWIDTH PRODUCT (MHz)
TA = 25°C VO +
15 RL = 10 kΩ
VO , OUTPUT VOLTAGE (Vp)
15 10 RL = 2.0 kΩ
5.0
10 0
VCC = +15 V –5.0
VEE = –15 V
5.0 f = 100 kHz –10 RL = 2.0 kΩ
RL = 10 kΩ
CL = 0 pF –15 RL = 10 kΩ
VO –
0 –20
–55 –25 0 25 50 75 100 125 5.0 10 15 20
TA, AMBIENT TEMPERATURE (°C) VCC |VEE| , SUPPLY VOLTAGE (V)

Figure 15. Output Voltage versus Frequency versus Supply Voltage
35 110
RL = 2.0 kΩ
30 f ≤ 10 Hz
∆VO = 2/3 (VCC –VEE)
25 TA = 25°C
100
20
15 VCC = +15 V
VCC = –15 V
RL = 2.0 kΩ 90
10 AV = +1.0
THD ≤ 1.0%
5.0 TA = 25°C
0 80
10 100 1.0 k 10 k 100 k 1.0 M 10 M 5.0 10 15 20
f, FREQUENCY (Hz) VCC |VEE| , SUPPLY VOLTAGE (V)

MC33078 MC33079
Figure 17. Open Loop Voltage Gain Figure 18. Output Impedance
110 50
VCC = +15 V VCC = +15 V
| Z O |, OUTPUT IMPEDANCE ( Ω )
VEE = –15 V VEE = –15 V
40
105 RL = 2.0 kΩ VO = 0 V
f ≤ 10 Hz TA = 25°C
∆VO = –10 V to +10 V
30
100
20
95
10 AV = 1000 AV = 100 AV = 10
AV = 1.0
90 0
–55 –25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M 10 M

160 1.0
Drive Channel THD, TOTAL HARMONIC DISTORTION (%) VCC = +15 V
MC33078 VCC = +15 V
150 VEE = –15 V –

VEE = –15 V VO = 1.0 Vrms VO
RL = 2.0 KΩ +
TA = 25°C
140 MC33079 ∆VOD = 20 Vpp 0.1
2.0 kΩ
TA = 25°C
130 100 Ω 10 kΩ
–
120 VOM 0.01
+
110 100 Ω
∆VOA
CS = 20 Log
Measurement Channel ∆VOM
100 0.001
10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k
Figure 21. Total Harmonic Distortion

versus Output Voltage Figure 22. Slew Rate versus Supply Voltage
1.0 10
VCC = +15 V Vin = 2/3 (VCC –VEE)

VEE = –15 V AV = 1000 TA = 25°C
0.5 f = 2.0 kHz
8.0
TA = 25°C Falling
AV = 100
0.1
RA 10 kΩ 6.0 Rising
–
0.05 VO
Vin +
2.0 kΩ
AV = 10 4.0
0.01 –
VO
∆Vin +
AV = 1.0 2.0 2.0 kΩ
0.005
0.001 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 5.0 10 15 20
VO, OUTPUT VOLTAGE (Vrms) VCC |VEE| , SUPPLY VOLTAGE (V)

MC33078 MC33079
Figure 24. Voltage Gain and Phase

Figure 23. Slew Rate versus Temperature versus Frequency
10 120 0
A VOL , OPEN LOOP VOLTAGE GAIN (dB)

VCC = +15 V VCC = +15 V
VEE = –15 V VEE = –15 V
∆Vin = 20 V 100

RL = 2.0 kΩ
8.0
TA = 25°C 45
Falling 80
Rising
6.0 60 Phase 90
Gain
–
VO 40
4.0 ∆Vin + 135
2.0 kΩ
20
2.0 0 180
–55 –25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
Figure 25. Open Loop Gain Margin and Figure 26. Overshoot versus Output
Phase Margin versus Load Capacitance Load Capacitance
14 0 100
– 125°C
VO –
φ m, PHASE MARGIN (DEGREES)
12 Vin + 10 VO
2.0 kΩ CL Phase 80 ∆Vin + 25°C
25°C CL
os, OVERSHOOT (%)
10 20 – 55°C
–55°C
60
8.0 30
125°C
6.0 125°C 40 40
VCC = +15 V
4.0 50 VEE = –15 V
VCC = +15 V 20 ∆Vin = 100 mV
2.0 VEE = –15 V 25°C –55°C 60
VO = 0 V Gain
0 70 0
1 10 100 1000 10 100 1.0 k 10 k
CL, OUTPUT LOAD CAPACITANCE (pF) CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 27. Input Referred Noise Voltage and Figure 28. Total Input Referred Noise Voltage
Current versus Frequency versus Source Resistance
i n, INPUT REFERRED NOISE CURRENT ( pA/ √ Hz )
1000
Vn, REFERRED NOISE VOLTAGE (nV/ √ Hz)
100 10
80 VCC = +15 V
VCC = +15 V
50 VEE = –15 V VEE = –15 V
f = 1.0 kHz
Ǹ
30 TA = 25°C
) en2 ) 4KTRS
100 TA = 25°C
20 Vn(total) = (inRs)2
10
8.0
5.0 Voltage 10
3.0
2.0 Current
1.0 0.1 1.0

10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k 1.0 M

MC33078 MC33079
Figure 29. Phase Margin and Gain Margin versus

Differential Source Resistance
14 70

12 60
Gain
Am, GAIN MARGIN (dB)

10 50
R1 Phase
–
8.0 VO 40
+
R2
6.0 30
VCC = +15 V
VEE = –15 V
4.0 20
RT = R1 +R2
AV = +100
2.0 VO = 0 V 10
TA = 25°C
0 0
10 100 1.0 k 10 k 100 k
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)
Figure 30. Inverting Amplifier Slew Rate Figure 31. Noninverting Amplifier Slew Rate
V O , OUTPUT VOLTAGE (5.0 V/DIV)

VCC = +15 V VCC = +15 V
VEE = –15 V VEE = –15 V

AV = –1.0 AV = +1.0
RL = 2.0 kΩ RL = 2.0 kΩ
CL = 100 pF CL = 100 pF
TA = 25°C TA = 25°C
Figure 33. Low Frequency Noise Voltage

Figure 32. Noninverting Amplifier Overshoot versus Time
e n , INPUT NOISE VOLTAGE (100 nV/DIV)
VCC = +15 V VCC = +15 V

VEE = –15 V VEE = –15 V
RL = 2.0 kΩ BW = 0.1 Hz to 10 Hz
CL = 100 pF TA = 25°C
AV = +1.0
TA = 25°C
t, TIME (200 µs/DIV) t, TIME (1.0 sec/DIV)

MC33078 MC33079
Figure 34. Voltage Noise Test Circuit

(0.1 Hz to 10 Hzp–p)
0.1 µF
100 kΩ
10 Ω
–
2.0 kΩ
D.U.T. + 22 µF
1/2 4.3 kΩ
+ 4.7 µF MC33078 Scope
– ×1
Rin = 1.0 MΩ
100 kΩ
Voltage Gain = 50,000 2.2 µF
24.3 kΩ 110 kΩ
0.1 µF
Note: All capacitors are non–polarized.

MC33102
Sleep-Mode Two-State,
Micropower Operational
Amplifier
The MC33102 dual operational amplifier is an innovative design concept DUAL SLEEP–MODE
employing Sleep–Mode technology. Sleep–Mode amplifiers have two
separate states, a sleepmode and an awakemode. In sleepmode, the
OPERATIONAL AMPLIFIER
amplifier is active and waiting for an input signal. When a signal is applied
causing the amplifier to source or sink 160 µA (typically) to the load, it will SEMICONDUCTOR
automatically switch to the awakemode which offers higher slew rate, gain TECHNICAL DATA
bandwidth, and drive capability.
• Two States: “Sleepmode” (Micropower) and “Awakemode”
(High Performance)
• Switches from Sleepmode to Awakemode in 4.0 µs when Output Current
Exceeds the Threshold Current (RL = 600 Ω)
• Independent Sleepmode Function for Each Op Amp
•
D SUFFIX
Standard Pinouts – No Additional Pins or Components Required PLASTIC PACKAGE
• Sleepmode State – Can Be Used in the Low Current Idle State as a CASE 751 8
1
Fully Functional Micropower Amplifier (SO–8)
• Automatic Return to Sleepmode when Output Current Drops Below

Threshold
• No Deadband/Crossover Distortion; as Low as 1.0 Hz in the Awakemode
• Drop–in Replacement for Many Other Dual Op Amps
P SUFFIX
• ESD Clamps on Inputs Increase Reliability without Affecting Device PLASTIC PACKAGE
Operation CASE 626 8
TYPICAL SLEEPMODE/AWAKEMODE PERFORMANCE

Sleepmode Awakemode
Characteristic (Typical) (Typical) Unit
Low Current Drain 45 750 µA

Low Input Offset Voltage 0.15 0.15 mV
High Output Current Capability 0.15 50 mA PIN CONNECTIONS
Low T.C. of Input Offset Voltage 1.0 1.0 µV/°C

High Gain Bandwidth (@ 20 kHz) 0.33 4.6 MHz Output 1 1 8 VCC
High Slew Rate 0.16 1.7 V/µs 2 7 Output 2
Inputs 1 1
Low Noise (@ 1.0 kHz) 28 9.0 nV/ √Hz 3 6
2 Inputs
MAXIMUM RATINGS VEE 4 5 2
Ratings Symbol Value Unit
(Dual, Top View)
Supply Voltage (VCC to VEE) VS + 36 V
Input Voltage Range VIR
Output Short Circuit Duration (Note 2) tSC (Note 2) sec

Storage Temperature Tstg – 65 to +150 ORDERING INFORMATION
Maximum Power Dissipation PD (Note 2) mW Operating
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) MC33102D SO–8
is not exceeded (refer to Figure 1). TA = – 40° to +85°C

MC33102
Simplified Block Diagram
Current Awake to
Threshold Sleepmode
Detector Delay Circuit
Fractional
Load Current % of IL IHysteresis
Detector
Buffer Buffer IEnable

Iref CStorage
IL
Vin Op Amp Vout

RL
IBias
Sleepmode Awakemode Enable

Current Isleep Current
Regulator Regulator
Iawake
Input Offset Voltage (RS = 50 Ω, VCM = 0 V, VO = 0 V) 2 VIO mV
Sleepmode
TA = +25°C — 0.15 2.0
TA = –40° to +85°C — — 3.0
Awakemode
TA = +25°C — 0.15 2.0
TA = –40° to +85°C — — 3.0
Input Offset Voltage Temperature Coefficient 3 ∆VIO/∆T µV/°C
(RS = 50 Ω, VCM = 0 V, VO = 0 V)
TA = –40° to +85°C (Sleepmode and Awakemode) — 1.0 —
Input Bias Current (VCM = 0 V, VO = 0 V) 4, 6 IIB nA
Sleepmode
TA = +25°C — 8.0 50
TA = –40° to +85°C — — 60
Awakemode
TA = +25°C — 100 500
TA = –40° to +85°C — — 600
Input Offset Current (VCM = 0 V, VO = 0 V) — IIO nA
Sleepmode
TA = +25°C — 0.5 5.0
TA = –40° to +85°C — — 6.0
Awakemode
TA = +25°C — 5.0 50
TA = –40° to +85°C — — 60

MC33102
Common Mode Input Voltage Range 5 VICR V
(∆VIO = 5.0 mV, VO = 0 V)
Sleepmode and Awakemode –13 –14.8 —
— +14.2 +13
Large Signal Voltage Gain 7 AVOL kV/V
Sleepmode (RL = 1.0 MΩ)
TA = +25°C 25 200 —
TA = –40° to +85°C 15 — —
Awakemode (VO = ±10 V, RL = 600 Ω)
TA = +25°C 50 700 —
TA = –40° to +85°C 25 — —
Sleepmode (VCC = +15 V, VEE = –15 V)
RL = 1.0 MΩ VO + +13.5 +14.2 —
RL = 1.0 MΩ VO – — –14.2 –13.5
Awakemode (VCC = +15 V, VEE = –15 V) V
RL = 600 Ω VO + +12.5 +13.6 —
RL = 600 Ω VO – — –13.6 –12.5
RL = 2.0 kΩ VO + +13.3 +14 —
RL = 2.0 kΩ VO – — –14 –13.3
Awakemode (VCC = +2.5 V, VEE = –2.5 V)
RL = 600 Ω VO + +1.1 +1.6 —
RL = 600 Ω VO – — –1.6 –1.1
Common Mode Rejection (VCM = ±13 V) 11 CMR dB
Sleepmode and Awakemode 80 90 —
Power Supply Rejection (VCC/VEE = +15 V/–15 V, 12 PSR dB

5.0 V/–15 V, +15 V/–5.0 V)
Sleepmode and Awakemode 80 100 —
Output Transition Current 13, 14 µA
Sleepmode to Awakemode (Source/Sink) ITH1
(VS = ±15 V) 200 160 —
(VS = ± 2.5 V) 250 200 —
Awakemode to Sleepmode (Source/Sink) ITH2
(VS = ±15 V) — 142 90
(VS = ± 2.5 V) — 180 140
Output Short Circuit Current (Awakemode) 15, 16 ISC mA
(VID = ±1.0 V, Output to Ground)
Source 50 110 —
Sink 50 110 —
Power Supply Current (per Amplifier) (ACL = 1, VO = 0V) 17 ID µA
Sleepmode (VS = ±15 V)
TA = +25°C — 45 65
TA = – 40° to +85°C — 48 70
Sleepmode (VS = ± 2.5 V)
TA = +25°C — 38 65
TA = – 40° to +85°C — 42 —
Awakemode (VS = ±15 V)
TA = +25°C — 750 800
TA = – 40° to +85°C — 800 900

MC33102
Slew Rate (Vin = –5.0 V to +5.0 V, CL = 50 pF, AV = 1.0) 18 SR V/µs
Sleepmode (RL = 1.0 MΩ) 0.10 0.16 —
Awakemode (RL = 600 Ω) 1.0 1.7 —
Gain Bandwidth Product 19 GBW MHz
Sleepmode (f = 10 kHz) 0.25 0.33 —
Awakemode (f = 20 kHz) 3.5 4.6 —
Sleepmode to Awakemode Transition Time 20, 21 ttr1 µs
(ACL = 0.1, Vin = 0 V to +5.0 V)
RL = 600 Ω — 4.0 —
RL = 10 kΩ — 15 —
Awakemode to Sleepmode Transition Time 22 ttr2 — 1.5 — sec
Unity Gain Frequency (Open Loop) fU kHz
Sleepmode (RL = 100 kΩ, CL = 0 pF) — 200 —
Awakemode (RL = 600 Ω, CL = 0 pF) — 2500 —
Gain Margin 23, 25 AM dB
Phase Margin 24, 26 ∅M Degrees
Channel Separation (f = 100 Hz to 20 kHz) 29 CS dB
Sleepmode and Awakemode — 120 —
Power Bandwidth (Awakemode) BWP kHz

(VO = 10 Vpp, RL = 100 kΩ, THD ≤ 1%) — 20 —
Total Harmonic Distortion (VO = 2.0 Vpp, AV = 1.0) 30 THD %

Awakemode (RL = 600 Ω)
f = 1.0 kHz — 0.005 —
f = 10 kHz — 0.016 —
f = 20 kHz — 0.031 —
DC Output Impedance (VO = 0 V, AV = 10, IQ = 10 µA) 31 RO Ω
Sleepmode — 1.0 k —
Awakemode — 96 —
Differential Input Resistance (VCM = 0 V) Rin MΩ
Sleepmode — 1.3 —
Awakemode — 0.17 —
Differential Input Capacitance (VCM = 0 V) Cin pF
Equivalent Input Noise Voltage (f = 1.0 kHz, RS = 100 Ω) 32 en nV/ √Hz
Sleepmode — 28 —
Equivalent Input Noise Current (f = 1.0 kHz) 33 in pA/ √Hz

MC33102
Figure 1. Maximum Power Dissipation Figure 2. Distribution of Input Offset Voltage

PD(max), MAXIMUM POWER DISSIPATION (mW) versus Temperature (MC33102D Package)
2500 50
Percent Sleepmode 204 Amplifiers tested
PERCENT OF AMPLIFIERS (%)

Percent Awakemode from 3 wafer lots.
2000 40 VCC = +15 V
VEE = –15 V
MC33102P TA = 25°C
1500 30
1000 MC33102D 20
500 10
0 0
–55 –40 –25 0 25 50 85 125 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
Figure 3. Input Offset Voltage Temperature Figure 4. Input Bias Current versus
Coefficient Distribution (MC33102D Package) Common Mode Input Voltage
I IB, AWAKEMODE INPUT BIAS CURRENT (nA)

I IB, SLEEPMODE INPUT BIAS CURRENT (nA)
35 10.5 100
Percent Sleepmode 204 Amplifiers tested
from 3 wafer lots. VCC = +15 V
PERCENT OF AMPLIFIERS (%)
30 Percent Awakemode VEE = –15 V

VCC = +15 V
VEE = –15 V 9.5 TA = 25°C 90
25
TA = – 40°C to 85°C
20 Sleepmode
8.5 80
15
Awakemode
10 7.5 70
5.0
0 6.5 60
–5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 –15 –10 –5.0 0 5.0 10 15
TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (µV/°C) VCM, COMMON MODE INPUT VOLTAGE (V)
Figure 5. Input Common Mode Voltage Range

VICR, INPUT COMMON MODE VOLTAGE RANGE (V)
I IB, AWAKEMODE INPUT BIAS CURRENT (nA)

I IB, SLEEPMODE INPUT BIAS CURRENT (nA)
VCC 10.0 100

Sleepmode Sleepmode
VCC–0.5 80
8.0
Awakemode Awakemode
VCC–1.0
6.0 60
4.0 40
VEE+1.0 VCC = +15 V
VEE = –15 V VCC = +15 V
∆VIO = 5.0 mV Awakemode 2.0 20
VEE+0.5 VEE = –15 V
Sleepmode VCM = 0 V
VEE 0 0
–55 –40 –25 0 25 50 85 125 –55 –40 –25 0 25 50 85 125

MC33102
Figure 7. Open Loop Voltage Gain Figure 8. Output Voltage Swing

130 35
TA = 25°C
30

120 Sleepmode (RL = 1.0 MΩ)
Awakemode (RL = 1.0 MΩ) 25
110
20
Sleepmode (RL = 1.0 MΩ) Awakemode (RL = 600 Ω)
100 15
10
90
5
80 0
–55 –40 –25 0 25 50 85 125 0 3.0 6.0 9.0 12 15 18
TA, AMBIENT TEMPERATURE (°C) VCC, VEE, SUPPLY VOLTAGE (V)
Figure 10. Maximum Peak–to–Peak Output

Figure 9. Output Voltage versus Frequency Voltage Swing versus Load Resistance
30 30
VO, OUTPUT VOLTAGE SWING (Vpp)
25
25
20
20
Sleepmode Awakemode
15 (RL = 1.0 MΩ) (RL = 600 Ω) Awakemode
15
10 VCC = +15 V VCC = +15 V
VEE = –15 V VEE = –15 V
AV = +1.0 10
5.0 f = 1.0 kHz
TA = 25°C TA = 25°C
0 5.0
100 1.0 k 10 k 100 k 500 k 10 100 1.0 k 10 k
f, FREQUENCY (Hz) RL, LOAD RESISTANCE TO GROUND (Ω)
100 120
+PSR
Sleepmode
100
80
Awakemode +PSR
80 Awakemode
60
–PSR
Sleepmode 60 Awakemode
40 –PSR
VCC = +15 V 40 Sleepmode
VCC = +15 V
VEE = –15 V
VEE = –15 V
20 VCM = 0 V
20 ∆VCC = ± 1.5 V
∆VCM = ± 1.5 V
TA = 25°C
TA = 25°C
0 0
10 100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k 1.0 M

MC33102
Figure 13. Sleepmode to Awakemode Figure 14. Awakemode to Sleepmode

Current Threshold versus Supply Voltage Current Threshold versus Supply Voltage
200 190
I TH1, CURRENT THRESHOLD ( µA)
I TH2, CURRENT THRESHOLD ( µA)

190 180
170
180 TA = 25°C
TA = 25°C 160
170 TA = – 55°C
TA = – 55°C 150
TA = 125°C
160
140
150 130
TA = 125°C
140 120
3.0 6.0 9.0 12 15 18 3.0 6.0 9.0 12 15 18
VCC, VEE, SUPPLY VOLTAGE (V) VCC, VEE, SUPPLY VOLTAGE (V)
Figure 15. Output Short Circuit Current Figure 16. Output Short Circuit Current
I SC, OUTPUT SHORT CIRCUIT CURRENT (mA)

versus Output Voltage versus Temperature

120 150
Sink 140 VCC = +15 V
100 VEE = –15 V
Source
Source 130 VID = ± 1.0 V
RL < 10 Ω
80
120 Awakemode
Sink
60 110
VCC = +15 V 100

40
VEE = –15 V 90
VID = ± 1.0 V
20 RL < 10 Ω 80
Awakemode
0 70
0 3.0 6.0 9.0 12 15 –55 –40 –25 0 25 50 85 125
VO, OUTPUT VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 17. Power Supply Current Per Amplifier

versus Temperature Figure 18. Slew Rate versus Temperature
I D , SUPPLY CURRENT PER AMPLIFIER (mA)
I D , SUPPLY CURRENT PER AMPLIFIER (µ A)
60 1.2 0.20 2.0

VCC = +15 V Awakemode (RL = 600 Ω)
55 1.0 VEE = –15 V
0.18 ∆Vin = – 5.0 V to + 5.0 V 1.8

50 0.8
0.16 1.6
Awakemode (mA)
45 0.6
Sleepmode (µA) 0.14 1.4
40 0.4
VCC = +15 V 0.12 1.2
35 VEE = –15 V 0.2
No Load Sleepmode (RL = 1.0 MΩ)
30 0 0.10 1.0
–55 –40 –25 0 25 50 85 125 –55 –40 –25 0 25 50 85 125

MC33102
Figure 19. Gain Bandwidth Product Figure 20. Sleepmode to Awakemode

versus Temperature Transition Time
GBW, GAIN BANDWIDTH PRODUCT (KHz)

GBW, GAIN BANDWIDTH PRODUCT (KHz)
5.0
V P , PEAK VOLTAGE (1.0 V/DIV)

Awakemode (MHz)
4.5 RL = 10 k
4.0
350 3.5
Sleepmode (kHz)
300
VCC = +15 V
250 VEE = –15 V
f = 20 kHz
200
–55 –40 –25 0 25 50 85 125
t, TIME (5.0 µs/DIV)
TA, AMBIENT TEMPERATURE (°C)
Figure 21. Sleepmode to Awakemode Figure 22. Awakemode to Sleepmode

Transition Time Transition Time versus Supply Voltage
2.0
RL = 600 Ω t tr2 , TRANSITION TIME (SEC)

1.5
TA = 25°C
1.0
TA = – 55°C
0.5
TA = 125°C
0
3.0 6.0 9.0 12 15 18
VCC, VEE, SUPPLY VOLTAGE (V)
Figure 23. Gain Margin versus Differential Figure 24. Phase Margin versus Differential
Source Resistance Source Resistance
15 70
Sleepmode
Sleepmode 60
∅ m, PHASE MARGIN (DEG)
13
VCC = +15 V
50 VEE = –15 V
RT = R1 + R2
11 Awakemode 40 VO = 0 V
TA = 25°C Awakemode
9.0 30
VCC = +15 V
VEE = –15 V 20
RT = R1 + R2
7.0 R1 R1
VO = 0 V 10
TA = 25°C VO VO
R2 R2
5.0 0
10 100 1.0 k 10 k 10 100 1.0 k 10 k 100 k
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω) RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)

MC33102
Figure 25. Open Loop Gain Margin versus Figure 26. Phase Margin versus
Output Load Capacitance Output Load Capacitance
14 70
Am, OPEN LOOP GAIN MARGIN (dB)
VCC = +15 V

12 60 VEE = –15 V
VO = 0 V
10 Sleepmode 50
8.0 40
Awakemode
6.0 30 Awakemode
4.0 VCC = +15 V 20

VEE = –15 V
2.0 VO = 0 V 10 Sleepmode
0 0
10 100 1.0 k 10 100 1.0 k 10 k
CL, OUTPUT LOAD CAPACITANCE (pF) CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 27. Sleepmode Voltage Gain and Phase Figure 28. Awakemode Voltage Gain and
versus Frequency Phase versus Frequency
70 40 70 40
1A) Phase, VS = ±18 V TA = 25°C
2A) Phase, VS = ± 2.5 V RL = 600 Ω
θ , EXCESS PHASE (DEGREES)
θ , EXCESS PHASE (DEGREES)

50 1B) Gain, VS = ±18 V 80 50 CL < 10 pF 80
2B) Gain, VS = ± 2.5 V Awakemode

1A
30 1A 120 30 120
2A 2A
10 160 10 1B 160
1B 2B
TA = 25°C
2B 1A) Phase, VS = ±18 V
–10 RL = 1.0 MΩ 200 –10 2A) Phase, VS = ± 2.5 V 200
CL < 10 pF 1B) Gain, VS = ±18 V
Sleepmode 2B) Gain, VS = ± 2.5 V
–30 240 –30 240
10 k 100 k 1.0 M 10 M 30 k 100 k 1.0 M 10 M

Figure 29. Channel Separation versus Frequency versus Frequency
140 100
VCC = +15 V VO = 2.0 Vpp
120 VEE = –15 V TA = 25°C

10 RL = 600 Ω Awakemode
100
AV = +1000
80 1.0
AV = +100
60 0.1 AV = +10
40 VCC = +15 V AV = +1.0
VEE = –15 V 0.01
20 RL = 600 Ω
Awakemode
0 0.001
100 1.0 k 10 k 100 k 100 1.0 k 10 k 100 k

MC33102
Figure 31. Awakemode Output Impedance Figure 32. Input Referred Noise Voltage
en, INPUT REFERRED NOISE VOLTAGE (nV/ Hz)

250 100
VCC = +15 V VCC = +15 V VO
VEE = –15 V VEE = –15 V

200 VCM = 0 V TA = 25°C
50
VO = 0 V
TA = 25°C
150 Awakemode
AV = 100 Sleepmode
100
AV = 1000 AV = 10 10 Awakemode
50
AV = 1.0
0 5.0
1.0 k 10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k
Figure 34. Percent Overshoot

Figure 33. Current Noise versus Frequency versus Load Capacitance
1.0 70
VCC = +15 V VCC = +15 V
RS VO
i n, INPUT NOISE CURRENT (pA/ Hz)
0.8 V = –15 V
EE os, PERCENT OVERSHOOT (%) 60 VEE = –15 V
TA = 25°C TA = 25°C
0.6 (RS = 10 k)
50
Sleepmode
0.4 40 (RL = 1.0 MΩ)
Awakemode 30
0.2 20
Awakemode
Sleepmode 10 (RL = 600 Ω)
0.1 0
10 100 1.0 k 10 k 100 k 10 100 1.0 k
f, FREQUENCY (Hz) CL, LOAD CAPACITANCE (pF)
Figure 35. Sleepmode Large Signal Figure 36. Awakemode Large Signal
Transient Response Transient Response
R RL = 600 Ω
RL =
t, TIME (50 µs/DIV) t, TIME (5.0 µs/DIV)

MC33102
Figure 37. Sleepmode Small Signal Figure 38. Awakemode Small Signal
RL =R RL = 600 Ω
V P , PEAK VOLTAGE (50 mV/DIV)
V P , PEAK VOLTAGE (50 mV/DIV)

CL = 0 pF CL = 0 pF
t, TIME (50 µs/DIV) t, TIME (50 µs/DIV)
CIRCUIT INFORMATION
The MC33102 was designed primarily for applications The awakemode uses higher drain current to provide a
where high performance (which requires higher current drain) high slew rate, gain bandwidth, and output current capability.
is required only part of the time. The two–state feature of this In the awakemode, this amplifier can drive 27 Vpp into a
op amp enables it to conserve power during idle times, yet be 600 Ω load with VS = ±15 V.
powered up and ready for an input signal. Possible An internal delay circuit is used to prevent the amplifier
applications include laptop computers, automotive, cordless from returning to the sleepmode at every zero crossing. This
phones, baby monitors, and battery operated test equipment. delay circuit also eliminates the crossover distortion
Although most applications will require low power commonly found in micropower amplifiers. This amplifier can
consumption, this device can be used in any application process frequencies as low as 1.0 Hz without the amplifier
where better efficiency and higher performance is needed. returning to sleepmode, depending on the load.
The Sleep–Mode amplifier has two states; a sleepmode The first stage PNP differential amplifier provides low noise
and an awakemode. In the sleepmode state, the amplifier is performance in both the sleep and awake modes, and an all
active and functions as a typical micropower op amp. When a NPN output stage provides symmetrical source and sink AC
signal is applied to the amplifier causing it to source or sink frequency response.
sufficient current (see Figure 13), the amplifier will
automatically switch to the awakemode. See Figures 20 and
21 for transition times with 600 Ω and 10 kΩ loads.
The MC33102 will begin to function at power supply current threshold (ITH) of approximately 160 µA. As a result,
voltages as low as VS = ±1.0 V at room temperature. (At this the output switching threshold voltage (VST) is controlled by
voltage, the output voltage swing will be limited to a few the output loading resistance (RL). This loading can be a load
hundred millivolts.) The input voltages must range between resistor, feedback resistors, or both. Then:
VCC and VEE supply voltages as shown in the maximum
rating table. Specifically, allowing the input to go more
negative than 0.3 V below VEE may cause product VST = (160 µA) × RL
damage. Also, exceeding the input common mode voltage
range on either input may cause phase reversal, even if the Large valued load resistors require a large output voltage
inputs are between VCC and VEE. to switch, but reduce unwanted transitions to the
When power is initially applied, the part may start to awakemode. For instance, in cases where the amplifier is
operate in the awakemode. This is because of the currents connected with a large closed loop gain (ACL), the input offset
generated due to charging of internal capacitors. When this voltage (VIO) is multiplied by the gain at the output and could
occurs and the sleepmode state is desired, the user will have produce an output voltage exceeding VST with no input
to wait approximately 1.5 seconds before the device will signal applied.
switch back to the sleepmode. To prevent this from occurring, Small values of RL allow rapid transition to the awakemode
ramp the power supplies from 1.0 V to full supply. Notice that because most of the transition time is consumed slewing in
the device is more prone to switch into the awakemode when the sleepmode until VST is reached (see Figures 20, 21). The
VEE is adjusted than with a similar change in VCC. output switching threshold voltage VST is higher for larger
The amplifier is designed to switch from sleepmode to values of RL, requiring the amplifier to slew longer in the
awakemode whenever the output current exceeds a preset slower sleepmode state before switching to the awakemode.

MC33102
The transition time (ttr1) required to switch from sleep to minimize this problem, a resistor may be added in series with
awake mode is: the output of the device (inserted as close to the device as
possible) to isolate the op amp from both parasitic and load
ttr1 = tD = ITH (RL/SRsleepmode) capacitance.
The awakemode to sleepmode transition time is controlled
by an internal delay circuit, which is necessary to prevent the
Where: tD = Amplifier delay (<1.0 µs)
amplifier from going to sleep during every zero crossing. This
ITH = Output threshold current for
time is a function of supply voltage and temperature as
= more transition (160 µA)
shown in Figure 22.
RL = Load resistance
Gain bandwidth product (GBW) in both modes is an
SRsleepmode = Sleepmode slew rate (0.16 V/µs) important system design consideration when using a
Although typically 160 µA, ITH varies with supply voltage sleepmode amplifier. The amplifier has been designed to
and temperature. In general, any current loading on the obtain the maximum GBW in both modes. “Smooth” AC
output which causes a current greater than ITH to flow will transitions between modes with no noticeable change in the
switch the amplifier into the awakemode. This includes amplitude of the output voltage waveform will occur as long
transition currents such as those generated by charging load as the closed loop gains (ACL) in both modes are
capacitances. In fact, the maximum capacitance that can be substantially equal at the frequency of operation. For smooth
driven while attempting to remain in the sleepmode is AC transitions:
approximately 1000 pF.
(ACLsleepmode) (BW) < GBWsleepmode
CL(max) = ITH/SRsleepmode
= 160 µA/(0.16 V/µs) Where: ACLsleepmode = Closed loop gain in
= 1000 pF ACLsleepmode = the sleepmode
Any electrical noise seen at the output of the MC33102 BW = The required system bandwidth
may also cause the device to transition to the awakemode. To BW = or operating frequency
TESTING INFORMATION
To determine if the MC33102 is in the awakemode or the of the currents caused by both the feedback loop and load
sleepmode, the power supply currents (ID+ and ID–) must be resistance. The total Iout needs to be subtracted from the
measured. When the magnitude of either power supply measured ID to obtain the correct ID of the dual op amp.
current exceeds 400 µA, the device is in the awakemode. An accurate way to measure the awakemode Iout current
When the magnitudes of both supply currents are less than on automatic test equipment is to remove the Iout current on
400 µA, the device is in the sleepmode. Since the total supply both Channel A and B. Then measure the ID values before
current is typically ten times higher in the awakemode than the device goes back to the sleepmode state. The transition
the sleepmode, the two states are easily distinguishable. will take typically 1.5 seconds with ±15 V power supplies.
The measured value of ID+ equals the ID of both devices The large signal sleepmode testing in the characterization
(for a dual op amp) plus the output source current of device A was accomplished with a 1.0 MΩ load resistor which ensured
and the output source current of device B. Similarly, the the device would remain in sleepmode despite large
measured value of ID– is equal to the ID– of both devices plus voltage swings.
the output sink current of each device. Iout is the sum

MC33171
MC33172
MC33174
Low Power, Single Supply
DUAL
Quality bipolar fabrication with innovative design concepts are employed
for the MC33171/72/74 series of monolithic operational amplifiers. These
devices operate at 180 µA per amplifier and offer 1.8 MHz of gain bandwidth 8
8 1
product and 2.1 V/µs slew rate without the use of JFET device technology. 1
Although this series can be operated from split supplies, it is particularly P SUFFIX D SUFFIX
suited for single supply operation, since the common mode input voltage PLASTIC PACKAGE PLASTIC PACKAGE
includes ground potential (VEE). With a Darlington input stage, these devices CASE 626 CASE 751
exhibit high input resistance, low input offset voltage and high gain. The all (SO–8)
NPN output stage, characterized by no deadband crossover distortion and
large output voltage swing, provides high capacitance drive capability, PIN CONNECTIONS
excellent phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33171/72/74 are specified over the industrial/ automotive Offset Null 1 8 NC
temperature ranges. The complete series of single, dual and quad Inv. Input 2
– 7 VCC
operational amplifiers are available in plastic as well as the surface mount Noninv. Input 3 + 6 Output
packages.
• Low Supply Current: 180 µA (Per Amplifier) VEE 4 5 Offset Null
• Wide Supply Operating Range: 3.0 V to 44 V or ±1.5 V to ±22 V (Single, Top View)
• Wide Input Common Mode Range, Including Ground (VEE)
• Wide Bandwidth: 1.8 MHz
Output 1 1
1
8 VCC
• Output 2
2 7
High Slew Rate: 2.1 V/µs Inputs 1 –
+ 2
•
3 6
Low Input Offset Voltage: 2.0 mV – Inputs 2
VEE 4 + 5
• Large Output Voltage Swing: –14.2 V to +14.2 V (with ±15 V Supplies)
• Large Capacitance Drive Capability: 0 pF to 500 pF (Top View)
• Low Total Harmonic Distortion: 0.03%

• Excellent Phase Margin: 60°C
• Excellent Gain Margin: 15 dB QUAD
• Output Short Circuit Protection
• ESD Diodes Provide Input Protection for Dual and Quad
14
14 1
1
P SUFFIX D SUFFIX
CASE 646 CASE 751A
(SO–14)
PIN CONNECTIONS
ORDERING INFORMATION Output 1 1 14 Output 4

Op Amp Operating 2 13
Function Device Temperature Range Package Inputs 1 – 1 4
– Inputs 4
3 + + 12
Single MC33171D TA = –40° to +85°C SO–8
MC33171P TA = –40° to +85°C Plastic DIP VCC 4 11 VEE
5 10
Dual MC33172D TA = –40° to +85°C SO–8 + +
Inputs 2 –
2 3
– Inputs 3
MC33172P TA = –40° to +85°C Plastic DIP 6 9
Quad MC33174D TA = –40° to +85°C SO–14 Output 2 7 8 Output 3

MC33174P TA = –40° to +85°C Plastic DIP
(Top View)

MC33171 MC33172 MC33174
MAXIMUM RATINGS
Supply Voltage VCC/VEE ±22 V
Operating Ambient Temperature Range TA –40 to +85 °C
is not exceeded.

(Each Amplifier)
VCC
Q3 Q4 Q5 Q6 Q7
Q1
Q17
Q2
R1 C1 R2 D2
Bias Q18
Q8 Q11 R6 R7
– Q9 Q10 Output
Inputs R8
+ C2 D3
Q19
Q13 Q14 Q15 Q16
Q12
Current
D1 Limit
R5
R3 R4
VEE/Gnd
Offset Null
(MC33171)

MC33171 MC33172 MC33174
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL connected to ground, TA = Tlow to Thigh [Note 3],
unless otherwise noted.)
Input Offset Voltage (VCM = 0 V) VIO mV
VCC = +15 V, VEE = –15 V, TA = +25°C — 2.0 4.5
VCC = +5.0 V, VEE = 0 V, TA = +25°C — 2.5 5.0
VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh — — 6.5
Average Temperature Coefficient of Offset Voltage ∆VIO/∆T — 10 — µV/°C
Input Bias Current (VCM = 0 V) IIB nA
TA = +25°C — 20 100
TA = Tlow to Thigh — — 200
Input Offset Current (VCM = 0 V) IIO nA
TA = +25°C — 5.0 20
Large Signal Voltage Gain (VO = ±10 V< RL = 10 k) AVOL V/mV
TA = +25°C 50 500 —
TA = Tlow to Thigh 25 — —
Output Voltage Swing VOH V
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C 3.5 4.3 —
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = +25°C 13.6 14.2 —
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = Tlow to Thigh 13.3 — —
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C VOL — 0.05 0.15
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = +25°C — –14.2 –13.6
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = Tlow to Thigh — — –13.3
Output Short Circuit (TA = +25°C) ISC mA
Input Overdrive = 1.0 V, Output to Ground
Source 3.0 5.0 —
Sink 15 27 —
TA = +25°C VEE to (VCC –1.8)
TA = Tlow to Thigh VEE to (VCC –2.2)
Common Mode Rejection Ratio (RS ≤ 10 k) TA = +25°C CMRR 80 90 — dB
Power Supply Rejection Ratio (RS = 100 Ω) TA = +25°C PSRR 80 100 — dB
Power Supply Current (Per Amplifier) ID µA
VCC = +5.0 V, VEE = 0 V, TA = +25°C — 180 250
VCC = +15 V, VEE = –15 V, TA = +25°C — 220 250
VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh — — 300
NOTE: 3. Tlow = –40°C Thigh = +85°C

MC33171 MC33172 MC33174
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)
Slew Rate (Vin = –10 V to +10 V, RL = 10 k, CL = 100 pF) SR V/µs
AV +1 1.6 2.1 —
AV –1 — 2.1 —
Gain Bandwidth Product (f = 100 kHz) GBW 1.4 1.8 — MHz
Power Bandwidth BWp — 35 — kHz
AV = +1.0 RL = 10 k, VO = 20 Vpp, THD = 5%
Phase Margin φm Degree

RL = 10 k — 60 — s
RL = 10 k, CL = 100 pF — 45 —
Gain Margin Am dB
RL = 10 k — 15 —
RL = 10 k, CL = 100 pF — 5.0 —
Equivalent Input Noise Voltage en — 32 — nV/ √ Hz
RS = 100 Ω, f = 1.0 kHz
Equivalent Input Noise Current (f = 1.0 kHz) In — 0.2 — pA/ √ Hz

Differential Input Resistance Rin — 300 — MΩ
Vcm = 0 V
Input Capacitance Ci — 0.8 — pF

Total Harmonic Distortion THD — 0.03 — %
AV = +10, RL = 10 k, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz
Channel Separation (f = 10 kHz) CS — 120 — dB

Open Loop Output Impedance (f = 1.0 MHz) zo — 100 — Ω
Figure 1. Input Common Mode Voltage Range Figure 2. Split Supply Output Saturation
versus Temperature versus Load Current
V ICR , INPUT COMMON MODE VOLTAGE RANGE (V)
0 0
VCC/VEE = ±1.5 V to ± 22 V
VCC VCC VCC/VEE = ± 5.0 V to ± 22 V

∆VIO = 5.0 mV TA = 25°C
–0.8
–1.0
Source
–1.6
–2.4 1.0
0.1 Sink
VEE
VEE
0 0
–55 –25 0 25 50 75 100 125 0 1.0 2.0 3.0 4.0
TA, AMBIENT TEMPERATURE (°C) IL, LOAD CURRENT (±mA)

MC33171 MC33172 MC33174
Figure 3. Open Loop Voltage Gain and Figure 4. Phase Margin and Percent
Phase versus Frequency Overshoot versus Load Capacitance
3 70 70
0 120

60 60
20
φ , EXCESS PAHSE (DEGREES)
%, PERCENT OVERSHOOT
Gain φm VCC/VEE = ±15 V
Phase 140 50 50
1 Margin AVOL = +1.0
10 Margin RL = 10 k
= 15 dB
= 58° 160 40 ∆VO = 20 mVpp 40
0 VCC/VEE = ±15 V 2 TA = 25°C
RL = 10 k 4 30 30
Vout = 0 V 180
–10 TA = 25°C 3 %
20 20
1 — Phase 200
–20 2 — Phase, CL = 100 pF 10 10
3 — Gain
220
4 — Gain, CL = 100 pF
–30 0 0
100 k 1.0 M 10 M 10 20 50 100 200 500 1.0 k
Figure 5. Normalized Gain Bandwidth Product Figure 6. Small and Large Signal
and Slew Rate versus Temperature Transient Response
5.0 µs/DIV
1.3
VCC/VEE = ±15 V
1.2
GBW AND SR (NORMALIZED)
RL = 10 k
VCC/VEE = ±15 V
50 mV/DIV
GBW
1.1 0 VCM = 0 V
VO = 0 V
∆IO = ±0.5 mA
1.0 TA = 25°C
SR
0.9
10 V/DIV
0.8
0
0.7
–55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) 5.0 µs/DIV
Figure 7. Output Impedance and Frequency Figure 8. Supply Current versus Supply Voltage
140 1.1
I D , I CC , POWER SUPPLY CURRENT (mA)
VCC/VEE = ±15 V 1. TA = –55°C 1

120 AV = +1.0 2. TA = 25°C Quad
2
zo , OUTPUT IMPEDANCE (Ω )
RL = 10 k AV = 1000 0.9 3. TA = 125°C

100 CL = 100 pF 3
TA = 25°C
AV = 100 0.7
80
Dual 1
60
0.5 2
3
40 AV = 10 AV = 1.0
0.3 Single 1
20 2
3
0 0.1
200 2.0 k 20 k 200 k 2.0 M 0 5.0 10 15 20 25
f, FREQUENCY (Hz) VCC/VEE, SUPPLY VOLTAGE (±V)

MC33171 MC33172 MC33174
APPLICATIONS INFORMATION – CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the voltage to approach within millivolts of VEE. For sink currents
MC33171/72/74 amplifier family is similar to low power op (> 0.4 mA), diode D3 clamps the voltage across R4. Thus the
amp products utilizing JFET input devices, these amplifiers negative swing is limited by the saturation voltage of Q15,
offer additional advantages as a result of the PNP transistor plus the forward diode drop of D3 (≈VEE +1.0 V). Therefore
differential inputs and an all NPN transistor output stage. an unprecedented peak–to–peak output voltage swing is
Because the input common mode voltage range of this possible for a given supply voltage as indicated by the output
input stage includes the VEE potential, single supply swing specifications.
operation is feasible to as low as 3.0 V with the common If the load resistance is referenced to VCC instead of
mode input voltage at ground potential. ground for single supply applications, the maximum possible
The input stage also allows differential input voltages up to output swing can be achieved for a given supply voltage. For
±44 V, provided the maximum input voltage range is not light load currents, the load resistance will pull the output to
exceeded. Specifically, the input voltages must range VCC during the positive swing and the output will pull the load
between VCC and VEE supply voltages as shown by the resistance near ground during the negative swing. The load
maximum rating table. In practice, although not resistance value should be much less than that of the
recommended, the input voltages can exceed the VCC feedback resistance to maximize pull–up capability.
voltage by approximately 3.0 V and decrease below the VEE Because the PNP output emitter–follower transistor has
voltage by 0.3 V without causing product damage, although been eliminated, the MC33171/72/74 family offers a 15 mA
output phase reversal may occur. It is also possible to source minimum current sink capability, typically to an output voltage
up to 5.0 mA of current from VEE through either inputs’ of (VEE +1.8 V). In single supply applications the output can
clamping diode without damage or latching, but phase directly source or sink base current from a common emitter
reversal may again occur. If at least one input is within the NPN transistor for current switching applications.
common mode input voltage range and the other input is In addition, the all NPN transistor output stage is inherently
within the maximum input voltage range, no phase reversal faster than PNP types, contributing to the bipolar amplifier’s
will occur. If both inputs exceed the upper common mode improved gain bandwidth product. The associated high
input voltage limit, the output will be forced to its lowest frequency low output impedance (200 Ω typ @ 1.0 MHz)
voltage state. allows capacitive drive capability from 0 pF to 400 pF without
Since the input capacitance associated with the small oscillation in the noninverting unity gain configuration. The
geometry input device is substantially lower (0.8 pF) than that 60°C phase margin and 15 dB gain margin, as well as the
of a typical JFET (3.0 pF), the frequency response for a given general gain and phase characteristics, are virtually
input source resistance is greatly enhanced. This becomes independent of the source/sink output swing conditions. This
evident in D–to–A current to voltage conversion applications allows easier system phase compensation, since output
where the feedback resistance can form a pole with the input swing will not be a phase consideration. The AC
capacitance of the op amp. This input pole creates a 2nd characteristics of the MC33171/72/74 family also allow
Order system with the single pole op amp and is therefore excellent active filter capability, especially for low voltage
detrimental to its settling time. In this context, lower input single supply applications.
capacitance is desirable especially for higher values of Although the single supply specification is defined at 5.0 V,
feedback resistances (lower current DACs). This input pole these amplifiers are functional to at least 3.0 V @ 25°C.
can be compensated for by creating a feedback zero with a However slight changes in parametrics such as bandwidth,
capacitance across the feedback resistance, if necessary, to slew rate, and DC gain may occur.
reduce overshoot. For 10 kΩ of feedback resistance, the If power to this integrated circuit is applied in reverse
MC33171/72/74 family can typically settle to within 1/2 LSB polarity, or if the IC is installed backwards in a socket, large
of 8 bits in 4.2 µs, and within 1/2 LSB of 12 bits in 4.8 µs for unlimited current surges will occur through the device that
a 10 V step. In a standard inverting unity gain fast settling may result in device destruction.
configuration, the symmetrical slew rate is typically As usual with most high frequency amplifiers, proper lead
± 2.1 V/µs. In the classic noninverting unity gain dress, component placement and PC board layout should
configuration the typical output positive slew rate is also be exercised for optimum frequency performance. For
2.1 V/µs, and the corresponding negative slew rate will example, long unshielded input or output leads may result in
usually exceed the positive slew rate as a function of the fall unwanted input/output coupling. In order to preserve the
time of the input waveform. relatively low input capacitance associated with these
The all NPN output stage, shown in its basic form on the amplifiers, resistors connected to the inputs should be
equivalent circuit schematic, offers unique advantages over immediately adjacent to the input pin to minimize additional
the more conventional NPN/PNP transistor Class AB output stray input capacitance. This not only minimizes the input
stage. A 10 kΩ load resistance can typically swing within 0.8 V pole for optimum frequency response, but also minimizes
of the positive rail (VCC) and negative rail (VEE), providing a extraneous “pick up” at this node. Supply decoupling with
28.4 Vpp swing from ±15 V supplies. This large output swing adequate capacitance immediately adjacent to the supply pin
becomes most noticeable at lower supply voltages. is also important, particularly over temperature, since many
The positive swing is limited by the saturation voltage of types of decoupling capacitors exhibit great impedance
the current source transistor Q7, the VBE of the NPN pull–up changes over temperature.
transistor Q17, and the voltage drop associated with the The output of any one amplifier is current limited and thus
short circuit resistance, R5. For sink currents less than protected from a direct short to ground. However, under such
0.4 mA, the negative swing is limited by the saturation conditions, it is important not to allow the device to exceed
voltage of the pull–down transistor Q15, and the voltage drop the maximum junction temperature rating. Typically for ±15 V
across R4 and R5. For small valued sink currents, the above supplies, any one output can be shorted continuously to
voltage drops are negligible, allowing the negative swing ground without exceeding the maximum temperature rating.

MC33171 MC33172 MC33174
Figure 9. AC Coupled Noninverting Amplifier Figure 10. AC Coupled Inverting Amplifier

with Single +5.0 V Supply with Single +5.0 V Supply
VCC
2.2 k 510 k
VCC
VO 0 3.6 Vpp 100 k VO 0 3.8 Vpp
Cin 100 k
+ CO
VO 100 k CO
– +
10 k VO
100 k –
Vin RL 100 k
Cin 10 k
1.0 k RL 100 k
Vin
AV = 101 AV = 10
BW ( –3.0 dB) = 20 kHz BW ( –3.0 dB) = 200 kHz
Figure 11. DC Coupled Inverting Amplifier

Maximum Output Swing with Single Figure 12. Offset Nulling Circuit
+5.0 V Supply
VCC
100 k
VCC
50 k 3 7
4.7 k RL + 6
+ 2
VO – 5
– 1
4 10 k
100 k 1.0 M
V 2.5 V 4.2 Vpp VEE

Vin O
Offset Nulling range is approximately ±80 mV with
AV = 10 a 10 k potentiometer, MC33171 only.
BW ( –3.0 dB) = 200 kHz
Figure 13. Active High–Q Notch Filter Figure 14. Active Bandpass Filter
VCC
Vin ≥ 0.2 Vdc
fo = 30 kHz
C R3 Q = 10
– 0.047
16 k 16 k VO R1 2.2 k HO = 1.0
Vin + 1.1 k
R R Vin –
0.01 C VO
C +
R2 0.047
5.6 k
2C 2C fo = 1.0 kHz 0.4
2R
0.02 32 k 0.02 1 VCC R3 R1 R3
Then: R1 = R2 =
fo = 2 HO 4Q2R1 –R3
4 π RC
Given fo = center frequency Q Qo fo
R3 = < 0.1
Ao = Gain at center frequency π foC GBW
Choose Value fo, Q, Ao, C
For less than 10% error for operational amplifier, where fo and GBW are expressed in Hz.

MC33178
High Output Current MC33179
Low Power, Low Noise Bipolar

The MC33178/9 series is a family of high quality monolithic amplifiers
HIGH OUTPUT CURRENT
employing Bipolar technology with innovative high performance concepts for LOW POWER, LOW NOISE
quality audio and data signal processing applications. This device family
incorporates the use of high frequency PNP input transistors to produce
amplifiers exhibiting low input offset voltage, noise and distortion. In addition,
the amplifier provides high output current drive capability while consuming
only 420 µA of drain current per amplifier. The NPN output stage used,
exhibits no deadband crossover distortion, large output voltage swing, DUAL
excellent phase and gain margins, low open–loop high frequency output
impedance, symmetrical source and sink AC frequency performance. P SUFFIX
PLASTIC PACKAGE
The MC33178/9 family offers both dual and quad amplifier versions,
CASE 626
tested over the vehicular temperature range, and are available in DIP and 8
SOIC packages. 1
• 600 Ω Output Drive Capability

• Large Output Voltage Swing
D SUFFIX
PLASTIC PACKAGE
• Low Offset Voltage: 0.15 mV (Mean) 8
1
CASE 751
• Low T.C. of Input Offset Voltage: 2.0 µV/°C
(SO–8)
• Low Total Harmonic Distortion: 0.0024% (@ 1.0 kHz w/600 Ω Load)

PIN CONNECTIONS
• High Slew Rate: 2.0 V/µs Output 1 1 8 VCC
• Dual Supply Operation: ±2.0 V to ±18 V Inputs 1
2
–
+
7 Output 2
•
3 6
ESD Clamps on the Inputs Increase Ruggedness –
+ 5 Inputs 2
VEE 4
without Affecting Device Performance
(Top View)
Representative Schematic Diagram (Each Amplifier)

VCC
QUAD
P SUFFIX
Iref
PLASTIC PACKAGE
Iref 14 CASE 646
1
Vin – Vin + CC
D SUFFIX
PLASTIC PACKAGE
VO
14 CASE 751A
CM
1 (SO–14)
PIN CONNECTIONS
VEE
2 13
– –
ORDERING INFORMATION Inputs 1 1 4 Inputs 4
3 + + 12
Op Amp Fully Operating
Function Compensated Temperature Range Package VCC 4 11 VEE
5 10
Dual MC33178D SO–8 + +
MC33178P Plastic DIP 6 – – 9
TA = –40° to +85°C
Quad MC33179D SO–14 Output 2 7 8 Output 3
(Top View)

MC33178 MC33179
MAXIMUM RATINGS
exceeded. (See power dissipation performance characteristic, Figure 1.)
Input Offset Voltage (RS = 50 Ω, VCM = 0 V, VO = 0 V) 2 |VIO| mV
(VCC = +2.5 V, VEE = –2.5 V to VCC = +15 V, VEE = –15 V)
TA = +25°C — 0.15 3.0
TA = –40° to +85°C — — 4.0
Average Temperature Coefficient of Input Offset Voltage 2 ∆VIO/∆T µV/°C
(RS = 50 Ω, VCM = 0 V, VO = 0 V)
TA = –40° to +85°C — 2.0 —
TA = +25°C — 100 500
TA = –40° to +85°C — — 600
Input Offset Current (VCM = 0 V, VO = 0 V) |IIO| nA
TA = +25°C — 5.0 50
TA = –40° to +85°C — — 60
Common Mode Input Voltage Range 5 VICR –13 –14 — V
(∆VIO = 5.0 mV, VO = 0 V) — +14 +13
Large Signal Voltage Gain (VO = –10 V to +10 V, RL = 600 Ω) 6, 7 AVOL V/V
TA = +25°C 50 k 200 k —
TA = –40° to +85°C 25 k — —
(VCC = +15 V, VEE = –15 V)
RL = 300 Ω VO+ — +12 —
RL = 300 Ω VO– — –12 —
RL = 600 Ω VO+ +12 +13.6 —
RL = 600 Ω VO– — –13 –12
RL = 2.0 kΩ VO+ +13 +14 —
RL = 2.0 kΩ VO– — –13.8 –13
(VCC = +2.5 V, VEE = –2.5 V)
RL = 600 Ω VO+ 1.1 1.6 —
RL = 600 Ω VO– — –1.6 –1.1
Common Mode Rejection (Vin = ±13 V) 11 CMR 80 110 — dB
Power Supply Rejection 12 PSR 80 110 — dB
VCC/VEE = +15 V/ –15 V, +5.0 V/ –15 V, +15 V/ –5.0 V
Output Short Circuit Current (VID = ±1.0 V, Output to Ground) 13, 14 ISC mA
Source (VCC = 2.5 V to 15 V) +50 +80 —
Sink (VEE = –2.5 V to –15 V) –50 –100 —
Power Supply Current (VO = 0 V) 15 ID mA
(VCC = 2.5 V, VEE = –2.5 V to VCC = +15 V, VEE = –15 V)
MC33178 (Dual)
TA = +25°C — — 1.4
TA = –40° to +85°C — — 1.6
MC33179 (Quad)
TA = +25°C — 1.7 2.4
TA = –40° to +85°C — — 2.6

MC33178 MC33179
Slew Rate 16, 31 SR 1.2 2.0 — V/µs
(Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 100 pF, AV = +1.0 V)
Gain Bandwidth Product (f = 100 kHz) 17 GBW 2.5 5.0 — MHz

AC Voltage Gain (RL = 600 Ω, VO = 0 V, f = 20 kHz) 18, 19 AVO — 50 — dB
Unity Gain Frequency (Open–Loop) (RL = 600 Ω, CL = 0 pF) fU — 3.0 — MHz
Gain Margin (RL = 600 Ω, CL = 0 pF) 20, 22, 23 Am — 15 — dB
Phase Margin (RL = 600 Ω, CL = 0 pF) 21, 22, 23 φm — 60 — Degree
s

Power Bandwidth (VO = 20 Vpp, RL = 600 Ω, THD ≤ 1.0%) BWp — 32 — kHz
Distortion (RL = 600 Ω,, VO = 2.0 Vpp, AV = +1.0 V) 25 THD %
(f = 1.0 kHz) — 0.0024 —
(f = 10 kHz) — 0.014 —
(f = 20 kHz) — 0.024 —
Open Loop Output Impedance 26 |ZO| — 150 — Ω
(VO = 0 V, f = 3.0 MHz, AV = 10 V)
Differential Input Resistance (VCM = 0 V) Rin — 200 — kΩ

Differential Input Capacitance (VCM = 0 V) Cin — 10 — pF
Equivalent Input Noise Voltage (RS = 100 Ω,) 27 en nV/ √ Hz
f = 10 Hz — 8.0 —
f = 1.0 kHz — 7.5 —
Equivalent Input Noise Current 28 in pA/ √ Hz
f = 10 Hz — 0.33 —
f = 1.0 kHz — 0.15 —
Figure 1. Maximum Power Dissipation Figure 2. Input Offset Voltage versus

PD (MAX), MAXIMUM POWER DISSIPATION (mW)
versus Temperature Temperature for 3 Typical Units

2400 4.0
VCC = +15 V
3.0 VEE = –15 V

2000 MC33178P/9P
RS = 10 Ω
2.0 VCM = 0 V
Unit 1
1600
1.0
MC33179D Unit 2
1200 0
Unit 3
–1.0
800 MC33178D
–2.0
400 –3.0
0 –4.0
–60 –40 –20 0 20 40 60 80 100 120 140 160 180 –55 –25 0 25 50 75 100 125

MC33178 MC33179

versus Common Mode Voltage versus Temperature
160 120
140 VCC = +15 V

110
VEE = –15 V
120
VCM = 0 V
100
100
80 90
60 VCC = +15 V
VEE = –15 V 80
40 TA = 25°C
70
20
0 60
–15 –10 –5.0 0 5.0 10 15 –55 –25 0 25 50 75 100 125
V ICR, INPUT COMMON MODE VOLTAGE RANGE (V)

VCC 250
VCC –0.5 V AVOL, OPEN LOOP VOLTAGE GAIN (kV/V)

200
VCC –1.0 V VCC = +5.0 V to +18 V
VEE = –5.0 V to –18 V
VCC –1.5 V ∆VIO = 5.0 mV 150
VCC –2.0 V
VCC = +15 V
100
VEE = –15 V
f = 10 Hz
VEE +1.0 V ∆VO = 10 V to +10 V
50
RL = 600 Ω
VEE +0.5 V
VEE 0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
Figure 7. Voltage Gain and Phase Figure 8. Output Voltage Swing

50 80 40
40 VCC = +15 V 100 35

, EXCESS PHASE (DEGREES)
VEE = –15 V TA = 25°C

30 120
VO = 0 V 30
20 TA = 25°C 140 RL = 10 kΩ
10 25
160
RL = 600 Ω
0 180 20
1A
–10 200 15
1B
–20 220
1A) Phase (RL = 600 Ω) 2B 10
–30 2A) Phase (RL = 600 Ω, CL = 300 pF) 240
φ
–40 1B) Gain (RL = 600 Ω)

2A 5.0
260
2B) Gain (RL = 600 Ω, CL = 300 pF)
–50 280 0
2 3 4 5 6 7 8 9 10 20 0 5.0 10 15 20

MC33178 MC33179
Figure 9. Output Saturation Voltage Figure 10. Output Voltage

versus Load Current versus Frequency
VCC
Source 28
TA = +125°C
VCC –1.0 V 24

TA = –55°C
20
VCC –2.0 V
16
VEE +2.0 V Sink 12 VCC = +15 V
VEE = –15 V
TA = –55°C 8.0 RL = 600 Ω
VEE +1.0 V AV = +1.0 V
VCC = +5.0 V to +18 V 4.0 THD = ≤1.0%
TA = +125°C TA = 25°C
VEE = –5.0 V to –18 V
VEE 0
0 5.0 10 15 20 1.0 k 10 k 100 k 1.0 M
IL, LOAD CURRENT (±mA) f, FREQUENCY (Hz)
versus Frequency Over Temperature versus Frequency Over Temperature
120 120
TA = –55° to +125°C
100 VCC = +15 V +PSR VCC = +15 V
VEE = –15 V 100 VEE = –15 V
VCM = 0 V ∆VCC = ±1.5 V
80 ∆VCM = ±1.5 V 80 –PSR
TA = –55° to +125°C
VCC
60 60 –
– ADM ∆VO
∆VCM ADM ∆VO +
40 40
+ VEE
20 ∆VCM 20 ∆VO/ADM
CMR = 20 Log x ADM PSR = 20 Log
∆VO ∆VCC
0 0
10 100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k 1.0 M
Figure 13. Output Short Circuit Current Figure 14. Output Short Circuit Current
versus Output Voltage versus Temperature
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)
100 100
Source
80 90 VCC = +15 V
Sink VEE = –15 V
Sink VID = ±1.0 V
60 80 RL < 10 Ω
Source
40 70
VCC = +15 V
VEE = –15 V
20 VID = ±1.0 V 60
0 50
–15 –9.0 –3.0 0 3.0 9.0 15 –55 –25 0 25 50 75 100 125
VO, OUTPUT VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

MC33178 MC33179
Figure 15. Supply Current versus Supply Figure 16. Normalized Slew Rate
Voltage with No Load versus Temperature
625 1.15
I CC, SUPPLY CURRENT/AMPLIFIER (µ A)
1.10
SR, SLEW RATE (NORMALIZED)

VCC = +15 V
500 TA = +125°C VEE = –15 V
1.05
∆Vin = 20 Vpp
375 TA = +25°C 1.00
0.95
250 TA = –55°C 0.90
–
0.85 VO
125 ∆Vin +
600 Ω 100 pF
0.80
0 0.75
0 2.0 4.0 6.0 8.0 10 12 14 16 18 –55 –25 0 25 50 75 100 125
VCC, |VEE| , SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 17. Gain Bandwidth Product Figure 18. Voltage Gain and Phase
10 50 80
40 100
Phase

8.0 30 120
20 140
6.0 10 Gain 160
0 180
4.0 VCC = +15 V VCC = +15 V 200
–10
VEE = –15 V VEE = –15 V
f = 100 kHz –20 RL = 600 Ω 220
2.0 RL = 600 Ω –30
TA = 25°C 240
CL = 0 pF CL = 0 pF
–40 260
0 –50 280
–55 –25 0 25 50 75 100 125 100 k 1.0 M 10 M 100 M
Figure 19. Voltage Gain and Phase Figure 20. Open Loop Gain Margin
versus Frequency versus Temperature
50 80 15
TA = 25°C CL = 10 pF
Am, OPEN LOOP GAIN MARGIN (dB)
40 100
RL = ∞
30 CL = 0 pF 120 12
φ , PHASE (DEGREES)
20 140
1A CL = 100 pF
10 1B 160 9.0
2A
0 180 CL = 300 pF
2B
–10 200 6.0
–20 1A) Phase V =18 V, V = –18 V 220 VCC = +15 V
CC EE VEE = –15 V
–30 2A) Phase VCC 1.5 V, VEE = –1.5 V 240 3.0 RL = 600 Ω
1B) Gain V = 18 V, V = –18 V
–40 2B) Gain VCC = 1.5 V, VEE = –1.5 V 260
CC EE
–50 280 0
100 k 1.0 M 10 M 100 M –55 –25 0 25 50 75 100 125

MC33178 MC33179
Figure 21. Phase Margin Figure 22. Phase Margin and Gain Margin
versus Temperature versus Differential Source Resistance
60 12 60

50 CL = 10 pF 10 50

VCC = +15 V Gain Margin
CL = 100 pF
40 8.0 VEE = –15 V 40
RT = R1+R2
VO = 0 V
30 6.0 TA = 25°C 30
CL = 300 pF
20 4.0 20
VCC = +15 V R1
– Phase Margin
VEE = –15 V 2.0 Vin VO 10
10
RL = 600 Ω +
R2
0 0 0
–55 –25 0 25 50 75 100 125 100 1.0 k 10 k 100 k
TA, AMBIENT TEMPERATURE (°C) RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)
Figure 23. Open Loop Gain Margin and Phase Figure 24. Channel Separation
Margin versus Output Load Capacitance versus Frequency
18 60 150
Phase Margin
VCC = +15 V
m, PHASE MARGIN (DEGREES)
Drive Channel
15 VEE = –15 V 50
140 VCC = +15 V
VO = 0 V CEE = –15 V
12 40 RL = 600 Ω
Gain Margin 130 TA = 25°C
9.0 30
120
6.0 – 20
Vin VO
+
3.0 600 Ω CL
10 110
φ
0 0 100
10 100 1.0 k 100 1.0 k 10 k 100 k 1.0 M
CL, OUTPUT LOAD CAPACITANCE (pF) f, FREQUENCY (Hz)
Figure 25. Total Harmonic Distortion Figure 26. Output Impedance

10 500
VCC = +15 V VO = 2.0 Vpp

|Z O |, OUTPUT IMPEDANCE ( Ω )
VEE = –15 V TA = 25°C VCC = +15 V

1. AV = 1.0
RL = 600 Ω AV = 1000 400
VEE = –15 V
2. AV = 10
3. AV = 100 VO = 0 V
1.0
300 4. AV = 1000 TA = 25°C
AV = 100
200
0.1
AV = 10 100 3
AV = 1.0 2 1
4
0.01 0
10 100 1.0 k 10 k 100 k 1.0 k 10 k 100 k 1.0 M 10 M

MC33178 MC33179
Figure 27. Input Referred Noise Voltage Figure 28. Input Referred Noise Current
e n , INPUT REFERRED NOISE VOLTAGE ( nV/ √ Hz ) versus Frequency versus Frequency
i n , INPUT REFERRED NOISE CURRENT (pA/ √ Hz )

20 0.5
Input Noise Voltage Test Circuit Input Noise Current Test Circuit
18
+ +
16 VO 0.4 RS VO
– –
14
12 0.3
10
(RS = 10 kΩ)
8.0 0.2
6.0
VCC = +15 V VCC = +15 V
4.0 0.1
VEE = –15 V VEE = –15 V
2.0 TA = 25°C TA = 25°C
0 0
10 100 1.0 k 10 k 10 k 10 100 1.0 k 10 k 100 k
Figure 29. Percent Overshoot versus

Load Capacitance Figure 30. Noninverting Amplifier Slew Rate
100
VCC = +15 V
90 VCC = +15 V
V O, OUTPUT VOLTAGE (5.0 V/DIV)
VEE = –15 V
80 VEE = –15 V AV = +1.0
PERCENT OVERSHOOT (%)
70
TA = 25°C RL = 600 Ω
CL = 100 pF
60 TA = 25°C
50 RL = 600 Ω
40 RL = 2.0 kΩ
30
20
10
0
10 100 1.0 k 10 k t, TIME (2.0 µs/DIV)
Figure 31. Small Signal Transient Response Figure 32. Large Signal Transient Response
VCC = +15 V VCC = +15 V

V O, OUTPUT VOLTAGE (50 mV/DIV)
VEE = –15 V VEE = –15 V

AV = +1.0 AV = +1.0
RL = 600 Ω RL = 600 Ω
CL = 100 pF CL = 100 pF
TA = 25°C TA = 25°C
t, TIME (2.0 ns/DIV) t, TIME (5.0 µs/DIV)

MC33178 MC33179
Figure 33. Telephone Line Interface Circuit
10 k
A1
To –
Receiver 10 k
+
10 k
1.0 µF
200 k
120 k
300 0.05 µF
From 2.0 k A2
Microphone – 820
+
Tip
VR
1N4678 Phone Line

10 k
Ring
10 k A3
–
+
VR
APPLICATION INFORMATION
This unique device uses a boosted output stage to could easily exceed the junction temperature to the extent of
combine a high output current with a drain current lower than causing permanent damage.
similar bipolar input op amps. Its 60° phase margin and 15 dB
gain margin ensure stability with up to 1000 pF of load Stability
capacitance (see Figure 23). The ability to drive a minimum As usual with most high frequency amplifiers, proper lead
600 Ω load makes it particularly suitable for telecom dress, component placement, and PC board layout should be
applications. Note that in the sample circuit in Figure 33 both exercised for optimum frequency performance. For example,
A2 and A3 are driving equivalent loads of approximately long unshielded input or output leads may result in unwanted
600 Ω . input/output coupling. In order to preserve the relatively
The low input offset voltage and moderately high slew rate low input capacitance associated with these amplifiers,
and gain bandwidth product make it attractive for a variety of resistors connected to the inputs should be immediately
other applications. For example, although it is not single adjacent to the input pin to minimize additional stray input
supply (the common mode input range does not include capacitance. This not only minimizes the input pole
ground), it is specified at +5.0 V with a typical common mode frequency for optimum frequency response, but also
rejection of 110 dB. This makes it an excellent choice for use minimizes extraneous “pick up” at this node. Supplying
with digital circuits. The high common mode rejection, which decoupling with adequate capacitance immediately adjacent
is stable over temperature, coupled with a low noise figure to the supply pin is also important, particularly over
and low distortion, is an ideal op amp for audio circuits. temperature, since many types of decoupling capacitors
The output stage of the op amp is current limited and exhibit great impedance changes over temperature.
therefore has a certain amount of protection in the event of a Additional stability problems can be caused by high load
short circuit. However, because of its high current output, it is capacitances and/or a high source resistance. Simple
especially important not to allow the device to exceed the compensation schemes can be used to alleviate these
maximum junction temperature, particularly with the effects.
MC33179 (quad op amp). Shorting more than one amplifier

MC33178 MC33179
If a high source of resistance is used (R1 > 1.0 kΩ), a For moderately high capacitive loads (500 pF < CL
compensation capacitor equal to or greater than the input < 1500 pF) the addition of a compensation resistor on the
capacitance of the op amp (10 pF) placed across the order of 20 Ω between the output and the feedback loop will
feedback resistor (see Figure 34) can be used to neutralize help to decrease miller loop oscillation (see Figure 35). For
that pole and prevent outer loop oscillation. Since the closed high capacitive loads (C L > 1500 pF), a combined
loop transient response will be a function of that capacitance, compensation scheme should be used (see Figure 36). Both
it is important to choose the optimum value for that capacitor. the compensation resistor and the compensation capacitor
This can be determined by the following Equation: affect the transient response and can be calculated for
optimum performance. The value of CC can be calculated
using Equation (1). The Equation to calculate RC is as
CC = (1 +[R1/R2])2 CL (ZO/R2) (1) follows:
where: ZO is the output impedance of the op amp.

R C = ZO R1/R2 (2)
Figure 34. Compensation for Figure 35. Compensation Circuit for

High Source Impedance Moderate Capacitive Loads
R2
R2
CC
–
RC
–
R1 +
+ CL
R1
ZL
Figure 36. Compensation Circuit for

High Capacitive Loads
R2
CC
–
RC
+
R1
CL

MC33201
MC33202
MC33204
Rail-to-Rail Operational
Amplifiers
LOW VOLTAGE
The MC33201/2/4 family of operational amplifiers provide rail–to–rail
operation on both the input and output. The inputs can be driven as high as
RAIL–TO–RAIL
200 mV beyond the supply rails without phase reversal on the outputs, and OPERATIONAL AMPLIFIERS
the output can swing within 50 mV of each rail. This rail–to–rail operation
enables the user to make full use of the supply voltage range available. It is
designed to work at very low supply voltages (± 0.9 V) yet can operate with a
supply of up to +12 V and ground. Output current boosting techniques
provide a high output current capability while keeping the drain current of the NC 1 8 NC
amplifier to a minimum. Also, the combination of low noise and distortion with 2 7 VCC
a high slew rate and drive capability make this an ideal amplifier for audio 8
Inputs
applications. 1 3 6 Output
• Low Voltage, Single Supply Operation P SUFFIX VEE 4 5 NC

(+1.8 V and Ground to +12 V and Ground) PLASTIC PACKAGE
CASE 626
• Input Voltage Range Includes both Supply Rails (Single, Top View)
• Output Voltage Swings within 50 mV of both Rails

• No Phase Reversal on the Output for Over–driven Input Signals Output 1 1 8 VCC
• High Output Current (ISC = 80 mA, Typ)
8
1 2 7 Output 2
• Low Supply Current (ID = 0.9 mA, Typ) D SUFFIX
Inputs 1
3
1
6
• 600 Ω Output Drive Capability PLASTIC PACKAGE
2
Inputs 2
• Extended Operating Temperature Ranges
CASE 751
(SO–8)
VEE 4 5
(–40° to +105°C and –55° to +125°C) (Dual, Top View)

• Typical Gain Bandwidth Product = 2.2 MHz
• Offered in New TSSOP Package Including Standard SOIC and
DIP Packages
14
14
ORDERING INFORMATION 1 1
Operating
P SUFFIX D SUFFIX
Operational Temperature
Amplifier Function Device Range Package CASE 646 CASE 751A
MC33201D SO–8 (SO–14)
TA= –40 ° to +105°C
MC33201P Plastic DIP 14
Single
MC33201VD TA = –55 ° to SO–8 1
MC33201VP +125°C Plastic DIP DTB SUFFIX

MC33202D SO–8 PLASTIC PACKAGE
TA= –40 ° to +105°C CASE 948G
MC33202P Plastic DIP (TSSOP–14)
Dual
MC33202VD TA = –55 ° to SO–8
MC33202VP +125°C Plastic DIP Output 1 1 14 Output 4
MC33204D SO–14 2 1
13
4
Inputs 1 Inputs 4
3 12
MC33204DTB TA= –40 ° to +105°C TSSOP–14
VCC 4 11 VEE
Quad 5 10
MC33204VD SO–14 Inputs 2 2 3 Inputs 3
6 9
55 ° to
TA = –55
MC33204VDTB TSSOP–14
+125°C Output 2 7 8 Output 3
MC33204VP Plastic DIP
(Quad, Top View)

MC33201 MC33202 MC33204
DC ELECTRICAL CHARACTERISTICS (TA = 25°C)

Characteristic VCC = 2.0 V VCC = 3.3 V VCC = 5.0 V Unit
Input Offset Voltage mV
VIO (max)
MC33201 ± 8.0 ± 8.0 ± 6.0
MC33202 ±10 ±10 ± 8.0
MC33204 ±12 ±12 ±10
Output Voltage Swing

VOH (RL = 10 kΩ) 1.9 3.15 4.85 Vmin
VOL (RL = 10 kΩ) 0.10 0.15 0.15 Vmax
Power Supply Current mA
per Amplifier (ID) 1.125 1.125 1.125
Specifications at VCC = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. VEE = Gnd.
MAXIMUM RATINGS
Common Mode Input Voltage Range (Note 2) VCM VCC + 0.5 V to V
VEE – 0.5 V
Output Short Circuit Duration ts (Note 3) sec
NOTES: 1. The differential input voltage of each amplifier is limited by two internal parallel back–to–back
diodes. For additional differential input voltage range, use current limiting resistors in series
with the input pins.
2. The input common mode voltage range is limited by internal diodes connected from the inputs
to both supply rails. Therefore, the voltage on either input must not exceed either supply rail by
more than 500 mV.
exceeded. (See Figure 2)
DC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Input Offset Voltage (VCM 0 V to 0.5 V, VCM 1.0 V to 5.0 V) 3 VIO mV
MC33201: TA = + 25°C – – 6.0
MC33201: TA = – 40° to +105°C – – 9.0
MC33201: TA = – 55° to +125°C – – 13
MC33202: TA = + 25°C – – 8.0
MC33202: TA = – 40° to +105°C – – 11
MC33202: TA = – 55° to +125°C – – 14
MC33204: TA = + 25°C – – 10
MC33204: TA = – 40° to +105°C – – 13
MC33204: TA = – 55° to +125°C – – 17
Input Offset Voltage Temperature Coefficient (RS = 50 Ω) 4 ∆VIO/∆T µV/°C
TA = – 40° to +105°C – 2.0 –
TA = – 55° to +125°C – 2.0 –
Input Bias Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V) 5, 6 IIB nA
TA = + 25°C – 80 200
TA = – 40° to +105°C – 100 250
TA = – 55° to +125°C – – 500
Input Offset Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V) – IIO nA
TA = + 25°C – 5.0 50
TA = – 40° to +105°C – 10 100
TA = – 55° to +125°C – – 200
Common Mode Input Voltage Range – VICR VEE – VCC V

MC33201 MC33202 MC33204
DC ELECTRICAL CHARACTERISTICS (continued) (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Large Signal Voltage Gain (VCC = + 5.0 V, VEE = – 5.0 V) 7 AVOL kV/V
RL = 10 kΩ 50 300 –
RL = 600 Ω 25 250 –
Output Voltage Swing (VID = ± 0.2 V) 8, 9, 10 V
RL = 10 kΩ VOH 4.85 4.95 –
RL = 10 kΩ VOL – 0.05 0.15
RL = 600 Ω VOH 4.75 4.85 –
RL = 600 Ω VOL – 0.15 0.25
Common Mode Rejection (Vin = 0 V to 5.0 V) 11 CMR 60 90 – dB

Power Supply Rejection Ratio 12 PSRR µV/V
VCC/VEE = 5.0 V/Gnd to 3.0 V/Gnd 500 25 –
Output Short Circuit Current (Source and Sink) 13, 14 ISC 50 80 – mA
Power Supply Current per Amplifier (VO = 0 V) 15 ID mA
TA = – 40° to +105°C – 0.9 1.125
TA = – 55° to +125°C – 0.9 1.125
AC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Slew Rate 16, 26 SR V/µs
(VS = ± 2.5 V, VO = – 2.0 V to + 2.0 V, RL = 2.0 kΩ, AV = +1.0) 0.5 1.0 –
Gain Bandwidth Product (f = 100 kHz) 17 GBW – 2.2 – MHz
Gain Margin (RL = 600 Ω, CL = 0 pF) 20, 21, 22 AM – 12 – dB
Phase Margin (RL = 600 Ω, CL = 0 pF) 20, 21, 22 OM – 65 – Deg
Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100) 23 CS – 90 – dB
Power Bandwidth (VO = 4.0 Vpp, RL = 600 Ω, THD ≤ 1 %) BWP – 28 – kHz
Total Harmonic Distortion (RL = 600 Ω, VO = 1.0 Vpp, AV = 1.0) 24 THD %
f = 1.0 kHz – 0.002 –
f = 10 kHz – 0.008 –
Open Loop Output Impedance ZO Ω
(VO = 0 V, f = 2.0 MHz, AV = 10) – 100 –
Differential Input Resistance (VCM = 0 V) Rin – 200 – kΩ
Differential Input Capacitance (VCM = 0 V) Cin – 8.0 – pF
Equivalent Input Noise Voltage (RS = 100 Ω) 25 en
nV/
f = 10 Hz – 25 –
f = 1.0 kHz Hz
– 20 –
Equivalent Input Noise Current 25 in
pA/
f = 10 Hz – 0.8 –
Hz
f = 1.0 kHz – 0.2 –

MC33201 MC33202 MC33204

(Each Amplifier)
VCC
VCC VEE
VCC
Vin –
Vout
VCC
Vin +
VEE
This device contains 70 active transistors (each amplifier).

MC33201 MC33202 MC33204

versus Temperature Figure 3. Input Offset Voltage Distribution
PD(max) , MAXIMUM POWER DISSIPATION (mW)
2500 40
360 amplifiers tested from

8 and 14 Pin DIP Pkg 35 3 (MC33204) wafer lots
2000 VCC = + 5.0 V
30 VEE = Gnd
TSSOP–14 Pkg TA = 25°C
1500 25 DIP Package
SO–14 Pkg
20
1000
15
SO–8 Pkg
10
500
5.0
0 0
– 55 – 40 – 25 0 25 50 85 125 –10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10
Figure 4. Input Offset Voltage Figure 5. Input Bias Current

Temperature Coefficient Distribution versus Temperature
50 200
360 amplifiers tested from VCC = + 5.0 V

3 (MC33204) wafer lots VEE = Gnd
40 VCC = + 5.0 V 160
VEE = Gnd
TA = 25°C
30 DIP Package 120
VCM = 0 V to 0.5 V
20 80
VCM > 1.0 V
10 40
0 0
– 50 – 40 – 30 – 20 –10 0 10 20 30 40 50 – 55 – 40 – 25 0 25 70 85 125
TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (µV/°C) TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Bias Current Figure 7. Open Loop Voltage Gain versus
versus Common Mode Voltage Temperature
150
A VOL , OPEN LOOP VOLTAGE GAIN (kV/V)
300
100
260
50
0 220
– 50
–100 180
VCC = + 5.0 V
–150 VCC = 12 V VEE = Gnd
140
VEE = Gnd RL = 600 Ω
– 200 TA = 25°C ∆VO = 0.5 V to 4.5 V
– 250 100
0 2.0 4.0 6.0 8.0 10 12 – 55 – 40 – 25 0 25 70 85 105 125
VCM, INPUT COMMON MODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

MC33201 MC33202 MC33204
Figure 8. Output Voltage Swing Figure 9. Output Saturation Voltage

12 VCC
VSAT, OUTPUT SATURATION VOLTAGE (V)

RL = 600 Ω TA = – 55°C
10 TA = 25°C TA = 125°C
VCC – 0.2 V
TA = 25°C
8.0
VCC – 0.4 V
6.0
VEE + 0.4 V
4.0 VCC = + 5.0 V
VEE = – 5.0 V TA = 25°C
2.0 VEE + 0.2 V
TA = 125°C
TA = – 55°C
0 VEE
±1.0 ± 2.0 ± 3.0 ± 4.0 ± 5.0 ± 6.0 0 5.0 10 15 20
VCC,VEE SUPPLY VOLTAGE (V) IL, LOAD CURRENT (mA)

12 100
80
9.0
60
6.0
VCC = + 6.0 V 40
VEE = – 6.0 V VCC = + 6.0 V
3.0 RL = 600 Ω VEE = – 6.0 V
AV = +1.0 20 TA = – 55° to +125°C
TA = 25°C
0 0
1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k 1.0 M
120 100
Source
100
80
PSR+
80
60
60 Sink
PSR– 40
40
VCC = + 6.0 V 20 VCC = + 6.0 V
20 VEE = – 6.0 V VEE = – 6.0 V
TA = – 55° to +125°C TA = 25°C
0 0
10 100 1.0 k 10 k 100 k 1.0 M 0 1.0 2.0 3.0 4.0 5.0 6.0
f, FREQUENCY (Hz) Vout, OUTPUT VOLTAGE (V)

MC33201 MC33202 MC33204
Figure 14. Output Short Circuit Current Figure 15. Supply Current per Amplifier
versus Temperature versus Supply Voltage with No Load
I CC , SUPPLY CURRENT PER AMPLIFIER (mA)

150 2.0
VCC = + 5.0 V
125 VEE = Gnd
1.6
100 TA = 125°C
Source 1.2
75 TA = 25°C
Sink
0.8
50 TA = – 55°C
25 0.4
0 0
– 55 – 40 – 25 0 25 70 85 105 125 ±0 ±1.0 ± 2.0 ± 3.0 ± 4.0 ± 5.0 ± 6.0
TA, AMBIENT TEMPERATURE (°C) VCC, VEE, SUPPLY VOLTAGE (V)

2.0 GBW, GAIN BANDWIDTH PRODUCT (MHz) 4.0
VCC = + 2.5 V VCC = + 2.5 V
VEE = – 2.5 V VEE = – 2.5 V
VO = ± 2.0 V f = 100 kHz
1.5 3.0
+Slew Rate
1.0 2.0
–Slew Rate
0.5 1.0
0 0
– 55 – 40 – 25 0 25 70 85 105 125 – 55 – 40 – 25 0 25 70 85 105 125
70 40 70 40
, OPEN LOOP VOLTAGE GAIN (dB)
VS = ± 6.0 V CL = 0 pF
TA = 25°C TA = 25°C
O , EXCESS PHASE (DEGREES)
O , EXCESS PHASE (DEGREES)

50 RL = 600 Ω 80 50 RL = 600 Ω 80
30 120 30 1 120
1 2 A
2 A A
10 A2 160 10 160
1
1A – Phase, CL = 0 pF B 1A – Phase, VS = ± 6.0 V B
1B – Gain, CL = 0 pF 2
–10 1 200 –10 1B – Gain, VS = ± 6.0 V 200
2A – Phase, CL = 300 pF B
2A – Phase, VS = ± 1.0 V
VOL
B
2B – Gain, CL = 300 pF 2B – Gain, VS = ± 1.0 V
A
– 30 240 – 30 240
10 k 100 k 1.0 M 10 M 10 k 100 k 1.0 M 10 M

MC33201 MC33202 MC33204
Figure 20. Gain and Phase Margin Figure 21. Gain and Phase Margin
70 70 75 75
Phase Margin Phase Margin
60 60
O M , PHASE MARGIN (DEGREES)

60 60
50 50
A , GAIN MARGIN (dB)

45 VCC = + 6.0 V 45
40 VCC = + 6.0 V 40 VEE = – 6.0 V
VEE = – 6.0 V
TA = 25°C
30 RL = 600 Ω 30
CL = 100 pF 30 30
20 20
M
15 Gain Margin 15
10 10
Gain Margin
0 0 0 0
– 55 – 40 – 25 0 25 70 85 105 125 10 100 1.0 k 10 k 100 k
Figure 22. Gain and Phase Margin Figure 23. Channel Separation
versus Capacitive Load versus Frequency
80 16 150
VCC = + 6.0 V
70 VEE = – 6.0 V 14
Phase Margin AV = 100

RL = 600 Ω 120
60 AV = 100 12
Gain Margin TA = 25°C

50 10 90
40 8.0
AV = 10
30 6.0 60
VCC = + 6.0 V
M
20 4.0 VEE = – 6.0 V

30
VO = 8.0 Vpp
10 2.0
TA = 25°C
0 0 0
10 100 1.0 k 100 1.0 k 10 k
CL, CAPACITIVE LOAD (pF) f, FREQUENCY (Hz)
Figure 24. Total Harmonic Distortion Figure 25. Equivalent Input Noise Voltage
en , EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)
versus Frequency and Current versus Frequency
i n , INPUT REFERRED NOISE CURRENT (pA/ Hz)

10 50 5.0
VCC = + 5.0 V VEE = – 5.0 V VCC = + 6.0 V

TA = 25°C RL = 600 Ω VEE = – 6.0 V
VO = 2.0 Vpp 40 TA = 25°C 4.0
1.0
AV = 1000 30 3.0
0.1 AV = 100
Noise Voltage
20 2.0
AV = 10
0.01
10 1.0
AV = 1.0 Noise Current
0.001 0 0
10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k

MC33201 MC33202 MC33204
General Information Circuit Information

The MC33201/2/4 family of operational amplifiers are Rail–to–rail performance is achieved at the input of the
unique in their ability to swing rail–to–rail on both the input amplifiers by using parallel NPN–PNP differential input
and the output with a completely bipolar design. This offers stages. When the inputs are within 800 mV of the negative
low noise, high output current capability and a wide common rail, the PNP stage is on. When the inputs are more than 800
mode input voltage range even with low supply voltages. mV greater than VEE, the NPN stage is on. This switching of
Operation is guaranteed over an extended temperature input pairs will cause a reversal of input bias currents (see
range and at supply voltages of 2.0 V, 3.3 V and 5.0 V and Figure 6). Also, slight differences in offset voltage may be
ground. noted between the NPN and PNP pairs. Cross–coupling
Since the common mode input voltage range extends from techniques have been used to keep this change to a
VCC to VEE, it can be operated with either single or split minimum.
voltage supplies. The MC33201/2/4 are guaranteed not to In addition to its rail–to–rail performance, the output stage
latch or phase reverse over the entire common mode range, is current boosted to provide 80 mA of output current,
however, the inputs should not be allowed to exceed enabling the op amp to drive 600 Ω loads. Because of this
maximum ratings. high output current capability, care should be taken not to
exceed the 150°C maximum junction temperature.
Figure 26. Noninverting Amplifier Slew Rate Figure 27. Small Signal Transient Response
VCC = + 6.0 V VCC = + 6.0 V

V , OUTPUT VOLTAGE (2.0 mV/DIV)
V , OUTPUT VOLTAGE (50 mV/DIV)

VEE = – 6.0 V VEE = – 6.0 V
RL = 600 Ω RL = 600 Ω
CL = 100 pF CL = 100 pF
TA = 25°C TA = 25°C
O
t, TIME (5.0 µs/DIV) t, TIME (10 µs/DIV)
Figure 28. Large Signal Transient Response
VCC = + 6.0 V
V , OUTPUT VOLTAGE (2.0 V/DIV)
VEE = – 6.0 V
RL = 600 Ω
CL = 100 pF
AV = 1.0
TA = 25°C
O
t, TIME (10 µs/DIV)

MC33206
MC33207
Advance Information
Rail-To-Rail Operational LOW VOLTAGE
Amplifiers with Enable RAIL–TO–RAIL
Feature SEMICONDUCTOR
TECHNICAL DATA
The MC33206/7 family of operational amplifiers provide rail–to–rail
operation on both the input and output. The inputs can be driven as high as
200 mV beyond the supply rails without phase reversal on the outputs and
the output can swing within 50 mV of each rail. This rail–to–rail operation MC33206
enables the user to make full use of the supply voltage range available. It is
designed to work at very low supply voltages (±0.9 V) yet can operate with a P SUFFIX
single supply of up to 12 V and ground. Output current boosting techniques PLASTIC PACKAGE
CASE 646
provide a high output current capability while keeping the drain current of the
14
amplifier to a minimum.
1
The MC33206/7 has an enable mode that can be controlled externally. D SUFFIX
The typical supply current in the standby mode is <1.0 µA (VEnable = Gnd). PLASTIC PACKAGE
14
The addition of an enable function makes this amplifier an ideal choice for CASE 751A
power sensitive applications, battery powered equipment (instrumentation and 1 (SO–14)
monitoring), portable telecommunication, and sample–and–hold applications.
N.C. 1 14 N.C.
• Standby Mode (ID ≤1.0 µA, Typ)
N.C. 2 13 VCC
• Low Voltage, Single Supply Operation Output 1 3 12 Output 2
(1.8 V and Ground to 12 V and Ground) 4 11
• Rail–to–Rail Input Common Mode Voltage Range 5 10
Enable 1 6 9
•
Enable 2
Output Voltage Swings within 50 mV of both Rails
VEE 7 8 N.C.
• No Phase Reversal on the Output for Over–Driven Input Signals
(Dual, Top View)
• High Output Current (ISC = 80 mA, Typ)
• Low Supply Current (ID = 0.9 mA, Typ) MC33207
• 600 Ω Output Drive Capability P SUFFIX

• Typical Gain Bandwidth Product = 2.2 MHz PLASTIC PACKAGE
CASE 648
16
1
D SUFFIX
ORDERING INFORMATION 16 PLASTIC PACKAGE
CASE 751B
Operational Operating
1 (SO–16)
Amplifier Function Device Temperature Range Package
MC33206D SO–14 Output 1 1 16 Enable 1, 4
Dual
MC33206P Plastic DIP 2 15 Output 4
TA= –40 ° to +105°C Inputs 1 1
3 14
MC33207D SO–16 4 Inputs 4
Quad VCC 4 13
5 12 VEE
Inputs 2 2
6 11
3 Inputs 3
Output 2 7 10
Enable 2, 3 8 9 Output 3
(Quad, Top View)

MC33206 MC33207
MAXIMUM RATINGS
Supply Voltage (VCC to VEE) VS 13 V
ESD Protection Voltage at any Pin VESD 2,000 V
Human Body Model
Voltage at any Device Pin VDP VS ± 0.5 V

Common Mode Input Voltage Range (Note 2) VCM VCC + 0.5 to V
VEE – 0.5
Output Short Circuit Duration (Note 3) ts (Note 3) sec
NOTES: 1. The differential input voltage of each amplifier is limited by two internal parallel back–to–back
diodes. For additional differential input voltage range, use current limiting resistors in series
with the input pins.
2. The common–mode input voltage range of each amplifier is limited by diodes connected from
the inputs to both power supply rails. Therefore, the voltage on either input must not exceed
either supply rail by more than 500 mV.
exceeded.
4. ESD data available upon request.
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = 0 V, VEnable = 5.0 V, TA = 25°C, unless otherwise noted.)
Input Offset Voltage (VCM 0 to 0.5 V, VCM 1.0 to 5.0 V) – VIO mV
MC33206: TA = 25°C – 0.5 8.0
MC33201: TA = –40° to +105°C – 1.0 11
MC33207: TA = 25°C – 0.5 10
MC33202: TA = –40° to +105°C – 1.0 13
Input Offset Voltage Temperature Coefficient (RS = 50 Ω) – ∆VIO/∆T – 2.0 – µV/°C

TA = –40° to +105°C
Input Bias Current (VCM = 0 to 0.5 V, VCM = 1.0 to 5.0 V) – IIB nA

TA = 25°C – 80 200
TA = –40° to +105°C – 100 250
Input Offset Current (VCM = 0 to 0.5 V, VCM = 1.0 to 5.0 V) – IIO nA
TA = 25°C – 5.0 50
TA = –40° to +105°C – 10 100
Common Mode Input Voltage Range – VICR – VCC + 0.2 VCC V
VEE VEE – 0.2 –
Large Signal Voltage Gain (VCC = 5.0 V, VEE = –5.0 V) – AVOL kV/V
RL = 10 kΩ 50 300 –
RL = 600 Ω 25 250 –
Output Voltage Swing (VID = ±0.2 V) – V
RL = 10 kΩ VOH 4.85 4.95 –
RL = 10 kΩ VOL – 0.05 0.15
RL = 600 Ω VOH 4.75 4.85 –
RL = 600 Ω VOL – 0.15 0.25
Common Mode Rejection (Vin = 0 to 5.0 V) – CMR 60 90 – dB

Power Supply Rejection Ratio – PSRR – 25 500 µV/V
VCC/VEE = 5.0 V/Gnd to 3.0 V/Gnd PSR 66 92 – dB
Output Short Circuit Current (Source and Sink) – ISC 50 80 – mA

MC33206 MC33207
DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 5.0 V, VEE = 0 V, VEnable = 5.0 V, TA = 25°C, unless otherwise noted.)
Power Supply Current (VO = 2.5 V, TA = –40° to +105°C, – ID
per Amplifier)
MC33206: VEnable = 5.0 Vdc – 0.8 1.125 mA
MC33206: VEnable = Gnd (Standby) – 0.5 6.0 µA
MC33207: VEnable = 5.0 Vdc – 1.5 2.25 mA
MC33207: VEnable = Gnd (Standby) – 0.5 6.0 µA
Enable Input Voltage (per Amplifier) – VEnable V
Enabled – Amplifier “On” – VEE + 1.8 –
Disabled – Amplifier “Off” (Standby) – VEE + 0.3 –
Enable Input Current (Note 5) (per Amplifier) – IEnable µA
VEnable = 12 V – 2.5 –
VEnable = 5.0 V – 2.2 –
VEnable = 1.8 V – 0.8 –
VEnable = Gnd – 0 –
NOTE: 5. External control circuitry must provide for an initial turn–off transient of <10 µA.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = 0 V, VEnable = 5.0 V, TA = 25°C, unless otherwise noted.)
Slew Rate (VS = ±2.5 V, VO = –2.0 to +2.0 V, – SR 0.5 1.0 – V/µs
RL = 2.0 kΩ, AV = 1.0)
Gain Bandwidth Product (f = 100 kHz) – GBW – 2.2 – MHz

Phase Margin (RL = 600 Ω, CL = 0 pF) – OM – 65 – Deg
Gain Margin (RL = 600 Ω, CL = 0 pF) – AM – 12 – dB
Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100) – CS – 90 – dB
Power Bandwidth (VO = 4.0 Vpp, RL = 600 Ω, THD ≤ 1%) – BWP – 28 – kHz
Total Harmonic Distortion (RL = 600 Ω, VO = 1.0 Vpp, AV = 1.0) – THD %
f = 1.0 kHz – 0.002 –
f = 10 kHz – 0.008 –
Open Loop Output Impedance – ZO – 100 – Ω
(VO = 0 V, f = 2.0 MHz, AV = 10)
Differential Input Resistance (VCM = 0 V) – Rin – 200 – kΩ

Differential Input Capacitance (VCM = 0 V) – Cin – 8.0 – pF
Equivalent Input Noise Voltage (RS = 100 Ω) – en nV/
f = 10 Hz – 25 – Hz
f = 1.0 kHz – 20 –
Equivalent Input Noise Current – in pA/
f = 10 Hz – 0.8 – Hz
f = 1.0 kHz – 0.2 –
Time Delay for Device to Turn On – ton – 10 – µs
Time Delay for Device to Turn Off – toff – 2.0 – µs

MC33206 MC33207
(Each Amplifier)
VCC
VCC
VCC VCC
Vin –
Enable
Vin +
VEE
This device contains 96 active transistors (each amplifier).

versus Temperature Figure 3. Input Offset Voltage Distribution
4000 40
360 amplifiers tested
3500 35 from 3 wafer lots

16 Pin DIP VCC = 5.0 V
3000 30 VEE = Gnd
TA = 25°C
2500 25 DIP Package
2000 20
14 Pin DIP
1500 15
1000 10
SO–14/SO–1
500 6 5.0
0 0
–60 –30 0 30 60 90 120 150 –10 –8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0 10

MC33206 MC33207
Figure 4. Input Offset Voltage Figure 5. Input Bias Current
Temperature Coefficient Distribution versus Temperature
50 200
360 amplifiers tested VCC = 5.0 V
VEE = Gnd

from 3 wafer lots
40 VCC = 5.0 V 160
VEE = Gnd
TA = 25°C
30 DIP Package 120
VCM = 0 V to 0.5 V
20 80
VCM > 1.0 V
10 40
0 0
–50 –40 –30 –20 –10 0 10 20 30 40 50 –55 –40 –25 0 25 70 85 125
TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (µV/°C) TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Bias Current Figure 7. Open Loop Voltage Gain

versus Common Mode Voltage versus Temperature
150 300
100 A VOL , OPEN LOOP VOLTAGE GAIN (kV/V)
260
50
0 220
–50
–100 180
VCC = 5.0 V
–150 VCC = 12 V VEE = Gnd
140
VEE = Gnd RL = 600 Ω
–200 TA = 25°C ∆VO = 0.5 V to 4.5 V
–250 100
0 2.0 4.0 6.0 8.0 10 12 –55 –40 –25 0 25 70 85 105 125
VCM, INPUT COMMON MODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

12 VCC
VSAT, OUTPUT SATURATION VOLTAGE (V)
RL = 600 Ω TA = –55°C
10 TA = 25°C
TA = 125°C VCC –
VO,OUTPUT VOLTAGE (Vpp)
TA = 25°C
8.0
VCC –
6.0
VEE +
4.0 VCC = 5.0 V
VEE = –5.0 V TA = 25°C
2.0 VEE +
TA = 125°C
TA = –55°C
0 VEE
±1.0 ±2.0 ±3.0 ±4.0 ±5.0 ±6.0 0 5.0 10 15 20
VCC,VEE SUPPLY VOLTAGE (V) IL, LOAD CURRENT (mA)

MC33206 MC33207
12 100

VO, OUTPUT VOLTAGE (Vpp)
80
9.0
60
6.0
VCC = 6.0 V 40
VEE = –6.0 V VCC = 6.0 V
3.0 RL = 600 Ω VEE = –6.0 V
AV = 1.0 20 TA = –55° to +125°C
TA = 25°C
0 0
1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k 1.0 M
ISC , OUTPUT SHORT CIRCUIT CURRENT (mA)

120 100
Source
100
80
PSR+
80
60
60 Sink
PSR– 40
40
VCC = 6.0 V 20 VCC = 6.0 V
20 VEE = –6.0 V VEE = –6.0 V
TA = –55° to +125°C TA = 25°C
0 0
10 100 1.0 k 10 k 100 k 1.0 M 0 1.0 2.0 3.0 4.0 5.0 6.0
f, FREQUENCY (Hz) Vout, OUTPUT VOLTAGE (V)
Figure 14. Output Short Circuit Current Figure 15. Supply Current per Amplifier
versus Temperature versus Supply Voltage with No Load
ISC , OUTPUT SHORT CIRCUIT CURRENT (mA)
I CC, SUPPLY CURRENT PER AMPLIFIER (mA)
150 2.0
VCC = 5.0 V
125 VEE = Gnd
1.6
100 TA = 125°C
Source 1.2
75 TA = 25°C
Sink
0.8
50 TA = –55°C
25 0.4
0 0
–55 –40 –25 0 25 70 85 105 125 ±0 ±1.0 ±2.0 ±3.0 ±4.0 ±5.0 ± .0
TA, AMBIENT TEMPERATURE (°C) VCC, VEE, SUPPLY VOLTAGE (V)

MC33206 MC33207
2.0 4.0

VCC = 2.5 V VCC = 2.5 V
VEE = –2.5 V VEE = –2.5 V
VO = ±2.0 V f = 100 kHz
1.5 3.0
+Slew Rate
1.0 2.0
–Slew Rate
0.5 1.0
0 0
–55 –40 –25 0 25 70 85 105 125 –55 –40 –25 0 25 70 85 105 125
70 40 70 40

VS = ±6.0 V
CL = 0 pF
TA = 25°C O , EXCESS PHASE (DEGREES) TA = 25°C
50 RL = 600 Ω 80 50 RL = 600 Ω 80
30 120 30 1A 120
1A 2A
2A
10 2B 160 10 160
1B
1A – Phase, CL = 0 pF 1A – Phase, VS = ±6.0 V
1B – Gain, CL = 0 pF 2B
–10 1B 200 –10 1B – Gain, VS = ±6.0 V 200
2A – Phase, CL = 300 pF 2A – Phase, VS = ±1.0 V
2B – Gain, CL = 300 pF 2B – Gain, VS = ±1.0 V
–30 240 –30 240
10 k 100 k 1.0 M 10 M 10 k 100 k 1.0 M 10 M
Figure 20. Gain and Phase Margin Figure 21. Gain and Phase Margin
70 70 75 75
Phase Margin Phase Margin
60 60
60 60
50 50
45 VCC = 6.0 V 45
40 VCC = 6.0 V 40 VEE = –6.0 V
VEE = –6.0 V
TA = 25°C
30 RL = 600 Ω 30
CL = 100 pF 30 30
20 20
M
15 Gain Margin 15
10 10
Gain Margin
0 0 0 0
–55 –40 –25 0 25 70 85 105 125 10 100 1.0 k 10 k 100 k

MC33206 MC33207
Figure 22. Gain and Phase Margin Figure 23. Output Voltage
versus Capacitive Load versus Load Resistance
80 16 5.0
VCC = 6.0 V
70 VEE = –6.0 V 14 VCC = 5.0 Vdc
Phase Margin
VO , OUTPUT VOLTAGE (Vpp)

RL = 600 Ω 4.0
60 AV = 100 12

Gain Margin TA = 25°C
50 10 3.0
40 8.0
30 6.0 2.0
VEE = Gnd VCC = 2.0 Vdc
M
20 4.0
1.0 CL = 0 pF
10 2.0 AV = 1.0
TA = 25°C
0 0 0
10 100 1.0 k 10 100 1.0 k 10 k 100 k
CL, CAPACITIVE LOAD (pF) RL, LOAD RESISTANCE

150 10

VCC = 5.0 V VEE = –5.0 V
TA = 25°C RL = 600 Ω
AV = 100
120 VO = 2.0 Vpp

1.0
90 AV = 1000
0.1 AV = 100
AV = 10
60
VCC = 6.0 V AV = 10
VEE = –6.0 V 0.01
30
VO = 8.0 Vpp
TA = 25°C AV = 1.0
0 0.001
100 1.0 k 10 k 10 100 1.0 k 10 k 100 k
Figure 26. Equivalent Input Noise Voltage

en , EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)
and Current versus Frequency

i n , INPUT REFERRED NOISE CURRENT (pA/ Hz)
50 5.0
VCC = 6.0 V
VEE = –6.0 V
40 TA = 25°C 4.0
30 3.0
Noise Voltage
20 2.0
10 1.0
Noise Current
0 0
10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz)

MC33206 MC33207
GENERAL INFORMATION Figure 28. ton Response

The MC33206/7 family of operational amplifiers are
unique in their ability to swing rail–to–rail on both the input
VO (1.0 V/DIV), V in (2.0 V/DIV)

and the output with a completely bipolar design. This offers
low noise, high output current capability and a wide common
mode input voltage range even with low supply voltages.
Operation is guaranteed over an extended temperature
range and at supply voltages of 2.0 V, 3.3 V and 5.0 V and
ground.
Since the common mode input voltage range extends from
VCC to VEE, it can be operated with either single or split
voltage supplies. The MC33206/7 are guaranteed not to latch
or phase reverse over the entire common mode range,
however, the inputs should not be allowed to exceed
maximum ratings. ton, TIME (2.0 µs/DIV)
CIRCUIT INFORMATION
Rail–to–rail performance is achieved at the input of the Figure 29. toff Response
amplifiers by using parallel NPN–PNP differential input
stages. When the inputs are within 800 mV of the negative
VO (1.0 V/DIV), V in (2.0 V/DIV)

rail, the PNP stage is on. When the inputs are more than
800 mV greater than VEE, the NPN stage is on. This
switching of input pairs will cause a reversal of input bias
currents (see Figure 6). Also, slight differences in offset
voltage may be noted between the NPN and PNP pairs.
Cross–coupling techniques have been used to keep this
change to a minimum.
In addition to its rail–to–rail performance, the output stage
is current boosted to provide 80 mA of output current,
enabling the op amp to drive 600 Ω loads. Because of this
high output current capability, care should be taken not to
exceed the 150°C maximum junction temperature. toff, TIME (2.0 µs/DIV)
Low Voltage Operation
Enable Function
The MC33206/07 will operate at supply voltages down to
The MC33206/07 enable pins allow the user to externally
1.8 V and ground. Since this device is a rail–to–rail on both
control the device. (Refer to the Pin Diagram on the first page
the input and output, one can be assured of continued
of this data sheet for enable pin connections.) If the enable
operation in battery applications when battery voltages drop
pins are pulled low (Gnd) each amplifier (MC33206) and
to low voltage levels. This is called End of Discharge (see
amplifier pair (MC33207) will be disabled. When the enable
Figure 30). Now, the user can select a minimum quantity of
pins are at a logic high (VEnable ≥ VEE = 1.8 V) the amplifiers
batteries best suited for the particular design depending on
will turn “on”. Refer to the data sheet characteristics for the
the type of battery chosen. This will minimize part count in
required levels needed to change logical state.
many designs.
The time to change states (from device “on” to “off” and
“off” to “on”) is defined as the time delay. The Circuit in Figure 30. Typical Battery Characteristics
Figure 27 is used to measure ton and toff. Typical ton and toff
Type Operating Voltage End of Discharge
measurements are shown in Figures 28 and 29. When the
device is turned off (VEnable = Gnd) an internal regulator is Alkaline 1.5 V 0.9 V
shut off disabling the amplifier. NiCd 1.2 V 1.0 V
NiMh 1.2 V 1.0 V
Figure 27. Test Circuit for ton and toff Silver Oxide 1.6 V 1.3 V
Lithium Ion 3.6 V 2.5 V
VCC
Compensating for Output Capacitance
The combination of device output impedance and
MC33206 Vout increasing capacitive loading will cause phase delay
ton toff
(reducing the phase margin) in any amplifier (Figure 22). If
2.0 V the loading is excessive, the resulting response can be circuit
2.0 k
oscillation. In other words, an amplifier can become unstable
VEnable when the phase becomes greater than 180 degrees before
ton toff the open loop gain drops to unity gain. Figures 18 and 19
show this situation as frequency increases for a given load.
The MC33206/7 can typically drive up to 300 pF loads at
unity gain without oscillating.

MC33206 MC33207
Figure 31. Capacitive Loads Compensation
Rf
CX
RO
CL
RL
Vin
There are several ways to compensate for this SPICE Model

phenomena. Adding series resistance to the output is one If a SPICE Macromodel is desired for the MC33206/07,
way, but not an ideal solution. A dc voltage error will occur at the user can define the characteristics from the following
the output. A better design solution to compensate for higher information. Obtain the SPICE Macromodel for the MC33204
capacitive loads would be to use the circuit in Figure 31. This Rail–to–Rail Operational Amplifier (device is the same as the
design helps to counteract the loss of phase margin by taking MC33207). For the Enable feature of the MC33207, simulate
the high frequency output signal and feeding it back into the it as a bipolar switch. The Macromodel does not include an
amplifier inverting input. This technique helps to overcome input capacitance between the inverting and noninverting
oscillation due to a highly capacitive load. Keep in mind that inputs. This capacitor is called Cin. Add 3.0 to 5.0 pF if
compensation will have the affect of lowering the Gain stability analysis is required.
Bandwidth Product (GPW). The values of CX and R0, are
determined experimentally. Typical CX and CL will be the
same value.
Figure 32. Noninverting Amplifier Slew Rate Figure 33. Small Signal Transient Response
VCC = 6.0 V VCC = 6.0 V

V , OUTPUT VOLTAGE (2.0 mV/DIV)
V , OUTPUT VOLTAGE (50 mV/DIV)
VEE = –6.0 V VEE = –6.0 V

RL = 600 Ω RL = 600 Ω
CL = 100 pF CL = 100 pF
TA = 25°C TA = 25°C
O
Figure 34. Large Signal Transient Response
VCC = 6.0 V
V , OUTPUT VOLTAGE (2.0 V/DIV)
VEE = –6.0 V
RL = 600 Ω
CL = 100 pF
AV = 1.0
TA = 25°C
O
t, TIME (10 µs/DIV)

MC33272A
MC33274A
Single Supply, High Slew Rate

HIGH PERFORMANCE
Low Input Offset Voltage,
OPERATIONAL
Bipolar Operational Amplifiers AMPLIFIERS
The MC33272/74 series of monolithic operational amplifiers are quality SEMICONDUCTOR
fabricated with innovative Bipolar design concepts. This dual and quad TECHNICAL DATA
operational amplifier series incorporates Bipolar inputs along with a patented
Zip–R–Trim element for input offset voltage reduction. The MC33272/74
series of operational amplifiers exhibits low input offset voltage and high gain
bandwidth product. Dual–doublet frequency compensation is used to DUAL
increase the slew rate while maintaining low input noise characteristics. Its
all NPN output stage exhibits no deadband crossover distortion, large output
voltage swing, and an excellent phase and gain margin. It also provides a 8
8
low open loop high frequency output impedance with symmetrical source 1 1
and sink AC frequency performance.
P SUFFIX D SUFFIX
The MC33272/74 series is specified over –40° to +85°C and are available PLASTIC PACKAGE PLASTIC PACKAGE
in plastic DIP and SOIC surface mount packages. CASE 626 CASE 751
• Input Offset Voltage Trimmed to 100 µV (Typ) (SO–8)
• Low Input Bias Current: 300 nA
• Low Input Offset Current: 3.0 nA
PIN CONNECTIONS
• High Input Resistance: 16 MΩ
• Low Noise: 18 nV/ √ Hz @ 1.0 kHz Output 1 1 8 VCC
• High Gain Bandwidth Product: 24 MHz @ 100 kHz
Inputs 1
2
–
7 Output 2
•
+
3 6
High Slew Rate: 10 V/µs –
+ Inputs 2
• VEE 4 5
Power Bandwidth: 160 kHz
• Excellent Frequency Stability (Top View)
• Unity Gain Stable: w/Capacitance Loads to 500 pF

• Large Output Voltage Swing: +14.1 V/ –14.6 V
• Low Total Harmonic Distortion: 0.003% QUAD
• Power Supply Drain Current: 2.15 mA per Amplifier
• Single or Split Supply Operation: +3.0 V to +36 V or ±1.5 V to ±18 V 14 14
• ESD Diodes Provide Added Protection to the Inputs 1 1
P SUFFIX D SUFFIX
ORDERING INFORMATION CASE 646 CASE 751A
Op Amp Operating (SO–14)
Function Device Temperature Range Package
PIN CONNECTIONS
Dual MC33272AD SO–8
MC33272AP Plastic DIP
TA = –40° to +85°C 2 13
Quad MC33274AD SO–14 Inputs 1 – –
Inputs 4
3 + 1 4 + 12
MC33274AP Plastic DIP
VCC 4 11 VEE
5 10
+ +
Inputs 2 – 2 3 – Inputs 3
6 9
(Top View)

MC33272A MC33274A
MAXIMUM RATINGS
Supply Voltage VCC to VEE +36 V
Input Offset Voltage (RS = 10 Ω, VCM = 0 V, VO = 0 V) 3 |VIO| mV
(VCC = +15 V, VEE = –15 V)
TA = +25°C — 0.1 1.0
TA = –40° to +85°C — — 1.8
(VCC = 5.0 V, VEE = 0)
TA = +25°C — — 2.0
Average Temperature Coefficient of Input Offset Voltage 3 ∆VIO/∆T µV/°C
RS = 10 Ω, VCM = 0 V, VO = 0 V, TA = –40° to +85°C — 2.0 —

TA = +25°C — 300 650
TA = –40° to +85°C — — 800
Input Offset Current (VCM = 0 V, VO = 0 V) |IIO| nA
TA = +25°C — 3.0 65
TA = –40° to +85°C — — 80
Common Mode Input Voltage Range (∆VIO = 5.0 mV, VO = 0 V) 6 VICR V
TA = +25°C VEE to (VCC –1.8)
Large Signal Voltage Gain (VO = 0 V to 10 V, RL = 2.0 kΩ) 7 AVOL dB

TA = +25°C 90 100 —
TA = –40° to +85°C 86 — —
(VCC = +15 V, VEE = –15 V)
RL = 2.0 kΩ VO + 13.4 13.9 —
RL = 2.0 kΩ VO – — –13.9 –13.5
RL = 10 kΩ VO + 13.4 14 —
RL = 10 kΩ VO – — –14.7 –14.1
(VCC = 5.0 V, VEE = 0 V) 10, 11
RL = 2.0 kΩ VOL — — 0.2
RL = 2.0 kΩ VOH 3.7 — 5.0
Common Mode Rejection (Vin = +13.2 V to –15 V) 13 CMR 80 100 — dB
Power Supply Rejection 14, 15 PSR dB
VCC/VEE = +15 V/ –15 V, +5.0 V/ –15 V, +15 V/ –5.0 V 80 105 —
Output Short Circuit Current (VID = 1.0 V, Output to Ground) 16 ISC mA

Source +25 +37 —
Sink –25 –37 —
Power Supply Current Per Amplifier (VO = 0 V) 17 ICC mA
(VCC = +15 V, VEE = –15 V)
TA = +25°C — 2.15 2.75
TA = –40° to +85°C — — 3.0
(VCC = 5.0 V, VEE = 0 V)
TA = +25°C — — 2.75

MC33272A MC33274A
Slew Rate 18, 33 SR 8.0 10 — V/µs
(Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 100 pF, AV = +1.0 V)
Gain Bandwidth Product (f = 100 kHz) 19 GBW 17 24 — MHz

AC Voltage Gain (RL = 2.0 kΩ, VO = 0 V, f = 20 kHz) 20, 21, 22 AVO — 65 — dB
Gain Margin (RL = 2.0 kΩ, CL = 0 pF) 23, 24, 26 Am — 12 — dB
Phase Margin (RL = 2.0 kΩ, CL = 0 pF) 23, 25, 26 φm — 55 — Degrees
Power Bandwidth (VO = 20 Vpp, RL = 2.0 kΩ, THD ≤ 1.0%) BWP — 160 — kHz
Total Harmonic Distortion 28 THD — 0.003 — %
(RL = 2.0 kΩ, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0)
Open Loop Output Impedance (VO = 0 V, f = 6.0 MHz) 29 |ZO| — 35 — Ω

Differential Input Resistance (VCM = 0 V) RIN — 16 — MΩ
Differential Input Capacitance (VCM = 0 V) CIN — 3.0 — pF
Equivalent Input Noise Voltage (RS = 100 Ω, f = 1.0 kHz) 30 en — 18 — nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz) 31 in — 0.5 — pA/ √ Hz
Figure 1. Equivalent Circuit Schematic

(Each Amplifier)
VCC
– +
Vin Vin
+
Sections VO
B C D
VEE

MC33272A MC33274A

versus Temperature Temperature for Typical Units
P D (MAX), MAXIMUM POWER DISSIPATION (mW)
2400 5.0

2000 VCC = +15 V
3.0
MC33272P & MC33274P VEE = –15 V
VCM = 0 V
1600
1.0 3
MC33274D 1
1200 2 2
1
–1.0 3
800 1. VIO > 0 @ 25°C
MC33272D
2. VIO = 0 @ 25°C
–3.0 3. VIO < 0 @ 25°C
400
0 –5.0
–60 –40 –20 0 20 40 60 80 100 120 140 160 180 –55 –25 0 25 50 75 100 125

400 600
350 VCC = +15 V
500
VEE = –15 V
300 VCM = 0 V
400
250
200 300
150
VCC = +15 V 200
100 VEE = –15 V
TA = 25°C 100
50
0 0
–16 –12 –8.0 –4.0 0 4.0 8.0 12 16 –55 –25 0 25 50 75 100 125
V ICR, INPUT COMMON MODE VOLTAGE RANGE (V)

A VOL, OPEN LOOP VOLTAGE GAIN (X 1.0 kV/V)
VCC 180
VCC –0.5 VCC
VCC –1.0 160

VCC –1.5
VCC –2.0 140
VCC = +15 V
VCC = +5.0 V to +18 V VEE = –15 V
VEE +1.0 120 RL = 2.0 kΩ
VEE = –5.0 V to –18 V
VEE ∆VIO = 5.0 mV f = 10 Hz
VEE +0.5 ∆VO = –10 V to +10 V
VO = 0 V
VEE 100
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125

MC33272A MC33274A
Figure 8. Split Supply Output Voltage Swing Figure 9. Split Supply Output Saturation
versus Supply Voltage Voltage versus Load Current

40 VCC
Source
TA = 25°C
VCC –1.0 TA = –55°C

30
RL = 10 kΩ TA = 125°C
VCC –2.0 TA = 25°C
20 RL = 2.0 kΩ
VEE +2.0 Sink TA = 25°C
TA = –55°C
10
VEE +1.0 TA = 125°C
VCC = +5.0 V to +18 V
VEE = –5.0 V to –18 V
0 VEE
0 5.0 10 15 20 0 5.0 10 15 20
VCC, VEE SUPPLY VOLTAGE (V) IL, LOAD CURRENT (±mA)
Figure 10. Single Supply Output Saturation Figure 11. Single Supply Output Saturation
Voltage versus Load Resistance to Ground Voltage versus Load Resistance to VCC
VCC 15
TA = 125°C V sat , OUTPUT SATURATION VOLTAGE (V)
VCC
VCC –4.0 14.6 TA = 125°C
TA = 55°C VCC = +5.0 V to +18 V
RL to Gnd TA = 25°C
VCC –8.0 14.2
VEE = Gnd
TA = 55°C
VCC –12
+0.2 8.0 TA = 25°C TA = 125°C VCC = +15 V

TA = 125°C RL to VCC
TA = +25°C TA = –55°C VEE = Gnd
+0.1 4.0
TA = –55°C RFdbk = 100 kΩ
Gnd
0 0
100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k
RL , LOAD RESISTANCE TO GROUND (kΩ) RL, LOAD RESISTANCE TO VCC (Ω)
Figure 13. Common Mode Rejection

Figure 12. Output Voltage versus Frequency versus Frequency
28 120
VCC = +15 V
24 100 VEE = –15 V
TA = –55°C VCM = 0 V
TA = 125°C
20
80 ∆VCM = ±1.5 V
16
60
12 VCC = +15 V –
VEE = –15 V ∆VCM ADM ∆VO
RL = 2.0 kΩ 40 +
8
AV = +1.0
∆VCM
4 THD = ≤1.0% 20 CMR = 20Log X ADM
TA = 25°C ∆VO
0 0
1.0 k 10 k 100 k 1.0 M 1 0M 10 100 1.0 k 10 k 100 k 1.0 M

MC33272A MC33274A
Figure 14. Positive Power Supply Rejection Figure 15. Negative Power Supply Rejection
120 120
+PSR, POWER SUPPLY REJECTION (dB)
–PSR, POWER SUPPLY REJECTION (dB)

TA = 125°C VCC = +15 V ∆VCC = ±1.5 V
VEE = –15 V VCC = +15 V
100 100
∆VCC = ±1.5 V VEE = –15 V
TA = –55°C
80 80
TA = –55°C
60 VCC 60 VCC
– –
40
ADM ∆VO 40
ADM ∆VO TA = 125°C
+ +
VEE VEE
20 ∆VO/ADM 20 ∆VO/ADM
+PSR = 20Log –PSR = 20Log
∆VCC ∆VEE
0 0
10 100 1.0 k 10 k 100 k 1 .0 M 10 100 1.0 k 10 k 100 k 1.0 M
60 11
VCC = +15 V
VEE = –15 V
I CC , SUPPLY CURRENT (mA) 10 TA = +125°C
50
VID = ±1.0 V 9.0
Sink RL < 100 Ω TA = +25°C
40 8.0
Source Sink TA = –55°C
30 7.0
Source 6.0
20
5.0
10
4.0
0 3.0
–55 –25 0 25 50 75 100 125 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
TA, AMBIENT TEMPERATURE (°C) VCC, |VEE| , SUPPLY VOLTAGE (V)
Figure 18. Normalized Slew Rate Figure 19. Gain Bandwidth Product
1.15 50
VCC = +15 V
– VEE = –15 V
1.1 VO
+ 40 f = 100 kHz
∆Vin 2.0 kΩ 100 pF RL = 2.0 kΩ
1.05 CL = 0 pF
30
1.0
VCC = +15 V 20
0.95 VEE = –15 V
∆Vin = 20 V
10
0.9
0.85 0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125

MC33272A MC33274A
Figure 20. Voltage Gain and Phase Figure 21. Gain and Phase
25 80 25 80
20 100 20 100

Gain
15 120 15 120
φ, PHASE (DEGREES)
1A

140 TA = 25°C 140
10 Phase 10
CL = 0 pF
5.0 160 5.0 160
0 180 0 2A 180
–5.0 VCC = +15 V 200 –5.0 1B 200
–10 VEE = –15 V 220 –10 1A — Phase V = 18 V, V = –18 V 220
RL = 2.0 kΩ CC EE
–15 TA = 25°C 240 –15 2A — Phase VCC = 1.5 V, VEE = –1.5 V 2B 240
1B — Gain VCC = 18 V, VEE = –18 V
–20 260 –20 2B — Gain V = 1.5 V, V = –1.5 V
CC EE
–25 280 –25
100 k 1.0 M 10 M 100 M 100 k 1.0 M 10 M 100 M
Figure 22. Open Loop Voltage Gain and Figure 23. Open Loop Gain Margin and Phase
Phase versus Frequency Margin versus Output Load Capacitance
20 100 12 0
120 Gain Margin

10 10
φ EXCESS PHASE (DEGREES)
10 140
1A VCC = +15 V
160 VEE = –15 V
2A 8.0 20
180 VO = 0 V
0
VCC = +15 V 6.0 – 30
VEE = –15 V 200
1B Vin VO
–10 Vout = 0 V 220 +
TA = 25°C 4.0 2.0 kΩ CL 40
240
1A — Phase (RL = 2.0 kΩ) 2B
–20 2A — Phase (RL = 2.0 kΩ, CL = 300 pF) 260
2.0 50
1B — Gain (RL = 2.0 kΩ) 280
2B — Gain (RL = 2.0 kΩ, CL = 300 pF) Phase Margin
–30 0
3.0 4.0 6.0 8.0 10 20 30 1.0 10 100 1000
f, FREQUENCY (MHz) CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 24. Open Loop Gain Margin

versus Temperature Figure 25. Phase Margin versus Temperature
12 60
CL = 10 pF
CL = 10 pF
φm, PHASE MARGIN (DEGREES)
10 50
CL = 100 pF
8.0 CL = 100 pF 40 CL = 300 pF
6.0 CL = 300 pF 30
CL = 500 pF
4.0 CL = 500 pF 20
2.0 VCC = +15 V

VCC = +15 V 10 VEE = –15 V
VEE = –15 V
0 0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125

MC33272A MC33274A
Figure 26. Phase Margin and Gain Margin Figure 27. Channel Separation
versus Differential Source Resistance versus Frequency
15 60 160
Gain Margin Driver Channel
CS, CHANNEL SEPERATION (dB)

12 50 150 VCC = +15 V
VEE = –15 V
Phase Margin
RL = 2.0 kΩ
9.0 40 140 ∆VOD = 20 Vpp
VCC = +15 V TA = 25°C
6.0 VEE = –15 V 30 130
RT = R1+R2
VO = 0 V
3.0 TA = 25°C 20 120
–
0 R1 VO 10 110
Vin +
R2
0 100
1.0 10 100 1.0 k 10 k 100 1.0 k 10 k 100 k 1.0 M
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω) f, FREQUENCY (Hz)

versus Frequency Figure 29. Output Impedance versus Frequency
1.0 50
AV = +1000 VCC = +15 V

|Z O |, OUTPUT IMPEDANCE ( Ω ) VEE = –15 V
AV = +100 40 VO = 0 V
TA = 25°C
0.1
30
AV = +10
AV = 1000
20
0.01
AV = +1.0 AV = 100
10 AV = 10 AV = 1.0
VO = 2.0 Vpp VCC = +15 V
TA = 25°C VEE = –15 V
0.001 0
10 100 1.0 k 10 k 100 k 10 k 100 k 1.0 M 10 M
Figure 30. Input Referred Noise Voltage Figure 31. Input Referred Noise Current
i n , INPUT REFERRED NOISE CURRENT ( pA/ √ Hz )
50 2.0
Input Noise Current Circuit
+ 1.8
40 VO 1.6 +
– RS VO
1.4 –
30 Input Noise Voltage 1.2

Test Circuit (RS = 10 kΩ)
1.0
20 0.8
0.6
VCC = +15 V
10 0.4 VCC = +15 V
VEE = –15 V
VEE = –15 V
TA = 25°C 0.2 TA = 25°C
0 0
10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k

MC33272A MC33274A
Figure 32. Percent Overshoot versus

Load Capacitance
60
VCC = +15 V
VEE = –15 V
50

RL = 2.0 kΩ
TA = 25°C
40
30
20
10
0
10 100 1.0 k
Figure 33. Noninverting Amplifier Slew Rate Figure 34. Noninverting Amplifier Overshoot
for the MC33274 for the MC33274

VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 kΩ CL = 100 pF
CL = 100 pF
TA = 25°C
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 kΩ
TA = 25°C CL = φ
t, TIME (2.0 µs/DIV) t, TIME (2.0 ns/DIV)
for MC33274 for MC33274
VCC = +15 V
V O, OUTPUT VOLTAGE (50 mV/DIV)
VCC = +15 V
VEE = –15 V
VEE = –15 V AV = +1.0
AV = +1.0 RL = 2.0 kΩ
RL = 2.0 kΩ CL = 300 pF
CL = 300 pF TA = 25°C
TA = 25°C

MC33282
MC33284
Low Input Offset, High Slew

HIGH PERFORMANCE
Rate, Wide Bandwidth, JFET
Input Operational Amplifiers
The MC33282/284 series of high performance operational amplifiers are SEMICONDUCTOR
quality fabricated with innovative bipolar and JFET design concepts. This TECHNICAL DATA
dual and quad amplifier series incorporates JFET inputs along with a
patented Zip–R–Trim element for input offset voltage reduction. These
devices exhibit low input offset voltage, low input bias current, high gain
bandwidth and high slew rate. Dual–doublet frequency compensation is DUAL
incorporated to produce high quality phase/gain performance. In addition,
8
the MC33282/284 series exhibit low input noise characteristics for JFET 8 1
input amplifiers. Its all NPN output stage exhibits no deadband crossover 1
D SUFFIX
distortion and a large output voltage swing. They also provide a low open P SUFFIX PLASTIC PACKAGE
loop high frequency output impedance with symmetrical source and sink AC PLASTIC PACKAGE CASE 751
frequency performance. CASE 626 (SO–8)
The MC33282/284 series are specified over –40° to +85°C and are
available in plastic DIP and SOIC surface mount packages. PIN CONNECTIONS
• Low Input Offset Voltage: Trimmed to 200 µV
• Low Input Bias Current: 30 pA Output 1 1 8 VCC
• Low Input Offset Current: 6.0 pA
2 7 Output 2
• High Input Resistance: 1012 Ω Inputs 1
–
1
+
• Low Noise: 18 nV √ Hz @ 1.0 kHz 3 – 6
Inputs 2
• High Gain Bandwidth Products: 35 MHz @ 100 kHz
VEE 4
2
+ 5
• High Slew Rate: 15 V/µs
• Power Bandwidth: 175 kHz (Top View)
• Unity Gain Stable: w/Capacitance Loads to 300 pF

• Large Output Voltage Swing: +14.1 V/–14.6 V QUAD
• Power Supply Drain Current: 2.15 mA per Amplifier 14
1
• Dual Supply Operation: ± 2.5 V to ±18 V (Max) 14
D SUFFIX
1
PLASTIC PACKAGE
P SUFFIX CASE 751A
PLASTIC PACKAGE (SO–14)
CASE 646
PIN CONNECTIONS
Op Amp Operating 2 – – 13
Function Device Temperature Range Package Inputs 1 1 4 Inputs 4
3 + + 12
MC33282D SOP–8
Dual VCC 4 11 VEE
TA = –40° to +85°C 5 10
MC33284D SO–14 + +
Quad Inputs 2 2 3 Inputs 3
6 – – 9
Zip–R–Trim is a registered trademark of Motorola Inc. Output 2 7 8 Output 3
(Top View)

MC33282 MC33284
MAXIMUM RATINGS
Characteristics Symbol Figure Min Typ Max Unit
Input Offset Voltage (RS = 10 Ω, VCM = 0 V, VO = 0 V) |VIO| 3 mV
TA = +25°C — 0.2 2.0
TA = –40° to +85°C — — 4.0
Average Temperature Coefficient of Input Offset Voltage |∆VIO|/∆T 3 µV/°C
RS = 10 Ω, VCM = 0 V, VO = 0 V, TA = Tlow to Thigh — 15 —
Input Bias Current (VCM = 0 V, VO = 0 V) IIB 4, 5

TA = +25°C –200 30 200 pA
TA = –40° to +85°C –2.0 — 2.0 nA
TA = +25°C –100 6.0 100 pA
TA = –40° to +85°C –1.0 — 1.0 nA
Common Mode Input Voltage Range VICR 6 –11 –12 — V
(∆VIO = 5.0 mV, VO = 0 V) — +14 +11
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kΩ) AVOL 7 V/mV
TA = +25°C 50 200 —
TA = –40° to +85°C 25 — —
RL = 2.0 kΩ VO + 13.2 +13.7 —
RL = 2.0 kΩ VO – — –13.9 –13.2
RL = 10 kΩ VO + 13.7 +14.1 —
RL = 10 kΩ VO – — –14.6 –14.3
Common Mode Rejection (Vin = ±11 V) CMR 11 70 90 — dB
Power Supply Rejection PSR 12 dB
VCC/VEE = +15 V/–15 V, +5.0 V/–15 V, +15 V/–5.0 V 75 100 —
Output Short Circuit Current (VID = 1.0 V, output to ground) ISC 13, 14 mA
Source 15 +21 —
Sink — –27 –15
Power Supply Current (VO = 0 V, per amplifier) ID 15 mA
TA = +25°C — 2.15 2.75
TA = –40° to +85°C — — 3.0

MC33282 MC33284
Characteristics Symbol Figure Min Typ Unit
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 100 pF, AV = +1.0) SR 16, 28, 29 8.0 15 V/µs
Gain Bandwidth Product (f = 100 kHz) GBW 17 20 35 MHz
AC Voltage Gain (RL = 2.0 kΩ, VO = 0 V, f = 20 kHz) AVO 18, 21 — 1750 V/V
Unity Gain Frequency (Open Loop) fU — 5.5 MHz
Gain Margin (RL = 2.0 kΩ, CL = 0 pF) Am 19, 20 — 15 dB
Phase Margin (RL = 2.0 kΩ, CL = 0 pF) φm 19, 20 — 40 Degrees
Channel Separation (f = 20 Hz to 20 kHz) CS 22 — –120 dB
Power Bandwidth (VO = 20 Vpp, RL = 2.0 kΩ, THD ≤ 1.0%) BWP — 175 kHz
Distortion (RL = 2.0 kΩ, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0) THD 23 — 0.003 %
Open Loop Output Impedance (VO = 0 V, f = 9.0 MHz) |ZO| 24 — 37 Ω
Differential Input Resistance (VCM = 0 V) Rin — 1012 Ω
Differential Input Capacitance (VCM = 0 V) Cin — 5.0 pF
Equivalent Input Noise Voltage (RS = 100 Ω, f = 1.0 kHz) en 25 — 18 nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz) in — 0.01 pA/ √ Hz
Figure 1. Equivalent Circuit Schematic

(Each Amplifier)
VCC
D1 R2 R3 R6 R10 R13
Q15
Q8
D2 D3 Q17
C1 J3 J4 C3
+
Q5
Vin Q11 Vin
J2 J5 D4
C4 R16
Q9
Q18
C5
J1 C6
R17
Q10
A B C D Q7
Q13 D5
VO
Q6 Q12
Q4
Q16
Q14
R5
R12
Q1 Q2 Q3 R4 R15
Z1 C2 R8 R13
R1
VEE

MC33282 MC33284

PD (max), MAXIMUM POWER DISSIPATION (mW) versus Temperature Temperature for Typical Units
2400 5.0
VCC = +15 V
VIO , INPUT OFFSET VOLTAGE (mV)

VEE = –15 V
2000 RS = 10 Ω
MC33282P & MC33284P 3.0
VCM = 0 V
Unit 3
1600 Unit 1
1.0
1200 MC33284D Unit 2 Unit 2
–1.0
800 MC33282D Unit 3 Unit 1
–3.0
400
0 –5.0
–60 –40 –20 0 20 40 60 80 100 120 140 160 180 –55 –25 0 25 50 75 100 125
Figure 4. Input Bias Current Figure 5. Input Bias Current versus

versus Temperature Common Mode Voltage
400 600
350 IIB, INPUT BIAS CURRENT (pA)

IIB, INPUT BIAS CURRENT (pA)
500 VCC = +15 V

300 VEE = –15 V
400 TA = 25°C
250
200 300
150 VCC, VEE = ±2.5 V

200
100
100
50
VCC, VEE = ±15 V
0 0
–55 –25 0 25 50 75 100 125 –15 –12 –9.0 –6.0 –3.0 0 3.0 6.0 9.0 12 15
TA, AMBIENT TEMPERATURE (°C) VCM, COMMON MODE VOLTAGE (V)
VICR , INPUT COMMON MODE VOLTAGE RANGE (V)

VCC 150
VCC = +5.0 V to +18 V VCC = +15 V

VCC–0.5 V
VEE = –5.0 V to –18 V VEE = –15V
140 RL = 2.0 kΩ
VCC–1.0 V ∆VIO = 5.0 mV
VO = 0 V f = 10 Hz
VCC–1.5 V ∆VO = 10 V to +10 V
130
VEE+1.5 V 120
VEE+1.0 V
110
VEE+0.5 V
VEE 100
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125

MC33282 MC33284
Figure 8. Output Voltage Swing Figure 9. Output Voltage

versus Supply Voltage versus Frequency
40 30
36 27

32 TA = 25°C 24
28 21
24 18
RL = 10 k
20 15 VCC = +15 V
16 RL = 2.0 k 12 VEE = –15 V
RL = 2.0 kΩ
12 9.0 AV = +1.0
8.0 6.0 THD = ≤ 1.0%
TA = 25°C
4.0 3.0
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 1.0 k 10 k 100 k 1.0 M
VCC, VEE SUPPLY VOLTAGE (V) f, FREQUENCY (Hz)
Figure 10. Output Saturation Voltage Figure 11. Common Mode Rejection
versus Load Current versus Frequency
VCC
120
TA = –55°C VCC = +15 V
VEE = –15 V
VCC–4.0 V VCC = +15 V 100
VCM = 0 V
RL to Gnd ∆VCM = ±1.5 V
VEE = –15 V TA = 125°C 80
VCC–8.0 V
TA = +25°C
VCC–12 V 60
–
∆VCM ADM ∆VO
+
VEE+4.0 V TA = 125°C 40
∆VCM
CMR = 20Logǒ
MVMNI
VEE+2.0 V 20 ∆VO DM Ǔ
x Axmi
MMM
TA = –55°C TA = +25°C
VEE 0
2.0 4.0 6.0 8.0 10 12 14 16 18 20 10 100 1.0 k 10 k 100 k 1.0 M
IL, LOAD CURRENT (mA) f, FREQUENCY (Hz)
Figure 12. Positive Power Supply Figure 13. Output Short Circuit Source
Rejection versus Frequency Current versus Temperature
|ISC|, OUTPUT SHORT CIRCUIT CURRENT (mA)
120
+PSR, POWER SUPPLY REJECTION (dB)
50
VID = ±1.0 V
PSR+
45 RL < 100 Ω
100
40
PSR– 35
80
30 VCC, VEE = ±15 V
60 VCC 25
–
ADM ∆VO 20
40 +
VEE VCC = +15 V 15
VEE = –15 V
10 VCC, VEE = ±2.5 V
20 ∆VO/ADM
MMNI ∆VCC = ±1.5 V
+PSR = 20Lo ǒ Ǔ
∆VCC
TA = 25°C 5.0
g MMM
0 0
10 100 1.0 k 10 k 100 k 1.0 M –55 –25 0 25 50 75 100 125

MC33282 MC33284
Figure 14. Output Short Circuit Sink Figure 15. Power Supply Current
|ISC |, OUTPUT SHORT CIRCUIT CURRENT (mA) Current versus Temperature versus Supply Voltage
50 3.0
VID = ±1.0 V
ID , POWER SUPPLY CURRENT (mA)

45 RL < 100 Ω VCC, VEE = ±15 V
2.5
40 VCC, VEE = ±15 V
35
2.0
30
25 1.5
20 VCC, VEE = ±2.5 V VCC, VEE = ±2.5 V
15 1.0
10
0.5
5.0
0 0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125


16 50
VCC = +15 V
14 Inverting Amplifier VEE = –15 V
40 f = 100 kHz
SR, SLEW RATE (V/µs)
12 Noninverting Amplifier RL = 2 kΩ
CL = 0 pF
10 30
8.0
6.0 VCC = +15 V 20
VEE = –15 V
4.0 ∆Vin = 20 V
CL = 100 pF 10
2.0 RL = 2.0 kΩ
0 0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
Figure 18. Gain and Phase Figure 19. Phase Margin and Gain Margin
versus Frequency versus Differential Source Resistance
50 80 20 50
TA = 25°C R1
40 CL = 0 pF 100 φ m , PHASE MARGIN (DEGREES)
Phase Margin Vin – VO
120 +
30 16 R2 40
A m, GAIN MARGIN (dB)

φ , PHASE (DEGREES)
20 140
1A
10 160 12 30
2A
0 1B 180 Gain Margin
–10 200 8.0 VCC = +15 V 20
2B VEE = –15 V
–20 220
1A) Phase VCC = 18 V, VEE = –18 V RT = R1 + R2
–30 2A) Phase VCC = 1.5 V, VEE = –1.5 V 240 4.0 VO = 0 V 10
TA = 25°C
–40 1B) Gain VCC = 18 V, VEE = –18 V 260
2B) Gain VCC = 1.5 V, VEE = –1.5 V
–50 0 0
100 k 1.0 M 10 M 100 M 10 100 1.0 k 10 k
f, FREQUENCY (Hz) RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)

MC33282 MC33284
Figure 20. Open Loop Gain and Phase Figure 21. Gain and Phase
Margin versus Output Load Capacitance versus Frequency
12 0 50 80
TA = 25°C
A m, OPEN LOOP GAIN MARGIN (dB)
100

40 CL = 0 pF
10 Gain Margin 10
30 Phase 120
φ, PHASE (DEGREES)
20 140
8.0 20 1A
10 Gain 160
2A
6.0 30 0 180
Phase Margin VCC = 15 V
–10 VEE = –15 V 1B 200
4.0 40 1A) Phase, VO = 10 V
–20 220
Vin +– 2A) Phase, VO = –10 V 2B
VO VCC = +15 V –30 240
2.0 VEE = –15 V 50 1B) Gain, VO = 10 V
2.0 kΩ CL 2B) Gain, VO = –10 V
VO = 0 V –40
0 60 –50
10 50 100 500 1.0 k 100 k 1.0 M 10 M 100 M


160 1.0
VCC = +15 V
AV = +1000
VEE = –15 V
150 VO = 2 Vpp
TA = 25°C
140 0.1
AV = +100
130
Drive Channel
VCC = +15 V 0.01
120 VEE = –15 V AV = +10
RL = 2.0 kΩ
110 ∆VOD = 20 Vpp
TA = 25°C AV = +1.0
100 0.001
100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k
Figure 24. Output Impedance Figure 25. Input Referred Noise Voltage
e n , INPUT REFERRED NOISE VOLTAGE (nV/√ Hz)
100 50
90 VCC = +15 V
VEE = –15 V Input Noise Voltage Test Circuit
|zo |, OUTPUT IMPEDANCE ( Ω )
80 VO = 0 V 40 +
– VO
70 TA = 25°C
2.0k
60 AV = 10 30 200 200
50
AV = 100
40 20
AV = 1000
30
20 10 VCC = +15 V
10 VEE = –15 V
AV = 1.0 TA = 25° C
0 0
10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k

MC33282 MC33284
Figure 26. Percent Overshoot versus Figure 27. Noninverting

Load Capacitance Amplifier Overshoot
100
VCC = +15 V
VO, OUTPUT VOLTAGE (50 MV/DIV)

90
VEE = –15 V
80 RL = 2.0 k
70 TA = 25° C
60
50
40
30
20
10
0
10 100 1.0 k t, TIME (1.0 µS/DIV)
Figure 28. Noninverting Figure 29. Inverting

Amplifier Slew Rate Amplifier Slew Rate
VO, OUTPUT VOLTAGE (5.0 V/DIV)
t, TIME (1.0 µS/DIV) t, TIME (1.0 µS/DIV)

v
MC33304
Low Voltage Rail-To-Rail
Sleep-Mode Operational t
Amplifier RAIL–TO–RAIL SLEEP–MODE
The MC33304 is a monolithic bipolar operational amplifier. This low OPERATIONAL AMPLIFIER
voltage rail–to–rail amplifier has both a rail–to–rail input and output stage,
with high output current capability. This amplifier also employs Sleep–Mode
SEMICONDUCTOR
technology. In sleepmode, the micropower amplifier is active and waiting for
TECHNICAL DATA
an input signal. When a signal is applied, causing the amplifier to source or
sink ≥200 µA (typically) to the load, it will automatically switch to the
awakemode (supplying up to 70 mA to the load). When the output current
drops below 90 µA, the amplifier automatically returns to the sleepmode.
Excellent performance can be achieved as an audio amplifier. This is due
to the amplifier’s low noise and low distortion. A delay circuit is incorporated
to prevent crossover distortion.
• Ideal for Battery Applications P SUFFIX
PLASTIC PACKAGE
• Full Output Signal (No Distortion) for Battery Applications Down 14 CASE 646
to ±0.9 VDC. 1
• Single Supply Operation (+1.8 to +12 V)
• Rail–To–Rail Performance on Both the Input and Output
• Output Voltages Swings Typically within 100 mV of Both Rails
(RL = 1.0 mΩ) D SUFFIX
• Two States: “Sleepmode” (Micropower, ID = 110 µA/Amp) and 14
PLASTIC PACKAGE
“Awakemode” (High Performance, ID = 1200 µA/Amp) 1
CASE 751A
(SO–14)
• Automatic Return to Sleepmode when Output Current Drops Below
Threshold, Allowing a Fully Functional Micropower Amplifier
• Independent Sleepmode Function for Each Amplifier
• No Phase Reversal on the Output for Overdriven Input Signals
• High Output Current (70 mA typically) PIN CONNECTIONS
• 600 Ω Drive Capability
• Standard Pinouts; No Additional Pins or Components Required
• Drop–In Replacement for Many Other Quad Operational Amplifiers
• Similar to MC33201, MC33202 and MC33204 Family 2

1 4
13
• The MC33304 Amplifier is Offered in the Plastic DIP or SOIC Package
Inputs 1
3 12
Inputs 4
(P and D Suffixes)
VCC 4 11 VEE
TYPICAL DC ELECTRICAL CHARACTERISTICS (TA = 25°C) 5 10

Characteristic VCC = 2.0 V VCC = 3.3 V VCC = 5.0 V Unit 6 9
Input Offset Voltage mV
VIO(max)
MC33304 ±10 ±10 ±10
Output Voltage Swing (Quad, Top View)
VOH (RL = 600 Ω) 1.85 3.10 4.75 Vmin
VOL (RL = 600 Ω) 0.15 0.15 0.15 Vmax
Power Supply Current ORDERING INFORMATION
per Amplifier (ID)
Operating
Awakemode 1.625 1.625 1.625 mA Device Temperature Range Package
Sleepmode 140 140 140 µA
Specifications are for reference only and not necessarily guaranteed. VEE = Gnd. MC33304D SO–14
TA = – 40° to +105°C

MC33304
MAXIMUM RATINGS
ESD Protection Voltage at Any Pin VESD V
Human Body Model 2000
Voltage at Any Device Pin (Note 2) VDP VS ± 0.5 V

Input Differential Voltage Range VIDR (Notes 1 & 2) V
Output Short Circuit Duration ts Indefinite sec
(Note 3)

RECOMMENDED OPERATING CONDITIONS

Supply Voltage VS V
Single Supply 1.8 – 12
Split Supplies ±0.9 – ±6.0
Input Voltage Range, Sleepmode and Awakemode VICR VEE – VCC V
Ambient Operating Temperature Range TA –40 – +105 °C
DC ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
Input Offset Voltage (VCM = 0 V, VO = 0 V) (Note 4) VIO mV
Sleepmode and Awakemode
TA = 25°C –10 0.7 +10
TA = –40° to +105°C –13 – +13
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T µV/°C
(RS = 50 Ω, VCM = 0 V, VO = 0 V)
TA = –40° to +105°C, Sleepmode and Awakemode – 2.0 –
Input Bias Current (VCM = 0 V, VO = 0 V) (Note 4)  IIB| nA
Awakemode
TA = 25°C – 90 +200
TA = –40° to +105°C – – +500
Input Offset Current (VCM = 0 V, VO = 0 V) (Note 4) |IIO| nA
Awakemode
TA = 25°C – 3.1 +50
TA = –40° to +105°C – – +100
Large Signal Voltage Gain (VCC = +5.0 V, VEE = –5.0 V) AVOL dB
Awakemode, RL = 600 Ω
TA = 25°C 90 116 –
TA = –40° to +105°C 85 – –
Power Supply Rejection Ratio, Awakemode PSRR 65 90 – dB
Output Short Circuit Current (Awakemode) ISC mA
(VID = ±0.2 V)
Source –200 –89 –50
Sink +50 +89 +200
Output Transition Current, Source/Sink µA
Sleepmode to Awakemode, VCC = +1.0 V, VEE = –1.0 V |ITH1| – – 200
Awakemode to Sleepmode, VCC = +5.0 V, VEE –5.0 V |ITH2| 90 – –

MC33304
DC ELECTRICAL CHARACTERISTICS (continued) (VCC = +5.0 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
Output Voltage Swing (VID = ±0.2 V) V
Sleepmode
VCC = +5.0 V, VEE = 0 V, RL = 1.0 MΩ VOH 4.90 4.97 –
VCC = 0 V, VEE = –5.0 V, RL = 1.0 MΩ VOL – –4.96 –4.90
VCC = +2.0 V, VEE = 0 V, RL = 1.0 MΩ VOH 1.90 1.98 –
VCC = 0 V, VEE = –2.0 V, RL = 1.0 MΩ VOL – –1.97 –1.90
Awakemode
VCC = +5.0 V, VEE = 0 V, RL = 600 Ω VOH 4.75 4.86 –
VCC = 0 V, VEE = –5.0 V, RL = 600 Ω VOL – –4.85 –4.75
VCC = +2.0 V, VEE = 0 V, RL = 600 Ω VOH 1.85 1.91 –
VCC = 0 V, VEE = –2.0 V, RL = 600 Ω VOL – –1.90 –1.85
VCC = +2.5 V, VEE = –2.5 V, RL = 600 Ω VOH – 2.41 –
VCC = +2.5 V, VEE = –2.5 V, RL = 600 Ω VOL – –2.40 –
Common Mode Rejection Ratio CMRR 60 90 – dB
Power Supply Current (per Amplifier) ID µA
Sleepmode
VCC = +2.0 V, VEE = 0 V TA = +25°C – 85 –
VCC = +2.5 V, VEE = –2.5 V TA = +25°C – 110 140
TA = –40° to +105°C – – 150
VCC = +12 V, VEE = 0 V TA = +25°C – 125 –
Awakemode
VCC = +2.5 V, VEE = –2.5 V TA = +25°C – 1200 1625
TA = –40° to +105°C – – 1750
Thermal Resistance θJA °C/W
SOIC – 145 –
Plastic DIP – 75 –
AC ELECTRICAL CHARACTERISTICS (VCC = +6.0 V, VEE = –6.0 V, RL = 600 Ω, TA = 25°C, unless otherwise noted.)
Slew Rate (VCC = +2.5 V, VEE = –2.5 V, AV = +1.0) (Note 6) SR V/µs
Awakemode 0.5 0.89 –
Gain Bandwidth Product (f = 100 kHz) GBW MHz

Awakemode – 2.2 –
Gain Margin (CL = 0 pF) Am dB

Sleepmode (RL = 1.0 kΩ) – 9.0 –
Phase Margin (RL = 1.0 kΩ, VO = 0 V, CL = 0 pF) φm Deg
Awakemode – 40 –
Sleepmode – 60 –
Sleepmode to Awakemode Transition Time ttr1 µsec
RL = 600 Ω – 4.0 –
RL = 10 k – 12 –
Awakemode to Sleepmode Transition Time ttr2 – 1.5 – sec
Channel Separation (f = 1.0 kHz) CS dB
NOTES: 1. The differential input voltage of each amplifier is limited by two internal diodes. The diodes are connected across the inputs in parallel and opposite to
each other. For more differential input voltage range, use current limiting resistors in series with the input pins.
2. The common–mode input voltage range of each amplifier is limited by diodes connected from the inputs to both power supply rails. Therefore, the
voltage on either input must not exceed supply rail by more than ±500 mV.
3. Simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratings and cause eventual
failure of the device.
4. Rail–to–rail performance is achieved at the input of the amplifier by using parallel NPN–PNP differential stages. When the inputs are near the
negative rail (VEE < VCM < 800 mV), the PNP stage is on. When the inputs are above 800 mV (i.e. 800 mV < VCM < VCC), the NPN stage is on.
This switching of the input pairs will cause a reversal of input bias current. Slight changes in the input offset voltage will be noted between the NPN
and PNP pairs. Cross–coupling techniques have been used to keep this change to a minimum.
5. Power dissipation must be considered to ensure maximum junction (TJ) is not exceeded. (See Figure 2)
6. When connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the
inverting input. This is because of the back to back diodes clamped across the inputs. The value of this resistor should be between 1.0 kΩ and
10 kΩ. If the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary.
(The output could be tied directly to the negative input.)

MC33304
AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +6.0 V, VEE = –6.0 V, RL = 600 Ω, TA = 25°C, unless otherwise noted.)
Power Bandwidth (VO = 4.0 Vpp, RL = 2.0 kΩ, THD ≤ 1.0%) BWp kHz
Distortion (VO = 2.0 Vpp, AV = +1.0) THD %

Awakemode (f = 10 kHz) – 0.009 –
Sleepmode (f = 1.0 kHz, RL = Infinite) – 0.007 –
Open Loop Output Impedance |ZO| Ω
(VO = 0 V, f = 2.0 MHz, AV = +10, IQ = 10 µA)
Differential Input Impedance (VCM = 0 V) RIN kΩ
Differential Input Capacitance (VCM = 0 V) CIN pF
Sleepmode – 0.4 –
Equivalent Input Noise Voltage (RS = 100 Ω, f = 1.0 kHz) en nVńǸHz
Equivalent Input Noise Current (f = 1.0 kHz) in pAńǸHz
Sleepmode – 0.20 –
NOTES: 1. The differential input voltage of each amplifier is limited by two internal diodes. The diodes are connected across the inputs in parallel and opposite to
each other. For more differential input voltage range, use current limiting resistors in series with the input pins.
2. The common–mode input voltage range of each amplifier is limited by diodes connected from the inputs to both power supply rails. Therefore, the
voltage on either input must not exceed supply rail by more than ±500 mV.
3. Simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratings and cause eventual
failure of the device.
4. Rail–to–rail performance is achieved at the input of the amplifier by using parallel NPN–PNP differential stages. When the inputs are near the
negative rail (VEE < VCM < 800 mV), the PNP stage is on. When the inputs are above 800 mV (i.e. 800 mV < VCM < VCC), the NPN stage is on.
This switching of the input pairs will cause a reversal of input bias current. Slight changes in the input offset voltage will be noted between the NPN
and PNP pairs. Cross–coupling techniques have been used to keep this change to a minimum.
5. Power dissipation must be considered to ensure maximum junction (TJ) is not exceeded. (See Figure 2)
6. When connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the
inverting input. This is because of the back to back diodes clamped across the inputs. The value of this resistor should be between 1.0 kΩ and
10 kΩ. If the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary.
(The output could be tied directly to the negative input.)

MC33304
Figure 1. Equivalent Circuit Block Diagram (Each Amplifier)
Current Awake to
Threshold Sleepmode
Detector Delay Circuit
Fractional
Load Current % of IL IHysteresis
Detector
IEnable
Buffer Buffer
Iref
CStorage
Bias
Bias
Boost
IL
Input Interface Output
Vin Vout
Stage Stage Stage
RL
Overdrive
Correction
IBias
Enable
Sleepmode ISleep Awakemode

Current Current IAwake
Regulator Regulator
There are 515 active components for the entire quad device.

MC33304
DEVICE DESCRIPTION
The MC33304 will begin to function at power supply to flow will switch the amplifier into the awakemode. This
voltages as low as VS = ±0.8 V. The device has the ability to includes transition currents like those generated by charging
swing rail–to–rail on both the input and the output. Since the load capacitances. In fact, the maximum capacitance that
common mode input voltage range extends from VCC to VEE, can be driven while attempting to remain in the sleepmode is
it can be operated with either single or split voltage supplies. approximately 300 pF.
The MC33304 is guaranteed not to latch up or phase reverse The awakemode to sleepmode transition time is controlled
over the entire common mode range. However, the output by an internal delay circuit, which is necessary to prevent the
could go into phase reversal state if input voltage is set higher amplifier from going to sleep during every zero crossing of
than +VCC or –VEE. the output waveform. This delay circuit also eliminates the
When power is initially applied, the part may start to crossover distortion commonly found in micropower
operate in the awakemode. This occurs because of bias amplifiers.
currents being generated from the charging of the internal The MC33304 rail–to–rail sleepmode operational amplifier
capacitors. When this occurs, the user will have to wait is unique in its ability to swing rail–to–rail on both the input
approximately 1.5 seconds before the device will switch back and output using a bipolar design. This offers a low noise and
to the sleepmode. wide common mode input voltage range. Since the common
The amplifier is designed to switch from sleepmode to mode input voltage range extends from VCC to VEE, it can be
awakemode whenever the output current exceeds a preset operated with either single or split voltage supplies.
current threshold (ITH) of approximately 200 µA. As a result, Rail–to–rail performance is achieved at the input of the
the output switching threshold voltage (VST) is controlled by amplifiers by using parallel NPN–PNP differential input
the output loading resistance (RL). Large valued load stages. When the inputs are within 800 mV of the negative
resistors require a large output voltage to switch, but reduce rail, the PNP stage is on. When the inputs are more than
unwanted transitions to the awakemode. 800 mV above VEE, the NPN stage is on. This switching of
Most of the transition time is consumed slewing in the input pairs will cause a reversal of input bias currents. Also,
sleepmode until VST is reached, therefore, small values of RL slight differences in offset voltage may be noted between the
allow rapid transition to the awakemode. The output NPN and PNP pairs. Cross–coupling techniques have been
switching threshold voltage (VST) is higher for the larger used to keep this change to a minimum.
values of RL, requiring the amplifier to slew longer in the In addition to the rail–to–rail performance, the output stage
slower sleepmode state before switching to the awakemode. is current boosted to provide enough output current to drive
Although typically 200 µA, ITH varies with supply voltage, 600 Ω loads. Because of this high current capability, care
temperature and the load resistance. Generally, any current should be taken not to exceed the 150°C maximum junction
loading on the ouput which causes a current greater than ITH temperature specification.

MC33304

2.5 k 150
VCC = +5.0 V

2.0 k 135 VEE = Gnd
VCM = 0 V
MC33304P
1.5 k 120
MC33304P
1.0 k 105
0.5 k 90 Awakemode
0 75
–55 –40 –25 0 25 50 85 125 –55 –40 –25 0 25 50 85 125
Figure 4. Input Bias Current versus Figure 5. Open Loop Voltage Gain
Common Mode Input Voltage versus Temperature
100 130

TA = 25°C
VCC = +5.0 V
IIB, INPUT BIAS CURRENT (nA)
50 VEE = Gnd 120
Sleepmode
0 110
–50 100
VCC = +5.0 V
Awakemode VEE = Gnd
–100 90 RL = 600 Ω
∆VO = 0.5 to 4.5 V
Awakemode
–150 80
–6.0 –4.0 –2.0 0 2.0 4.0 6.0 –55 –40 –25 0 25 50 85 125
VCM, COMMON MODE INPUT VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 6. Output Voltage Swing

versus Supply Voltage Figure 7. Output Voltage versus Frequency
12 12
RL = 600 Ω – 1.0 MΩ
10 TA = 25°C 10
Awakemode/ Sleepmode
Sleepmode (RL = 1.0 MΩ)
8.0 8.0
6.0 6.0 Awakemode

(RL = 600 Ω)
4.0 4.0
VCC = +6.0 V
VEE = –6.0 V
2.0 2.0 AV = +1.0
TA = 25°C
0 0
±1.0 ± 2.0 ± 3.0 ± 4.0 ± 5.0 ± 6.0 0.1 1.0 10 100 1.0 k
VCC,VEE SUPPLY VOLTAGE (V) f, FREQUENCY (kHz)

MC33304
Figure 8. Maximum Peak–to–Peak Output Figure 9. Common Mode Rejection

Voltage Swing versus Load Resistance versus Frequency
100 100
CMR, COMMOM MODE REJECTION (dB)

80
10
60 Awakemode
Sleepmode
40
1.0
VCC = +6.0 V
VEE = –6.0 V 20 VCC = +6.0 V
f = 1.0 kHz VEE = –6.0 V
TA = 25°C TA = 25°C
0.1 0
10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k 1.0 m 10 m
RL, LOAD RESISTANCE TO GROUND (Ω) f, FREQUENCY (Hz)
Figure 10. Power Supply Rejection Figure 11. Awakemode to Sleepmode

versus Frequency Current Threshold versus Supply Voltage
80 240
I TH2, CURRENT THRESHOLD ( µ A)

Source Current
±PSR
Awakemode 200
60
±PSR TA = 125°C
Sleepmode
40 160
TA = 25°C
TA = –55°C
20 VCC = +6.0 V 120
VEE = –6.0 V
TA = 25°C
0 80
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 1.0 2.0 3.0 4.0 5.0 6.0
f, FREQUENCY (Hz) VCC, VEE, SUPPLY VOLTAGE (V)
Figure 12. Sleepmode to Awakemode Figure 13. Output Short Circuit Current
Current Threshold versus Supply Voltage versus Output Voltage
260 80
ITH1, CURRENT THRESHOLD ( µ A)
Source Current
240
70
Source
220 TA = 25°C
60
Sink
200
TA = –55°C
VCC = +6.0 V
50 VEE = –6.0 V
180
VID = ±1.0 V
TA = 125°C
Awakemode
160 40
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0 2.0 4.0 6.0
VCC, VEE, SUPPLY VOLTAGE (V) IVOI, OUTPUT VOLTAGE (V)

MC33304
versus Temperature Supply Voltage with Load
120
VCC = +5.0 V 4.0 k
Source VEE = Gnd
VID = ±0.2 V
I D, SUPPLY CURRENT ( µ A)
100
RL = 1.0 MΩ 3.0 k
Awakemode
Sink
80
2.0 k
60 1.0 k
Single Supply
RL = 600 Ω
40 0
–55 –40 –25 0 25 50 85 125 0 3.5 7.0 10.5 14
TA, AMBIENT TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V)
Figure 16. Supply Current versus Supply Voltage Figure 17. Slew Rate versus Temperature
600 2.0
VCC = +2.5 V
500 VEE = –2.5 V
I D, SUPPLY CURRENT ( µ A)
1.5 VO = ±2.0 V
RL= 600 Ω
400
Sleepmode (µA) + Slew Rate
300 1.0
– Slew Rate
200
0.5
100 Single Supply
No Load
0 0
0 2.0 4.0 6.0 8.0 10 12 14 –55 –40 –25 0 25 70 85 105 125
V CC , SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 18. Gain Bandwidth Product Figure 19. Gain Margin versus
versus Temperature Differential Source Resistance
4.0 14
VCC = + 2.5 V
VEE = – 2.5 V 12
f = 100 kHz
3.0 Sleepmode
10
8.0
2.0
Awakemode
6.0
4.0
1.0
VCC = +6.0 V VO = 0 V
2.0 VEE = –6.0 V TA = 25°C
RT = R1 + R2
0 0
–55 –40 –25 0 25 70 85 105 125 10 100 1.0 k 10 k

MC33304
Figure 20. Phase Margin versus Figure 21. Gain Margin versus
Differential Source Resistance Output Load Capacitance
80 9.0
70
Sleepmode Sleepmode
φ m , PHASE MARGIN ( ° )

7.0
60
50
5.0
40 Awakemode
Awakemode
30
3.0
VCC = +6.0 V VO = 0 V
20 VEE = –6.0 V TA = 25°C VCC = +6.0 V
RT = R1 + R2 VEE = –6.0 V
10 1.0
10 100 1.0 k 10 k 10 100 1.0 k
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω) CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 22. Phase Margin versus Figure 23. Channel Separation

Output Load Capacitance versus Frequency
70 140
Sleepmode
60 CS, CHANNEL SEPARATION (dB) 120
PHASE MARGIN ( ° )
50 100
40 80
30 Awakemode 60
VCC = +6.0 V
20 40 VEE = –6.0 V
RL = 600 Ω
10 20 Awakemode
0 0
10 100 1.0 k 100 1.0 k 10 k 100 k
Figure 24. Total Harmonic Distortion Figure 25. Input Referred Noise Voltage
en , INPUT REFERRED NOISE VOLTAGE (nV/ √Hz)
100 100
VCC = +6.0 V VO = 2.0 Vpp VCC = +6.0 V

VEE = –6.0 V TA = 25°C VEE = –6.0 V
10 80
RL = 600 Ω Awakemode TA = 25°C
Sleepmode
1.0 60
AV = 1000
0.1 AV = 100 40
AV = 10
20 Awakemode
0.01
AV = 1.0
0.001 10
100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k

MC33304
Figure 27. Percent Overshoot

Figure 26. Current Noise versus Frequency versus Load Capacitance
1.4 100
i n , INPUT NOISE CURRENT (pA/√ Hz)
VCC = +6.0 V VCC = +6.0 V

1.2
OS, PERCENT OVERSHOOT (%)

VEE = –6.0 V 80 VEE = –6.0 V
TA = 25°C TA = 25°C
1.0 (RS = 100 k)
Awakemode
60
0.8
0.6 40 Awakemode
(RL = 600 Ω)
0.4
20
0.2 Sleepmode
Sleepmode (RL = ∞)
0 0
10 100 1.0 k 10 k 100 k 10 100 1.0 k

MC34001, B
MC34002, B
MC34004, B
JFET Input Operational
Amplifiers
These low cost JFET input operational amplifiers combine two JFET INPUT
state–of–the–art analog technologies on a single monolithic integrated
circuit. Each internally compensated operational amplifier has well matched OPERATIONAL AMPLIFIERS
high voltage JFET input devices for low input offset voltage. The BIFET
technology provides wide bandwidths and fast slew rates with low input bias
currents, input offset currents, and supply currents.
The Motorola BIFET family offers single, dual and quad operational
amplifiers which are pin–compatible with the industry standard MC1741,
MC1458, and the MC3403/LM324 bipolar devices. The MC34001/
34002/34004 series are specified from 0° to +70°C. 8 8
1
• Input Offset Voltage Options of 5.0 mV and 10 mV Maximum 1
• Low Input Bias Current: 40 pA P SUFFIX

PLASTIC PACKAGE
D SUFFIX
PLASTIC PACKAGE
• Low Input Offset Current: 10 pA CASE 626 CASE 751
• Wide Gain Bandwidth: 4.0 MHz (SO–8)
• High Slew Rate: 13 V/µs PIN CONNECTIONS

• Low Supply Current: 1.4 mA per Amplifier
Offset Null 1 8 NC
• High Input Impedance: 1012 Ω
Inv. Input 2 7 VCC
• High Common Mode and Supply Voltage Rejection Ratios: 100 dB Noninv. Input 3 + 6 Output
• Industry Standard Pinouts VEE 4 5 Offset Null
MC34001 (Top View)
Output A 1 8 VCC
2
–
7 Output B
Inputs A +
3 6
–
+ Inputs B
VEE 4 5
MC34002 (Top View)
P SUFFIX
PLASTIC PACKAGE
14 CASE 646
1
PIN CONNECTIONS

Op Amp Operating 2 13
Function Device Temperature Range Package Inputs 1 – –
Inputs 4
+ +
3 1 4 12
MC34001BD, D SO–8
Single TA = 0° to+ 70°C VCC 4 11 VEE
MC34001BP, P Plastic DIP
5 10
+ +
MC34002BD, D SO–8 Inputs 2 – – Inputs 3
2 3
Dual TA = 0° to +70°C 6 9
MC34002BP, P Plastic DIP
Quad MC34004BP, P TA = 0° to +70°C Plastic DIP
MC34004 (Top View)

MC34001, B MC34002, B MC34004, B
MAXIMUM RATINGS
Supply Voltage VCC, VEE ±18 V
Differential Input Voltage (Note 1) VID ±30 V
Input Voltage Range VIDR ±16 V
Open Short Circuit Duration tSC Continuous
NOTES: 1. Unless otherwise specified, the absolute maximum negative input voltage is equal to the
negative power supply.
Input Offset Voltage (RS ≤ 10 k) VIO mV
MC3400XB — 3.0 5.0
MC3400X — 5.0 10
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T — 10 — µV/°C
RS ≤ 10 k, TA = Tlow to Thigh (Note 2)
Input Offset Current (VCM = 0) (Note 3) IIO pA

MC3400XB — 25 100
MC3400X — 25 100
Input Bias Current (VCM = 0) (Note 3) IIB pA
MC3400XB — 50 200
MC3400X — 50 200
Input Resistance ri — 1012 — Ω
Common Mode Input Voltage Range VICR ±11 +15 — V
— –12 —
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 k) AVOL V/mV

MC3400XB 50 150 —
MC3400X 25 100 —
(RL ≥ 10 k) ±12 ±14 —
(RL ≥ 2.0 k) ±10 ±13 —
Common Mode Rejection Ratio (RS ≤ 10 k) CMRR dB
MC3400XB 80 100 —
MC3400X 70 100 —
Supply Voltage Rejection Ratio (RS ≤ 10 k) (Note 4) PSRR dB
MC3400XB 80 100 —
MC3400X 70 100 —
Supply Current (Each Amplifier) ID mA
MC3400XB — 1.4 2.5
MC3400X — 1.4 2.7
Slew Rate (AV = 1.0) SR — 13 — V/µs
Gain–Bandwidth Product GBW — 4.0 — MHz
(RS = 100 Ω, f = 1000 Hz)
Equivalent Input Noise Current (f = 1000 Hz) in — 0.01 — pA/ √ Hz

NOTES: 2. Tlow = 0°C for MC34001/34001B Thigh = +70°C for MC34001/34001B
0°C for MC34002 +70°C for MC34002
0°C for MC34004/34004B +70°C for MC34004/34004B
3. The input bias currents approximately double for every 10°C rise in junction temperature, TJ. Due to limited test time, the input bias currents are
correlated to junction temperature. Use of a heatsink is recommended if input bias current is to be kept to a minimum.
4. Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.

MC34001, B MC34002, B MC34004, B
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh [Note 2].)
Input Offset Voltage (RS ≤ 10 k) VIO mV
MC3400XB — — 7.0
MC3400X — — 13
Input Offset Current (VCM = 0) (Note 3) IIO nA
MC3400XB — — 4.0
MC3400X — — 4.0
Input Bias Current (VCM = 0) (Note 3) IIB nA
MC3400XB — — 8.0
MC3400X — — 8.0
Common Mode Input Voltage Range VICR ±11 — — V
Large Signal (VO = ±10 V, RL = 2.0 k) AVOL V/mV
MC3400XB 25 — —
MC3400X 15 — —
(R ≥ 10 k) ±12 — —
(R ≥ 2.0 k) ±10 — —
MC3400XB 80 — —
MC3400X 70 — —
Supply Voltage Rejection Ratio (RS ≤ 10 k) (Note 4) PSRR dB
MC3400XB 80 — —
MC3400X 70 — —
Supply Current (Each Amplifier) ID mA
MC3400XB — — 2.8
MC3400X — — 3.0
NOTES: 2. Tlow = 0°C for MC34001/34001B Thigh = +70°C for MC34001/34001B
0°C for MC34002 +70°C for MC34002
0°C for MC34004/34004B +70°C for MC34004/34004B
3. The input bias currents approximately double for every 10°C rise in junction temperature, TJ. Due to limited test time, the input bias currents are
correlated to junction temperature. Use of a heatsink is recommended if input bias current is to be kept to a minimum.
4. Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.

MC34001, B MC34002, B MC34004, B
Figure 1. Input Bias Current Figure 2. Output Voltage Swing

100 35

30
VCC/VEE = ±15 V VCC/VEE = ±15 V
10 RL = 2.0 k
25
TA = 25°C
20 ±10 V
1.0
15
10 ± 5.0 V
0.1
5.0
0.01 0
–75 –50 –25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M 10 M

40 40
RL = 2.0 k
VO ,OUTPUT VOLTAGE SWING (V pp)
TA = 25°C
30 VCC/VEE = ±15 V
TA = 25°C 30
20
20
10
10
5.0
0 0
0.1 0.2 0.4 0.7 1.0 2.0 4.0 7.0 10 0 5.0 10 15 20
RL, LOAD RESISTANCE (kΩ) VCC/VEE , SUPPLY VOLTAGE (V)
Figure 5. Output Voltage Swing Figure 6. Supply Current per Amplifier

2.0
VCC/VEE = ±15 V
1.8
VCC/VEE = ±15 V
I D, SUPPLY DRAIN CURRENT (mA)
35
1.6
30 RL = 10 k
1.4
25 1.2
RL = 2.0 k
20 1.0
15 0.8
0.6
10
0.4
5.0 0.2
0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

MC34001, B MC34002, B MC34004, B
Figure 7. Large–Signal Voltage Gain and Figure 8. Large–Signal Voltage Gain

Phase Shift versus Frequency versus Temperature
1000
VCC/VEE = ±15 V
VO = ±10 V
A VOL, VOLTAGE GAIN (V/mV)

VCC/VEE = ±15 V
PHASE SHIFT (DEGREES)

A VOL , OPEN–LOOP GAIN
RL = 2.0 k
106 RL = 2.0 k
TA = 25°C 100
105
104 0°
Gain
103 45°
10
102 90°
Phase Shift
101 135°
1 180° 1.0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 1.0 M 10 M –50 –25 0 25 50 75 100 125
Figure 9. Normalized Slew Rate Figure 10. Equivalent Input Noise Voltage
1.15 en , EQUIVALENT INPUT NOISE VOLTAGE ( nV/ √ Hz ) VCC/VEE = ±15 V

60
AV = 10
NORMALIZED SLEW RATE
1.10 RS = 100 Ω
50
TA = 25°C
1.05
40
1.00
30
0.95
20
0.90
0.85 10
0
–50 –25 0 25 50 75 100 125 0.01 0.05 0.1 0.5 1.0 5.0 10 50 100
TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (kHz)

versus Frequency
1.0
0.5
VCC/VEE = ±15 Vdc
0.1 AV = 1.0
VO = 6.0 V (RMS)
TA = 25°C
0.05
0.01
0.005
0.001
0.1 0.5 1.0 5.0 10 50 100
f, FREQUENCY (kHz)

MC34001, B MC34002, B MC34004, B
Representative Circuit Schematic

(Each Amplifier)
Bias Circuitry
Output Common to All
Amplifiers
VCC
Q4 Q5 Q2
Q3 Q1
Q6
– J1 J2
Inputs
+ Q17 2.0 k
Q20
J3
Q15 Q19 Q23
10 pF
24
Q14
Q21 Q24
Q22
Q12 Q13 Q16
Q10 Q9 Q8 Q25
Q11 Q7
Q18
Offset
Null 1.5 k 1.5 k
(MC34001 only)
VEE
Figure 12. Output Current to Voltage Transformation

for a D–to–A Converter
VCC
Settling time to within 1/2 LSB is approximately 4.0 µs

from the time all bits are switched (C = 68 pF).
R1
MSB A1 Vref The value of C may be selected to minimize overshoot
A2 and ringing.
A3
A4 R2 VCC = 15 V Theoretical VO
D–to–A
A5 Vref A1 A2 A3 A4 A5 A6 A7 A8
1 VO = (RO) + + + + + + +
A6 R1 2 4 8 16 32 64 128 256
A7 + VO
LSB A8 Io
–
MC34001
15 pF VEE = –15 V
VEE
RO
C

MC34001, B MC34002, B MC34004, B
Figure 13. Positive Peak Detector
8 VCC 6
– 1/2
– D1 MC34002 7 VO
2 1/2 5
3 MC34002 +
Vin + *
1N914 1 µF
4 VEE
Reset Reset
*Polycarbonate capacitor
Network
D1 = Hi–speed, low–reverse leakage diode
or Relay
Figure 14. Long Interval RC Timer Figure 15. Isolating Large Capacitive Loads
R2 5.1 k
+15 V VO
7 MC34001 VCC 20 pF
R1 V1 R3 2
VR – 6
R1 5.1 k 2 CC IO
R4 R2 3 – 7
+ 6 R3 10
4 MC34001 +
R6 3
+2.0 V 4 CL 0.5 µF
–15 V RL 5.1 k
Run Clear C* 0
–2.0 V
VEE
t
Overshoot 10%
R5 *Polycarbonate or ts = 10 µs
Polystyrene Capacitor When driving large CL, the VO slew rate is determined by CL
and IO(max):
Time (t) = R4 Cn (VR/VR–VI), R3 = R4, R5 = 0.1 R6 ∆VO IO 0.02
= = V/µs = 0.04 V/µs (with CL shown)
If R1 = R2: t = 0.693 R4C ∆t CL 0.5
Design Example: 100 Second Timer

VR = 10 V C = l.0 µF R3 = R4 = 144 M
R6 = 20 k R5 = 2.0 k R1 = R2 = 1.0 k
Figure 16. Wide BW, Low Noise,

Low Drift Amplifier
C2
^ 240 kHz
R2
fmax
VCC
7 10 V
R1 2 8
Vin –10 V
6
C1
3 MC34001
4
VEE
Power BW: fmax =

Sr
2π Vp
^ 240 kHz
Parasitic input capacitance (C1 ^ 3.0 pF plus any additional layout capacitance)
To compensate add C2 such that: R2C2 ^ R1C1.

interacts with feedback elements and creates undesirable high–frequency pole.

MC34071,2,4,A
MC33071,2,4,A
High Slew Rate, Wide
Bandwidth, Single Supply
HIGH BANDWIDTH
SINGLE SUPPLY
Quality bipolar fabrication with innovative design concepts are employed OPERATIONAL AMPLIFIERS
for the MC33071/72/74, MC34071/72/74 series of monolithic operational
amplifiers. This series of operational amplifiers offer 4.5 MHz of gain
bandwidth product, 13 V/µs slew rate and fast setting time without the use of
JFET device technology. Although this series can be operated from split
supplies, it is particularly suited for single supply operation, since the
8
common mode input voltage range includes ground potential (VEE). With A 8 1
Darlington input stage, this series exhibits high input resistance, low input 1
offset voltage and high gain. The all NPN output stage, characterized by no P SUFFIX D SUFFIX
deadband crossover distortion and large output voltage swing, provides high PLASTIC PACKAGE PLASTIC PACKAGE
capacitance drive capability, excellent phase and gain margins, low open CASE 626 CASE 751
(SO–8)
loop high frequency output impedance and symmetrical source/sink AC
frequency response.
PIN CONNECTIONS
The MC33071/72/74, MC34071/72/73 series of devices are available in
standard or prime performance (A Suffix) grades and are specified over the
Offset Null 1 8 NC
commercial, industrial/vehicular or military temperature ranges. The
2 – 7 VCC
complete series of single, dual and quad operational amplifiers are available Inputs
+ Output
in plastic DIP and SOIC surface mount packages. 3 6
• Wide Bandwidth: 4.5 MHz VEE 4 5 Offset Null

• High Slew Rate: 13 V/µs (Single, Top View)
• Fast Settling Time: 1.1 µs to 0.1%
Output 1 1 8 VCC
• Wide Single Supply Operation: 3.0 V to 44 V 2
–
7 Output 2
• Wide Input Common Mode Voltage Range: Includes Ground (VEE) Inputs 1 3
+
–
6
• + Inputs 2
Low Input Offset Voltage: 3.0 mV Maximum (A Suffix) VEE 4 5
• Large Output Voltage Swing: –14.7 V to +14 V (with ±15 V Supplies) (Dual, Top View)
• Large Capacitance Drive Capability: 0 pF to 10,000 pF
• Excellent Phase Margin: 60°
• Excellent Gain Margin: 12 dB 14 14
• Output Short Circuit Protection 1
1
• ESD Diodes/Clamps Provide Input Protection for Dual and Quad P SUFFIX D SUFFIX
ORDERING INFORMATION CASE 646 CASE 751A
Op Amp Operating (SO–14)
Function Device Temperature Range Package PIN CONNECTIONS
Single MC34071P, AP Plastic DIP
TA = 0° to +70°C
MC34071D, AD SO–8 Output 1 1 14 Output 4
MC33071P, AP Plastic DIP 13
TA = –40° to +85°C 2
– 1 4 –
MC33071D, AD SO–8 Inputs 1 Inputs 4
+ +
3 12
Dual MC34072P, AP Plastic DIP
TA = 0° to +70°C
MC34072D, AD SO–8 VCC 4 11 VEE
MC33072P, AP Plastic DIP 5 2 3 10
TA = –40° to +85°C + +
MC33072D, AD SO–8 Inputs 2 – – Inputs 3
6 9
Quad MC34074P, AP Plastic DIP
TA = 0° to +70°C Output 2 7 8 Output 3
MC34074D, AD SO–14
MC33074P, AP Plastic DIP (Quad, Top View)
TA = –40° to +85°C
MC33074D, AD SO–14

MC34071,2,4,A MC33071,2,4,A
MAXIMUM RATINGS
Supply Voltage (from VEE to VCC) VS +44 V
Input Voltage Range VIR Note 1 V
NOTES: 1. Either or both input voltages should not exceed the magnitude of VCC or VEE.
exceeded (see Figure 1).

(Each Amplifier)
VCC
Q3 Q4 Q5 Q6 Q7
Q1
Q17
Q2
R1 C1 R2
D2 Q18
Bias R6 R7
Q8 Q9 Q10 Q11
– Output
Inputs R8
+ C2 D3
Q19
Base Q13 Q14 Q15 Q16

Current
Cancellation Q12
Current
D1 Limit
R5
R3 R4
VEE/Gnd
Offset Null
(MC33071, MC34071 only)

MC34071,2,4,A MC33071,2,4,A
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL = connected to ground, unless otherwise noted. See Note 3 for
TA = Tlow to Thigh)
A Suffix Non–Suffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Input Offset Voltage (RS = 100 Ω, VCM = 0 V, VO = 0 V) VIO mV
— —
VCC = +15 V, VEE = –15 V, TA = +25°C — 0.5 3.0 — 1.0 5.0
VCC = +5.0 V, VEE = 0 V, TA = +25°C — 0.5 3.0 — 1.5 5.0
VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh — 5.0 — 7.0
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T — 10 — — 10 — µV/°C
RS = 10 Ω, VCM = 0 V, VO = 0 V,
TA = Tlow to Thigh
TA = +25°C — 100 500 — 100 500
TA = Tlow to Thigh — — 700 — — 700
Input Offset Current (VCM = 0 V, VO = 0V) IIO nA
TA = +25°C — 6.0 50 — 6.0 75
TA = Tlow to Thigh — — 300 — — 300
TA = +25°C VEE to (VCC –1.8) VEE to (VCC –1.8)
TA = Tlow to Thigh VEE to (VCC –2.2) VEE to (VCC –2.2)
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kΩ) AVOL V/mV
TA = +25°C 50 100 — 25 100 —
TA = Tlow to Thigh 25 — — 20 — —
Output Voltage Swing (VID = ±1.0 V) VOH V
VCC = +5.0 V, VEE = 0 V, RL = 2.0 kΩ, TA = +25°C 3.7 4.0 — 3.7 4.0 —
VCC = +15 V, VEE = –15 V, RL = 10 kΩ, TA = +25°C 13.6 14 — 13.6 14 —
VCC = +15 V, VEE = –15 V, RL = 2.0 kΩ, 13.4 — — 13.4 — —
TA = Tlow to Thigh
VCC = +5.0 V, VEE = 0 V, RL = 2.0 kΩ, TA = +25°C VOL 0.1 0.3 — 0.1 0.3 V
—
VCC = +15 V, VEE = –15 V, RL = 10 kΩ, TA = +25°C –14.7 –14.3 — –14.7 –14.3
—
VCC = +15 V, VEE = –15 V, RL = 2.0 kΩ, — –13.5 — — –13.5
—
TA = Tlow to Thigh
Output Short Circuit Current (VID = 1.0 V, VO = 0 V, ISC mA
TA = 25°C)
Source 10 30 — 10 30 —
Sink 20 30 — 20 30 —
Common Mode Rejection CMR 80 97 — 70 97 — dB
RS ≤ 10 kΩ, VCM = VICR, TA = 25°C
Power Supply Rejection (RS = 100 Ω) PSR 80 97 — 70 97 — dB

VCC/VEE = +16.5 V/–16.5 V to +13.5 V/–13.5 V,
TA = 25°C
Power Supply Current (Per Amplifier, No Load) ID mA
VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25°C — 1.6 2.0 — 1.6 2.0
VCC = +15 V, VEE = –15 V, VO = 0 V, TA = +25°C — 1.9 2.5 — 1.9 2.5
VCC = +15 V, VEE = –15 V, VO = 0 V, — — 2.8 — — 2.8
TA = Tlow to Thigh
NOTES: 3. Tlow = –40°C for MC33071, 2, 4, /A Thigh = +85°C for MC33071, 2, 4, /A
= 0°C for MC34071, 2, 4, /A = +70°C for MC34071, 2, 4, /A

MC34071,2,4,A MC33071,2,4,A
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL = connected to ground. TA = +25°C, unless otherwise noted.)
A Suffix Non–Suffix
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 500 pF) SR V/µs
AV = +1.0 8.0 10 — 8.0 10 —
AV = –1.0 — 13 — — 13 —
Setting Time (10 V Step, AV = –1.0) ts µs
To 0.1% (+1/2 LSB of 9–Bits) — 1.1 — — 1.1 —
To 0.01% (+1/2 LSB of 12–Bits) — 2.2 — — 2.2 —
Gain Bandwidth Product (f = 100 kHz) GBW 3.5 4.5 — 3.5 4.5 — MHz
Power Bandwidth BW — 160 — — 160 — kHz
AV = +1.0, RL = 2.0 kΩ, VO = 20 Vpp, THD = 5.0%
Phase margin fm Deg

RL = 2.0 kΩ — 60 — — 60 —
RL = 2.0 kΩ, CL = 300 pF — 40 — — 40 —
Gain Margin Am dB
RL = 2.0 kΩ — 12 — — 12 —
RL = 2.0 kΩ, CL = 300 pF — 4.0 — — 4.0 —
Equivalent Input Noise Voltage en — 32 — — 32 — nV/ √ Hz
RS = 100 Ω, f = 1.0 kHz
Equivalent Input Noise Current in — 0.22 — — 0.22 — pA/ √ Hz

f = 1.0 kHz
Differential Input Resistance Rin — 150 — — 150 — MΩ

VCM = 0 V
Differential Input Capacitance Cin — 2.5 — — 2.5 — pF

VCM = 0 V
Total Harmonic Distortion THD — 0.02 — — 0.02 — %

AV = +10, RL = 2.0 kΩ, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz
Channel Separation (f = 10 kHz) — — 120 — — 120 — dB

Open Loop Output Impedance (f = 1.0 MHz) |ZO| — 30 — — 30 — W
Figure 1. Power Supply Configurations Figure 2. Offset Null Circuit
VCC
3.0 V to 44 V VCC+|VEE|≤44 V
7
2
–
VCC VCC 6
3 5
1 +
VCC 1 1
4
2 2
10 k
3 3 VEE
4 VEE 4 Offset nulling range is approximately ± 80 mV with a 10 k

potentiometer (MC33071, MC34071 only).
VEE VEE

MC34071,2,4,A MC33071,2,4,A
Figure 3. Maximum Power Dissipation versus Figure 4. Input Offset Voltage versus
Temperature for Package Types Temperature for Representative Units
2400
4.0 VCC = +15 V
VV IO , INPUT OFFSET VOLTAGE (mV)

2000 VEE = –15 V
VCM = 0
2.0
1600
SO–14 Pkg 8 & 14 Pin Plastic Pkg
1200 0
800
–2.0
SO–8 Pkg
400
–4.0
0
–55 –40 –20 0 20 40 60 80 100 120 140 160 –55 –25 0 25 50 75 100 125
Figure 5. Input Common Mode Voltage Figure 6. Normalized Input Bias Current
Range versus Temperature V ICR , INPUT COMMON MODE VOLTAGE RANGE (V) versus Temperature
VCC 1.3
I IB, INPUT BIAS CURRENT (NORMALIZED)
VCC VCC/VEE = +1.5 V/ –1.5 V to +22 V/ –22 V VCC = +15 V
1.2 VEE = –15 V
VCC –0.8
VCM = 0
1.1
VCC –1.6
1.0
VCC –2.4
0.9
VEE +0.01 0.8

VEE
VEE 0.7
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
Figure 7. Normalized Input Bias Current versus Figure 8. Split Supply Output Voltage
Input Common Mode Voltage Swing versus Supply Voltage
I IB, INPUT BIAS CURRENT (NORMALIZED)
1.4 50
VCC = +15 V RL Connected
VEE = –15 V to Ground TA = 25°C

40
1.2 TA = 25°C
30
RL = 10 k RL = 2.0 k
1.0
20
0.8
10
0.6 0
–12 –8.0 –4.0 0 4.0 8.0 12 0 5.0 10 15 20 25
VIC, INPUT COMMON MODE VOLTAGE (V) VCC, |VEE|, SUPPLY VOLTAGE (V)

MC34071,2,4,A MC33071,2,4,A
Figure 9. Single Supply Output Saturation Figure 10. Split Supply Output Saturation
versus Load Resistance to VCC versus Load Current
VCC VCC

VCC/VEE = +5.0 V/ –5.0 V to +22 V/ –22 V VCC
VCC TA = 25°C
VCC –1.0 VCC –2.0
VCC = +15 V
Source RL = Gnd
VCC –2.0 VCC –4.0 TA = 25°C
VEE +2.0 0.2
VEE +1.0 Sink 0.1

VEE Gnd
VEE 0
0 5.0 10 15 20 100 1.0 k 10 k 100 k
IL, LOAD CURRENT (± mA) RL, LOAD RESISTANCE TO GROUND (Ω)
Figure 11. Single Supply Output Saturation Figure 12. Output Short Circuit Current
versus Load Resistance to Ground versus Temperature
0 60
VCC
50
I SC, OUTPUT CURRENT (mA)
–0.4 Sink
40
–0.8
Source
30
2.0
VCC = +15 V 20
RL to VCC VCC = +15 V
1.0 TA = 25°C VEE = –15 V
10
Gnd RL ≤ 0.1 Ω
∆Vin = 1.0 V
0
100 1.0 k 10 k 100 k –55 –25 0 25 50 75 100 125
RL, LOAD RESISTANCE TO VCC (Ω) TA, AMBIENT TEMPERATURE (°C)
Figure 13. Output Impedance Figure 14. Output Voltage Swing

50 28
VCC = +15 V
VCC = +15 V
VEE = –15 V 24
Z O, OUTPUT IMPEDANCE (Ω )
40 VCM = 0 VEE = –15 V

VO = 0 AV = +1.0
20
∆IO = ±0.5 mA RL = 2.0 k
30 TA = 25°C THD ≤ 1.0%
16 TA = 25°C
20 12
AV = 1000 AV = 100 AV = 10 AV = 1.0 8.0

10
4.0
0 0
1.0 k 10 k 100 1.0 M 10 M 3.0 k 10 k 30 k 100 k 300 k 1.0 M 3.0 M

MC34071,2,4,A MC33071,2,4,A
Figure 15. Total Harmonic Distortion Figure 16. Total Harmonic Distortion
versus Frequency versus Output Voltage Swing
0.4 4.0

AV = 1000 VCC = +15 V
VEE = –15 V
0.3 3.0 AV = 1000 RL = 2.0 k
TA = 25°C
VCC = +15 V
VEE = –15 V
0.2 VO = 2.0 Vpp 2.0
RL = 2.0 k
TA = 25°C AV = 100
AV = 100
0.1 1.0 AV = 10
AV = 10
AV = 1.0
AV = 1.0
0 0
10 100 1.0 k 10 k 100 k 0 4.0 8.0 12 16 20
f, FREQUENCY (Hz) VO, OUTPUT VOLTAGE SWING (Vpp)
Figure 17. Open Loop Voltage Gain Figure 18. Open Loop Voltage Gain and
versus Temperature Phase versus Frequency
116 100
0
VCC = +15 V

112 80
VEE = –15 V Gain
VO= –10 V to +10 V Phase 45
108 RL = 10 k 60
f ≤ 10Hz Phase
Margin 90
104 40 = 60°
VCC = +15 V 135
VEE = –15 V
100 20 VO = 0 V
RL = 2.0 k
180
TA = 25°C
96 0
–55 –25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
Figure 19. Open Loop Voltage Gain and Figure 20. Normalized Gain Bandwidth
Phase versus Frequency Product versus Temperature
GBW, GAIN BANDWIDTH PRODUCT (NORMALIED)
20 1.15
1 100
Phase VCC = +15 V
10 Margin = 60° 1.1 VEE = –15 V
Gain 120 RL = 2.0 k

0 Margin = 12 dB
1.05
140
–10 1.0
1. Phase RL = 2.0 k
160
2. Phase RL = 2.0 k, CL = 300 pF 3
–20 3. Gain R = 2.0 k 0.95
L
4. Gain RL = 2.0 k, CL = 300 pF 180
4
–30 VCC = +15 V 0.9
VEE = 15 V 2
V =0V TA = 25°C
–40 O 0.85
1.0 2.0 3.0 5.0 7.0 10 20 30 –55 –25 0 25 50 75 100 125
f, FREQUENCY (MHz) TA, AMBIENT TEMPERATURE (°C)

MC34071,2,4,A MC33071,2,4,A
Figure 21. Percent Overshoot versus Figure 22. Phase Margin versus
Load Capacitance Load Capacitance
100 70
VCC = +15 V

60 VCC = +15 V
80 VEE = –15 V VEE = –15 V
PERCENT OVERSHOOT
R
RL = 2.0 k AV = +1.0
VO = –10 V to +10 V 50
RL = 2.0 k to
60 TA = 25°C VO = –10 V to +10 V
40
TA = 25°C
30
40
20
20
10
0 0
10 100 1.0 k 10 k 10 100 1.0 k 10 k
CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF)
Figure 23. Gain Margin versus Load Capacitance Figure 24. Phase Margin versus Temperature
14 80
12 VCC = +15 V φ m , PHASE MARGIN (DEGREES) CL = 10 pF

VEE = –15 V
AV = +1.0 60 CL = 100 pF
10
RL = 2.0 k to ∞
VO = –10 V to +10 V
8.0 TA = 25°C VCC = +15 V
40 VEE = –15 V
6.0 AV = +1.0
RL = 2.0 k to ∞
4.0 CL = 1,000 pF VO = –10 V to +10 V
20
2.0 CL = 10,000 pF
0 0
10 100 1.0 k 10 k –55 –25 0 25 50 75 100 125
CL, LOAD CAPACITANCE (pF) TA, AMBIENT TEMPERATURE (°C)
Figure 26. Phase Margin and Gain Margin

Figure 25. Gain Margin versus Temperature versus Differential Source Resistance
16 12 70
VCC = +15 V
10 60
CL = 10 pF Gain
12 VEE = –15 V 8.0 50

AV = +1.0 R1
VO
RL = 2.0 k to ∞ –
6.0 + 40
VO = –10 V to +10 V CL = 100 pF
8.0 R2
4.0 30
VCC = +15 V
CL = 10,000 pF VEE = –15 V
2.0 RT = R1 + R2 20
4.0 CL = 1,000 pF Phase
AV = +100
0 VO = 0 V 10
TA = 25°C
0 0
–55 –25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k

MC34071,2,4,A MC33071,2,4,A
Figure 27. Normalized Slew Rate

versus Temperature Figure 28. Output Settling Time
∆ V O , OUTPUT VOLTAGE SWING FROM 0 V (V)

1.15 10
VCC = +15 V VCC = +15 V
1.0 mV
1.1 VEE = –15 V 10 mV 1.0 mV VEE = –15 V

AV = +1.0 5.0 AV = –1.0
RL = 2.0 k TA = 25°C
1.05
CL = 500 pF
Compensated
1.0 0
Uncompensated
0.95
–5.0 1.0 mV
0.9 10 mV
1.0 mV
0.85 –10
–55 –25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TA, AMBIENT TEMPERATURE (°C) ts, SETTLING TIME (µs)
Figure 29. Small Signal Transient Response Figure 30. Large Signal Transient Reponse
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
50 mV/DIV
5.0 V/DIV
0 0 TA = 25°C
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
TA = 25°C
2.0 µs/DIV 1.0 µs/DIV
100 100
TA = 125°C VCC = +15 V VCC = +15 V

TA = 25°C VEE = –15 V VEE = –15 V

80 VCM = 0 V 80 TA = 25°C
TA = –55°C ∆VCM = ±1.5 V ∆VCC
– (∆VCC = +1.5 V)
60 60 ADM ∆VO
+
∆VEE
40 – 40 ∆VO/ADM
+PSR
∆VCM ADM ∆VO +PSR = 20 Log
+ ∆VCC
20 20
∆VCM ∆VO/ADM
CMR = 20 Log x ADM –PSR = 20 Log –PSR
∆VO ∆VEE (∆VEE = +1.5 V)
0 0
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M

MC34071,2,4,A MC33071,2,4,A
Figure 33. Supply Current versus Figure 34. Power Supply Rejection
Supply Voltage versus Temperature
9.0 105

–PSR (∆VEE = +1.5 V) VCC = +15 V
TA = –55°C
8.0 VEE = –15 V

95
7.0 +PSR (∆VCC = +1.5 V)

TA = 25°C
85
6.0 ∆VCC
∆VO/ADM
TA = 125°C +PSR = 20 Log –
∆VCC ADM ∆VO
75 +
5.0 ∆VO/ADM
–PSR = 20 Log ∆VEE
∆VEE
4.0 65
0 5.0 10 15 20 25 –55 –25 0 25 50 75 100 125
Figure 35. Channel Separation versus Frequency Figure 36. Input Noise versus Frequency
120 70 2.8
en , INPUT NOICE VOLTAGE ( nV √ Hz )
i n , INPUT NOISE CURRENT (pA √ Hz )

VCC = +15 V
100 VCC = +15 V 60 VEE = –15 V 2.4
CHANNEL SEPARATION (dB)
VEE = –15 V VCM = 0

TA = 25°C 50 TA = 25°C 2.0
80
40 1.6
60 Voltage
30 1.2
40
20 Current 0.8
20 10 0.4
0 0 0
10 20 30 50 70 100 200 300 10 100 1.0 k 10 k 100 k
f, FREQUENCY (kHz) f, FREQUENCY (kHz)
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the between VEE and VCC supply voltages as shown by the
MC34071 amplifier series are similar to op amp products maximum rating table. In practice, although not
utilizing JFET input devices, these amplifiers offer other recommended, the input voltages can exceed the VCC
additional distinct advantages as a result of the PNP voltage by approximately 3.0 V and decrease below the VEE
transistor differential input stage and an all NPN transistor voltage by 0.3 V without causing product damage, although
output stage. output phase reversal may occur. It is also possible to source
Since the input common mode voltage range of this input up to approximately 5.0 mA of current from VEE through
stage includes the VEE potential, single supply operation is either inputs clamping diode without damage or latching,
feasible to as low as 3.0 V with the common mode input although phase reversal may again occur.
voltage at ground potential. If one or both inputs exceed the upper common mode
The input stage also allows differential input voltages up to voltage limit, the amplifier output is readily predictable and
±44 V, provided the maximum input voltage range is not may be in a low or high state depending on the existing input
exceeded. Specifically, the input voltages must range bias conditions.

MC34071,2,4,A MC33071,2,4,A
Since the input capacitance associated with the small light load currents, the load resistance will pull the output to
geometry input device is substantially lower (2.5 pF) than the VCC during the positive swing and the output will pull the load
typical JFET input gate capacitance (5.0 pF), better resistance near ground during the negative swing. The load
frequency response for a given input source resistance can resistance value should be much less than that of the
be achieved using the MC34071 series of amplifiers. This feedback resistance to maximize pull up capability.
performance feature becomes evident, for example, in fast Because the PNP output emitter–follower transistor has
settling D–to–A current to voltage conversion applications been eliminated, the MC34071 series offers a 20 mA
where the feedback resistance can form an input pole with minimum current sink capability, typically to an output voltage
the input capacitance of the op amp. This input pole creates of (VEE +1.8 V). In single supply applications the output can
a 2nd order system with the single pole op amp and is directly source or sink base current from a common emitter
therefore detrimental to its settling time. In this context, lower NPN transistor for fast high current switching applications.
input capacitance is desirable especially for higher values of In addition, the all NPN transistor output stage is inherently
feedback resistances (lower current DACs). This input pole fast, contributing to the bipolar amplifier’s high gain
can be compensated for by creating a feedback zero with a bandwidth product and fast settling capability. The
capacitance across the feedback resistance, if necessary, to associated high frequency low output impedance (30 Ω typ
reduce overshoot. For 2.0 kΩ of feedback resistance, the @ 1.0 MHz) allows capacitive drive capability from 0 pF to
MC34071 series can settle to within 1/2 LSB of 8 bits in 1.0 10,000 pF without oscillation in the unity closed loop gain
µs, and within 1/2 LSB of 12–bits in 2.2 µs for a 10 V step. In configuration. The 60° phase margin and 12 dB gain margin
a inverting unity gain fast settling configuration, the as well as the general gain and phase characteristics are
symmetrical slew rate is ±13 V/µs. In the classic noninverting virtually independent of the source/sink output swing
unity gain configuration, the output positive slew rate is +10 conditions. This allows easier system phase compensation,
V/µs, and the corresponding negative slew rate will exceed since output swing will not be a phase consideration. The
the positive slew rate as a function of the fall time of the input high frequency characteristics of the MC34071 series also
waveform. allow excellent high frequency active filter capability,
Since the bipolar input device matching characteristics are especially for low voltage single supply applications.
superior to that of JFETs, a low untrimmed maximum offset Although the single supply specifications is defined at
voltage of 3.0 mV prime and 5.0 mV downgrade can be 5.0 V, these amplifiers are functional to 3.0 V @ 25°C
economically offered with high frequency performance although slight changes in parametrics such as bandwidth,
characteristics. This combination is ideal for low cost slew rate, and DC gain may occur.
precision, high speed quad op amp applications. If power to this integrated circuit is applied in reverse
The all NPN output stage, shown in its basic form on the polarity or if the IC is installed backwards in a socket, large
equivalent circuit schematic, offers unique advantages over unlimited current surges will occur through the device that
the more conventional NPN/PNP transistor Class AB may result in device destruction.
output stage. A 10 kΩ load resistance can swing within 1.0 V Special static precautions are not necessary for these
of the positive rail (VCC), and within 0.3 V of the negative bipolar amplifiers since there are no MOS transistors on
rail (VEE), providing a 28.7 Vpp swing from ±15 V supplies. the die.
This large output swing becomes most noticeable at lower As with most high frequency amplifiers, proper lead dress,
supply voltages. component placement, and PC board layout should
The positive swing is limited by the saturation voltage of be exercised for optimum frequency performance. For
the current source transistor Q7, and VBE of the NPN pull up example, long unshielded input or output leads may result in
transistor Q17, and the voltage drop associated with the short unwanted input–output coupling. In order to preserve the
circuit resistance, R7. The negative swing is limited by the relatively low input capacitance associated with these
saturation voltage of the pull–down transistor Q16, the amplifiers, resistors connected to the inputs should be
voltage drop ILR6, and the voltage drop associated with immediately adjacent to the input pin to minimize additional
resistance R7, where IL is the sink load current. For small stray input capacitance. This not only minimizes the input
valued sink currents, the above voltage drops are negligible, pole for optimum frequency response, but also minimizes
allowing the negative swing voltage to approach within extraneous “pick up” at this node. Supply decoupling with
millivolts of VEE. For large valued sink currents (>5.0 mA), adequate capacitance immediately adjacent to the supply pin
diode D3 clamps the voltage across R6, thus limiting the is also important, particularly over temperature, since many
negative swing to the saturation voltage of Q16, plus the types of decoupling capacitors exhibit great impedance
forward diode drop of D3 (≈VEE +1.0 V). Thus for a given changes over temperature.
supply voltage, unprecedented peak–to–peak output voltage The output of any one amplifier is current limited and thus
swing is possible as indicated by the output swing protected from a direct short to ground. However, under such
specifications. conditions, it is important not to allow the device to exceed
If the load resistance is referenced to VCC instead of the maximum junction temperature rating. Typically for ±15 V
ground for single supply applications, the maximum possible supplies, any one output can be shorted continuously to
output swing can be achieved for a given supply voltage. For ground without exceeding the maximum temperature rating.

MC34071,2,4,A MC33071,2,4,A
(Typical Single Supply Applications VCC = 5.0 V)
Figure 37. AC Coupled Noninverting Amplifer Figure 38. AC Coupled Inverting Amplifier
VCC
5.1 M VO
0 3.7 Vpp 0 3.7 Vpp
VCC
100 k
20 k Cin 1.0 M
+ CO VO 68 k
+
MC34071 Cin 10 k MC34071 VO
36.6 mVpp – – CO 10 k
Vin 100 k 10 k 100 k RL
RL Vin 370 mVpp
1.0 k AV = 101
AV = 10 BW (–3.0 dB) = 450 kHz
BW (–3.0 dB) = 45 kHz
Figure 39. DC Coupled Inverting Amplifer

Maximum Output Swing Figure 40. Unity Gain Buffer TTL Driver
2.5 V
VO
4.75 Vpp VCC 0 0 to 10,000 pF
2.63 V Vin + MC54/74XX
91 k MC34071
– Cable TTL Gate
5.1 k
RL
5.1 k
+
100 k
MC34071 VO
–
1.0 M Figure 42. Active Bandpass Filter
Vin AV = 10
BW (–3.0 dB) = 450 kHz
C R3
0.047 2.2 k
R1
Vin –
Figure 41. Active High–Q Notch Filter 1.1 k C MC34071 VO
R2 0.047 +
VCC
5.6 k fo = 30 kHz
Vin ≥ 0.2 Vdc Ho = 10
0.4 VCC Ho = 1.0
– VO
R R MC34071 Given fo = Center Frequency
Vin + AO = Gain at Center Frequency
16 k 16 k Choose Value fo, Q, Ao, C
C
Then: Q R3 R1 R3
0.01
R3 = R1 = R2 =
πfoC 2Ho 4Q2R1–R3
fo = 1.0 kHz
2.0 R Qofo
32 k For less than 10% error from operational amplifier < 0.1
1 GBW
fo =
4πRC where fo and GBW are expressed in Hz.
2.0 C 2.0 C GBW = 4.5 MHz Typ.
0.02 0.02

MC34071,2,4,A MC33071,2,4,A
Figure 43. Low Voltage Fast D/A Converter Figure 44. High Speed Low Voltage Comparator
CF
Vin
2.0 V
RF
Vin
+ VO
5.0 k 5.0 k 5.0 k
– VO MC34071 t
–
MC34071
+ 2.0 k VO
10 k 10 k 10 k VCC RL
1.0 V 0.2 µs
4.0 V Delay
Bit
Switches 13 V/µs
25 V/µs
(R–2R) Ladder Network
0.1 t
Settling Time
1.0 µs (8–Bits, 1/2 LSB) Delay
1.0 µs
Figure 45. LED Driver Figure 46. Transistor Driver
VCC VCC
“ON” VCC
Vin < Vref
RL
+ +
Vin +
MC34071 MC34071
MC34071 – –
–
Vref RL
“ON” (A) PNP (B) NPN

Vin > Vref
Figure 47. AC/DC Ground Current Monitor Figure 48. Photovoltaic Cell Amplifier
ILoad
RF
+ ICell –
MC34071 MC34071 VO
VO
– +
Ground Current RS
Sense Resistor
R1
R2 R1 VCell = 0 V
VO = ILoad RS 1+
R2 VO = ICell RF
VO > 0.1 V
For VO > 0.1V
R2
BW ( –3.0 dB) = GBW
R1+R2

MC34071,2,4,A MC33071,2,4,A
Figure 49. Low Input Voltage Comparator Figure 50. High Compliance Voltage to
with Hysteresis Sink Current Converter
VO Hysteresis
R2 Iout
Vref R1 VOH Vin

+ +
MC34071 MC34071
VOL
– –
Vin
Vin
VinL VinH
R1 Vref
VinL = (V –V )+V
R1+R2 OL ref ref
R1 Vin±VIO R
VinH = (V –V )+V Iout =
R1+R2 OH ref ref R
R1
VH = (VOH –VOL)
R1+R
Figure 51. High Input Impedance Figure 52. Bridge Current Amplifier
Differential Amplifier
+Vref
R1 R2
R4 RF
R R
– 1/2 R3
MC34072 – 1/2 VO – VO
+V1 + MC34072 MC34071
+ R = ∆R R +
+V2
R2
=
R4
(Critical to CMRR) ∆R RF
R1 R3 VO = Vref
RF 2R2
R4 R4 ∆R < < R
VO = 1 + V2–V1
R3 R3 RF > > R (VO ≥ 0.1 V)
For (V2 ≥ V1), V > 0
Figure 54. High Frequency Pulse

Figure 53. Low Voltage Peak Detector Width Modulation
fOSC ^ 0.85
+ IB
Vin RC V +
+ VO = Vin (pk) ISC
MC34071 VP 0 t
–
t – Base Charge
Removal
+ Iout
RL VP 10,000 pF
– 1/2 R + 1/2
MC34072 MC34072
C + – ±IB
Vin
VP V+ 100 k
100 k VP Pulse Width
47 k Control Group
OSC Comparator High Current

Output

MC34071,2,4,A MC33071,2,4,A
GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = ±15.0 V
Figure 55. Second Order Low–Pass Active Filter Figure 56. Second Order High–Pass Active Filter
C2 R1
0.02 C2
0.05 C1 46.1 k
1.0
R2
R1 R3 5.6 k –
560 510 C1 MC34071
– 1.0 fo = 100 Hz
R2 +
MC34071 1.1 k Ho = 20
C1 fo = 1.0 kHz
0.44 +
Ho = 10
Ho+0.5
Choose: fo, Ho, C1 Then: R1 =
Choose: fo, Ho, C2 πfoC1 Ǹ2
Then: C1 = 2C2 (Ho+1) Ǹ2
R2 =
2πfoC1 (1/Ho+2)
Ǹ2 R2 R2
R2 = R3 = R1 = C
4πfoC2 Ho+1 Ho C2 =
Ho
Figure 57. Fast Settling Inverter Figure 58. Basic Inverting Amplifier
CF*
VO = 10 V
RF Step +
MC34071 VO
2.0 k R1
– RL
– Vin R2
MC34071 VO
+
VO R2 R1
I = BW (–3.0 dB) = GBW
ts = 1.0 µs Vin R1 R1 +R2
Uncompensated
to 1/2 LSB (8–Bits)
SR = 13 V/µs
ts = 2.2 µs
High Speed Compensated
DAC to 1/2 LSB (12–Bits)
*Optional Compensation SR = 13 V/µs
Figure 59. Basic Noninverting Amplifier Figure 60. Unity Gain Buffer (AV = +1.0)
+
Vin +
MC34071 VO
MC34071 VO
–
Vin –
R2
RL
BWp = 200 kHz

R1 VO = 20 Vpp
VO R2
= 1+ SR = 10 V/µs
Vin R1
R1
BW (–3.0 dB) = GBW
R1 +R2

MC34071,2,4,A MC33071,2,4,A
Figure 61. High Impedance Differential Amplifier
+ R
R
MC34074
–
R
–
RE MC34074 VO
R +
–
R Example:
MC34074
Let: R = RE = 12 k R
+ Then: AV = 3.0 AV = 1 + 2
R BW = 1.5 MHz RE
Figure 62. Dual Voltage Doubler
+VO
+
+ +
MC34074
100 k – RL
10 10
+10
–
MC34074
220 pF +
100 k
–10
+
+ RL
+ 10
MC34074
RL +VO –VO 100 k – 10
∞ 18.93 –18.78
10 k 18 –18
–VO
5.0 k 15.4 –15.4

t MC34080
thru
High Slew Rate, Wide MC34085
Bandwidth, JFET Input
HIGH PERFORMANCE
These devices are a new generation of high speed JFET input monolithic
operational amplifiers. Innovative design concepts along with JFET JFET INPUT
technology provide wide gain bandwidth product and high slew rate. OPERATIONAL AMPLIFIERS
Well–matched JFET input devices and advanced trim techniques ensure low
input offset errors and bias currents. The all NPN output stage features large
output voltage swing, no deadband crossover distortion, high capacitive
drive capability, excellent phase and gain margins, low open loop output
impedance, and symmetrical source/sink AC frequency response.
This series of devices is available in fully compensated or
decompensated (AVCL≤2) and is specified over a commercial temperature 8
8
1
range. They are pin compatible with existing Industry standard operational 1
amplifiers, and allow the designer to easily upgrade the performance of P SUFFIX D SUFFIX
existing designs. PLASTIC PACKAGE PLASTIC PACKAGE
CASE 626 CASE 751
• Wide Gain Bandwidth: 8.0 MHz for Fully Compensated Devices (SO–8)
Wide Gain Bandwidth: 16 MHz for Decompensated Devices
• High Slew Rate: 25 V/µs for Fully Compensated Devices PIN CONNECTIONS
High Slew Rate: 50 V/µs for Decompensated Devices
• High Input Impedance: 1012Ω Offset Null 1 8 NC
• Input Offset Voltage: 0.5 mV Maximum (Single Amplifier) Inv. Input 2 – 7 VCC
• Large Output Voltage Swing: –14.7 V to +14 V for Noninv. Input 3 + 6 Output
Large Output Voltage Swing: VCC/VEE = ±15 V VEE 4 5 Offset Null
• Low Open Loop Output Impedance: 30 Ω @ 1.0 MHz (Single, Top View)
• Low THD Distortion: 0.01%
• Excellent Phase/Gain Margins: 55°/7.6 dB for Fully Compensated Output 1 1 8 VCC
Devices 2
–
7 Output 2
Inputs 1
3 + 6
–
+
Inputs 2
ORDERING INFORMATION VEE 4 5
Fully Operating (Dual, Top View)

Op Amp Compen- AVCL≥2 Temperature
Function sated Compensated Range Package
MC34081BD MC34080BD SO–8
Single
MC34081BP MC34080BP TA = 0° to +70°C Plastic DIP
Dual MC34082P MC34083BP Plastic DIP 16
14
MC34084DW MC34085BDW SO–16L 1
1
Quad TA = 0° to +70°C
MC34084P MC34085BP Plastic DIP P SUFFIX DW SUFFIX
CASE 646 CASE 751G
PIN CONNECTIONS (SO–16L)
Output 1 1 16 Output 4 Output 1 1 14 Output 4

2 15
– – 2 13
Inputs 1 Inputs 4 Inputs 1 – –
3 +
1 4
+ 14 + + Inputs 4
3 1 4 12
VCC 4 13 VEE VCC 4 11 VEE

5 + + 12
5 + 10
Inputs 2 – – Inputs 3 Inputs 2 +
6 2 3 11 – 2 3 – Inputs 3
6 9
Output 2 7 10 Output 3 Output 2 7 8 Output 3
NC 8 9 NC
(Quad, Top View)

MC34080 thru MC34085
MAXIMUM RATINGS
(TJ) is not exceeded.

(Each Amplifier)
VCC
200 µA 50 µA 850 µA
Q1
D1 Q6
R1
240 18
– J1 J2 Output
Inputs RSC 700
+ R2
5.0
CC pF D2
+ Q7
20 CM
CF pF
Q8
+ 3.0
pF
Q5
Q2
R3 R4 Q3
Q10 Q4
Q9 1.0 k 1.0 k
D3
500 R6
50 µA 500
Ω Q11
D4 100 µA 300 µA R7
66 k
VEE
1 5 RM
Null Adjust
(MC34080, 081)*
*Pins 1 & 5 (MC34080,081) should not be directly grounded or connected to VCC.

DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = – 15 V, TA = Tlow to Thigh [Note 3], unless otherwise noted.)
Single
TA = +25°C — 0.5 2.0
TA = 0° to +70°C (MC34080B, MC34081B) — — 4.0
Dual
TA = +25°C — 1.0 3.0
TA = 0° to +70°C (MC34082, MC34083) — — 5.0
Quad
TA = +25°C — 6.0 12
TA = 0° to +70°C (MC34084, MC34085) — — 14
Input Bias Current (VCM = 0 Note 5) IIB
TA = +25°C — 0.06 0.2 nA
TA = 0° to +70°C — — 4.0
Input Offset Current (VCM = 0 Note 5) IIO
TA = +25°C — 0.02 0.1 nA
TA = 0° to +70°C — — 2.0
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 k) AVOL V/mV

TA = +25°C 25 80 —
Output Voltage Swing VOH V
RL = 2.0 k, TA = +25°C 13.2 13.7 —
RL = 10 k, TA = +25°C 13.4 13.9 —
RL = 10 k, TA = Tlow to Thigh 13.4 — —
RL = 2.0 k, TA = +25°C VOL — –14.1 –13.5
RL = 10 k, TA = +25°C — –14.7 –14.1
RL = 10 k, TA = Tlow to Thigh — — –14.0
Output Short Circuit Current (TA = +25°C) ISC mA
Input Overdrive = 1.0 V, Output to Ground
Source 20 31 —
Sink 20 28 —
Input Common Mode Voltage Range VICR (VEE +4.0) to V

TA = +25°C (VCC – 2.0)
Common Mode Rejection Ratio (RS ≤ 10 k, TA = +25°C) CMRR 70 90 — dB

Power Supply Rejection Ratio (RS = 100 Ω, TA = 25°C) PSRR 70 86 — dB
Power Supply Current ID mA
Single
TA = +25°C — 2.5 3.4
TA = Tlow to Thigh — — 4.2
Dual
TA = +25°C — 4.9 6.0
TA = Tlow to Thigh — — 7.5
Quad
TA = +25°C — 9.7 11
NOTES: (continued)
3. Tlow = 0°C for MC34080B Thigh = +70°C for MC34080B
0°C for MC34081B +70°C for MC34081B
0°C for MC34084 +70°C for MC34084
0°C for MC34085 +70°C for MC34085
4. See application information for typical changes in input offset voltage due to solderability and temperature cycling.
5. Limits at TA = +25°C are guaranteed by high temperature (Thigh) testing.

AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = – 15 V, TA = +25°C, unless otherwise noted.)

Slew Rate (Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 100 pF) SR V/µs
Compensated AV = +1.0 20 25 —
AV = –1.0 — 30 —
Decompensated AV = +2.0 35 50 —
AV = –1.0 — 50 —
Settling Time (10 V Step, AV = –1.0) ts µs
To 0.10% (±1/2 LSB of 9–Bits) — 0.72 —
To 0.01% (±1/2 LSB of 12–Bits) — 1.6 —
Gain Bandwidth Product (f = 200 kHz) GBW MHz
Compensated 6.0 8.0 —
Decompensated 12 16 —
Power Bandwidth (RL = 2.0 k, VO = 20 Vpp, THD = 5.0%) BWp kHz
Compensated AV = +1.0 — 400 —
Decompensated AV = – 1.0 — 800 —
Phase Margin (Compensated) φm De-
RL = 2.0 k — 55 — grees
RL = 2.0 k, CL = 100 pF — 39 —
Gain Margin (Compensated) Am dB
RL = 2.0 k — 7.6 —
RL = 2.0 k, CL = 100 pF — 4.5 —
RS = 100 Ω, f = 1.0 kHz
Equivalent Input Noise Current (f = 1.0 kHz) In — 0.01 — pA/ √ Hz

Input Capacitance Ci — 5.0 — pF
Input Resistance ri — 1012 — Ω
AV = +10, RL = 2.0 k, 2.0 ≤ VO ≤ 20 Vpp, f = 10 kHz
Channel Separation (f = 10 kHz) — — 120 — dB

Open Loop Output Impedance (f = 1.0 MHz) Zo — 35 — Ω
Figure 1. Input Common Mode Voltage Range Figure 2. Input Bias Current
VICR , INPUT COMMON MODE VOLTAGE RANGE (V)

0 100 k
VCC/VEE = ±3.0 V to ±22 V VCC/VEE = ±15 V
∆VIO = 5.0 mA VCC VCM = 0 V
IIB , INPUT BIAS CURRENT (pA)
–1.0 10 k
3.0 1.0 k
2.0 100
1.0 10
VEE
0 1.0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125

Figure 3. Input Bias Current versus Figure 4. Output Voltage Swing

Input Common Mode Voltage versus Supply Voltage
140 50
VCC/VEE = ±15 V

120
40 RL Connected to Ground
TA = 25°C
TA = 25°C
100
30
RL = 10 k RL = 2.0 k
80
20
60
40 10
20 0
–12 –8.0 –4.0 0 4.0 8.0 12 0 ±5.0 ±10 ±15 ±20 ±25
VIC, INPUT COMMON MODE VOLTAGE (V) VCC |VEE|, SUPPLY VOLTAGE (V)
Figure 5. Output Saturation versus Figure 6. Output Saturation vesus

Load Current Load Resistance to Ground
0 0
VCC V sat , OUTPUT SATURATION VOLTAGE (V) VCC

–1.0 –2.0
Source VCC/VEE = ±15 V
TA = 25°C
VCC/VEE = +15 V to +22 V –4.0
–2.0
TA = 25°C
–3.0 2.0
1.0 Sink 1.0

VEE VEE
0 0
0 4.0 8.0 12 16 300 3.0 k 30 k 300 k
IL, LOAD CURRENT (±mA) RL, LOAD RESISTANCE TO GROUND (Ω)
Figure 7. Output Saturation versus Figure 8. Output Short Circuit Current

Load Resistance to VCC versus Temperature
40
0
VCC
–0.4 Source
30
Sink
–0.8
20
2.0
VCC/VEE = +15 V
RL to VCC 10 VCC/VEE = ±15 V
1.0
TA = 25°C RL ≤ 0.1 Ω
∆Vin = 1.0 V
VEE
0 0
300 3.0 k 30 k 300 k –55 –25 0 25 50 75 100 125
RL, LOAD RESISTANCE TO VCC (Ω) TA, AMBIENT TEMPERATURE (°C)

Figure 9. Output Impedance versus Frequency Figure 10. Output Impedance versus Frequency
80 80
VCC/VEE = ±15 V VCC/VEE = ±15 V
VCM = 0 VCM = 0
Z O , OUTPUT IMPEDANCE (Ω )
Z O , OUTPUT IMPEDANCE ( Ω )
VO = 0 VO = 0
60 60
∆IO = ±0.5 mA ∆IO = ±0.5 mA
TA = 25°C TA = 25°C
Compensated Decompensated
40 Units Only 40 Units Only
20 AV = 1.0 20
AV = 1000 AV = 100 AV = 10 AV = 1000 AV = 100 AV = 10
AV = 2.0
0 0
1.0 k 10 k 100 k 1.0 M 10 M 1.0 k 10 k 100 k 1.0 M 10 M
Figure 11. Output Voltage Swing

versus Frequency Figure 12. Output Distortion versus Frequency
28 0.5
VCC/VEE = ±15 V
AV = 1000
24 RL = 2.0 k THD, OUTPUT DISTORTION (%)

THD = 1.0% 0.4
20 TA = 25°C VCC/VEE = ±15 V
Compensated VO = 2.0 Vpp
16 Units AV = +1.0 Decompensated 0.3 RL = 2.0 k
Units AV = –1.0 TA = 25°C
12 *Compensated
0.2 Units Only
8.0 AV = 100
0.1
4.0 AV = 10
0 0 AV = 1.0*
10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k

versus Temperature
A VOL , OPEN LOOP VOLTAGE GAIN
1.08 VCC/VEE = ±15 V

VO = –10 V to +10 V
RL = 10 k
(dB NORMALIZED)
1.04 f ≤ 10 Hz
1.00
0.96
0.92
–55 –25 0 25 50 75 100 125


Figure 14. Open Loop Voltage Gain and Figure 15. Open Loop Voltage Gain and
Phase versus Frequency Phase versus Frequency
100 20

VCC/VEE = ±15 V 100

0

VO = 0 V

80 10
RL = 2.0 k
TA = 25°C 120
45 VCC/VEE = ±15 V Gain
0 Margin
Phase Gain VO = 0 V
60 Phase = 7.6 dB 140
TA = 25°C
90 –10 Margin
= 54° 1
40 160
–20 1 — Gain, RL = 2.0 k
135 2
2 — Gain, RL = 2.0 k, CL = 100 pF 180
20 –30 3 — Phase, RL = 2.0 k
Solid Line Curves — Compensated Units 4 — Phase, RL = 2.0 k, CL = 100 pF 3
180 200
Dashed Line Curves — Decompensated Units Compensated Units Only
0 –40 4
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M 1.0 2.0 3.0 5.0 7.0 10 20 30 50
Figure 16. Open Loop Voltage Gain and Figure 17. Normalized Gain Bandwidth
Phase versus Frequency Product versus Temperature
GBW, GAIN BANDWIDTH PRODUCT (NORMALIZED)

20 1.20
100
10 Gain
Margin 120 1.10 VCC/VEE = ±15 V
VCC/VEE = ±15 V RL = 2.0 k
= 5.5 dB
0 VO = 0 V
TA = 25°C Phase 140
–10 Margin 1.00
= 43° 160
–20 1 — Gain, RL = 2.0 k
2 — Gain, RL = 2.0 k, CL = 100 pF 180 0.90
–30 3 — Phase, RL = 2.0 k
4 — Phase, RL = 2.0 k, CL = 100 pF
200
Decompensated Units Only
–40 0.80
1.0 2.0 3.0 5.0 7.0 10 20 30 50 –55 –25 0 25 50 75 100 125
Figure 18. Percent Overshoot versus Figure 19. Phase Margin versus
100 70
VCC/VEE = ±15 V
R
φ M , PHASE MARGIN (DEGREES)
Decompensated 60 Compensated
Units AV = +2.0 Units AV = +1.0 RL = 2.0 k to
80
∆VO = 100 mVpp
PERCENT OVERSHOOT
50 VO = –10 V to +10 V
60 TA = 25°C
40
Compensated
Units AV = +1.0 30
40
VCC/VEE = ±15 V
RL = 2.0 k 20
Decompensated
20 ∆VO = 100 mVpp Units AV = +2.0
VO = –10 V to +10 V 10
TA = 25°C
0 0
10 100 1.0k 10 100 1.0k

Figure 20. Gain Margin versus Load Capacitance Figure 21. Phase Margin versus Temperature
10 60
VCC/VEE = ±15 V

Compensated
RL = 2.0 k to ∞ 50 Solid Line Curves–Compensated Units AV = +1.0
Units AV = +1.0
8.0 ∆VO = 100 mVpp CL = 10 pF Dashed Line Curves–Decompensated Units AV = +2.0
VO = –10 V to +10 V
TA = 25°C 40
6.0
30 CL = 100 pF
4.0
20
Decompensated CL = 360 pF
2.0 Units AV = +2.0 10
VCC/VEE = ±15 V ∆VO = 100 mVpp
CL = 200 pF RL = 2.0 k to ∞ VO = –10 V to +10 V
0 0
10 100 10 k –55 –25 0 25 50 75 100 125
CL, LOAD CAPACITANCE (pF) TA, AMBIENT TEMPERATURE (°C)
Figure 23. Normalized Slew Rate

Figure 22. Gain Margin versus Temperature versus Temperature
10 1.40
Solid Line Curves–Compensated Units AV = +1.0
VCC/VEE = ±15 V
Dashed Line Curves–Decompensated Units AV = +2.0
8.0 AV = +1.0 for Compensated Units
1.20 AV = –1.0 for Decompensated Units

RL = 2.0 k
CL = 10 pF ∆VO = 100 mVpp CL = 100 pF
6.0 VCC/VEE = ±15 V VO = –10 V to +10 V
RL = 2.0 k to ∞ VO = –10 V to +10 V 1.00
4.0
CL = 100 pF CL = 200 pF 0.80

2.0
CL = 360 pF
0 0.60
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125

MC34084 Transient Response

AV = +1.0, RL = 2.0 k, VCC/VEE = ±15 V, TA = 25°C
Figure 24. Small Signal Figure 25. Large Signal
CL = 10 pF CL = 100 pF
5.0 mV/Div
50 mV/Div
0
0
0.2 µs/Div 0.5 µs/Div
MC34085 Transient Response

AV = +2.0, RL = 2.0 k, VCC/VEE = ±15 V, TA = 25°C
Figure 26. Small Signal Figure 27. Large Signal
CL = 10 pF CL = 100 pF
5.0 mV/Div
50 mV/Div
0 0
0.2 µs/Div 0.5 µs/Div

Figure 28. Common Mode Rejection Ratio Figure 29. Power Supply Rejection Ratio
PSSR, POWER SUPPLY REJECTION RATIO (dB)

CMRR, COMMON MODE REJECTION RATIO (dB)
100 120
TA = 25°C TA = –55°C VCC/VEE = ±15 V VCC/VEE = ±15 V
∆VS = 3.0 V ∆VS = 3.0 V
80 TA = 125°C 100
VO = 0 V VO = 0 V
TA = 25°C
80
60
Positive
60 Supply
VCC ± ∆VCC VCC ± ∆VCC
40
+ 40 +
VO
VO –
–
20 Negative
Compensated Units AV = +1.0 20
Supply
VEE ± ∆VEE Decompensated Units AV = +2.0 VEE ± ∆VEE
0 0
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
Figure 30. Power Supply Rejection Ratio Figure 31. Normalized Supply Current
PSSR, POWER SUPPLY REJECTION RATION (dB)
110 1.20
I CC , SUPPLY CURRENT (NORMALIZED)
TA = 125°C
Negative 1.10
100 VCC/VEE = ±15 V
Supply
∆VS = 3.0 V
VO = 0 V 1.00
f ≤ 10 Hz TA = 25°C
90
Supply Current
VCC ± ∆VCC 0.90 Normalized to
Positive
+
VO Supply VCC/VEE = ±15 V, TA = 25°C
80 – RL = ∞
0.80 VO = 0
Compensated Units AV = +1.0
VEE ± ∆VEE Decompensated Units AV = +2.0 TA = –55°C
70 0.70
–55 –25 0 25 50 75 100 125 0 ±5.0 ±10 ±15 ±20 ±25
TA, AMBIENT TEMPERATURE (°C) VS, SUPPLY VOLTAGE (V)
Figure 32. Channel Separation versus Frequency Figure 33. Spectral Noise Density
120 100
e n , INPUT NOISE VOLTAGE (nV/ √ Hz )
100 VCC/VEE = ±15 V

CHANNEL SEPERATION (dB)
80
VCM = 0
80 TA = 25°C
60
60
40
40
VCC/VEE = ±15 V
20 TA = 25°C 20
0 0
10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k

The bandwidth and slew rate of the MC34080 series is input stage also allows a differential up to ±44 V, provided the
nearly double that of currently available general purpose maximum input voltage range is not exceeded. The supply
JFET op–amps. This improvement in AC performance is due voltage operating range is from ±5.0 V to ±22 V.
to the P–channel JFET differential input stage driving a For optimum frequency performance and stability, careful
compensated miller integration amplifier in conjunction with component placement and printed circuit board layout should
an all NPN output stage. be exercised. For example, long unshielded input or output
The all NPN output stage offers unique advantages over leads may result in unwanted input–output coupling. In order
the more conventional NPN/PNP transistor Class AB output to reduce the input capacitance, resistors connected to the
stage. With a 10 k load resistance, the op amp can typically input pins should be physically close to these pins. This not
swing within 1.0 V of the positive rail (VCC), and within 0.3 V only minimizes the input pole for optimum frequency
of the negative rail (VEE), providing a 28.7 p–p swing from response, but also minimizes extraneous “pickup” at
±15 V supplies. This large output swing becomes most this node.
noticeable at lower supply voltages. If the load resistance is Supply decoupling with adequate capacitance close to the
referenced to VCC instead of ground, the maximum possible supply pin is also important, particularly over temperature,
output swing can be achieved for a given supply voltage. For since many types of decoupling capacitors exhibit large
light load currents, the load resistance will pull the output to impedance changes over temperature.
VCC during the positive swing and the NPN output transistor Primarily due to the JFET inputs of the op amp, the input
will pull the output very near VEE during the negative swing. offset voltage may change due to temperature cycling and
The load resistance value should be much less than that of board soldering. After 20 temperature cycles (– 55° to
the feedback resistance to maximize pull–up capability. 165°C), the typical standard deviation for input offset voltage
The all NPN transistor output stage is also inherently is 559 µV in the plastic packages. With respect to board
fast, contributing to the operation amplifier ’s high soldering (260°C, 10 seconds), the typical standard deviation
gain–bandwidth product and fast settling time. The for input offset voltage is 525 µV in the plastic package.
associated high frequency output impedance is 50 Ω (typical) Socketed devices should be used over a minimal
at 8.0 MHz. This allows driving capacitive loads from 0 pF to temperature range for optimum input offset voltage
300 pF without oscillations over the military temperature performance.
range, and over the full range of output swing. The 55°C
phase margin and 7.6 dB gain margin as well as the general
gain and phase characteristics are virtually independent of Figure 34. Offset Nulling Circuit
the sink/source output swing conditions. The high frequency VCC
characteristics of the MC34080 series is especially useful for
active filter applications.
3 + 7
The common mode input range is from 2.0 V below the
6
positive rail (VCC) to 4.0 V above the negative rail (VEE). The 2
– 5
amplifier remains active if the inputs are biased at the positive
1
rail. This may be useful for some applications in that single 4
supply operation is possible with a single negative supply. 5.0 k
However, a degradation of offset voltage and voltage gain
may result.
Phase reversal does not occur if either the inverting or
noninverting input (or both) exceeds the positive common
mode limit. If either input (or both) exceeds the negative VEE
common mode limit, the output will be in the high state. The

MC34181,2,4
MC33181,2,4
Low Power, High Slew Rate,
Wide Bandwidth, JFET Input
Quality bipolar fabrication with innovative design concepts are employed
for the MC33181/2/4, MC34181/2/4 series of monolithic operational 8
8 1
amplifiers. This JFET input series of operational amplifiers operates at 1
210 µA per amplifier and offers 4.0 MHz of gain bandwidth product and P SUFFIX D SUFFIX
10 V/µs slew rate. Precision matching and an innovative trim technique of PLASTIC PACKAGE PLASTIC PACKAGE
the single and dual versions provide low input offset voltages. With a JFET CASE 626 CASE 751
input stage, this series exhibits high input resistance, low input offset voltage (SO–8)
and high gain. The all NPN output stage, characterized by no deadband
crossover distortion and large output voltage swing, provides high PIN CONNECTIONS
capacitance drive capability, excellent phase and gain margins, low open
loop high frequency output impedance and symmetrical source/sink AC Offset Null 1 8 NC
frequency response. 2 – 7 VCC
The MC33181/2/4, MC34181/2/4 series of devices are specified over the Inputs
3 + 6 Output
commercial or industrial/vehicular temperature ranges. The complete series
VEE 4 5 Offset Null
of single, dual and quad operational amplifiers are available in the plastic
DIP as well as the SOIC surface mount packages. (Single, Top View)
• Low Supply Current: 210 µA (Per Amplifier)
• Wide Supply Operating Range: ±1.5 V to ±18 V Output 1 1 8 VCC
• Wide Bandwidth: 4.0 MHz 2
–
1 7 Output 2
Inputs 1
• High Slew Rate: 10 V/µs 3 + 2
–
6
Inputs 2
•
+
VEE 4 5
Low Input Offset Voltage: 2.0 mV
• Large Output Voltage Swing: –14 V to +14 V (with ±15 V Supplies) (Dual, Top View)
• Large Capacitance Drive Capability: 0 pF to 500 pF

• Excellent Phase Margin: 67°
• Excellent Gain Margin: 6.7 dB 14 14
1
•
1
Output Short Circuit Protection
• Offered in New TSSOP Package Including the Standard SOIC and
P SUFFIX
PLASTIC PACKAGE
D SUFFIX
PLASTIC PACKAGE
DIP Packages CASE 646 CASE 751A
(SO–14)
ORDERING INFORMATION 14
1
Op Amp Operating
Function Device Temperature Range Package DTB SUFFIX
PLASTIC PACKAGE
Single MC34181P Plastic DIP CASE 948G
TA = 0° to +70°C
MC34181D SO–8 (TSSOP–14)
MC33181P Plastic DIP PIN CONNECTIONS
TA = –40° to +85°C
MC33181D SO–8
Dual MC34182P Plastic DIP Output 1 1 14 Output 4
TA = 0° to +70°C
MC34182D SO–8
2 13
Inputs 1 – –– Inputs 4
MC33182P Plastic DIP 3
+
1 4
+
12
TA = –40° to +85°C
MC33182D SO–8
VCC 4 11 VEE
Quad MC34184P Plastic DIP
MC34184D TA = 0° to +70°C SO–14 5 +
10
+
Inputs 2 – –
Inputs 3
MC34184DTB TSSOP–14 6 2 3 9
MC33184P Plastic DIP Output 2 7 8 Output 3

MC33184D TA = –40° to +85°C SO–14
MC33184DTB TSSOP–14 (Quad, Top View)

MC34181,2,4 MC33181,2,4
MAXIMUM RATINGS
Input Voltage Range VIR Note 1 V
exceeded (see Figure 1).

(Each Amplifier)
Internal VCC
Bias Q8
Network Q9
Q7
Neg Pos
J1 J2 D1 D3
C1
+
R6
Q1 D2 R7
Q4 VO
Q2 Q3 C2
R1 R2 Q5 Q6
I3
I4
R3 R4
R5
VEE
1 5
Null Offsets
MC3X181 (Single) Only
–
+
5
1 VEE
25 kΩ
MC3X181 Input Offset

Voltage Null CIrcuit

MC34181,2,4 MC33181,2,4
Input Offset Voltage (RS = 50 Ω, VO = 0 V) VIO mV
Single
TA = +25°C — 0.5 2.0
TA = 0° to +70°C (MC34181) — — 3.0
TA = –40° to +85°C (MC33181) — — 3.5
Dual
TA = +25°C — 1.0 3.0
TA = 0° to +70°C (MC34182) — — 4.0
TA = –40° to +85°C (MC33182) — — 4.5
Quad
TA = +25°C — 4.0 10
TA = 0° to +70°C (MC34184) — — 11
TA = –40° to +85°C (MC33184) — — 11.5
Average Temperature Coefficient of VIO (RS = 50 Ω, VO = 0V) ∆VIO/∆T — 10 — µV/°C
Input Offset Current (VCM = 0 V, VO = 0V) IIO nA
TA = +25°C — 0.001 0.05
TA = 0° to +70°C — — 1.0
TA = –40° to +85°C — — 2.0
Input Bias Current (VCM = 0 V, VO = 0V) IIB nA
TA = +25°C — 0.003 0.1
TA = 0° to +70°C — — 2.0
TA = –40° to +85°C — — 4.0
Input Common Mode Voltage Range VICR (VEE +4.0 V) to (VCC –2.0 V) V
Large Signal Voltage Gain (RL = 10 kΩ, VO = ±10 V) AVOL V/mV
TA = +25°C 25 60 —
Output Voltage Swing (VID = 1.0 V, RL = 10 kΩ) VO+ +13.5 +14 — V

TA = +25°C VO– — –14 –13.5
Common Mode Rejection (RS = 50 Ω, VCM = VICR, VO = 0 V) CMR 70 86 — dB

Power Supply Rejection (RS = 50 Ω, VCM = 0 V, VO = 0 V) PSR 70 84 — dB
Output Short Circuit Current (VID = 1.0 V, Output to Ground) ISC mA
Source 3.0 8.0 —
Sink 8.0 11 —
Power Supply Current (No Load, VO = 0 V) ID µA

Single
TA = +25°C — 210 250
Dual
TA = +25°C — 420 500
Quad
TA = +25°C — 840 1000

MC34181,2,4 MC33181,2,4
Slew Rate (Vin = –10 V to +10 V, RL = 10 kΩ, CL = 100 pF) SR V/µs
AV = +1.0 7.0 10 —
AV = –1.0 — 10 —
Settling Time (AV = –1.0, RL = 10 kΩ, VO = 0 V to +10 V Step) ts µs

To Within 0.10% — 1.1 —
To Within 0.01% — 1.5 —
Gain Bandwidth Product (f = 100 kHz) GBW 3.0 4.0 — MHz

Power Bandwidth (AV = +1.0, RL = 10 kΩ, VO = 20 Vpp, THD = 5.0%) BWp — 120 — kHz
Phase Margin (–10 V < VO < +10 V) fm Degrees
RL = 10 kΩ — 67 —
RL = 10 kΩ, CL = 100 pF — 34 —
Gain Margin (–10 V < VO < +10 V) Am dB
RL = 10 kΩ — 6.7 —
RL = 10 kΩ, CL = 100 pF — 3.4 —
RS = 100 Ω, f = 1.0 kHz
Equivalent Input Noise Current in — 0.01 — pA/ √ Hz

f = 1.0 kHz
Differential Input Capacitance Ci — 3.0 — pF

Differential Input Resistance Ri — 1012 — W
AV = 10, RL = 10 kΩ, 2.0 Vpp < VO < 20 Vpp, f = 1.0 kHz
Channel Separation (RL = 10 kΩ, –10 V < VO < +10 V, 0 Hz < f < 10 kHz) — — 120 — dB
Open Loop Output Impedance |Zo| — 200 — Ω
(f = 1.0 MHz)
Figure 1. Maximum Power Dissipation versus Figure 2. Input Common Mode Voltage Range
Temperature for Package Variations versus Temperature
2400 0
V ICR, INPUT COMMON MODE VOLTAGE
VCC = +3.0 V to +15 V VCC (VCM to VCC)

2000 –1.0 VEE = –3.0 V to –15 V
8/14 Pin ∆VIO = 5.0 mV
1600 Plastic –2.0
RANGE (V)
TSSOP–14
1200 SO–14 3.0
800 2.0
SO–8
400 1.0
VEE
0 0
–55 –40 –20 0 20 40 60 80 100 120 140 160 –55 –25 0 25 50 75 100 125

MC34181,2,4 MC33181,2,4
Figure 3. Input Bias Current Figure 4. Input Bias Current versus

versus Temperature Input Common Mode Voltage
1000 20
VCC = +15 V
VCC = +15 V

100 VEE = –15 V VEE = –15 V
VCM = 0 V 15 TA = 25°C
10
1.0 10
0.1
5
0.01
0.001 0
–55 –25 0 25 50 75 100 125 –10 –5.0 0 5.0 10
TA, AMBIENT TEMPERATURE (°C) VICR, INPUT COMMON MODE VOLTAGE (V)

40 0
RL Connected to Ground V sat , OUTPUT SATURATION VOLTAGE (V) VCC
–1.0
VO, OUTPUT VOLTAGE SWING (V)
TA = 25°C
VCC = +15 V Source
30 –2.0 VEE = –15 V
–3.0 TA = +25°C
20
RL = 10 k
+3.0
10 +2.0
Sink
+1.0 VEE
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
VCC, |VEE|, SUPPLY VOLTAGE (V) IL, LOAD CURRENT (mA)
Figure 7. Output Saturation Voltage versus Figure 8. Output Saturation Voltage versus
Load Resistance to Ground Load Resistance to VCC
0 0
VCC VCC
–1.0 –1.0
VCC = +15 V
–2.0 VEE = –15 V –2.0
TA = +25°C
–3.0 –3.0
3.0 3.0
VCC = +15 V
2.0 2.0 VEE = –15 V
TA = +25°C
1.0 1.0
VEE VEE
0 0
1.0 k 10 k 100 k 1.0 M 1.0 k 10 k 100 k 1.0 M
RL, LOAD RESISTANCE TO GROUND (Ω) RL, LOAD RESISTANCE (Ω)

MC34181,2,4 MC33181,2,4
Figure 9. Output Short Circuit Current

versus Temperature Figure 10. Output Impedance versus Frequency
30
VCC = +15 V VCC = +15 V
VEE = –15 V 300 VEE = –15 V
|Z O |, OUTPUT IMPEDANCE ( Ω )
RL ≤ 0.1 Ω VCM = 0 V
VID = 1.0 V VO = 0 V
20 ∆IO = 10 µA
200 TA = 25°C
Sink AV = 1000
100 10 1.0
10
100
Source
0 0
–55 –25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M
Figure 11. Output Voltage Swing Figure 12. Output Distortion versus
versus Frequency Frequency
30 1.0
VO , OUTPUT VOLTAGE SWING (V p–p )
VCC = +15 V VCC = +15 V

VEE = –15 V VEE = –15 V
24 0.8 VO = 2.0 Vpp
RL = 10 kΩ
THD = 1.0% RL = 10 kΩ
TA = 25°C TA = 25°C
18 0.6
AV = 1000
12 0.4
100
6 0.2 10
1.0
0 0
1.0 k 10 k 109 k 1.0 M 10 100 1.0 k 10 k 100 k
Figure 13. Open Loop Voltage Gain Figure 14. Open Loop Voltage Gain and
versus Temperature Phase versus Frequency
A VOL, OPEN LOOP VOLTAGE GAIN (V/mV)
70 100
VCC = +15 V
60 VEE = –15 V
80 VO = 0 V 0
Gain
RL = 10 kΩ
50 TA = 25°C
60 45
Phase
40 40 90
VCC = +15 V
VEE = –15 V
30 RL = 10 kΩ 20 135
f ≤ 10 Hz
TA = 25°C
20 0 180
–55 –25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M

MC34181,2,4 MC33181,2,4
Figure 15. Normalized Gain Bandwidth Figure 16. Output Voltage Overshoot
Product versus Temperature versus Load Capacitance
GBW, GAIN BANDWIDTH PRODUCT (NORMALIZED)
1.3 100
V OS , OUTPUT VOLTAGE OVERSHOOT (%)

VCC = +15 V VCC = +15 V
1.2 VEE = –15 V VEE = –15 V
80 RL = 10 kΩ
RL = 10 kΩ
∆VO = 100 mVpp
1.1 –10 V < VO < +10 V
60 AV = +1.0
1.0 TA = 25°C
40
0.9
20
0.8
0.7 0
–55 –25 0 25 50 75 100 125 10 100 1.0 k
TA, AMBIENT TEMPERATURE (°C) CL, LOAD CAPACITANCE (pF)
Figure 17. Phase Margin versus Figure 18. Gain Margin versus
70 10
VCC = +15 V VCC = +15 V
, PHASE MARGIN (DEGREES)
60 VEE = –15 V VEE = –15 V

RL = 10 kΩ to ∞ 8.0 RL = 10 kΩ to ∞
50 –10 V < VO < +10 V –10 V < VO < +10 V

TA = 25°C TA = 25°C
40 6.0
30
4.0
20
2.0
m
10
φ
0 0
10 100 1.0 k 10 100 1.0 k
Figure 19. Phase Margin Figure 20. Gain Margin

70 10
CL = 10 pF 9.0
60
8.0
CL = 10 pF
50 7.0
6.0
40 CL = 100 pF 5.0
CL = 100 pF
4.0
30
VCC = +15 V 3.0 VCC = +15 V
VEE = –15 V 2.0 VEE = –15 V
20
RL = 10 kΩ to ∞ RL = 10 kΩ to ∞
–10 V < VO < +10 V 1.0 –10 V < VO < +10 V
10 0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125

MC34181,2,4 MC33181,2,4
Figure 21. Normalized Slew Rate Figure 22. Common Mode Rejection
1.1 140

VCC = +15 V –
1.0 120 VEE = –15 V ∆VCM ADM ∆VO

∆VCM = 3.0 V +
100 TA = 25°C
0.9 ∆VCM
CMR = 20 Log X ADM
80 ∆VO
0.8
VCC = +15 V 60
0.7 VEE = –15 V
AV = +1.0 40
RL = 10 kΩ
0.6 CL = 100 pF 20
Vin = –10 V to +10 V
0.5 0
–55 –25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M
Figure 23. Input Noise Voltage Figure 24. Power Supply Rejection
100 110

VCC = +15 V
en , INPUT NOISE VOLTAGE ( nV/ √ Hz )
VEE = –15 V Positive Supply

80 VCM = 0 V
TA = 25°C
100
60
∆VCC, ∆VEE = 3.0 V
f ≤ 10 Hz
40
90
20 Negative Supply
0 80
10 100 1.0 k 10 k 100 k –55 –25 0 25 50 75 100 125
f, FREQUENCY (Hz) TA < AMBIENT TEMPERATURE (°C)
Figure 25. Power Supply Rejection Figure 26. Normalized Supply Current
|IEE |, I CC , SUPPLY CURRENT (NORMALIZED)
140 1.2
∆VO/ADM
120 +PSR = 20Log
∆VCC
+PSR (∆VCC = ±1.5 V) 1.1
100 ∆VO/ADM
–PSR = 20Log
–PSR (∆VEE = ±1.5 V) ∆VEE TA = 25°C
80 1.0
125°C
60 –55°C
0.9
VCC = +15 V VCC = +15 V
40 VEE = –15 V ∆VCC VEE = –15 V
TA = 25°C –
ADM ∆VO
0.8 TA = 25°C
20 + RL = ∞
∆VEE VO = 0V
0 0.7
100 1.0 k 10 k 100 k 1.0 M 0 5.0 10 15 20

MC34181,2,4 MC33181,2,4
Figure 27. Channel Separation versus Frequency Figure 28. Transient Response
140
VCC = +15 V

120 VEE = –15 V
CHANNEL SEPARATION (dB)
RL = 10 kΩ
100 AV = +1.0
TA = 25°C
80
60
40 VCC = +15 V
VEE = –15 V
20 TA = +25°C
0
10 k 100 k 1.0 M 10 M t, TIME (2.0 µs/DIV)
f, FREQUENCY (Hz)
Figure 29. Small Signal Transient Reponse
VCC = +15 V
V O , OUTPUT VOLTAGE (20 mV/DIV)
VEE = –15 V
RL = 10 kΩ
AV = +1.0
TA = 25°C

TCA0372
Advance Information
Dual Power Operational
DW SUFFIX
PLASTIC PACKAGE 16
Amplifier
CASE 751G 1
SOP (12+2+2)L
The TCA0372 is a monolithic circuit intended for use as a power

DP2 SUFFIX
operational amplifier in a wide range of applications, including servo PLASTIC PACKAGE
amplifiers and power supplies. No deadband crossover distortion provides 16 CASE 648
better performance for driving coils. 1
• Output Current to 1.0 A

DP1 SUFFIX
• Slew Rate of 1.3 V/µs PLASTIC PACKAGE
• Wide Bandwidth of 1.1 MHz CASE 626 8
1
• Internal Thermal Shutdown
• Single or Split Supply Operation
• Excellent Gain and Phase Margins
PIN CONNECTIONS
• Common Mode Input Includes Ground
• Zero Deadband Crossover Distortion TCA0372DP2
Output A 1 16 Gnd
VCC 2 15 Gnd
Output B 3 14 Gnd
VEE/Gnd 4 13 Gnd
– +
5 12 Gnd
Representative Block Diagram Inputs B
6 11 Gnd
VCC + –
7 10 Gnd
Inputs A
Current 8 9 Gnd
Bias
Monitoring (Top View)
*Pins 4 and 9 to 16 are internally connected.
Inv.
Input TCA0372DW
VCC 1 16 Output A
Output
Output B 2 15 NC
Noninv. NC 3 14 NC
Input
4 13
Thermal VEE/Gnd VEE/Gnd
Protection 5 12
NC 6 11 NC
Inputs –B 7 10 Input –A
VEE
Inputs +B 8 9 Input +A
(Top View)
TCA0372DP1
Operating
Device Temperature Range Package 8
Output A 1 –
Inputs A
+
TCA0372DW SOP (12+2+2) L VCC 2 7
TCA0372DP1 TJ = –40° to +150°C Plastic DIP Output B 3 + 6
Inputs B
– 5
TCA0372DP2 Plastic DIP VEE/Gnd 4
(Top View)

TCA0372
MAXIMUM RATINGS
Supply Voltage (from VCC to VEE) VS 40 V
Junction Temperature (Note 2) TJ +150 °C
DC Output Current IO 1.0 A
Peak Output Current (Nonrepetitive) I(max) 1.5 A
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL connected to ground, TJ = –40° to +125°C.)
Input Offset Voltage (VCM = 0) VIO mV
TJ = +25°C — 1.0 15
TJ, Tlow to Thigh — — 20
Input Bias Current (VCM = 0) IIB — 100 500 nA
Input Offset Current (VCM = 0) IIO — 10 50 nA
Large Signal Voltage Gain AVOL 30 100 — V/mV
VO = ±10 V, RL = 2.0 k
Output Voltage Swing (IL = 100 mA) VOH V
TJ = +25°C 14.0 14.2 —
TJ = Tlow to Thigh 13.9 — —
TJ = +25°C VOL — –14.2 –14.0
TJ = Tlow to Thigh — — –13.9
Output Voltage Swing (IL = 1.0 A) VOH V
VCC = +24 V, VEE = 0 V, TJ = +25°C 22.5 22.7 —
VCC = +24 V, VEE = 0 V, TJ = Tlow to Thigh 22.5 — —
VCC = +24 V, VEE = 0 V, TJ = +25°C VOL — 1.3 1.5
VCC = +24 V, VEE = 0 V, TJ = Tlow to Thigh — — 1.5
TJ = +25°C VEE to (VCC –1.0)
TJ = Tlow to Thigh VEE to (VCC –1.3)
Common Mode Rejection Ratio (RS = 10 k) CMRR 70 90 — dB
Power Supply Rejection Ratio (RS = 100 Ω) PSRR 70 90 — dB
Power Supply Current ID mA
TJ = +25°C — 5.0 10
TJ = Tlow to Thigh — — 14
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL connected to ground, TJ = +25°C, unless otherwise noted.)
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 k, CL = 100 pF) SR 1.0 1.4 — V/µs
AV = –1.0, TJ = Tlow to Thigh
Gain Bandwidth Product (f = 100 kHz, CL = 100 pF, RL = 2.0 k) GBW MHz
TJ = 25°C 0.9 1.4 —
TJ = Tlow to Thigh 0.7 — —
Phase Margin TJ = Tlow to Thigh φm — 65 — Degrees
RL = 2.0 k, CL = 100 pF
Gain Margin Am — 15 — dB
RL = 2.0 k, CL = 100 pF
RS = 100 Ω, f = 1.0 to 100 kHz
AV = –1.0, RL = 50 Ω, VO = 0.5 VRMS, f = 1.0 kHz
NOTE: In case VEE is disconnected before VCC, a diode between VEE and Ground is recommended to avoid damaging the device.

TCA0372
Figure 1. Supply Current versus Suppy Voltage Figure 2. Output Saturation Voltage
with No Load versus Load Current
6.5 VCC

VCC = 24 V
VEE = 0 V
VCC–1.0
5.5
VCC–2.0
4.5
VCC+2.0
3.5
VCC+1.0
2.5 VEE
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 0.5 1.0
VCC, |VEE|, SUPPLY VOLTAGE (V) IL, LOAD CURRENT (A)
Figure 3. Voltage Gain and Phase Figure 4. Phase Margin versus Output
versus Frequency Load Capacitance
80 80 70
VCC = +15 V VCC = +15 V
VEE = –15 V φ m , PHASE MARGIN (DEGREES) VEE = –15 V
60 RL = 2.0 kΩ 90 60 RL = 2.0 kΩ
PHASE (DEGREES)
AV = –100
GAIN (dB)
40 100 50
20 110 40
120 30
–20 130 20
1.0 10 100 1000 10000 0 0.4 0.8 1.2 1.6 2.0
f, FREQUENCY (kHz) CL, OUTPUT LOAD CAPACITANCE (nF)
VCC = +15 V VCC = +15 V

VO,OUTPUT VOLTAGE (50 mV/DIV)
VEE = –15 V VEE = –15 V

AV = +1.0 AV = +1.0
RL = 2.0 kΩ RL = 2.0 kΩ

TCA0372
Figure 7. Sine Wave Reponse Figure 8. Bidirectional DC Motor Control with

Microprocessor–Compatible Inputs
VCC = +15 V
VEE = –15 V VCC
AV = +100
5.0 V/DIV
RL = 50 Ω E1 + + E2
VS/2 – –
VS = Logic Supply Voltage

200 mV/DIV
Must Have VCC > VS

E1, E2 = Logic Inputs
t, TIME (100
µs/DIV)
Figure 9. Bidirectional Speed Control of DC Motors
VS
Rx 0.1 µF
0.1 µF
R7 10 k
Vin R1
+ +
10 k R3
– 5.0 Ω –
R6 R8 10 k
10 k
R2 R5
10 k 10 k
2R3 R1
For circuit stability, ensure that Rx >
@
where, RM = internal resistance of motor.
RM
The voltage available at the terminals of the motor is: VM +
2 (V1 – S)
V
2
)
|Ro| IM @
where, |Ro| =
2R3 R1 @ and IM is the motor current.
Rx
THERMAL INFORMATION
The maximum power consumption an integrated circuit This must be greater than the sum of the products of the
can tolerate at a given operating ambient temperature can be supply voltages and supply currents at the worst case
found from the equation: operating condition.
TJ(max) = Maximum operating junction temperature
TJ(max)–TA as listed in the maximum ratings section.
PD(TA) = TA = Maximum desired operating ambient
RθJA (typ)
temperature.
where, PD(TA) = power dissipation allowable at a given RθJA(typ) = Typical thermal resistance junction–to–
operating ambient temperature. ambient.

TL062
TL064
Low Power JFET Input
These JFET input operational amplifiers are designed for low power LOW POWER JFET INPUT
applications. They feature high input impedance, low input bias current and OPERATIONAL AMPLIFIERS
low input offset current. Advanced design techniques allow for higher slew
rates, gain bandwidth products and output swing.
The commercial and vehicular devices are available in Plastic dual in–line SEMICONDUCTOR
and SOIC packages. TECHNICAL DATA
• Low Supply Current: 200 µA/Amplifier
• Low Input Bias Current: 5.0 pA
• High Gain Bandwidth: 2.0 MHz DUAL
• High Input Impedance: 1012 Ω 8
8
1
• Large Output Voltage Swing: ±14 V 1
• Output Short Circuit Protection P SUFFIX

PLASTIC PACKAGE
D SUFFIX
PLASTIC PACKAGE
CASE 626 CASE 751
(SO–8)
(Each Amplifier) PIN CONNECTIONS
VCC
Output 1 1 8 VCC
2
–
7 Output 2
Inputs 1 +
3 6
–
+
Inputs 2
Q7 VEE 4 5
– J1 J2 (Top View)
D2
Inputs R3 R4
+
+ D1 Output
QUAD
Q4 C1
Q3
C2 14 14
Q1 Q2 Q5 1
1
Q6
N SUFFIX D SUFFIX
R1 R2 CASE 646 CASE 751A
R5 VEE (SO–14)
PIN CONNECTIONS
Op Amp Operating
Function Device Temperature Range Package
Inputs 1
2
* 1 4 * 13
Inputs 4
+ +
TL062CD, ACD SO–8 3 12
TA = 0° to +70°C
TL062CP, ACP Plastic DIP
VCC 4 11 VEE
Dual TL062VD SO–8
TA = –40° to +85°C 5 2 3 10
TL062VP Plastic DIP Inputs 2
+ +
Inputs 3
– –
6 9
TL064CD, ACD SO–14
TA = 0° to +70°C Output 3
TL064CN, ACN Plastic DIP Output 2 7 8
Quad TL064VD SO–14

TA = –40° to +85°C (Top View)
TL064VN Plastic DIP

TL062 TL064
MAXIMUM RATINGS
Input Voltage Range (Notes 1 and 2) VIR ±15 V
NOTES: 1. Differential voltages are at the noninverting input terminal with respect to the inverting input
terminal.
2. The magnitude of the input voltage must never exceed the magnitude of the supply or 15 V,
whichever is less.
exceeded. (See Figure 1.)
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 0° to +70°C, unless otherwise noted.)
TL062AC TL062C
TL064AC TL064C

Input Offset Voltage (RS = 50 Ω, VO = 0V) VIO mV
TA = 25°C — 3.0 6.0 — 3.0 15
TA = 0° to +70°C — — 7.5 — — 20
Average Temperature Coefficient for Offset Voltage ∆VIO/∆T — 10 — — 10 — µV/°C
(RS = 50 Ω, VO = 0 V)

TA = 25°C — 0.5 100 — 0.5 200 pA
TA = 0° to +70°C — — 2.0 — — 2.0 nA
TA = 25°C — 3.0 200 — 3.0 200 pA
TA = 0° to +70°C — — 2.0 — — 10 nA
Input Common Mode Voltage Range VICR — +14.5 +11.5 — +14.5 +11 V
TA = 25°C –11.5 –12.0 — –11 –12.0 —

TA = 25°C 4.0 58 — 3.0 58 —
TA = 0° to +70°C 4.0 — — 3.0 — —
Output Voltage Swing (RL = 10 kΩ, VID = 1.0 V) V
TA = 25°C VO+ +10 +14 — +10 +14 —
VO– — –14 –10 — –14 –10
TA = 0° to +70°C VO+ +10 — — +10 — —
VO– — — –10 — — –10
Common Mode Rejection CMR 80 84 — 70 84 — dB

(RS = 50 Ω, VCM = VICR min, VO = 0 V, TA = 25°C)
Power Supply Rejection PSR 80 86 — 70 86 — dB

(RS = 50 Ω, VCM = 0 V, VO = 0, TA = 25°C)
Power Supply Current (each amplifier) ID — 200 250 — 200 250 µA

(No Load, VO = 0 V, TA = 25°C)
Total Power Dissipation (each amplifier) PD — 6.0 7.5 — 6.0 7.5 mW

(No Load, VO = 0 V, TA = 25°C)

TL062 TL064
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh [Note 4], unless otherwise noted.)
TL062V TL064V
Input Offset Voltage (RS = 50 Ω, VO = 0V) VIO mV
TA = 25°C — 3.0 6.0 — 3.0 9.0
TA = Tlow to Thigh — — 9.0 — — 15
Average Temperature Coefficient for Offset Voltage ∆VIO/∆T µV/°C

(RS = 50 Ω, VO = 0 V) — 10 — — 10 —
TA = 25°C — 5.0 100 — 5.0 100 pA
TA = Tlow to Thigh — — 20 — — 20 nA

TA = 25°C — 30 200 — 30 200 pA
TA = Tlow to Thigh — — 50 — — 50 nA
Input Common Mode Voltage Range (TA = 25°C) VICR — +14.5 +11.5 — +14.5 +11.5 V
–11.5 –12.0 — –11.5 –12.0 —

TA = 25°C 4.0 58 — 4.0 58 —
TA = Tlow to Thigh 4.0 — — 4.0 — —
Output Voltage Swing (RL = 10 kΩ, VID = 1.0 V) V

TA = 25°C VO+ +10 +14 — +10 +14 —
VO– — –14 –10 — –14 –10
TA = Tlow to Thigh VO+ +10 — — +10 — —
VO– — — –10 — — –10
(RS = 50 Ω, VCM = VICR min, VO = 0, TA = 25°C) 80 84 — 80 84 —
Power Supply Rejection PSR dB
(RS = 50 Ω, VCM = 0 V, VO = 0, TA = 25°C) 80 86 — 80 86 —
Power Supply Current (each amplifier) ID µA
(No Load, VO = 0 V, TA = 25°C) — 200 250 — 200 250
Total Power Dissipation (each amplifier) PD mW
(No Load, VO = 0 V, TA = 25°C) — 6.0 7.5 — 6.0 7.5
NOTE: 4. Tlow = –40°C Thigh = +85°C for TL062,4V
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = +25°C, unless otherwise noted.)
Slew Rate (Vin = –10 V to +10 V, RL = 10 kΩ, CL = 100 pF, AV = +1.0) SR 2.0 6.0 — V/µs
Rise Time (Vin = 20 mV, RL = 10 kΩ, CL = 100 pF, AV = +1.0) tr — 0.1 — µs

Overshoot (Vin = 20 mV, RL = 10 kΩ, CL = 100 pF, AV = +1.0) OS — 10 — %
Settling Time tS µs
(VCC = +15 V, VEE = –15 V, AV = –1.0, To within 10 mV — 1.6 —
RL = 10 kΩ, VO = 0 V to +10 V step) To within 1.0 mV — 2.2 —
Gain Bandwidth Product (f = 200 kHz) GBW — 2.0 — MHz
Equivalent Input Noise (RS = 100 Ω, f = 1.0 kHz) en — 47 — nV/ √ Hz
Input Resistance Ri — 1012 — W
Channel Separation (f = 10 kHz) CS — 120 — dB

TL062 TL064
Figure 1. Maximum Power Dissipation versus Figure 2. Output Voltage Swing

Temperature for Package Variations versus Supply Voltage
2400 40

35 RL = 10 kΩ
2000
TA = 25°C
30
1600
SO–14 25
1200 20
SO–8 15
800
10
400
5.0
0 0
–55 –40 –20 0 20 40 60 80 100 120 140 160 0 2.0 4.0 6.0 8.0 10 12 14 16

versus Temperature versus Load Resistance
40 30
VCC = +15 V

35 VEE = –15 V
24 TA = 25°C
30
25 18
20
15 12
10 VCC = +15 V
VEE = –15 V 6.0
5.0 RL = 10 kΩ
0 0
–75 –50 –25 0 25 50 75 100 125 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10
TA, AMBIENT TEMPERATURE (°C) RL, LOAD RESISTANCE (kΩ)
Figure 5. Output Voltage Swing Figure 6. Large Signal Voltage Gain

A VOL , LARGE SIGNAL VOLTAGE GAIN (V/mV)
35 100
VCC = +15 V
30 RL = 10 kΩ 70 VEE = –15 V
VCC = +15 V, VEE = –15 V TA = 25°C RL = 10 kΩ
25 50
VCC = +12 V, VEE = –12 V
40
20
30
15
20
10 VCC = +5.0 V, VEE = –5.0 V
5.0
VCC = +2.5 V, VEE = –2.5 V
0 10
100 1.0 k 10 k 100 k 1.0 M 10 M –75 –50 –25 0 25 50 75 100 125

TL062 TL064
Figure 7. Open Loop Voltage Gain Figure 8. Supply Current per Amplifier
and Phase versus Frequency versus Supply Voltage
100 250
VCC = +15 V

VEE = –15 V
I CC , SUPPLY CURRENT (µ A)
80 VO = 0 V 0 200
Gain
RL = 10 kΩ
CL = 0 pF
60 TA = 25°C 45 150
Phase
40 90 100
TA = 25°C
VO = 0 V
20 135 50 RL = ∞Ω
0 180 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
Figure 9. Supply Current per Amplifier Figure 10. Total Power Dissipation
250 25
P D, TOTAL POWER DISSIPATION (MW) TL064
I CC , SUPPLY CURRENT (µ/A)
200 20 VCC = +15 V

VEE = –15 V
VO = 0 V
150 15 RL = ∞Ω
TL062
100 10
VCC = +15 V
50 VEE = –15 V 5.0
VO = 0 V
RL = ∞Ω
0 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Figure 11. Common Mode Rejection Figure 12. Common Mode Rejection
88 140
VCC = +15 V –
87 VCC = +15 V
VEE = –15 V 120 ADM ∆VO
VEE = –15 V
VO = 0 V ∆VCM +
86 ∆VCM = ±1.5 V
RL = 10 kΩ 100 TA = 25°C ∆VCM
85 CMR = 20 Log X ADM
80 ∆VO
84
60
83
40
82
81 20
80 0
–75 –50 –25 0 25 50 75 100 125 100 1k 10 k 100 k 1M

TL062 TL064
Figure 14. Normalized Gain Bandwidth

Figure 13. Power Supply Rejection Product, Slew Rate and Phase
versus Frequency Margin versus Temperature
140 1.4 1.08
∆VO/ADM
VCC = +15 V
φ m , NORMALIZED PHASE MARGIN

+PSR = 20Log 1.3 1.06
∆VCC
NORMALIZED GAIN BANDWIDTH

120 VEE = –15 V
+PSR (∆VCC = ±1.5 V)
PRODUCT AND SLEW RATE

1.2 RL = 10 kΩ 1.04
100 ∆VO/ADM
–PSR = 20Log CL = 0 pF
–PSR (∆VEE = ±1.5 V) ∆VEE 1.1 GBW 1.02
80
1.0 Slew Rate 1.0
60
VCC = +15 V 0.9 0.98
40 VEE = –15 V VCC Phase Margin
– 0.8 0.96
TA = 25°C ADM ∆VO
20 + 0.7 0.94
VEE
0 0.6 0.92
100 1.0 k 10 k 100 k 1.0 M –75 –50 –25 0 25 50 75 100 125
Figure 15. Input Bias Current Figure 16. Input Noise Voltage
1000 e n , INPUT NOISE VOLTAGE ( nV/ √ Hz ) 70
VCC = +15 V
100 VEE = –15 V 60

VCM = 0 V
50
10
40
1.0
30 VCC = +15 V
0.1 VEE = –15 V
20 RS = 100 Ω
TA = 25°C
0.01 10
0.001 0
–55 –25 0 25 50 75 100 125 10 100 1.0 k 10 k 100 k
Figure 17. Small Signal Response Figure 18. Large Signal Response
VCC = +15 V VCC = +15 V

V O , OUTPUT VOLTAGE (10 mV/DIV)
VEE = –15 V VEE = –15 V

RL = 10 kΩ RL = 10 kΩ
CL = 0 pF CL = 0 pF
AV = +1.0 AV = +1.0

TL062 TL064
Figure 19. AC Amplifier Figure 20. High–Q Notch Filter

VCC
VCC
0.1 µF –
10 kΩ 1/2
1.0 MΩ Output
R1 R2 TL062
10 kΩ +
– Input
1/2 C3 VEE
Inputs TL062 Output
+
R3 R1 = R2 = 2R3 = 1.5 MΩ
50 Ω 5
1 C1 C2 C3
10 kΩ C1 = C2 = = 110 pF
2
250 kΩ
0.1 µF 1
fo = = 1.0 kHz
2π R1 C1
Figure 21. Instrumentation Amplifier
VCC
– 10 kΩ 10 kΩ
0.1% 0.1%
TL064
100 kΩ
Input A +
VEE
VCC
–
TL064 Output
+ 100 kΩ
VEE 1.0
MΩ
100 kΩ VCC VCC
Input B + –
TL064 TL064
10 kΩ 10 kΩ 100 Ω
– +
0.1% 0.1%
VEE VEE
Figure 22. 0.5 Hz Square–Wave Oscillator Figure 23. Audio Distribution Amplifier
RF = 100 kΩ VCC
–
+15 V 1.0 MΩ TL064 Output A
3.3 kΩ +
–
1/2 VCC
TL062 –
CF = 3.3 µF
+
1.0 kΩ 1.0 µF TL064 VCC
–15 V Input + –
TL064 Output B
3.3 kΩ 100 kΩ +
100 kΩ
1 9.1 kΩ
f= VCC
2π RF CF 100 kΩ VCC
100 µF 100 kΩ –
TL064 Output C
+

TL071C,AC
TL072C,AC
TL074C,AC
Low Noise, JFET Input
These low noise JFET input operational amplifiers combine two LOW NOISE, JFET INPUT
state–of–the–art analog technologies on a single monolithic integrated OPERATIONAL AMPLIFIERS
circuit. Each internally compensated operational amplifier has well matched
high voltage JFET input device for low input offset voltage. The BIFET
technology provides wide bandwidths and fast slew rates with low input bias SEMICONDUCTOR
currents, input offset currents, and supply currents. Moreover, the devices TECHNICAL DATA
exhibit low noise and low harmonic distortion, making them ideal for use in
high fidelity audio amplifier applications.
These devices are available in single, dual and quad operational
MC1458, and the MC3403/LM324 bipolar products.
8
Typ 8 1
•
1
Low Harmonic Distortion: 0.01% Typ
P SUFFIX D SUFFIX
• Low Input Bias and Offset Currents PLASTIC PACKAGE PLASTIC PACKAGE
• High Input Impedance: 1012 Ω Typ
CASE 626 CASE 751
(SO–8)
• High Slew Rate: 13 V/µs Typ
• Wide Gain Bandwidth: 4.0 MHz Typ PIN CONNECTIONS
• Low Supply Current: 1.4 mA per Amp Offset Null 1 8 NC

Inv + Input 2 7 VCC
Noninvt Input 3 + 6 Output
VEE 4 5 Offset Null
TL071 (Top View)
Output A 1 8 VCC
2
–
7 Output B
Inputs A 3
+
6
–
+ Inputs B
VEE 4 5
TL072 (Top View)
N SUFFIX
PLASTIC PACKAGE
CASE 646
14
(TL074 Only)
1
PIN CONNECTIONS

2 13
Op Amp Operating Inputs 1 – – Inputs 4
Function Device Temperature Range Package 3
+
1 4
+
12
TL071ACD, CD SO–8 VCC 4 11 VEE

Single TA = 0° to +70°C
TL071ACP, CP Plastic DIP 5 10
+ +
Inputs 2 – –
Inputs 3
TL072ACD, CD SO–8 2 3
6 9
Dual TA = 0° to +70°C
TL072ACP, CP Plastic DIP Output 2 7 8 Output 3
Quad TL074ACN, CN TA = 0° to +70°C Plastic DIP
TL074 (Top View)

TL071C,AC TL072C,AC TL074C,AC
MAXIMUM RATINGS
Supply Voltage VCC +18 V
VEE –18

Power Dissipation
Plastic Package (N, P) PD 680 mW
Derate above TA = +47°C 1/θJA 10 mW/°C
NOTES: 1. The magnitude of the input voltage must not exceed the magnitude of the supply voltage or 15 V,
whichever is less.
2. The output may be shorted to ground or either supply. Temperature and/or supply voltages must
be limited to ensure that power dissipation ratings are not exceeded.
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Thigh to Tlow [Note 3])
TL071C, TL072C — — 13
TL074C — — 13
TL07_AC — — 7.5
TL07_C — — 2.0
TL07_AC — — 2.0
TL07_C — — 7.0
TL07_AC — — 7.0
Large–Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) AVOL V/mV
TL07_C 15 — —
TL07_AC 25 — —
Output Voltage Swing (Peak–to–Peak) VO V
(RL ≥ 10 k) 24 — —
(RL ≥ 2.0 k) 20 — —
NOTES: 3. Tlow = 0°C for TL071C,AC Thigh = +70°C for TL071C,AC
0°C for TL072C,AC +70°C for TL072C,AC
4. Input Bias currents of JFET input op amps approximately double for every 10°C rise in junction temperature as shown in Figure 3. To maintain
junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing.
Figure 1. Unity Gain Voltage Follower Figure 2. Inverting Gain of 10 Amplifier
10 k
1.0 k
– –
VO Vin VO
+ +
Vin
RL = 2.0 k CL = 100 pF RL CL = 100 pF

TL071C, TL072C — 3.0 10
TL074C — 3.0 10
TL07_AC — 3.0 6.0
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T  10  µV/°C
RS = 50 Ω, TA = Tlow to Thigh (Note 3)

TL07_C — 5.0 50
TL07_AC — 5.0 50
TL07_C — 30 200
TL07_AC — 30 200
Input Resistance ri  1012  Ω
Common Mode Input Voltage Range VICR V
TL07_C ±10 +15, –12 —
TL07_AC ±11 +15, –12 —
Large–Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) AVOL V/mV
TL07_C 25 150 —
TL07_AC 50 150 —
Output Voltage Swing (Peak–to–Peak) VO 24 28  V
(RL = 10 k)

TL07_C 70 100 —
TL07_AC 80 100 —
Supply Voltage Rejection Ratio (RS ≤ 10 k) PSRR dB
TL07_C 70 100 —
TL07_AC 80 100 —
Supply Current (Each Amplifier) ID  1.4 2.5 mA
Unity Gain Bandwidth BW  4.0  MHz
Slew Rate (See Figure 1) SR  13  v/µs
Vin = 10 V, RL = 2.0 k, CL = 100 pF
Rise Time (See Figure 1) tr  0.1  µs

Overshoot (Vin = 20 mV, RL = 2.0 k, CL = 100 pF) OS  10  %
Equivalent Input Noise Voltage en  18  nV/ √ Hz
RS = 100 Ω, f = 1000 Hz
Equivalent Input Noise Current in  0.01  pA/ √ Hz

RS = 100 Ω, f = 1000 Hz
Total Harmonic Distortion THD  0.01  %

VO (RMS) = 10 V, RS ≤ 1.0 k, RL ≥ 2.0 k, f = 1000 Hz
Channel Separation CS  120  dB

AV = 100
NOTES: 3. Tlow = 0°C for TL071C,AC Thigh = +70°C for TL071C,AC
4. Input Bias currents of JFET input op amps approximately double for every 10°C rise in junction temperature as shown in Figure 3. To maintain


100

30
VCC/VEE = ±15 V
VCC/VEE = ±15 V RL = 2.0 k

10
25 TA = 25°C
See Figure 2
20 ±10 V
1.0
15
10 ±5.0 V
0.1
5.0
0.01 0
–75 –50 –25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M 10 M

40
RL = 2.0 k

TA = 25°C
30 VCC/VEE = ±15 V
TA = 25°C 30
See Figure 2
20
20
10
10
5.0
0 0
0.1 0.2 0.4 0.7 1.0 2.0 4.0 7.0 10 0 5.0 10 15 20
RL, LOAD RESISTANCE (kΩ) VCC, |VEE| , SUPPLY VOLTAGE (±V)

2.0
VCC/VEE = ±15 V
1.8
I D , SUPPLY DRAIN CURRENT (mA)
VCC/VEE = ±15 V
35
See Figure 2 1.6
30 RL = 10 k
1.4
25 1.2
RL = 2.0 k
20 1.0
0.8
15
0.6
10
0.4
5.0 0.2
0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

Figure 9. Large Signal Voltage Gain and Figure 10. Large Signal Voltage Gain
1000
VCC/VEE = ±15 V
VCC/VEE = ±15 V VO = ±10 V
V VOL , VOLTAGE GAIN (V/mV)

RL = 2.0 k
106 RL = 2.0 k
VVOL, OPEN LOOP GAIN
TA = 25°C 100
105
104 0°
Gain
103 45° 10
102 90°
Phase Shift
101 135°
1 180° 1.0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M –50 –25 0 25 50 75 100 125
1.15 e en , EQUIVALENT INPUT NOISE VOLTAGE ( nV/ √ Hz ) 60 VCC/VEE = ±15 Vdc

AV = 10
1.10
50 RS = 100 Ω
TA = 25°C
1.05
40
1.00
30
0.95
20
0.90
0.85 10
0
–50 –25 0 25 50 75 100 125 0.01 0.05 0.1 0.5 1.0 5.0 10 50 100

versus Frequency
1.0
0.5 VCC/VEE = ±15 V

AV = 1.0
VO = 6.0 V (RMS)
TA = 25°C
0.1
0.05
0.01
0.005
0.001
0.1 0.5 1.0 5.0 10 50 100
f, FREQUENCY (Hz)


(Each Amplifier) Bias Circuitry
Output Common to All
Amplifiers
VCC
Q4 Q5 Q2
Q3 Q1
Q6
– J1 J2
Inputs
+ Q17 2.0 k
Q20
J3
Q15 Q19 Q23
10 pF
24
Q14
Q21 Q24
Q22
Q12 Q13 Q16
Q10 Q9 Q8 Q25
Q11 Q7
Offset Q18
Null
(TL071 1.5 k 1.5 k
only)
VEE
Figure 14. Audio Tone Control Amplifier

10 k 100 k 10 k
Input
0.033 µF 0.033 µF VCC

10 k
–
TL071 Output
3.3 k +
68 k VEE
0.033 µF 0.033 µF Turn–Over Frequency = 1.0 kHz
Bass Boost/Cut — ±20 dB at 20 Hz
100 k Treble Boost/Cut — ±19 dB at 20 kHz
Figure 15. High Q Notch Filter
–
R R TL071
Input +
C1
R1 fo = 1 = 350 Hz
2πRC
R = 2R1 = 1.5 M
C C C = C1 = 300 pF
2

TL081C,AC
TL082C,AC
TL084C,AC
JFET Input Operational
Amplifiers
These low–cost JFET input operational amplifiers combine two state–of– JFET INPUT
the–art linear technologies on a single monolithic integrated circuit. Each OPERATIONAL AMPLIFIERS
internally compensated operational amplifier has well matched high voltage
JFET input devices for low input offset voltage. The BIFET technology
provides wide bandwidths and fast slew rates with low input bias currents, SEMICONDUCTOR
input offset currents, and supply currents. TECHNICAL DATA
These devices are available in single, dual and quad operational
MC1458, and the MC3403/LM324 bipolar products.
• Input Offset Voltage Options of 6.0 mV and 15 mV Max
• Low Input Bias Current: 30 pA 8
• Low Input Offset Current: 5.0 pA 8
1
1
• Wide Gain Bandwidth: 4.0 MHz P SUFFIX D SUFFIX

• High Slew Rate: 13 V/µs PLASTIC PACKAGE
CASE 626
PLASTIC PACKAGE
CASE 751
• Low Supply Current: 1.4 mA per Amplifier (SO–8)
• High Input Impedance: 1012 Ω
PIN CONNECTIONS
Offset Null 1 8 NC
Representative Circuit Schematic (Each Amplifier)
Inv + Input 2 7 VCC
Output Noninvt Input + Output
VCC 3 6
Q4 Q5
VEE 4 5 Offset Null
Q2
Q3 Q1
TL081 (Top View)
Q6
– J1 J2
Inputs Output A 1 8 VCC
+ 2.0 k
Q17
2
–
7 Output B
Q20
J3 Inputs A 3
+
6
Q23 –
Q15 Q19 + Inputs B
10 pF 24 VEE 4 5
Q14
Q21 TL082 (Top View)
Q22 Q24
Q12 Q13 Q16
Q10 Q11 Q9 Q8 Q25
Q7
N SUFFIX
Q18 PLASTIC PACKAGE
Offset
Null 1.5 k 1.5 k
CASE 646
(TL081 14
only) 1
Bias Circuitry VEE
Common to All
Amplifiers PIN CONNECTIONS
ORDERING INFORMATION 2 13
–
Inputs 1 +
– Inputs 4
+
Op Amp Operating 3 1 4 12
Function Device Temperature Range Package VCC 4 11 VEE
TL081ACD, CD SO–8
TA = 0° to +70°C
5 10
Single Inputs 2 + +
Inputs 3
TL081ACP, CP Plastic DIP 6
– 2 3 –
9
TL082ACD, CD SO–8 Output 2
Dual TA = 0° to +70°C 7 8 Output 3
TL082ACP, CP Plastic DIP
TL084 (Top View)
Quad TL084ACN, CN TA = 0° to +70°C Plastic DIP

MAXIMUM RATINGS
Supply Voltage VCC +18 V
VEE –18

Power Dissipation
Plastic Package (N, P) PD 680 mW
NOTES: 1. The magnitude of the input voltage must not exceed the magnitude of the supply voltage or 15 V,
whichever is less.
2. The output may be shorted to ground or either supply. Temperature and/or supply voltages must be
limited to ensure that power dissipation ratings are not exceeded.
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh [Note 3].)
TL081C, TL082C — — 20
TL084C — — 20
TL08_AC — — 7.5

TL08_C — — 5.0
TL08_AC — — 3.0

TL08_C — — 10
TL08_AC — — 7.0
Large–Signal Voltage Gain (VO= ±10 V,RL ≥ 2.0 k) AVOL V/mV

TL08_C 15 — —
TL08_AC 25 — —
Output Voltage Swing (Peak–to–Peak) VO V

(RL ≥ 10 k) 24 — —
(RL ≥ 2.0 k) 20 — —
NOTES: 3. Tlow = 0°C for TL081AC,C Thigh = +70°C for TL081AC
0°C for TL082AC,C +70°C for TL082AC,C
4. Input Bias currents of JFET input op amps approximately double for every 10°C rise in Junction Temperature as shown in Figure 3. To maintain
Figure 1. Unity Gain Voltage Follower Figure 2. Inverting Gain of 10 Amplifier

10 k
1.0 k
– –
VO Vin VO
+ +
Vin
RL = 2.0 k CL = 100 pF RL CL = 100 pF

ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = +25°C, unless otherwise noted.)
TL081C, TL082C — 5.0 15
TL084C — 5.0 15
TL08_AC — 3.0 6.0
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T  10  µV/°C
RS = 50 Ω, TA = Tlow to Thigh (Note 3)

TL08_C — 5.0 200
TL08_AC — 5.0 100
TL08_C — 30 400
TL08_AC — 30 200
Input Resistance ri  1012  Ω
Common Mode Input Voltage Range VICR V
TL08_C ±10 +15, –12 —
TL08_AC ±11 +15, –12 —
Large Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) AVOL V/mV
TL08_C 25 150 —
TL08_AC 50 150 —
Output Voltage Swing (Peak–to–Peak) VO 24 28  V
(RL = 10 k)

TL08_C 70 100 —
TL08_AC 80 100 —
Supply Voltage Rejection Ratio (RS ≤ 10 k) PSRR dB
TL08_C 70 100 —
TL08_AC 80 100 —
Supply Current (Each Amplifier) ID  1.4 2.8 mA
Unity Gain Bandwidth BW  4.0  MHz
Slew Rate (See Figure 1) SR  13  V/µs
Vin = 10 V, RL = 2.0 k, CL = 100 pF
Rise Time (See Figure 1) tr  0.1  µs

Overshoot (Vin = 20 mV, RL = 2.0 k, CL = 100 pF) OS  10  %
Equivalent Input Noise Voltage en  25  nV/ √ Hz
RS = 100 Ω, f = 1000 Hz
Channel Separation CS  120  dB

AV = 100
NOTES: 3. Tlow = 0°C for TL081AC,C Thigh = +70°C for TL081AC
4. Input Bias currents of JFET input op amps approximately double for every 10°C rise in Junction Temperature as shown in Figure 3. To maintain


100
RL = 2.0 k

30 TA = 25°C
VCC/VEE = ±15 V
VCC/VEE = ±15 V (See Figure 2)

10
25
20 ±10 V
1.0
15
10 ±5.0 V
0.1
5.0
0.01 0
–75 –50 –25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 M 10 M

40
RL = 2.0 k
VCC/VEE = ±15 V VO, OUTPUT VOLTAGE SWING (Vpp)

TA = 25°C TA = 25°C
30
(See Figure 2) 30
20
20
10
10
5.0
0 0
0.1 0.2 0.4 0.7 1.0 2.0 4.0 7.0 10 0 5.0 10 15 20
RL, LOAD RESISTANCE (kΩ) VCC, |VEE| , SUPPLY VOLTAGE (±V)

2.0
VCC/VEE = ±15 V
VCC/VEE = ±15 V 1.8
I D , SUPPLY DRAIN CURRENT (mA)
35
(See Figure 2)
1.6
30 RL = 10 k
1.4
25 1.2
RL = 2.0 k
20 1.0
15 0.8
0.6
10 0.4
5.0 0.2
0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

Figure 9. Large Signal Voltage Gain and Figure 10. Large Signal Voltage Gain
1000
A VOL , OPEN–LOOP GAIN (V/mV)
VCC/VEE = ±15 V
A VOL , OPEN–LOOP GAIN (V/mV)

VCC/VEE = ±15 V VO = ±10 V

RL = 2.0 k
106 RL = 2.0 k
TA = 25°C 100
105
104 0°
Gain
103 45° 10
102 90°
Phase Shift
101 135°
1 180° 1.0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M –50 –25 0 25 50 75 100 125
e n , EQUIVALENT INPUT NOISE VOLTAGE ( nV/ √ Hz )

1.15 60 VCC/VEE = ±15 V
AV = 10
1.10
50 RS = 100 Ω
TA = 25°C
1.05
40
1.00
30
0.95
20
0.90
0.85 10
0
–50 –25 0 25 50 75 100 125 0.01 0.05 0.1 0.5 1.0 5.0 10 50 100

versus Frequency
1.0
0.5
VCC/VEE = ±15 V
AV = 1.0
0.1
VO = 6.0 V (RMS)
TA = 25°C
0.05
0.01
0.005
0.001
0.1 0.5 1.0 5.0 10 50 100
f, FREQUENCY (Hz)

Figure 14. Positive Peak Detector Figure 15. Voltage Controlled Current Source
R3
R1
Vin + R5
– TL081 IO
1/2
– TL082 VO –
1/2 R2
TL082 +
*
Vin + 1N914 1.0 µF
R4
Vin
If R1 through R4 > > R5 then Iout =
*Polycarbonate or R5
Reset
Polystyrene Capacitor
Figure 16. Long Interval RC Timer Figure 17. Isolating Large Capacitive Loads
R2 5.1 k
VO
R1 V1 R3
VR – CC 20 pF
TL081
6
R1 5.1 k IO
R4 R2 + –
TL081
R3 10
R6
+2.0 V + CL 0.5 µF
Clear C* RL 5.1 k
0
Run –2.0 V
R5 *Polycarbonate or • Overshoot t 10%

Polystyrene Capacitor • ts = 10 µs
• When driving large CL, the VO slew rate is determined by CL
• and IO(max):
ȏ
^ 0.02
Time (t) = R4 C n (VR/VR–VI), R3 = R4, R5 = 0.1 R6 ∆VO IO
If R1 = R2: t = 0.693 R4C = V/µs = 0.04 V/µs (with CL shown)
∆t CL 0.5
Design Example: 100 Second Timer

VR = 10 V C = l.0 mF R3 = R4 = 144 M
R6 = 20 k R5 = 2.0 k R1 = R2 = 1.0 k

Addendum
Application Information

OPERATIONAL AMPLIFIER APPLICATION INFORMATION
The Ideal Operational Amplifier

An ideal op amp has infinite input impedance, infinite gain, mismatches between the inputs create an error voltage and
and zero output impedance. Its output is proportional to the current, the input impedance is finite, requiring a small bias
differential voltage between the inputs. In reality, slight current, and gain and operating frequency are limited.
Ideal Op Amp Equivalent Circuit for Actual Op Amp
VIO
+ Ro
+ + +
IBias
Vi aVi VO IIO a (jw) vi VO
Vi zin
— 2 —
—
—
IBias
³R
³R
a
zin
zo = 0
ESD Protection
Newer Motorola devices are equipped with either An alternate scheme uses a CEO transistor clamp with the
electrostatic discharge (ESD) diodes or CEO clamps on the collector connected to the input and the emitter and base
inputs to increase their reliability. ESD diodes are connected connected to VEE. This ESD protection method is totally
with the anode attached to the input and the cathode to VCC. transparent to the user. Although it is not recommended that
During normal operation, the diode should be transparent to the inputs be allowed to exceed VCC, the CEO clamp will not
the user. However, if the input exceeds VCC by more than a affect device operation. The inputs should never exceed VEE,
diode drop, the ESD diode will be forward biased and will with or without ESD protection. Single supply op amps are
provide a current path from the input to VCC. Unless the particularly sensitive to damage in a reverse bias condition.
current is limited externally the device could be damaged If ESD protection is used on an amplifier, the ESD scheme
from overheating. used will be identified in the data sheet.
ESD Diodes CEO Clamps

+VCC +VCC
–VEE –VEE

JFET Inputs versus Bipolar Inputs
Although JFET input op amps are generally associated input op amp is a better choice. A bipolar input is also
with high speed, there are now bipolar input op amps with required for true single supply operation. Any op amp can be
comparable slew rates. JFETS do offer higher input operated with one supply. But the common mode input
impedance and lower input bias current than a typical bipolar voltage range of a single supply op amp includes ground.
input. But for the lowest noise and offset voltage, a bipolar
Phase Reversal
Most op amp data sheets describe both a maximum input
voltage and a minimum common mode input voltage range
for the device. The input voltage limit given in the Maximum
Ratings Table is considered to be the highest voltage that can
be applied without damaging the device. It does not
guarantee the device will function normally or within the given
electrical specifications. The input common mode voltage
range (VICR), on the other hand, provides the maximum input
voltage (for the conditions listed) for normal operation.
Exceeding the input common mode range may cause the
device to exceed the electrical specifications, latch or go into
phase reversal. (As shown in figure at right.)
In a latch condition, the op amp output goes to one of the
supply rails, and will remain in that state until the power is
removed and reapplied with the error condition corrected. In
phase reversal, a normal output low would be seen as an
output high, but phase reversal will self correct once the peaks, and phase reversing on the positive peaks. But as the
input drops below a certain level. The input voltage required input drops on the negative going part of the waveform, the
for phase reversal to occur varies, but it is usually seen if the output returns the the correct state without powering down
input voltage approaches or exceeds the supply voltage. As the device.
you can see in the figure the output is clipping on the negative
Thermal Considerations
Thermal resistance (θJA ) information is given on most hundred milliamps to an amp in a short circuit condition, extra
packages in the back of the data book. Low power op amps care is needed to ensure that the maximum junction
can handle a short circuit current condition indefinitely. Since temperature of the part is not exceeded.
some of the higher current drive op amps can deliver a
TJ = TA + PDQJA
TJ = Junction Temperature (Should not exceed 150°C)
TA = Ambient Temperature
PD = Power Dissipation
QA = Package Thermal Impedance

Stability and Compensation
Most op amps are internally compensated, enabling them distributed capacitance or an actual load capacitor, can be a
to be used in a unity gain configuration. Uncompensated or problem with as little as 100 pF. Sensitivity to load
decompensated amplifiers have a higher slew rate if no capacitance varies from op amp to op amp and is not always
external compensation capacitor is used, but must either be given in the data sheets. To compensate for capacitive
used in a gain of 2 or more or with positive feedback to loading, add a small resistor in series with the output.
ensure stable operation. When externally compensating an Depending on the load and the external loop, 10 Ω to 100 Ω
amplifier, use a capacitor equal or greater than the value is generally sufficient (see Figure A). For high capacitive
recommended in the data sheet. Since the external loop loading, (CL>1500 pF) a capacitor in the feedback loop may
affects the stability of the op amp, the amplifier needs to be also be necessary (see Figure B).
evaluated in the circuit and over temperature to determine Keeping the differential source resistance low not only
the minimum amount of compensation required. limits the noise generated in the circuit, but avoids stability
Insufficient compensation will cause a high frequency problems as well. Most op amps are stable with a source
oscillation — higher than the unity gain frequency of the resistance of up to 2 kΩ, but will vary from op amp to op amp.
device. This high frequency oscillation is indicative of an The differential source resistance (which includes any
instability in the Miller loop, internal to the device. Lower feedback resistance) combines with the input capacitance of
frequency oscillation (below the unity gain frequency of the the op amp to create a low frequency pole. The higher the
amplifier) is generally caused by an instability in the outer resistance, the more likely you are to have an oscillation
loop. problem. Adding a small capacitor in parallel with the
The two primary causes of low frequency oscillation are feedback resistor may solve the problem (see Figure C). The
capacitive loading on the output and high differential source capacitor should be greater than the input capacitance of the
resistance. Capacitive loading, which can be either op amp which is typically about 10 pF.
Figure A. Compensation Circuit Figure B. Compensation Circuit

for Moderate Capacitive Loads for High Capacitive Loads
R2 R2
CC
– RC – RC
R1 + R1 +
CL CL
Figure C. Compensation for

High Source Impedance
R2
CC
R1 +
ZL

Layout Considerations
Higher frequency op amps may require special attention to Test Information
layout. Since most layout problems are not reflected in
computer simulations, it is worth it to follow proper layout The following circuit can be used to test VIO, IIO, and IIB.
rules consistently. Some suggestions: Op Amp A is the device under test, and Op Amp B is a buffer
amplifier which reduces CMRR errors and improves the
• Always bypass the supply pins with at least 0.01 µF to ground,
accuracy of the measurement. The 30 nF capacitors across
whether or not it is a high frequency application. Some the 10k Ω source resistors are for stability and may not be
amplifiers have a much lower power supply rejection with needed.
respect to the negative supply than to the positive supply due
to the internal compensation. A larger bypass capacitor from
VEE to ground may be used to prevent high frequency A) Without Buffer Amplifier
transients from appearing on the output. Generally 10 µF to 20
50 kΩ
µF is sufficient.
SW1
• Make sure you have a good ground plane.
• Keep AC and DC grounds separate. 30 nF
–
• Don’t use proto boards or wire wrap for high frequency 10 kΩ A VO
circuits. 10 kΩ
+
• Use appropriate external components — avoid 50 Ω 50 Ω
30 nF
electrolytics in high frequency paths.
• Keep high frequency paths short (including the leads on SW2
discrete components).
• Ground the inputs of unused op amps.
B) With Buffer Amplifier

50 kΩ
SW1 1.6 nF
1.6 nF 50 Ω
30 nF
–
10 kΩ A –
10 kΩ 100 kΩ
+ B VO
30 nF +
50 Ω 50 Ω
SW2
VIO can be measured directly with SW1 and SW2 closed.

To determine IIB–: To determine IIB+:
• Measure VIO with both switches close, • Close SW1 and open SW2; Measure VIO2
• Open SW1 only; Measure VIO1 IIO equals the difference between IIB+ and IIB–

GLOSSARY
Input Offset Voltage (VIO) — The voltage which must be Power Supply Rejection Ratio (PSR or PSRR) — The ratio
applied between the inputs of an op amp to obtain a zero of the change in VIO to the change in power supply voltage.
output voltage. For an ideal op amp, VIO would be zero. Some Measures the immunity of the amplifier to changes in power
vendors abbreviate it VOS. supply voltage.
Input Bias Current (IIB) — The current flowing in or out of both Output Short Circuit Current (ISC) — The maximum current
inputs of an op amp. JFET input op amps provide the lowest an amplifier can deliver into a short circuit. Care must be
input bias current; typically in the picoamp range. A bipolar exercised to ensure the maximum junction temperature of the
input op amp is typically in nanoamps. IIB is highly sensitive to device is not exceeded to prevent damage to the device.
slight process variations and can vary an order
of magnitude. Supply Current (ID or ICC) — The operating current required
with no load and with the output at zero volts.
Input Offset Current (IIO) — Ideally, the bias currents on the
two inputs are equal. The input offset current is the difference Slew Rate (SR) — The rate of change of the output voltage in
between the two currents when the output is at zero volts. response to a large amplitude pulse applied to the input. The
Sometimes abbreviated IOS. This should not be confused with slew rate determines the power bandwidth of the device.
the output short circuit current (ISC).
Gain Bandwidth Product (GBW) — The product of the
Input Common Mode Voltage Range (VICR) — The closed–loop gain times the frequency response at a given
maximum input voltage range for normal operation within frequency. For an op amp with a single pole roll–off, the gain
given specifications. Exceeding the input common mode bandwidth product is equal to the unity gain frequency.
range generally will not damage the inputs if the maximum
ratings are not exceeded. However, VIO may not meet the Phase Margin (φM) — 180° minus the phase shift at the unity
specification given in the data sheet, and phase reversal may gain frequency of the device. The phase margin must be
occur as the input voltage approaches VCC or VEE. positive for unconditionally stable operation. Phase margin
Sometimes abbreviated VCM. (and stability) are affected by the external circuit, particularly
the capacitive loading on the output and the differential source
Common Mode Rejection Ratio (CMR or CMRR) — CMRR resistance on the input.
is defined as the ratio of the common mode gain to the
differential mode gain. It is also equal to the ratio of the input Channel Separation (CS) — A measurement of the immunity
common mode voltage to the peak–to–peak change in VIO. of one op amp to a signal present on another amplifier in a dual
Measures the ability of an op amp to reject a signal present at or quad.
both inputs simultaneously. May be given in dB or volts
per volt. Power Bandwidth (BWP) — The frequency at which the
output starts to clip or distort at maximum peak–to–peak
input voltage.

Power Supply Circuits
In Brief . . .
In most electronic systems, some form of voltage Page
regulation is required. In the past, the task of voltage Linear Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Fixed Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
regulator design was tediously accomplished with discrete
Adjustable Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
devices, and the results were quite often complex and costly. Micropower Voltage Regulators for Portable Applications . . . . . 3–5
Today, with bipolar monolithic regulators, this task has been 80 mA Micropower Voltage Regulator . . . . . . . . . . . . . . . . . . . 3–5
significantly simplified. The designer now has a wide choice 120 mA Micropower Voltage Regulator . . . . . . . . . . . . . . . . . . 3–6
of fixed, low VDiff and adjustable type voltage regulators. Micropower Voltage Regulator for
These devices incorporate many built–in protection External Power Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
features, making them virtually immune to the catastrophic Micropower Voltage Regulators with On/Off Control . . . . . . . 3–7
failures encountered in older discrete designs. Special Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Voltage Regulator/Supervisory . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
The switching power supply continues to increase in
SCSI Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
popularity and is one of the fastest growing markets in the Switching Regulator Control Circuits . . . . . . . . . . . . . . . . . . . . . . 3–12
world of power conversion. They offer the designer several Single–Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
important advantages over linear series–pass regulators. Single–Ended with On–Chip Power Switch . . . . . . . . . . . . . . 3–14
These advantages include significant advancements in the Easy Switcher Single–Ended Controllers with
areas of size and weight reduction, improved efficiency, and On–Chip Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
the ability to perform voltage step–up, step–down, and Very High Voltage Single–Ended with
voltage–inverting functions. Motorola offers a diverse On–Chip Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Double–Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
portfolio of full featured switching regulator control circuits
CMOS Micropower DC–to–DC Converters . . . . . . . . . . . . . . 3–17
which meet the needs of today’s modern compact electronic Single–Ended GreenLine Controllers . . . . . . . . . . . . . . . . . 3–18
equipment. Very High Voltage Switching Regulator . . . . . . . . . . . . . . . . . 3–20
Power supplies, MPU/MCU–based systems, industrial Special Switching Regulator Controllers . . . . . . . . . . . . . . . . . . . 3–23
controls, computer systems and many other product Dual Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
applications are requiring power supervisory functions Universal Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
which monitor voltages to ensure proper system operation. Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
Motorola offers a wide range of power supervisory circuits Supervisory Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27
Overvoltage Crowbar Sensing . . . . . . . . . . . . . . . . . . . . . . . . . 3–27
that fulfill these needs in a cost effective and efficient
Over/Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . 3–27
manner. MOSFET drivers are also provided to enhance the CMOS Micropower Undervoltage Sensing . . . . . . . . . . . . . . 3–28
drive capabilities of first generation switching regulators or CMOS Micropower Undervoltage Sensing with
systems designed with CMOS/TTL logic devices. These Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29
drivers can also be used in dc–to–dc converters, motor Undervoltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–30
controllers or virtually any other application requiring high Universal Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31
speed operation of power MOSFETs. Battery Management Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–32
Battery Charger ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–32
Battery Pack ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–34
MOSFET/IGBT Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–38
High Speed Dual Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–38
Single IGBT Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–38
Package Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–40
Device Listing and Related Litarature . . . . . . . . . . . . . . . . . . . . . . 3–42

Linear Voltage Regulators
Fixed Output
These low cost monolithic circuits provide positive and/or Although designed primarily as fixed voltage regulators,
negative regulation at currents from 100 mA to 3.0 A. They are these devices can be used with external components to obtain
ideal for on–card regulation employing current limiting and adjustable voltages and currents.
thermal shutdown. Low VDiff devices are offered for battery
powered systems.
Table 1. Linear Voltage Regulators

Typ. Temp.
25°C Vin–Vout Regline Regload Coefficient
Tol. Vin Diff. Max Max mV (Vout) Suffix/
Device Vout ±% Max Typ. (% Vout) (% Vout) °C Package
Fixed Voltage, 3–Terminal Regulators, 0.1 Amperes

LM2931*/A–5.0* 5.0 5.0/3.8 40 0.16 0.6 1.0 0.2 D/751,
D2T/936,
DT, DT–1,
T/221A, Z
LP2950C*/AC* 3.0 0.5 30 0.38 0.2/0.1 0.2/0.1 0.04 DT–3.0,
Z–3.0
3.3 DT–3.3,
Z–3.3
5.0 DT–5.0,
Z–5.0
MC78LXXC/AC/AB* 5.0, 8.0, 9.0 8.0/4.0 30 1.7 4.0/3.0 1.2 0.2 D/751, P/29
MC78LXXC/AC/AB* 12, 15, 18 8.0/4.0 35 1.7 2.0 1.0 0.2 D/751, P/29
MC78L24C/AC/AB* 24 8.0/4.0 40 1.7 2.0 1.0 0.2 D/751, P/29
MC79L05C/AC/AB* –5.0 8.0/4.0 30 1.7 4.0/3.0 1.2 0.2 D/751, P/29
MC79LXXC/AC/AB* –(12, 15, 18) 8.0/4.0 35 1.7 2.0 1.0 0.2 D/751, P/29
MC79L24C/AC/AB* –24 8.0/4.0 40 1.7 2.0 1.0 0.2 D/751, P/29
MC33160** 5.0 5.0 40 2.0 0.8 1.0 – P/626

MC78MXXB*/C 5.0, 6.0, 8.0, 12 4.0 35 2.0 1.0 2.0 ±0.04 DT, DT–1,
T/221A
MC78MXXB*/C 15, 18 4.0 35 2.0 1.0 2.0 ±0.04 DT, DT–1,
T/221A
MC78MXXB*/C 20, 24 4.0 40 2.0 0.25 2.0 ±0.04 DT, DT–1,
T/221A
MC79MXXB*/C –(5.0, 8.0, 12, 15) 4.0 35 1.1 1.0 2.0 –0.07 to DT, DT–1,
±0.04 T/221A
MC33267* 5.05 2.0 40 0.58 1.0 1.0 – D2T/936A,
T/314D, TV
Fixed Voltage, 3–Terminal Medium Dropout Regulators, 0.8 Amperes

MC33269–XX* 3.3, 5.0, 12 1.0 20 1.0 0.3 1.0 – D/751, DT,
T/221A
MC34268 2.85 1.0 15 0.95 0.3 1.0 – D/751, DT
Unless otherwise noted, TJ = 0° to +125°C
* TJ = –40° to +125°C
** TA = –40° to +85°C

Table 1. Linear Voltage Regulators (continued)
Typ. Temp.
25°C Vin–Vout Regline Regload Coefficient
Tol. Vin Diff. Max Max mV (Vout) Suffix/
Device Vout ±% Max Typ. (% Vout) (% Vout) °C Package

MC78XXB*/C/AC 5.0, 6.0, 8.0, 12, 4.0/2.0 35 2.0 2.0/1.0 2.0 –0.06 to D2T/936,
18 –0.22 T/221A
MC7824B*/C/AC 24 4.0/2.0 40 2.0 2.0/1.0 2.0/0.4 0.125 D2T/936,
T/221A
MC79XXC/AC –(5.0, 5.2, 6.0) 4.0/2.0 35 2.0 2.0/1.0 2.0 –0.2 D2T/936,
T/221A
MC79XXC/AC –(8.0, 12, 15, 18) 4.0/2.0 35 2.0 2.0/1.0 2.0/1.25 –0.12 to D2T/936,
–0.06 T/221A
MC7924C –24 4.0 40 2.0 1.0 2.0 –0.04 D2T/936,
T/221A
LM340/A–XX 5.0, 6.0, 12, 15, 18 4.0/2.0 35 1.7 1.0/0.2 1.0/0.5 ±0.12 T/221A
LM340–24 24 4.0 40 1.7 1.0 1.0 ±0.12 T/221S
TL780–XXC 5.0, 12, 15 1.0 35 2.0 0.10 0.5 0.012 KC

MC78TXXC/AC 5.0, 8.0, 12 4.0/2.0 35 2.5 0.5 0.6 0.04 T/221A
MC78T15C/AC 15 4.0/2.0 40 2.5 0.5 0.6 0.04 T/221A
LM323/A 5.0 4.0/2.0 20 2.3 0.5/0.3 2.0/1.0 ±0.2 T/221A
* TJ = –40° to +125°C
** TA = –40° to +85°C
Table 2. Fixed Voltage Medium and Low Dropout Regulators

Typ.
Temp.
25°C IO Vin–Vout Regline Regload Coefficient
Tol. (mA) Vin Diff. Max Max mV (Vout) Suffix/
Device Vout ±% Max Max Typ. (% Vout) (% Vout) °C Package
Fixed Voltage, Medium Dropout Regulators

MC33267* 5.05 2.0 500 40 0.58 1.0 1.0 – D2T/936A,
T/314D,
TV
MC34268 2.85 1.0 800 15 0.95 0.3 1.0 D/751, DT
MC33269–XX* 3.3, 5.0, 12 20 1.0 D/751, DT,
T/221A
Fixed Voltage, Low Dropout Regulators

LM2931*/A* 5.0 5.0/3.8 100 37 0.16 1.12 1.0 ±2.5 D/751,
D2T/936A,
DT, DT–1,
T/221A, Z
LP2950C*/AC* 3.0 1.0/0.5 100 30 0.38 0.2/0.1 0.2/0.1 0.2 DT–3.0,
Z–3.0
3.3 DT–3.3,
Z–3.3
5.0 DT–5.0,
Z–5.0
* TJ = –40° to +125°C

Table 2. Fixed Voltage Medium and Low Dropout Regulators (continued)
Typ.
Temp.
25°C IO Vin–Vout Regline Regload Coefficient
Tol. (mA) Vin Diff. Max Max mV (Vout) Suffix/
Device Vout ±% Max Max Typ. (% Vout) (% Vout) °C Package
Fixed Voltage, Low Dropout Regulators

LP2951C*/AC* 3.0 1.0/0.5 100 28.75 0.38 0.04/0.02 0.04/0.02 ±1.0 D–3.0/751,
DM–3.0/
846A,
N–3.0/626
3.3 D–3.3/751,
DM–3.3/
846A,
N–3.3/626
5.0 D/751,
DM/846A,
N/626
LM2935* 5.0/5.0 5.0/5.0 500/10 60 0.45/0.55 1.0 1.0 – D2T/936A,
T/314D,
TH, TV
* TJ = –40° to +125°C
Adjustable Output
Motorola offers a broad line of adjustable output voltage output voltages for industrial and communications
regulators with a variety of output current capabilities. applications. The three–terminal devices require only two
Adjustable voltage regulators provide users the capability of external resistors to set the output voltage.
stocking a single integrated circuit offering a wide range of
Table 3. Adjustable Output Regulators

Typ. Temp.
IO Vin–Vout Regline Regload Coefficient
(mA) Vin Diff. Max Max mV (Vout) Suffix/
Device Vout Max Max Typ. (% Vout) (% Vout) °C Package
Adjustable Regulators
LM317L/B* 2.0–37 100 40 1.9 0.07 1.5 ±0.35 D/751, Z
LM2931C* 3.0–24 100 37 0.16 1.12 1.0 ±2.5 D/751,
D2T/936A,
T/314D,
TH, TV
LP2951C*/AC* 1.25–29 100 28.75 0.38 0.04/0.02 0.04/0.02 ±1.0 D–3.0/751,
DM–3.0/
846A,
N–3.0/626
D–3.3/751,
DM–3.3/
846A,
N–3.3/626
D/751,
DM/846A,
N/626
MC1723C# 2.0–37 150 38 2.5 0.5 0.2 ±0.033 D/751,
P/646
* TJ = –40° to +125°C
# TA = 0° to +70°C

Table 3. Adjustable Output Regulators (continued)
Typ. Temp.
IO Vin–Vout Regline Regload Coefficient
(mA) Vin Diff. Max Max mV (Vout) Suffix/
Device Vout Max Max Typ. (% Vout) (% Vout) °C Package
Adjustable Regulators
LM317M/B* 1.2–37 500 40 2.1 0.04 0.5 ±0.35 DT, DT–1,
T/221A
LM337M/B* –(1.2–37) 500 40 1.9 0.07 1.5 ±0.3 T/221A
MC33269* 1.25–19 800 18.75 1.0 0.3 0.5 ±0.4 D/751, DT,
T/221A
LM317/B* 1.2–37 1500 40 2.25 0.07 1.5 ±0.35 D2T/936,
T/221A
LM337/B* –(1.2–37) 1500 40 2.3 0.07 1.5 ±0.3 D2T/936,
T/221A
LM350/B* 1.2–33 3000 35 2.7 0.07 1.5 ±0.5 T/221A
* TJ = –40° to +125°C
# TA = 0° to +70°C
Micropower Voltage Regulators for Portable Applications

80 mA Micropower Voltage Regulator
MC78LC00H, N ORDERING INFORMATION
Output Operating
TA = –30° to +80°C, Case 1213, 1212
Device Voltage Temperature Range Package
The MC78LC00 series voltage regulators are specifically MC78LC30HT1 3.0
designed for use as a power source for video instruments, MC78LC33HT1 3.3
handheld communication equipment, and battery powered SOT–89
MC78LC40HT1 4.0
equipment. MC78LC50HT1 5.0
The MC78LC00 series features an ultra–low quiescent of TA = –30°
30° to +80°C
MC78LC30NTR 3.0
1.1 µA and a high accuracy output voltage. Each device
MC78LC33NTR 3.3
contains a voltage reference, an error amplifier, a driver SOT–23
MC78LC40NTR 4.0
transistor and resistors for setting the output voltage. These
MC78LC50NTR 5.0
devices are available in either SOT–89, 3 pin, or SOT–23, 5
pin, surface mount packages. Other voltages from 2.0 to 6.0 V, in 0.1 V increments, are available upon
request. Consult your local Motorola sales office for information.
MC78LC00 Series Features:
• Low Quiescent Current of 1.1 µA Typical
2 3
• Low Dropout Voltage (30 mV Typical)
Vin Vout
• Excellent Line Regulation (0.1%)
• High Accuracy Output Voltage (±2.5%)
• Wide Output Voltage Range (2.0 V to 6.0 V)
• Output Current for Low Power (80 mA Typical)
• Two Surface Mount Packages (SOT–89, 3 Pin, or
SOT–23, 5 Pin)
Vref
Gnd

Micropower Voltage Regulators for Portable Applications (continued)
120 mA Micropower Voltage Regulator
MC78FC00H ORDERING INFORMATION
Output Operating
TA = –30° to +80°C, Case 1213
The MC78FC00 series voltage regulators are specifically MC78FC30HT1 3.0
designed for use as a power source for video instruments, MC78FC33HT1 3.3
handheld communication equipment, and battery powered TA = –30° to +80°C SOT–89
MC78FC40HT1 4.0
equipment. MC78FC50HT1 5.0
The MC78FC00 series voltage regulator ICs feature a high
Other voltages from 2.0 to 6.0 V, in 0.1 V increments, are available upon
accuracy output voltage and ultra–low quiescent current. request. Consult your local Motorola sales office for information.
Each device contains a voltage reference unit, an error
amplifier, a driver transistor, and resistors for setting output
voltage, and a current limit circuit. These devices are
available in SOT–89 surface mount packages, and allow 2 3
construction of an efficient, constant voltage power supply Vin Vout
circuit.
MC78FC00 Series Features:
• Ultra–Low Quiescent Current of 1.1 µA Typical
• Ultra–Low Dropout Voltage (0.5 V Typical)
• Large Output Current (120 mA Typical)
• Excellent Line Regulation (0.1%)
• Wide Operating Voltage Range (2.0 V to 10 V) Vref
• High Accuracy Output Voltage (±2.5%) 1
• Wide Output Voltage Range (2.0 V to 6.0 V) Gnd
• Surface Mount Package (SOT–89)
Micropower Voltage Regulator for External Power Transistor

MC78BC00N ORDERING INFORMATION
Output Operating
TA = –30° to +80°C, Case 1212
The MC78BC00 voltage regulators are specifically MC78BC30NTR 3.0
designed to be used with an external power transistor to MC78BC33NTR 3.3
deliver high current with high voltage accuracy and low TA = –30° to +80°C SOT–23
MC78BC40NTR 4.0
quiescent current. MC78BC50NTR 5.0
The MC78BC00 series are devices suitable for
Other voltages from 2.0 to 6.0 V, in 0.1 V increments, are available upon
constructing regulators with ultra–low dropout voltage and request. Consult your local Motorola sales office for information.
output current in the range of several tens of mA to hundreds
of mA. These devices have a chip enable function, which
minimizes the standby mode current drain. Each of these EXT 4
devices contains a voltage reference unit, an error amplifier, 2 3
a driver transistor and resistors. These devices are available Vin Vout
in the SOT–23, 5 pin surface mount packages.
These devices are ideally suited for battery powered
equipment, and power sources for hand–held audio
instruments, communication equipment and domestic
appliances.
MC78BC00 Series Features:
• Ultra–Low Supply Current (50 µA)
Vref
• Standby Mode (0.2 µA)
• Ultra–Low Dropout Voltage (0.1 V with External 1
Transistor and IO = 100 mA) Gnd
• Excellent Line Regulation (Typically 0.1%/V) CE 5

Micropower Voltage Regulators for Portable Applications (continued)
Micropower Voltage Regulators with On/Off Control
MC33264D, DM
TA = –40° to +85°C, Case 751, 846A

The MC33264 series are micropower low dropout voltage • Internal Current and Thermal Limiting
regulators available in SO–8 and Micro–8 surface mount
• Logic Level ON/OFF Control
packages and a wide range of output voltages. These
devices feature a very low quiescent current (100 µA in the • Functionally Equivalent to TK115XXMC and LP2980
ON mode; 0.1 µA in the OFF mode), and are capable of
supplying output currents up to 100 mA. Internal current and
thermal limiting protection is provided. ORDERING INFORMATION
Additionally, the MC33264 has either active HIGH or Operating
active LOW control (Pins 2 and 3) that allows a logic level Device Temperature Range Package
signal to turn–off or turn–on the regulator output. MC33264D–2.8
Due to the low input–to–output voltage differential and MC33264D–3.0
bias current specifications, these devices are ideally suited MC33264D–3.3
for battery powered computer, consumer, and industrial MC33264D–3.8 SO–8
equipment where an extension of useful battery life is MC33264D–4.0
desirable. MC33264D–4.75
MC33264 Features: MC33264D–5.0
40° to +85°C
TA = –40°
• Low Quiescent Current (0.3 µA in OFF Mode; 95 µA in MC33264DM–2.8
ON Mode) MC33264DM–3.0
MC33264DM–3.3
• Low Input–to–Output Voltage Differential of 47 mV at 10 MC33264DM–3.8 Micro–8
mA, and 131 mV at 50 mA MC33264DM–4.0
• Multiple Output Voltages Available MC33264DM–4.75
• Extremely Tight Line and Load Regulation MC33264DM–5.0
• Stable with Output Capacitance of Only

0.33 µF for 5.0 V, 6.0 V and 4.75 V Output Voltages
1 8
Vin Vout
Thermal and
Anti–Sat 7
Protection
2 Base
On/Off
Rint
Adj
1.23 V
Vref 52.5 k
3 MC33264 6
On/Off
Gnd

Special Regulators
Voltage Regulator/Supervisory
Table 4. Voltage Regulator/Supervisory
Vout Vin
(V) IO (V)
(mA) Regline Regload TA Suffix/
Device Min Max Max Min Max (mV) Max (mV) Max (°C) Package
MC33128* 2.9 3.1 35 3.2 7.0 n/a 30 –30 to +60 D/751B
2.9 3.1 60 40
2.9 3.1 20 25
–2.65 –2.35 1.0 20
MC34160 4.75 5.25 100 7.0 40 40 50 0 to +70 P/648C,
DW/751G
MC33160 –40 to +85
MC33267 4.9 5.2 500 6.0 26 50 50 –40 to +105 T/314D,
TH, TV
MC33169* 4.7 6.4 – 2.7 9.5 – – –40 to +85 DTB/948G

6.4 7.0
–2.35 –2.65
* These ICs are intended for powering cellular phone GaAs power amplifiers and can be used for other portable applications as well.

Voltage Regulator/Supervisory (continued)
Microprocessor Voltage Regulator and Supervisory Circuit
MC34160P, DW
TA = 0° to +70°C, Case 648C, 751G
MC33160P, DW
TA = –40° to +85°C, Case 648C, 751G VCC Regulator
The MC34160 series is a voltage 14
Thermal 0.913R 11 Output
regulator and supervisory circuit Shutdown
0.01R Reset
containing many of the necessary 7
monitoring functions required in
R
microprocessor based systems. It is
specifically designed for appliance and Chip 2.6 V Reference
industrial applications offering the designer Disable 15 Reference 16 Output
a cost effective solution with minimal
external components. These integrated
circuits feature a 5.0 V, 100 mA regulator Power
Power
8 Warning
with short circuit current limiting, pinned out Sense 9
2.6 V bandgap reference, low voltage reset
IH
comparator, power warning comparator Hysteresis
with programmable hysteresis, and an IH “On”/“Off”
Adjust 10
uncommitted comparator ideally suited for
microprocessor line synchronization.
Noninverting
Additional features include a chip disable Input 2
input for low standby current, and internal
thermal shutdown for over temperature Comparator
Inverting
protection. 6 Output
Input 1
These devices are contained in a 16 pin
dual–in–line heat tab plastic package for
improved thermal conduction. Gnd 4, 5,12, 13
Low Dropout Regulator

MC33267T, TV
TJ = –40° to +105°C, Case 314D, 314B
The MC33267 is a positive fixed 5.0 V
regulator that is specifically designed to
Input Output
maintain proper voltage regulation with an
extremely low input–to–output voltage 1 5
3.01
differential. This device is capable of R 20 µA
supplying output currents in excess of 500 Reference Reset
1.25 V Reset
mA and contains internal current limiting and 0.03 2
thermal shutdown protection. Also featured R +
is an on–chip power–up reset circuit that is 3.8 V
ideally suited for use in microprocessor R Delay
Thermal
based systems. Whenever the regulator Delay
Over 200 4
output voltage is below nominal, the reset Current +
output is held low. A programmable time Detector
delay is initiated after the regulator has 1.25 V
reached its nominal level and upon timeout,
the reset output is released. Ground 3
Due to the low dropout voltage
specifications, the MC33267 is ideally
suited for use in battery powered industrial
and consumer equipment where an
extension of useful battery life is desirable.
This device is contained in an economical
five lead TO–220 type package.

Voltage Regulator/Supervisory (continued)
VCC VBB CPC
Power Management Controller VBB Output
MC33128D 16 3 2 4
+ 8
TA = –30° to +60°C, Case 751B Charge Output 4
Pump CPC
The MC33128 is a power management
“On”/“Off” 11 7
controller specifically designed for use in 10 Control
Toggle
battery powered cellular telephone and 9 Logic Negative 5 Output 4
pager applications. This device contains all Standby
Regulator –2.5 V/1.0 mA
of the active functions required to interface
the user to the system electronics via a Low Battery
Shutdown Standby 15 Output 1
microprocessor. This integrated circuit
Regulator 1 3.0 V/30 mA
consists of a low dropout voltage regulator
with power–up reset for MPU power, two 1 Output 2
Thermal Standby
low dropout voltage regulators for Protection 3.0 V/60 mA
Regulator 2
independant powering of analog and digital Output 3
circuitry, and a negative charge pump MPU 14 3.0 V/20 mA
voltage regulator for full depletion of gallium Reference Regulator
arsenide MESFETs.
Also included are protective system MPU Power 13
Up Reset R VDD
shutdown features consisting of a battery
latch that is activated upon battery
Gnd 6 12 Reference Output
insertion, low battery voltage shutdown, I MPU
O
and a thermal over temperature detector.
O
This device is available in a 16–pin narrow I V
body surface mount plastic package. SS
GaAs Power Amplifier Support IC

MC33169DTB
TA = –40° to +85°C, Case 948G
The MC33169 is a support IC for GaAs
Power Amplifier Enhanced FETs used in
hand portable telephones such as GSM, C3
PCN and DECT. This device provides +
VBB Double +
12 VBattery
negative voltages for full depletion of + – – + VCC
(2.7 to 7.0 V)
Enhanced MESFETs as well as a priority C1 2 C2 1 14
management system of drain switching, 8 MMSF4N01HD
ensuring that the negative voltage is always VBB 11 3 VBB
Generator Gate Drive Output
present before turning “on” the Power Triple + MC33169
C4 (Voltage Tripler)
Amplifier. Additional features include an –
idle mode input and a direct drive of the Tx Power Priority
N–Channel drain switch transistor. Control 9 Management
Input RF RF
This product is available in two versions, In Out
– 2.5 and – 4.0 V. The – 4.0 V version is 13
Sense
Power Amplifier
Idle 10
intended for supplying RF modules for Mode Input
GSM and DCS1800 applications, whereas Gnd
6 Sense Input
the – 2.5 V version is dedicated for DECT Negative
Generator
and PHS systems. Charge
Pump
• Negative Regulated Output for Full
Depletion of GaAs MESFETs 7 – + 5 4 – +
C
• Drain Switch Priority Management Cp VO Ci + f
Output
Circuit (– 2.5 V or – 4.0 V) Rf
• CMOS Compatible Inputs
• Idle Mode Input (Standby Mode) for
Very Low Current Consumption
• Output Signal Directly Drives
N–Channel FET
• Low Startup and Operating Current

SCSI Regulator
Table 5. SCSI Regulator
Vout Vin
(V) (V)
Isink Regline Regload TJ Suffix/
Device Min Max (mA) Min Max (%) (%) (°C) Package
MC34268 2.81 2.89 800 3.9 20 0.3 0.5 150 D/751, DT
SCSI–2 Active Terminator Regulator

MC34268D, DT
TJ = 0° to +125°C, Case 751, 369A
The MC34268 is a medium current, low dropout positive • 2.85 V Output Voltage for SCSI–2 Active Termination
voltage regulator specifically designed for use in SCSI–2 • 1.0 V Dropout
active termination circuits. This device offers the circuit • Output Current in Excess of 800 mA
designer an economical solution for precision voltage • Thermal Protection
regulation, while keeping power losses to a minimum. The • Short Circuit Protection
regulator consists of a 1.0 V dropout composite PNP/NPN • Output Trimmed to 1.4% Tolerance
pass transistor, current limiting, and thermal limiting. These • No Minimum Load Required
devices are packaged in the 8–pin SOP–8 and 3–pin DPAK • Space Saving DPAK and SOP–8 Surface Mount Power
surface mount power packages. Packages
Applications include active SCSI–2 terminators and post
regulation of switching power supplies.
Input
Thermal Control
Limiting Circuit
Current
Limit Output
Ground

Switching Regulator Control Circuits
These devices contain the primary building blocks which and are designed to drive many of the standard switching
are required to implement a variety of switching power topologies. The single–ended configurations include buck,
supplies. The product offerings fall into three major categories boost, flyback and forward converters. The double–ended
consisting of single–ended and double–ended controllers, devices control push–pull, half bridge and full bridge
plus single–ended ICs with on–chip power switch transistors. configurations.
These circuits operate in voltage, current or resonant modes
Table 6. Single–Ended Controllers

These single–ended voltage and current mode controllers are designed for use in buck, boost, flyback, and forward
converters. They are cost effective in applications that range from 0.1 to 200 W power output.
Minimum Maximum
Operating Useful
IO Voltage Oscillator
(mA) Range Operating Reference Frequency TA Suffix/
Max (V) Mode (V) (kHz) Device (°C) Package
500 7.0 to 40 Voltage 5.0 ± 1.5% 200 MC34060A 0 to +70 D/751A
(Uncommitted P/646
Drive Output)
MC33060A –40 to +85 D/751A
P/646
1000 4.2 to 12 Current 1.25 ± 2.0% 300 MC34129 0 to +70 D/751A
(Totem Pole MOSFET P/646
Drive Output)
MC33129 –40 to +85 D/751A
P/646
11.5 to 30 5.0 ± 2.0% 500 UC3842A 0 to +70 D/751A
N/626
11 to 30 5.0 ± 1.0% UC2842A –25 to +85 D/751A
N/626
8.2 to 30 5.0 ± 2.0% UC3843A 0 to +70 D/751A
N/626
5.0 ± 1.0% UC2843A –25 to +85 D/751A
N/626
11.5 to 30 5.0 ± 2.0% 500 UC3844 0 to +70 D/751A
(50% Duty N/626
Cycle Limit)
11 to 30 5.0 ± 1.0% UC2844 –25 to +85 D/751A
N/626
8.2 to 30 5.0 ± 2.0% UC3845 0 to +70 D/751A
N/626
5.0 ± 1.0% UC2845 –25 to +85 D/751A
N/626
11.5 to 30 5.0 ± 2.0% 500 UC3842B 0 to +70 D/751A
(I
(Improvedd
D1/751
Oscillator
Specifications N/626
with
Frequency
q y UC3842BV –40 to +105 D/751A
Guaranteed D1/751
at 250 kHz)
N/626

Table 6. Single–Ended Controllers (continued)
These single–ended voltage and current mode controllers are designed for use in buck, boost, flyback, and forward
converters. They are cost effective in applications that range from 0.1 to 200 W power output.
Minimum Maximum
Operating Useful
1000 11 to 30 Current 5.0 ± 1.0% 500 UC2842B –25 to +85 D/751A
(Totem Pole MOSFET (Improved D1/751
Drive Output) Oscillator
Specifications
S ecifications N/626
8.2 to 30 5.0 ± 2.0% with UC3843B 0 to +70 D/751A
Frequency D1/751
Guaranteed
at 250 kHz) N/626
UC3843BV –40 to +105 D/751A
D1/751
N/626
5.0 ± 1.0% UC2843B –25 to +85 D/751A
D1/751
N/626
11.5 to 30 5.0 ± 2.0% 500 UC3844B 0 to +70 D/751A
(50% Duty D1/751
Cycle Limit)
N/626
UC3844BV –40 to +105 D/751A
D1/751
N/626
11 to 30 5.0 ± 1.0% UC2844B –25 to +85 D/751A
D1/751
N/626
8.2 to 30 5.0 ± 2.0% UC3845B 0 to +70 D/751A
D1/751
N/626
UC3845BV –40 to +105 D/751A
D1/751
N/626
5.0 ± 1.0% UC2845B –25 to +85 D/751A
D1/751
N/626
1000 Source 11 to 18 5.0 ± 6.0% MC44602 P2/648C
1500 Sink
(Split Totem Pole
Bipolar Drive Output)
2000 9.2 to 30 Current 5.1 ± 1.0% 1000 MC34023 0 to +70 DW/751G
(Totem Pole MOSFET or FN/775
Drive Output) Voltage
P/648
MC33023 –40 to +105 DW/751G
FN/775
P/648

Table 7. Single–Ended Controllers with On–Chip Power Switch
These monolithic power switching regulators contain all the active functions required to implement standard dc
dc–to–dc
to dc
converter configurations with a minimum number of external components.
Minimum Maximum
Operating Useful
1500 2.5 to 40 Voltage 1.25 ± 5.2%(1) 100 µA78S40 0 to +70 PC/648
(Uncommitted
(U itt d
–40 to +85 PV/648
Power Switch)
1.25 ± 2.0% MC34063A 0 to +70 D/751
P1/626
MC33063A –40 to +85 D/751
P1/626
–40 to +125 D/751
1500 3.0 to 65 Voltage 1.25 ± 2.0% 100 MC34165 0 to +70 P/648C,
(Uncommitted and DW/751G
Power Switch) 5.05 ± 3.0% MC33165 –40 to +85
3400 2.5 to 40 MC34163 0 to +70

(Uncommitted
Power Switch) MC33163 –40 to +85
3400(2) 7.5 to 40 5.05 ± 2.0% 72 ± 12% MC34166 0 to +70 D2T/936A,

(Dedicated Emitter Internally TH TV,
TH, TV
Power Switch) Fixed MC33166 –40 to +85 T/314D
5500(3) MC34167 0 to +70

(Dedicated Emitter
Power Switch) MC33167 –40 to +85
(1) Tolerance applies over the specified operating temperature range.

(2) Guaranteed minimum, typically 4300 mA.
(3) Guaranteed minimum, typically 6500 mA.
Table 8. Easy Switcher Single–Ended Controllers with On–Chip Power Switch

The Easy Switcher series is ideally suited for easy,
easy convenient design of a step–down converter),
step down switching regulator (buck converter)
with a minimum number of external components.
Minimum
Operating
IO Voltage Oscillator O tp t
Output
(mA) Range Operating Frequency Voltage TJ Suffix/
Max (V) Mode (kHz) (V) Device (°C) Package
1000 4.75 to 40 Voltage 52 Fixed 3.3 LM2575T 3.3
LM2575T–3.3 –40
40 to +125 T/314D
8.0 to 40 Internal 5.0 LM2575T–5
15 to 40 12 LM2575T–12
18 to 40 15 LM2575T–15
8 0 to
8.0 t 40 1 23 to
1.23 t 37 LM2575T Adj
LM2575T–Adj
4.75 to 40 3.3 LM2575TV–3.3

LM2575TV 3.3 TV/314B
8.0 to 40 5.0 LM2575TV–5
15 to 40 12 LM2575TV–12
18 to 40 15 LM2575TV–15
8 0 to
8.0 t 40 1 23 to
1.23 t 37 LM2575TV Adj
LM2575TV–Adj
4.75 to 40 3.3 LM2575D2T 3.3

LM2575D2T–3.3 D2T/936A
8.0 to 40 5.0 LM2575D2T–5
15 to 40 12 LM2575D2T–12
18 to 40 15 LM2575D2T–15
8 0 to
8.0 t 40 1 23 to
1.23 t 37 LM2575D2T Adj
LM2575D2T–Adj

Table 9. Very High Voltage Single–Ended Controller with On–Chip Power Switch
This monolithic high
g voltage
g switching g regulator
g is specifically
y designed
g to operate from a rectified ac line voltage
g source.
Included are an on–chip high voltage power switch, active off–line startup circuitry and a full featured PWM controller with fault
protection.
Maximum
Power Switch Useful
Maximum Rating Startup
p Feedback Oscillator
Input Max Operating Threshold Frequency TJ Suffix/
VDS (V) IDS (mA) (V) Mode (V) (kHz) Device (°C) Package
500 2000 250 Voltage 2.6 ± 3.1% 1000 MC33362 –25 to +125 DW/751N,
P/648E
700 1000 450 MC33363
700 1000 450 MC33363A
Table 10. Double–Ended Controllers

These double–ended voltage, current and resonant mode controllers are designed for use in push–pull, half–bridge, and
full–bridge converters. They are cost effective in applications that range from 100 to 2000 watts power output.
Minimum Maximum
Operating Useful
500 7.0 to 40 Voltage 5.0 ± 5.0%(1) 200 TL494 0 to +70 CN/648
(Uncommitted
(U itt d
–25 to +85 IN/648
Drive Out
Outputs)
uts)
5.0 ± 1.5% 300 TL594 0 to +70 CN/648
–25 to +85 IN/648
± 500 8.0 to 40 5.1 ± 2.0% 400 SG3525A 0 to +70 N/648
(Totem Pole MOSFET
Drive Outputs) SG3527A N/648
± 200 5.0 ± 2.0% SG3526 0 to +125(2) N/707

(Totem Pole MOSFET
Drive Outputs)
±1500 9.6 to 20 Resonant 5.1 ± 2.0% 1000 MC34066 0 to +70 DW/751G
(Totem
(T t P l MOSFET
Pole (Z
(Zero
P/648
Drive Out
Outputs)
uts) Current)
MC33066 –40 to +85 DW/751G
P/648
Resonant 2000 MC34067 0 to +70 DW/751G

(Z
(Zero
P/648
Voltage)
MC33067 –40 to +85 DW/751G
P/648
2000 9.2 to 30 Current 5.1 ± 1.0% 1000 MC34025 0 to +70 DW/751G
(T t
(Totem P l MOSFET
Pole or
FN/775
Drive Out
Outputs)
uts) Voltage
P/648
MC33025 –40 to +105 DW/751G
FN/775
P/648
(1) Tolerance applies over the specified operating temperature range.
(2) Junction Temperature Range.

Switching Regulator Control Circuits (continued)
CMOS Micropower DC–to–DC Converters

Variable Frequency Micropower DC–to–DC Converter
MC33463H
TA = –30° to +80°C, Case 1213
The MC33463 series are micropower switching voltage Due to the low bias current specifications, these devices
regulators, specifically designed for handheld and laptop are ideally suited for battery powered computer, consumer,
applications, to provide regulated output voltages using a and industrial equipment where an extension of useful
minimum of external parts. A wide choice of output voltages battery life is desirable.
are available. These devices feature a very low quiescent
MC33463 Series Features:
bias current of 4.0 µA typical.
The MC33463H–XXLT1 series features a highly accurate • Low Quiescent Bias Current of 4.0 µA
voltage reference, an oscillator, a variable frequency
• High Output Voltage Accuracy of ±2.5%
modulation (VFM) controller, a driver transistor (Lx), an error
amplifier and feedback resistive divider. • Low Startup Voltage of 0.9 V at 1.0 mA
T h e M C 3 3 4 6 3 H – X X LT 1 i s i d e n t i c a l t o t h e
MC33463H–XXKT1, except that a drive pin (EXT) for an • Surface Mount Package
external transistor is provided.
Output Operating Package
Device Voltage Type Temperature Range (Tape/Reel)
MC33463H–30KT1 3.0 Int. SOT–89
MC33463H–33KT1 3.3 Switch (Tape)
MC33463H–50KT1 5.0
TA = –30°
30° to +80°C
MC33463H–30LT1 3.0 Ext. SOT–89
MC33463H–33LT1 3.3 Switch (Tape)
MC33463H–50LT1 5.0 Di
Drive
Other voltages from 2.5 V to 7.5 V, in 0.1 V increments are available upon request. Consult your local Motorola
sales office for information.
MC33463H–XXKT1 MC33463H–XXLT1
Vin
Vin 3 2 VO
VLx Limiter
Lx Output
(Voltage 3 2 VO
Drive Feedback) Drive
EXT Output
(Voltage
VFM VFM Feedback)
Controller Controller
100 kHz Vref 100 kHz Vref

Oscillator Oscillator
1 Gnd 1 Gnd

CMOS Micropower DC–to–DC Converters (continued)
Fixed Frequency PWM Micropower DC–to–DC Converter

MC33466H
TA = –30° to +80°C, Case 1213
The MC33466 series are micropower switching voltage Due to the low bias current specifications, these devices
regulators, specifically designed for handheld and laptop are ideally suited for battery powered computer, consumer,
applications, to provide regulated output voltages using a and industrial equipment where an extension of useful
minimum of external parts. A wide choice of output voltages battery life is desirable.
are available. These devices feature a very low quiescent
MC33466 Series Features:
bias current of 15 µA typical.
The MC33466H–XXJT1 series features a highly accurate • Low Quiescent Bias Current of 15 µA
voltage reference, an oscillator, a pulse width modulation
• High Output Voltage Accuracy of ±2.5%
(PWM) controller, a driver transistor (Lx), an error amplifier
and feedback resistive divider. • Low Startup Voltage of 0.9 V at 1.0 mA
T h e M C 3 3 4 6 6 H – X X LT 1 i s i d e n t i c a l t o t h e
MC33466H–XXJT1, except that a drive pin (EXT) for an • Soft–Start = 500 µs
external transistor is provided. • Surface Mount Package
Output Operating Package
Device Voltage Type Temperature Range (Tape/Reel)
MC33466H–30JT1 3.0 Int. SOT–89
MC33466H–33JT1 3.3 Switch (Tape)
MC33466H–50JT1 5.0
TA = –30°
30° to +80°C
MC33466H–30LT1 3.0 Ext. SOT–89
MC33466H–33LT1 3.3 Switch (Tape)
MC33466H–50LT1 5.0 Di
Drive
Other voltages from 2.5 V to 7.5 V, in 0.1 V increments are available upon request. Consult your local Motorola
MC33466H–XXJT1 MC33466H–XXLT1
Vin
VO VO
Vin 3 2 2
VLx Limiter
Lx Output Output
(Voltage 3 (Voltage
Drive Feedback) Drive Feedback)
EXT
PWM PWM
Controller Controller
Phase Phase
50 kHz Comp 50 kHz Comp
Oscillator Vref Oscillator Vref
Soft–Start Soft–Start
1 Gnd
1 Gnd

Single–Ended GreenLine Controllers

Mixed Frequency Mode GreenLine PWM Controller:
Fixed Frequency, Variable Frequency, Standby Mode
MC44603P, DW
TA = –25° to +85°C, Case 648, 751G
The MC44603 is an enhanced high performance controller High Flexibility
that is specifically designed for off–line and dc–to–dc • Externally Programmable Reference Current
converter applications. This device has the unique ability of • Secondary or Primary Sensing
automatically changing operating modes if the converter • Synchronization Facility
output is overloaded, unloaded, or shorted, offering the • High Current Totem Pole Output
designer additional protection for increased system reliability.
• Undervoltage Lockout with Hysteresis
The MC44603 has several distinguishing features when
compared to conventional SMPS controllers. These features Safety/Protection Features
consist of a foldback facility for overload protection, a • Overvoltage Protection Against Open Current and Open
standby mode when the converter output is slightly loaded, a Voltage Loop
demagnetization detection for reduced switching stresses on • Protection Against Short Circuit on Oscillator Pin
transistor and diodes, and a high current totem pole output • Fully Programmable Foldback
ideally suited for driving a power MOSFET. It can also be
• Soft–Start Feature
used for driving a bipolar transistor in low power converters
• Accurate Maximum Duty Cycle Setting
(< 150 W). It is optimized to operate in discontinuous mode
• Demagnetization (Zero Current Detection) Protection
but can also operate in continuous mode. Its advanced
• Internally Trimmed Reference
design allows use in current mode or voltage mode control
applications. GreenLine Controller: Low Power Consumption in
Standby Mode
Current or Voltage Mode Controller
• Operation up to 250 kHz Output Switching Frequency
• Fully Programmable Standby Mode
• Inherent Feed Forward Compensation
• Controlled Frequency Reduction in Standby Mode
• Latching PWM for Cycle–by–Cycle Current Limiting
• Low dV/dT for Low EMI Radiations
• Oscillator with Precise Frequency Control
High Safety Standby Ladder Mode GreenLine PWM Controller

MC44604P
TA = –25° to +85°C, Case 648
The MC44604 is an enhanced high performance controller High Flexibility
that is specifically designed for off–line and dc–to–dc • Externally Programmable Reference Current
converter applications. • Secondary or Primary Sensing
The MC44604 is a modification of the MC44603. The • High Current Totem Pole Output
MC44604 offers enhanced safety and reliable power • Undervoltage Lockout with Hysteresis
management in its protection features (foldback, overvoltage
detection, soft–start, accurate demagnetization detection). Safety/Protection Features
Its high current totem pole output is also ideally suited for • Overvoltage Protection Facility Against Open Loop
driving a power MOSFET but can also be used for driving a • Protection Against Short Circuit on Oscillator Pin
bipolar transistor in low power converters (< 150 W). • Fully Programmable Foldback
In addition, the MC44604 offers a new efficient way to • Soft–Start Feature
reduce the standby operating power by means of a patented • Accurate Maximum Duty Cycle Setting
standby ladder mode operation of the converter significantly
• Demagnetization (Zero Current Detection) Protection
reducing the converter consumption in standby mode.
• Internally Trimmed Reference
Current or Voltage Mode Controller
GreenLine Controller:
• Operation Up to 250 kHz Output Switching Frequency
• Inherent Feed Forward Compensation
• Patented Standby Ladder Mode for Low Standby Losses
• Latching PWM for Cycle–by–Cycle Current Limiting
• Low dV/dT for Low EMI
• Oscillator with Precise Frequency Control

Single–Ended GreenLine Controllers (continued)
High Safety Latched Mode GreenLine PWM Controller

for (Multi)Synchronized Applications
MC44605P
TA = –25° to +85°C, Case 648
The MC44605 is a high performance current mode • High Current Totem Pole Output
controller that is specifically designed for off–line converters. • Undervoltage Lockout with Hysteresis
The MC44605 has several distinguishing features that make • Low Output dV/dT for Low EMI
it particularly suitable for multisynchronized monitor • Low Startup and Operating Current
applications.
The MC44605 synchronization arrangement enables Safety/Protection Features
operation from 16 kHz up to 130 kHz. This product was • Soft–Start Feature
optimized to operate with universal ac mains voltage from • Demagnetization (Zero Current Detection) Protection
80 V to 280 V, and its high current totem pole output makes • Overvoltage Protection Facility Against Open Loop
it ideally suited for driving a power MOSFET. • EHT Overvoltage Protection (E.H.T.OVP): Protection
The MC44605 protections provide well controlled, safe Against Excessive Amplitude Synchronization Pulses
power management. Safety enhancements detect four • Winding Short Circuit Detection (W.S.C.D.)
different fault conditions and provide protection through a • Limitation of the Maximum Input Power (M.P.L.):
disabling latch. Calculation of Input Power for Overload Protection
Current or Voltage Mode Controller • Over Heating Detection (O.H.D.): to Prevent the Power
Switch from Excessive Heating
• Current Mode Operation Up to 250 kHz Output Switching
Frequency Latched Disabling Mode
• Inherent Feed Forward Compensation • When one of the following faults is detected: EHT
• Latching PWM for Cycle–by–Cycle Current Limiting overvoltage, Winding Short Circuit (WSCD), excessive
• Oscillator with Precise Frequency Control input power (M.P.L.), power switch over heating (O.H.D.),
• Externally Programmable Reference Current a counter is activated
• Secondary or Primary Sensing (Availability of Error • If the counter is activated for a time that is long enough,
Amplifier Output) the circuit gets definitively disabled. The latch can only be
• Synchronization Facility reset by removing and then re–applying power

Very High Voltage Switching Regulator

MC33362DW, P
TJ = –25° to +125°C, Case 751N, 658E
The MC33362 is a monolithic high voltage switching thermal shutdown. This device is available in a 16–lead
regulator that is specifically designed to operate from a dual–in–line and wide body surface mount packages.
rectified 120 VAC line source. This integrated circuit features • On–Chip 500 V, 2.0 A SenseFET Power Switch
an on–chip 500 V/2.0 A SenseFET power switch, 250 V active • Rectified 120 VAC Line Source Operation
off–line startup FET, duty cycle controlled oscillator, current • On–Chip 250 V Active Off–Line Startup FET
limiting comparator with a programmable threshold and • Latching PWM for Double Pulse Suppression
leading edge blanking, latching pulse width modulator for • Cycle–By–Cycle Current Limiting
double pulse suppression, high gain error amplifier, and a • Input Undervoltage Lockout with Hysteresis
trimmed internal bandgap reference. Protective features • Output Overvoltage Protection Comparator
include cycle–by–cycle current limiting, input undervoltage • Trimmed Internal Bandgap Reference
lockout with hysteresis, output overvoltage protection, and • Internal Thermal Shutdown
20 W Off–Line Converter
AC Input
Startup Input 1
Regulator Startup
Output Mirror VCC
Reg
8 3
DC Output
UVLO Overvoltage
Protection Input
6
RT OVP 11
PWM Latch 16
Osc
CT 7 Power Switch
S Driver
Drain
Q
R
PWM
LEB
Ipk
Thermal Compensation
EA 10
Voltage Feedback
Input
Gnd 4, 5, 12, 13

Very High Voltage Switching Regulator

MC33363DW, P, MC33363ADW, P
TJ = –25° to +125°C, Case 751N, 648E
The MC33363 is a monolithic high voltage switching • On–Chip 700 V, 1.0 A SenseFET Power Switch
regulator that is specifically designed to operate from a • On–Chip 700 V, 1.5 A SenseFET Power Switch in
rectified 240 Vac line source. This integrated circuit features MC33363A
an on–chip 700 V/1.0 A (1.5 A in MC33363A) SenseFET • Rectified 240 Vac Line Source Operation
power switch, 450 V active off–line startup FET, duty cycle • On–Chip 450 V Active Off–Line Startup FET
controlled oscillator, current limiting comparator with a • Latching PWM for Double Pulse Suppression
programmable threshold and leading edge blanking, latching • Cycle–By–Cycle Current Limiting
pulse width modulator for double pulse suppression, high gain • Input Undervoltage Lockout with Hysteresis
error amplifier, and a trimmed internal bandgap reference. • Output Overvoltage Protection Comparator
Protective features include cycle–by–cycle current limiting, • Trimmed Internal Bandgap Reference
input undervoltage lockout with hysteresis, output overvoltage • Internal Thermal Shutdown
protection, and thermal shutdown. This device is available in
a 16–lead wide body surface mount package.
AC Input
Startup Input 1
Startup
Regulator Mirror VCC
Output
Reg
8 3
DC Output
UVLO
Overvoltage
6 Protection Input
RT OVP 11
PWM Latch 16
Osc
CT 7 Power Switch
S Driver
Drain
Q
R
PWM
LEB
Ipk
Thermal Compensation
EA 10
Voltage
Feedback
Gnd 4, 5, 12, 13 Input

Critical Conduction SMPS Controller

MC33364D, D1, D2
TJ = –25° to +125°C, Case 751, 751B
The MC33364 series are variable frequency SMPS frequency clamp limits the maximum operating frequency,
controllers that operate in the critical conduction mode. They preventing excessive switching losses and EMI radiation.
are optimized for low power, high density power supplies The MC33364D2 is available in the SO–8 package without
requiring minimum board area, reduced component count, an internal frequency clamp.
and low power dissipation. Each narrow body SOIC package The MC33364D is available in the SO–16 package. It
provides a small footprint. Integration of the high voltage has an internal 144 kHz frequency clamp which is pinned
startup saves approximately 0.7 W of power compared to out, so that the designer can adjust the clamp frequency
resistor bootstrapped circuits. by connecting appropriate values of resistance and
Each MC33364 features an on–board reference, UVLO capacitance.
function, a watchdog timer to initiate output switching, a zero • Lossless Off–Line Startup
current detector to ensure critical conduction operation, a • Leading Edge Blanking for Noise Immunity
current sensing comparator, leading edge blanking, and a • Watchdog Timer to Initiate Switching
CMOS driver. Protection features include the ability to shut • Minimum Number of Support Components
down switching, and cycle–by–cycle current limiting. • Shutdown Capability
The MC33364D1 is available in a surface mount SO–8 • Over Temperature Protection
package. It has an internal 144 kHz frequency clamp. For • Optional Frequency Clamp
loads which have a low power operating condition, the
Line
Restart
Delay
PWM VCC
Comparator VCC
FB UVLO
S
Leading Vref Bandgap Vref
R Q
Current Edge R UVLO Reference
Sense Blanking Gnd
Watchdog
Zero Timer
ZC Det Current Gate
Detector Thermal Frequency
Shutdown Optional
Clamp
Frequency
Clamp

Special Switching Regulator Controllers
These high performance dual channel controllers are and lower voltage dc–to–dc converters, respectively.
optimized for off–line, ac–to–dc power supplies and dc–to–dc Applications include desktop computers, peripherals,
converters in the flyback topology. They also have televisions, games, and various consumer appliances.
undervoltage lockout voltages which are optimized for off–line
Table 11. Dual Channel Controllers

Minimum Maximum
Operating Useful
500 4.0 Voltage 1.25 ± 2.0% 700 MC34270 0 to +70 FB/873A
MC34271
±1000 11 to 15.5 Current 5.0 ± 2.6% 500 MC34065 0 to +70 DW/751G
(T t
(Totem Pole
P l MOSFET
P/648
Drive Out
Outputs)
uts)
MC33065 –40 to +85 DW/751G
P/648
11 to 20 MC34065 0 to +70 DW–H/751G
P–H/648
MC33065 –40 to +85 DW–H/751G
P–H/648
8.4 to 20 MC34065 0 to +70 DW–L/751G
P–L/648
MC33065 –40 to +85 DW–L/751G
P–L/648
Table 12. Universal Microprocessor Power Supply Controllers

A versatile power supply control circuit for microprocessor–based systems, this device is mainly intended for automotive
applications and battery powered instruments. The circuit provides a power–on reset delay and a Watchdog feature for orderly
microprocessor operation.
VCC
Key
(V)
Regulated Output Reference Supervisory TA
Outputs Current (mA) Min Max (V) Features Device (°C) Package
E2PROM Programmable 150 peak 6.0 35 2.5 ± 3.2% MPU Reset and TCF5600 –40 to +85 707
Output: Watchdog TCA5600
24 V (Write Mode) Circuit
5.0 V (Read Mode)

Table 13. Power Factor Controllers
Minimum
Operating Maximum
IO Voltage Startup
Start p
(mA) Range Voltage Reference TA Suffix/
Max (V) (V) (V) Features Device (°C) Package
± 500 9.0 to 30 30 2.5 ± 1.4% Undervoltage Lockout, MC34261 0 to +70 D/751
(T t
(Totem P l MOSFET
Pole I t l Startup
Internal St t
P/626
Drive Out
Outputs)
uts) Timer
MC33261 –40 to +85 D/751
P/626
Overvoltage MC34262 0 to +85 D/751
Comparator,
C t
P/626
Undervoltage Lockout,
Internal Startup MC33262 –40 to +105 D/751
Timer P/626
1500 9.0 to 16 500 5.0 ± 1.5% Off–Line High Voltage MC33368 –25 to +125 D/751K
(CMOS Totem Pole Startup Overvoltage
MOSFET Drive Comparator,
Outputs) Undervoltage Lockout,
Timer, Low Load Detect

Power Factor Controllers
MC34262D, P
TA = 0° to +85°C, Case 751, 626
MC33262D, P
TA = –40° to +105°C, Case 751, 626
The MC34262, MC33262 series are active power factor Also included are protective features consisting of an
controllers specifically designed for use as a preconverter in overvoltage comparator to eliminate runaway output voltage
electronic ballast and in off–line power converter applications. due to load removal, input undervoltage lockout with
These integrated circuits feature an internal startup timer for hysteresis, cycle–by–cycle current limiting, multiplier output
stand alone applications, a one quadrant multiplier for near clamp that limits maximum peak switch current, an RS latch
unity power factor, zero current detector to ensure critical for single pulse metering, and a drive output high state clamp
conduction operation, transconductance error amplifier, for MOSFET gate protection. These devices are available in
quickstart circuit for enhanced startup, trimmed internal dual–in–line and surface mount plastic packages.
bandgap reference, current sensing comparator, and a totem
pole output ideally suited for driving a power MOSFET.
1 100 k
1N4934
MC34262
36 V 100
Zero Current 1.2 V
85 to 265 RFI Detector
Vac Filter 6.7 V 22 k
1.6 V T
UVLO
2.5 V
Reference
14 V MUR460
VO
Timer R 16 V
MTP 330 400 V/0.44 A
10
Drive 14N50E
Delay Output
10
RS
Latch
1.3 M 20 k 1.6 M
Overvoltage 10 pF 0.1
Current Sense 1.5 V Comparator
Comparator
1.08 Vref
Error Amp
10 µA
Multiplier Vref
0.01 12 k
10 k
Quickstart
0.68

Power Factor Controllers (continued)
MC33368D
TJ = –25° to +125°C, Case 751K
The MC33368 is an active power factor controller that reference, an undervoltage lockout (UVLO) circuit which
functions as a boost preconverter in off–line power supply monitors the VCC supply voltage, and a CMOS driver for
applications. MC33368 is optimized for low power, high driving MOSFETs. The MC33368 also includes a
density power supplies requiring minimum board area, programmable output switching frequency clamp. Protection
reduced component count, and low power dissipation. The features include an output overvoltage comparator to
narrow body SOIC package provides a small footprint. minimize overshoot, a restart delay timer, and cycle–by–
Integration of the high voltage startup saves approximately cycle current limiting.
0.7 W of power compared to resistor bootstrapped circuits. • Lossless Off–Line Startup
The MC33368 features a watchdog timer to initiate output • Output Overvoltage Comparator
switching, a one quadrant multiplier to force the line current to • Leading Edge Blanking (LEB) for Noise Immunity
follow the instantaneous line voltage, a zero current detector • Watchdog Timer to Initiate Switching
to ensure critical conduction operation, a transconductance • Restart Delay Timer
error amplifier, a current sensing comparator, a 5.0 V
D2 1N5406 C5
D4
1
92 to D1 D3
270 EMI
Vac Filter
16 Line
Vref Vref MC33368
R8
10 k
RD
15 V D8 R13 D6
2
C9 VCC 1N4744 51 1N4934
UVLO
330
AGND 12
µF Q Timer R Zero C4
8 Current 13/8.0 100
Detect 7 15 V
RS Latch ZCD T
R4
R 22 k MUR460
1.5 V
R D5
S Gate
S Q
11 Q1 400 V
1.5 V S
Set C3
PGND R11
Dominant 330
10
Overvoltage 10 Vref
Comparator MTW
14N50E
R10
Low Load R2
15 k
Detect Frequency FC 820 k
R5 Clamp C7
1.3 M 13
1.08 X Vref 470 pF
Quickstart LEB
9
CS
Leading Edge
Blanking 6 C8 R9
.001 10
Error Amp
MULT R7
5 0.1
5.0 V
Multiplier Reference
R3 C2 Comp 4 Vref 1 FB 3
10 k 0.01 C1
0.68
Vref R1
C6 10 k
0.1

Supervisory Circuits
A variety of Power Supervisory Circuits are offered. pin–programmable trip voltages or additional features, such
Overvoltage sensing circuits which drive ‘‘Crowbar’’ SCRs as an indicator output drive and remote activation capability.
are provided in several configurations from a low cost An over/undervoltage protection circuit is also offered.
three–terminal version to 8–pin devices which provide
Overvoltage Crowbar Sensing Circuit

MC3423P1, D
TA = 0° to +70°C, Case 626, 751
VCC 1
This device can protect sensitive
circuitry from power supply transients or
regulator failure when used with an external
200 µA
‘‘Crowbar’’ SCR. The device senses
4
voltage and compares it to an internal 2.6 V
reference. Overvoltage trip is adjustable by Current
2
means of an external resistive voltage Source
divider. A minimum duration before trip is Sense 1
programmable with an external capacitor.
Other features include a 300 mA high
current output for driving the gate of a
Vref
‘‘Crowbar’’ SCR, an open–collector 8
2.6 V
indicator output and remote activation
capability. Output
7 3 5 6
VEE Sense 2 Indicator
Remote Output
Activation
Over/Undervoltage Protection Circuit

MC3425P1
TA = 0° to +70°C, Case 626
VCC
The MC3425 is a power supply 8
supervisory circuit containing all the
OV
necessary functions required to monitor Sense
over and undervoltage fault conditions. 200 µA
This device features dedicated over and 3
undervoltage sensing channels with
independently programmable time delays.
OV
The overvoltage channel has a high current Drive
drive output for use in conjunction with an 1
external SCR ‘‘Crowbar’’ for shutdown. The
undervoltage channel input comparator 6
200 µA
UV
has hysteresis which is externally UV Indicator
programmable, and an open–collector Sense
output for fault indication. IH
4 2.5 V
Vref
12.5 µA
5 2 7 Gnd
Input Section UV OV Output Section
DLY DLY

Supervisory Circuits (continued)
CMOS Micropower Undervoltage Sensing Circuits
MC33464H, N
TA = –30° to +80°C, Case 1213, 1212
The MC33464 series are micropower undervoltage sensing Applications include direct monitoring of the MPU/logic
circuits that are specifically designed for use with battery power supply used in portable, appliance, automotive and
powered microprocessor based systems, where extended industrial equipment.
battery life is required. A choice of several threshold voltages
MC33464 Features:
from 0.9 V to 4.5 V are available. These devices feature a very
• Extremely Low Standby Current of 0.8 µA at Vin = 1.5 V
low quiescent bias current of 0.8 µA typical.
The MC33464 series features a highly accurate voltage • Wide Input Voltage Range (0.7 V to 10 V)
reference, a comparator with precise thresholds and built–in • Monitors Power Supply Voltages from 1.1 V to 5.0 V
hysteresis to prevent erratic reset operation, a choice of • High Accuracy Detector Threshold (±2.5%)
output configurations between open drain or complementary • Two Reset Output Types (Open Drain or Complementary
MOS, and guaranteed operation below 1.0 V with extremely Drive)
low standby current. These devices are available in either • Two Surface Mount Packages (SOT–89 or SOT–23
SOT–89 3–pin or SOT–23 5–pin surface mount packages. 5–Pin)
Threshold Operating Package
Device Voltage Type Temperature Range (Qty/Reel)
MC33464H–09AT1 0.9
MC33464H–20AT1 2.0 Open
MC33464H–27AT1 2.7 Drain
MC33464H–30AT1 3.0 Reset
MC33464H–45AT1 4.5 SOT–89
MC33464H–09CT1 0.9 (1000)
MC33464H–20CT1 2.0 Compl.
MC33464H–27CT1 2.7 MOS
MC33464H–30CT1 3.0 Reset
MC33464H–45CT1 4.5
TA = –30°
30° to +80°C
MC33464N–09ATR 0.9
MC33464N–20ATR 2.0 Open
MC33464N–27ATR 2.7 Drain
MC33464N–30ATR 3.0 Reset
MC33464N–45ATR 4.5 SOT–23
MC33464N–09CTR 0.9 (3000)
MC33464N–20CTR 2.0 Compl.
MC33464N–27CTR 2.7 MOS
MC33464N–30CTR 3.0 Reset
MC33464N–45CTR 4.5
Other voltages from 0.9 to 6.0 V, in 0.1 V increments, are available upon request. Consult your local Motorola
MC33464X–YYATZ MC33464X–YYCTZ
Open Drain Configuration Complementary Drive Configuration
2 Input 2 Input
1
Reset
1
Reset
Vref Vref
3 Gnd X Denotes Package Type 3 Gnd

YY Denotes Threshold Voltage
TZ Denotes Taping Type

CMOS Micropower Undervoltage Sensing Circuits with Output Delay
MC33465N
TA = –30° to +80°C, Case 1212
The MC33465 series are micropower undervoltage Applications include direct monitoring of the MPU/logic
sensing circuits that are specifically designed for use with power supply used in portable, appliance, automotive and
battery powered microprocessor based systems, where industrial equipment.
extended battery life is required. A choice of several
threshold voltages from 0.9 V to 4.5 V are available. This MC33465 Features:
device features a very low quiescent bias current of 1.0 µA • Extremely Low Standby Current of 1.0 µA at Vin = 3.5 V
typical. • Wide Input Voltage Range (0.7 V to 10 V)
The MC33465 series features a highly accurate voltage • Monitors Power Supply Voltages from 1.1 V to 5.0 V
reference, a comparator with precise thresholds and built–in • High Accuracy Detector Threshold (±2.5%)
hysteresis to prevent erratic reset operation, a choice of • Two Reset Output Types (Open Drain or Complementary
output configurations between open drain or complementary Drive)
MOS, a time delayed output, which can be programmed by • Programmable Output Delay by External Capacitor (100
the system designer, and guaranteed operation below 1.0 V ms typ. with 0.15 µF)
with extremely low standby current. This device is available • Surface Mount Package (SOT–23 5–Pin)
in a SOT–23 5–pin surface mount packages. • Convenient Tape and Reel (3000 per Reel)
Threshold Operating
Device Voltage Type Temperature Range Package
MC33465N–09ATR 0.9
MC33465N–20ATR 2.0 Open
MC33465N–27ATR 2.7 Drain
MC33465N–30ATR 3.0 Reset
MC33465N–45ATR 4.5
30° to +80°C
TA = –30° SOT 23
SOT–23
MC33465N–09CTR 0.9
MC33465N–20CTR 2.0 Compl.
MC33465N–27CTR 2.7 MOS
MC33465N–30CTR 3.0 Reset
MC33465N–45CTR 4.5
Other voltages from 0.9 to 6.0 V, in 0.1 V increments, are available upon request. Consult your local Motorola
MC33465N–YYATZ MC33465N–YYCTZ
Open Drain Configuration Complementary Drive Configuration
2 Input 1 Reset 2 Input
RD RD
1
Reset
Vref Vref
3 Gnd 5 CD 3 Gnd 5 CD
YY Denotes Threshold Voltage
TZ Denotes Taping Type

Undervoltage Sensing Circuit

MC34064P–5, D–5, DM–5
TA = 0° to +70°C, Case 29, 751, 846A Input
MC33064P–5, D–5, DM–5 2 (2)
TA = –40° to +85°C, Case 29, 751, 846A Reset
1 (1)
MC34164P–3, P–5, D–3, D–5, DM–3, DM–5
TA = 0° to +70°C, Case 29, 751, 846A Pin numbers in
MC33164P–3, P–5, D–3, D–5, DM–3, DM–5 parenthesis
are for the
TA = –40° to +85°C, Case 29, 751, 846A D suffix package.
The MC34064 and MC34164 are two families of 1.2 Vref
undervoltage sensing circuits specifically designed for use as
reset controllers in microprocessor–based systems. They
offer the designer an economical solution for low voltage 3 (4)
detection with a single external resistor. Both parts feature a Gnd
trimmed bandgap reference, and a comparator with precise
thresholds and built–in hysteresis to prevent erratic reset 3.0 V ± 5% power supplies with significantly lower power
operation. consumption, making them ideal for applications where
The two families of undervoltage sensing circuits taken extended battery life is required such as consumer products
together, cover the needs of the most commonly specified or hand held equipment.
power supplies used in MCU/MPU systems. Key parameter Applications include direct monitoring of the 5.0 V MPU/
specifications of the MC34164 family were chosen to logic power supply used in appliance, automotive, consumer,
complement the MC34064 series. The table summarizes and industrial equipment.
critical parameters of both families. The MC34064 fulfills the The MC34164 is specifically designed for battery powered
needs of a 5.0 V ± 5% system and features a tighter hysteresis applications where low bias current (1/25th of the MC34064’s)
specification. The MC34164 series covers 5.0 V ± 10% and is an important characteristic.
Table 14. Undervoltage Sense/Reset Controller Features

MC34X64 devices are specified to operate from 0° to +70°C, and MC33X64 devices operate from –40° to +85°C.
Power
Standard Typical Typical Minimum Supply Maximum
Power Threshold Hysteresis Output
O tp t Inp t
Input Quiescent
Q iescent
Supply Voltage Voltage Sink Voltage Input Suffix/
Device Supported (V) (V) Current (mA) Range (V) Current Package
MC34064/MC33064 5.0 V ± 5% 4.6 0.02 10 1.0 to 10 500 µA P–5/29
@
D–5/751
Vin = 5.0 V
DM–5/846A
MC34164/MC33164 5.0 V ± 10% 4.3 0.09 7.0 1.0 to 12 20 µA P–5/29
@
D–5/751
Vin = 5.0 V
DM–5/846A
MC34164/MC33164 3.0 V ± 5% 2.7 0.06 6.0 1.0 to 12 15 µA P–3/29
@
D–3/751
Vin = 3.0 V
DM–3/846A

Universal Voltage Monitor

MC34161P, D MC33161P, D
TA = 0° to +70°C, Case 626, 751 TA = –40° to +85°C, Case 626, 751
The MC34161, MC33161 series are universal voltage
monitors intended for use in a wide variety of voltage sensing VCC
applications. These devices offer the circuit designer an 8
economical solution for positive and negative voltage
detection. The circuit consists of two comparator channels
2.54 V
each with hysteresis, a unique Mode Select Input for channel Vref
Reference
programming, a pinned out 2.54 V reference, and two open 1
collector outputs capable of sinking in excess of 10 mA. Each
Mode Channel 1
comparator channel can be configured as either inverting or
Select 7
noninverting by the Mode Select Input. This allows over,
2.8 V Output 1
under, and window detection of positive and negative 6
Input 1
voltages. The minimum supply voltage needed for these 2
devices to be fully functional is 2.0 V for positive voltage
1.27 V
sensing and 4.0 V for negative voltage sensing.
Applications include direct monitoring of positive and Channel 2
negative voltages used in appliance, automotive, consumer,
and industrial equipment. Output 2
• Unique Mode Select Input Allows Channel Programming 0.6 V
Input 2 5
• Over, Under, and Window Voltage Detection 3
• Positive and Negative Voltage Detection 1.27 V
• Fully Functional at 2.0 V for Positive Voltage Sensing and
4.0 V for Negative Voltage Sensing
Gnd 4
• Pinned Out 2.54 V Reference with Current Limit Protection
• Low Standby Current
• Open Collector Outputs for Enhanced Device Flexibility
TRUTH TABLE
Mode Select Input 1 Output 1 Input 2 Output 2
Pin 7 Pin 2 Pin 6 Pin 3 Pin 5 Comments
GND 0 0 0 0 Channels 1 & 2: Noninverting
1 1 1 1
Vref 0 0 0 1 Channel 1: Noninverting
1 1 1 0 Channel 2: Inverting
VCC (>2.0 V) 0 1 0 1 Channels 1 & 2: Inverting
1 0 1 0
POSITIVE AND NEGATIVE OVERVOLTAGE DETECTOR VCC
8
V4
Input VS2 VHys2 2.54 V
V3 Reference
1
Gnd –
7 + +
R4
–VS1 + 2.8 V
V1 6
Input –VS1 VHys1 R3 2 + –
V2
1.27 V –
Output VCC + +
R2
Voltage LED “On” VS2 + 0.6 V
5
Pins 5, 6 Gnd 3 + –
R1 1.27 V

Battery Management Circuits
Battery Charger ICs
Battery Fast Charge Controller
MC33340P, D
TA = –25° to +85°C, Case 626, 751
The MC33340 is a monolithic control IC that is specifically a rapid test mode are available for enhanced end product
designed as a fast charge controller for Nickel Cadmium testing. This device is available in an economical 8–lead
(NiCd) and Nickel Metal Hydride (NiMH) batteries. This device surface mount package.
features negative slope voltage detection as the primary • Negative Slope Voltage Detection
means for fast charge termination. Accurate detection is • Accurate Zero Current Battery Voltage Sensing
ensured by an output that momentarily interrupts the charge • Programmable 1 to 4 Hour Fast Charge Time Limit
current for precise voltage sampling. An additional secondary • Programmable Over/Under Temperature Detection
backup termination method can be selected that consists of • Battery Over and Undervoltage Fast Charge Protection
either a programmable time or temperature limit. Protective • Rapid System Test Mode
features include battery over and undervoltage detection, • Power Supply Input Undervoltage Lockout with
latched over temperature detection, and power supply input Hysteresis
undervoltage lockout with hysteresis. Provisions for entering • Operating Voltage Range of 3.0 V to 18 V
DC
Input VCC 8
Regulator
Undervoltage
Lockout
Internal Bias
VCC
Vsen Voltage to
Frequency
Converter Over
1
Temp
Latch
Ck F/V R R
High Over Q Battery
S Pack
Battery Temp
Detect Detect
Low Under
t1/Tref High
t1
–∆V Detect 7
Counter
Vsen Timer t2/Tsen
Gate t2
Vsen 6
2 Gate
t3/Tref Low
t3
3 5
Fast/ VCC
F/T t/T
Trickle Time/
Temp
Select
Gnd 4

Battery Charger ICs (continued)
Power Supply
Battery Charger
Regulation Control Circuit
MC33341P, D
TA = –40° to +85°C, Case 626, 751
The MC33341 is a monolithic regulation control circuit that • Differential Amplifier for High–Side Source and Load
is specifically designed to close the voltage and current Current Sensing
feedback loops in power supply and battery charger • Inverting Amplifier for Source Return Low–Side Current
applications. This device features the unique ability to perform Sensing
source high–side, load high–side, source low–side, and load • Noninverting Input Path for Load Low–Side Current
low–side current sensing, each with either an internally fixed Sensing
or externally adjustable threshold. The various current • Fixed or Adjustable Current Threshold in all Current
sensing modes are accomplished by a means of selectively Sensing Modes
using the internal differential amplifier, inverting amplifier, or a • Positive Voltage Sensing in all Current Sensing Modes
direct input path. Positive voltage sensing is performed by an • Fixed Voltage Threshold in all Current Sensing Modes
internal voltage amplifier. The voltage amplifier threshold is • Adjustable Voltage Threshold in all Low–Side Current
internally fixed and can be externally adjusted in all low–side Sensing Modes
current sensing applications. An active high drive output is • Output Driver Directly Interfaces with Economical
provided to directly interface with economical optoisolators for Optoisolators
isolated output power systems. This device is available in • Operating Voltage Range of 2.3 V to 18 V
8–lead dual–in–line and surface mount packages.
Current Sense Input B/ Voltage Sense

Drive Output VCC Voltage Threshold Adjust Input
8 7 6 5
VCC VCC
VCC
VCC
1.2 V Differential Amp 1.2 V
Disable Logic 0.4 V
Vsen
Transconductance
VCC
Vth V Amp
Differential Amp
Isen
R
R Ith I
VCC
R
R
VCC Reference
R
R
VCC 0.2 V 0.4 V 1.2 V
VCC
0.2 V
Inverting Amp
1 2 3 4
Current Sense Current Compensation Gnd
Input A Threshold Adjust

Battery Pack ICs
Lithium Battery Protection Circuit for One to Four Cell Battery Packs
MC33345DW, DTB
TA = –25° to +85°C, Case 751D, 948E
The MC33345 is a monolithic lithium battery protection • Charge and Discharge Current Limit Detection with
circuit that is designed to enhance the useful operating life of Delayed Shutdown
one to four cell rechargeable battery packs. Cell protection
• Cell Voltage Balancing
features consist of independently programmable charge and
discharge limits for both voltage and current with a delayed • On–Chip Balancing Resistors
current shutdown, cell voltage balancing with on–chip
balancing resistors, and a virtually zero current sleepmode • Virtually Zero Current Sleepmode State when Cells are
state when the cells are discharged. Additional features Discharged
include an on–chip charge pump for reduced MOSFET losses • Charge Pump for Reduced Losses with a Low Cell
while charging or discharging a low cell voltage battery pack, Voltage Battery Pack
and the programmability for a one to four cell battery pack.
This protection circuit requires a minimum number of external • Programmable for One, Two, Three or Four Cell
components and is targeted for inclusion within the battery Applications
pack. The MC33345 is available in standard and low profile 20 • Minimum External Components for Inclusion within the
lead surface mount packages. Battery Pack
• Independently Programmable Charge and Discharge • Available in Low Profile Surface Mount Packages
Limits for Both Voltage and Current
Typical Four Cell Smart Battery Pack
Cell 4/VCC/
Discharge Current Sense Charge
Current Limit Common 6 7 Current Limit
Cell 3 Cell Voltage
20 3
Discharge Voltage
Threshold
Cell 2
4
19 Charge Voltage
Threshold
Cell 1/VC MC33345
5
18 Cell Voltage
Return
Ground
1
16 Test Input
Program 1
15
11
Fault Output
Program 2
17
10
Charge Pump 14 Discharge 13 Charge 9 8 Charge
Output Gate Drive Gate Drive Gate Drive
Output Output Common

Battery Pack ICs (continued)
Lithium Battery Protection Circuit for Three or Four Cell Battery Packs
MC33346DW, DTB
TA = –40° to +85°C, Case 751E, 948H
The MC33346 is a monolithic lithium battery protection • Independently Programmable Charge and Discharge
circuit that is designed to enhance the useful operating life of Limits for Both Voltage and Current
three or four cell rechargeable battery packs. Cell protection
features consist of independently programmable charge and • Delayed Current Shutdown
discharge limits for both voltage and current with a delayed • Cell Voltage Balancing with On–Chip Resistors
current shutdown, cell voltage balancing with on–chip
balancing resistors, and virtually zero current sleepmode • Six Wire Microcontroller Interface Bus
state when the cells are discharged. Additional features • Data Output for Reference, Voltage, Current, and
consists of a six wire microcontroller interface bus that can Temperature
selectively provide a pulse output that represents the internal
reference voltage, cell voltage, cell current and temperature, • Microcontroller Time Reference Output for Gas Gauging
as well as control the states of four internal balancing and two
• Virtually Zero Current Sleepmode State when Cells are
external MOSFET switches. A microcontroller time reference
Discharged
output is available for gas gauge implementation. This
protection circuit requires a minimum number of external • Programmable for Three or Four Cell Applications
components and is targeted for inclusion within the battery
pack. The MC33346 is available in standard and low profile • Minimum External Components for Inclusion within the
24 lead surface mount packages. Battery Pack
• Available in Low Profile Surface Mount Packages
Current Charge Discharge Charge Charge

Cell 4/VCC/ Sense Current Gate Drive Gate Drive Gate Drive
Discharge Common Limit Output Output Common
Current Limit 7 6 14 20 21 Cell Voltage
3 2
Discharge Voltage
Cell 3 Threshold
24 4
Charge Voltage
Cell 2 Threshold
23 5
Cell Voltage
Cell 1 MC33346 Return
22 1
Data Output
Ground Ref/V/I/T
Cell 15 16
Program Reference Clock Output
11 19
Temp Interrupt Output
8 12
17 18 13 10 9
A–to–D VC Address Data Charge Gate
Converter Logic Input Input Turn Off/
Period Supply Test Input

Lithium Battery Protection Circuit for One or Two Cell Battery Packs
MC33347D, DTB
TA = –25° to +85°C, Case 751B, 948F
The MC33347 is a monolithic lithium battery protection
• Charge and Discharge Current Limit Detection with
circuit that is designed to enhance the useful operating life of
Delayed Shutdown
one or two cell rechargeable battery packs. Cell protection
features consist of independently programmable charge and • Continuous Cell Voltage Balancing
discharge limits for both voltage and current with a delayed
current shutdown, continuous cell voltage balancing with the • On–Chip or External Balancing Resistors
choice of on–chip or external balancing resistors, and a • Virtually Zero Current Sleepmode State when Cells are
virtually zero current sleepmode state when the cells are Discharged
discharged. Additional features include an on–chip charge
pump for reduced MOSFET losses while charging or • Charge Pump for Reduced Losses with a Low Cell
discharging a low cell voltage battery pack, and the Voltage Battery Pack
programmability for one or two cell battery pack. This
• Programmable for One or Two Cell Applications
protection circuit requires a minimum number of external
components and is targeted for inclusion within the battery • Minimum External Components for Inclusion within the
pack. This MC33347 is avaialble in standard and low profile Battery Pack
16 lead surface mount packages.
• Independently Programmable Charge and Discharge
Limits for Both Voltage and Current
Typical Two Cell Smart Battery Pack
Cell Program/ Current Sense Charge

Test 13 Common 9 10 Current Limit
Cell 2/VCC/
Discharge Cell Voltage
Current Limit
6
4 Discharge Voltage
Balance 2 Threshold
2 MC33347 7
Cell 1/VC Charge Voltage
Threshold
3
8
Balance 1
Cell Voltage
1 Return
Ground 5
16

Lithium Battery Protection Circuit for One Cell Battery Packs
MC33348D, DM
TA = –25° to +85°C, Case 751, 846A
The MC33348 is a monolithic lithium battery protection Typical One Cell Smart Battery Pack
circuit that is designed to enhance the useful operating life of
one cell rechargeable battery pack. Cell protection features
consist of internally trimmed charge and discharge voltage
limits, discharge current limit detection with a delayed
shutdown, and a virtually zero current sleepmode state when 7 VCC
the cell is discharged. An additional feature includes an Cell
Voltage
on–chip charge pump for reduced MOSFET losses while
charging or discharging a low cell voltage battery pack. This 1
protection circuit requires a minimum number of external
components and is targeted for inclusion within the battery
pack. This MC33348 is available in standard and micro 8 lead MC33348
surface mount packages.
Ground
• Internally Trimmed Charge and Discharge Voltage Limits 3
Test
• Discharge Current Limit Detection with Delayed
2
Shutdown Charge Pump 8 Discharge 4 Charge 6 5 Charge
• Virtually Zero Current Sleepmode State when Cells are Output Output Common/
Discharge
Discharged Current Limit
• Charge Pump for Reduced Losses with a Low Cell

Voltage Battery Pack
• Dedicated for One Cell Applications
• Minimum Components for Inclusion within the Battery
Pack
Charge Charge Discharge Discharge
Overvoltage Overvoltage Undervoltage Current Limit Operating
Device Threshold (V) Hysteresis (mV) Threshold (V) Threshold (mV) Temperature Range Package
MC33348D–1 4.20 300 2.25 400 TA = –25° to +85°C SO–8
MC33348D–2 200
MC33348D–3 4.25 2.28 400
MC33348D–4 200
MC33348D–5 4.35 2.30 400
MC33348D–6 200
MC33348DM–1 4.20 2.25 400 Micro–8
MC33348DM–2 200
MC33348DM–3 4.25 2.28 400
MC33348DM–4 200
MC33348DM–5 4.35 2.30 400
MC33348DM–6 200
NOTE: Additional threshold limit options can be made available. Consult your local Motorola sales office for information.

MOSFET/IGBT Drivers
High Speed Dual Drivers
(Inverting) (Noninverting)
MC34151P, D MC34152P, D
TA = 0° to +70°C, Case 626, 751 TA = 0° to +70°C, Case 626, 751
MC33151P, D MC33152P, D
TA = –40° to +85°C, Case 626, 751 TA = –40° to +85°C, Case 626, 751
VCC
These two series of high speed dual MOSFET driver ICs 6 MC34151
are specifically designed for applications requiring low current
digital circuitry to drive large capacitive loads at high slew
rates. Both series feature a unique undervoltage lockout
function which puts the outputs in a defined low state in an
5.7 V
undervoltage condition. In addition, the low “on” state
resistance of these bipolar drivers allows significantly higher
output currents at lower supply voltages than with competing Logic Drive
Output A
drivers using CMOS technology. Input A 7
2 100 k
The MC34151 series is pin–compatible with the MMH0026
and DS0026 dual MOS clock drivers, and can be used as
drop–in replacements to upgrade system performance. The
MC34152 noninverting series is a mirror image of the inverting
MC34151 series.
These devices can enhance the drive capabilities of first Drive
generation switching regulators or systems designed with Logic Output B
Input B 5
CMOS/TTL logic devices. They can be used in dc–to–dc 4 100 k
converters, motor controllers, capacitor charge pump
converters, or virtually any other application requiring high
speed operation of power MOSFETs.
Gnd 3
VCC Short Circuit

Single IGBT Driver Output
Comparator
VCC
S
MC33153P, D Over– Q R Overcurrent Current
7 Comparator
current Sense
TA = –40° to +105°C, Case 626, 751 Latch
VEE S 1 Input
The MC33153 is specifically designed to drive the gate of Q VEE
R Kelvin
an IGBT used for ac induction motors. It can be used with VCC
Desat./Blank. VCC 2 Gnd
discrete IGBTs and IBGT modules up to 100 A. Comparator
Blanking
Typical applications are ac induction motor control, Desatirat
brushless dc motor control, and uninterruptable power 8 opm
VEE
supplies.
These devices are available in dual–in–line and surface VCC
mount packages and include the following features:
• High Current Output Stage : 1.0 A Source – 2.0 A Sink VCC
• Protection Circuits for Both Conventional and
Gate
SenseIGBTs Input Drive
• Current Source for Blanking Timing 4 VCC 5 Ouptut
• Protection Against Overcurrent and Short Circuit
VEE
• Undervoltage Lockout Optimized for IGBT’s VEE
3
• Negative Gate Drive Capability
VCC VEE VEE
6

MOSFET/IGBT Drivers (continued)
Single IGBT Gate Driver
MC33154D, P
TA = –40° to +85°C, Case 626, 751
The MC33154 is specifically designed as an IGBT driver
• High Current Output Stage: 4.0 A Source/2.0 A Sink
for high power applications including ac induction motor
control, brushless dc motor control and uninterruptible power • Protection Circuits for Both Conventional and Sense
supplies. IGBTs
The MC33154 is similar to the MC33153, except that the
output drive is in–phase with the logic input, the output • Programmable Fault Blanking Time
source current drive is four times higher and the supply • Protection against Overcurrent and Short Circuit
voltage rating is higher.
Although designed for driving discrete and module IGBTs, • Undervoltage Lockout Optimzed for IGBTs
this device offers a cost effective solution for driving power
MOSFETs and Bipolar Transistors.
These devices are available in dual–in–line and surface • Cost Effectively Drives Power MOSFETs and Bipolar
mount packages and include the following features: Transistors
VCC Short Circuit

Short Circuit Comparator
Latch
Fault S VCC
Output 7 Q
R Overcurrent
Current
Overcurrent Comparator
Sense
VEE Latch 130 mV 1 Input
S
Q
R 65 mV
VEE
VCC VCC Kelvin
VCC Gnd
2
VCC 1.0 mA
6 Fault
VEE 8 Blanking/
Desaturation
3 Desat/Blank 6.5 V Input
VEE
VEE Comparator
VCC
VCC Output
Stage
Gate
Input Drive
4 VCC 5 Output
Under
Voltage
VEE Lockout
VEE
12 V/
11 V

Power Supply Circuits Package Overview
CASE 314B
CASE 29 CASE 221A CASE 314A
TV SUFFIX
P, Z SUFFIX T, KC SUFFIX TH SUFFIX
CASE 314D CASE 369 CASE 369A CASE 626

T SUFFIX DT–1 SUFFIX DT SUFFIX N, P, P1 SUFFIX
CASE 646 CASES 648, 648C CASE 648E CASE 707

P SUFFIX N, P, P2 SUFFIX P SUFFIX N SUFFIX
CASE 751 CASE 751A CASE 751B CASE 751D

D, D1, D2 SUFFIX D SUFFIX D SUFFIX DW SUFFIX
CASE 751E CASE 751G CASE 751K CASE 751N

DW SUFFIX DW SUFFIX D SUFFIX DW SUFFIX

Power Supply Circuits Package Overview (continued)
CASE 775 CASE 846A CASE 873A CASE 936

FN SUFFIX DM SUFFIX FB SUFFIX D2T SUFFIX
CASE 936A CASE 948E CASE 948F CASE 948G

D2T SUFFIX DTB SUFFIX DTB SUFFIX DTB SUFFIX
CASE 948H CASE 1212 CASE 1213

DTB SUFFIX N SUFFIX H SUFFIX

Device Listing and Related Literature
Linear Voltage Regulators
LM317 Three–Terminal Adjustable Output Positive Voltage Regulator . . . . . . . . . 3–45
LM317L Three–Terminal Adjustable Output Voltage Regulator . . . . . . . . . . . . . . . . 3–53
LM317M Three–Terminal Adjustable Output Positive Voltage Regulator . . . . . . . . . 3–61
LM323, A Positive Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–69
LM337 Three–Terminal Adjustable Output Negative Voltage Regulator . . . . . . . . 3–75
LM337M Three–Terminal Adjustable Output Negative Voltage Regulator . . . . . . . . 3–82
LM340, A Series Three–Terminal Positive Fixed Voltage Regulators . . . . . . . . . . . . . . . . . . . 3–89
LM350 Three–Terminal Adjustable Output Positive Voltage Regulator . . . . . . . . . 3–105
LM2931 Series Low Dropout Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–136
LM2935 Low Dropout Dual Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–146
LP2950, 2951 Micropower Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–150
MC1723C Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–162
MC7800 Series Three–Terminal Positive Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . 3–182
MC78L00, A Series Three–Terminal Low Current Positive Voltage Regulators . . . . . . . . . . . . . 3–197
MC78M00 Series Three–Terminal Medium Current Positive Voltage Regulators . . . . . . . . . 3–204
MC78T00 Series Three–Ampere Positive Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . 3–213
MC78BC00 Series Micropower Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–222
MC78FC00 Series Micropower Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–223
MC78LC00 Series Micropower Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–224
MC7900 Series Three–Terminal Negative Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . 3–225
MC79L00, A Series Three–Terminal Low Current Negative Voltage Regulators . . . . . . . . . . . . 3–235
MC79M00 Series Three–Terminal Negative Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . 3–240
MC33264 Micropower Voltage Regulators with On/Off Control . . . . . . . . . . . . . . . . . . 3–273
MC33267 Low Dropout Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–280
MC33269 Low Dropout Positive Fixed and Adjustable Voltage Regulators . . . . . . . . 3–285
MC34268 SCSI–2 Active Terminator Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–638
TL780 Series Three–Terminal Positive Fixed Voltage Regulators . . . . . . . . . . . . . . . . . . . 3–736
Switching Regulator Control

LM2575 Easy Switcher 1.0 A Step–Down Voltage Regulator . . . . . . . . . . . . . . . . . . 3–113
MC33362 High Voltage Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–348
MC33363 High Voltage Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–359
MC33363A High Voltage Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–370
MC33364 Critical Conduction SMPS Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–371
MC33463 Variable Frequency Micropower DC–to–DC Converter . . . . . . . . . . . . . . . . 3–384
MC33466 Fixed Frequency PWM Micropower DC–to–DC Converter . . . . . . . . . . . . 3–390
MC34023, 33023 High Speed Single–Ended PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . 3–392
MC34025, 33025 High Speed Double–Ended PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . 3–408
MC34060A, 33060A Precision Switchmode Pulse Width Modulator Control Circuit . . . . . . . . . . 3–425
MC34063A, 33063A DC–to–DC Converter Control Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–437
MC34065, 33065 High Performance Dual Channel Current Mode Controller . . . . . . . . . . . . 3–451
MC34065–H, L, 33065–H, L High Performance Dual Channel Current Mode Controllers . . . . . . . . . . . 3–465
MC34066, 33066 High Performance Resonant Mode Controller . . . . . . . . . . . . . . . . . . . . . . . 3–478
MC34067, 33067 High Performance Resonant Mode Controllers . . . . . . . . . . . . . . . . . . . . . . 3–486
MC34129, 33129 High Performance Current Mode Controllers . . . . . . . . . . . . . . . . . . . . . . . . 3–499
MC34163, 33163 Power Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–550
SG3525A, 3527A Pulse Width Modulator Control Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–691
SG3526 Pulse Width Modulation Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–697

Switching Regulator Control (continued)
TL494 Switchmode Pulse Width Modulation Control Circuit . . . . . . . . . . . . . . . . . 3–716
TL594 Precision Switchmode Pulse Width Modulation Control Circuit . . . . . . . . . 3–726
UC3842A, 43A, High Performance Current Mode Controllers . . . . . . . . . . . . . . . . . . . . . . . . 3–742
UC2842A, 43A
UC3842B, 43B, High Performance Current Mode Controllers . . . . . . . . . . . . . . . . . . . . . . . . 3–755
UC2842B, 43B
UC3844, 45, UC2844, 45 High Performance Current Mode Controllers . . . . . . . . . . . . . . . . . . . . . . . . 3–769
UC3844B, 45B, High Performance Current Mode Controllers . . . . . . . . . . . . . . . . . . . . . . . . 3–782
UC2844B, 45B
µA78S40 Universal Switching Regulator Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . 3–796
Special Switching Regulator Controllers

MC34270, 34271 Liquid Crystal Display and Backlight Integrated Controller . . . . . . . . . . . . . 3–641
MC44602 High Performance Current Mode Controller . . . . . . . . . . . . . . . . . . . . . . . . . 3–651
MC44603 Mixed Frequency Mode GreenLine PWM Controller . . . . . . . . . . . . . . . . . . 3–667
MC44604 High Safety Standby Ladder Mode GreenLine PWM Controller . . . . . . . . 3–689
MC44605 High Safety Latched Mode GreenLine PWM Controller for
(Multi) Synchronized Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–690
TCA5600, TCF5600 Universal Microprocessor Power Supply/Controllers . . . . . . . . . . . . . . . . . 3–705
Power Factor Correction Controllers

MC34261, 33261 Power Factor Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–612
MC34262, 33262 Power Factor Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–623
MC33368 High Voltage GreenLine Power Factor Controller . . . . . . . . . . . . . . . . . . . . 3–372
Power Drivers
MC33153 Single IGBT Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–251
MC33154 Single IGBT Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–262
MC34151, 33151 High Speed Dual MOSFET Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–514
MC34152, 33152 High Speed Dual MOSFET Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–522
Power Supervisory
MC3423 Overvoltage Crowbar Sensing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–168
MC3425 Power Supply Supervisory/Over and Undervoltage Protection Circuit . . . 3–174
MC33128 Power Management Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–244
MC33169 GaAs Power Amplifier Support IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–263
MC33340 Battery Fast Charge Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–290
MC33341 Power Supply/Battery Charger Regulation Control Circuit . . . . . . . . . . . . . 3–301
MC33345 Lithium Battery Protection Circuit for
One to Four Cell Battery Packs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–316
MC33346 Lithium Battery Protection Circuit for
Three or Four Cell Battery Packs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–328
MC33347 Lithium Battery Protection Circuit for One or Two Cell Battery Packs . . . 3–329
MC33348 Lithium Battery Protection Circuit for One Cell Battery Packs . . . . . . . . . . 3–339
MC33464 Micropower Undervoltage Sensing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 3–386
MC33465 Micropower Undervoltage Sensing Circuits with Output Delay . . . . . . . . . 3–388
MC34064, 33064 Undervoltage Sensing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–446
MC34160, 33160 Microprocessor Voltage Regulator and Supervisory Circuit . . . . . . . . . . . . 3–530
MC34161, 33161 Universal Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–537
MC34164, 33164 Micropower Undervoltage Sensing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 3–564

ADDENDUM
Page
Linear & Switching Voltage Regulator Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–802
RELATED APPLICATION NOTES

App Note Title Related Device
AN703 Designing Digitally–Controlled Power Supplies . . . . . . . . . . . . . . . . . . . . MC1723C

AN719 A New Approach to Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . General
AN1040 Mounting Techniques for Power Semiconductors . . . . . . . . . . . . . . . . . . LM317, LM337,
MC7800, MC78M00,
MC7900, MC79M00
AN1065 Use of the MC68HC68T1 Real–Time Clock with
Multiple Time Bases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC34164, MC33164
AN1315 An Evaluation System Interfacing the MPX2000 Series
Pressure Sensors to a Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . MC34064, MC33064
AN920 Theory and Applications of the MC34063 and µA78S40
Switching Regulator Control CIrcuits . . . . . . . . . . . . . . . . . . . . . . . . . . . µA78S40
AN976 A New High Performance Current–Mode Controller Teams
Up with Current Sensing Power MOSFETs . . . . . . . . . . . . . . . . . . . . . MC34129
AN983 A Simplified Power Supply Design Using the TL494
Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL494
ANE424 50 W Current Mode Controlled Offline Switchmode
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UC3842A, UC2842A
UC3843A, UC2843A

LM317
Three-Terminal Adjustable
Output Positive Voltage
Regulator
The LM317 is an adjustable 3–terminal positive voltage regulator capable THREE–TERMINAL
of supplying in excess of 1.5 A over an output voltage range of 1.2 V to 37 V.
This voltage regulator is exceptionally easy to use and requires only two ADJUSTABLE POSITIVE
external resistors to set the output voltage. Further, it employs internal VOLTAGE REGULATOR
current limiting, thermal shutdown and safe area compensation, making it
essentially blow–out proof.
The LM317 serves a wide variety of applications including local, on card
SEMICONDUCTOR
regulation. This device can also be used to make a programmable output
TECHNICAL DATA
regulator, or by connecting a fixed resistor between the adjustment and
output, the LM317 can be used as a precision current regulator.
• Output Current in Excess of 1.5 A
• Output Adjustable between 1.2 V and 37 V
• Internal Thermal Overload Protection
• Internal Short Circuit Current Limiting Constant with Temperature
• Output Transistor Safe–Area Compensation
T SUFFIX
PLASTIC PACKAGE
• Floating Operation for High Voltage Applications CASE 221A
• Available in Surface Mount D2PAK, and Standard 3–Lead Transistor
Heatsink surface
Package connected to Pin 2.
• Eliminates Stocking many Fixed Voltages 1
2
3
Pin 1. Adjust
2. Vout
3. Vin
Standard Application
Vin Vout
LM317
D2T SUFFIX
R1 PLASTIC PACKAGE
240
IAdj CASE 936 2
Adjust (D2PAK) 1
Cin* + C ** 3
O
0.1 µF 1.0 µF
R2
Heatsink surface (shown as terminal 4 in
case outline drawing) is connected to Pin 2.
ǒ Ǔ
** Cin is required if regulator is located an appreciable distance from power supply filter. Operating
** CO is not needed for stability, however, it does improve transient response.
V out + 1.25 V 1 ) R ) IAdj R2

R2
LM317BD2T
TJ = – 40° to +125°C
Surface Mount
1 LM317BT Insertion Mount
Since IAdj is controlled to less than 100 µA, the error associated with this term is
LM317D2T Surface Mount
negligible in most applications. TJ = 0° to +125°C
LM317T Insertion Mount

LM317
MAXIMUM RATINGS
Input–Output Voltage Differential VI–VO 40 Vdc
Power Dissipation
Case 221A
TA = +25°C PD Internally Limited W
Thermal Resistance, Junction–to–Ambient θJA 65 °C/W
Thermal Resistance, Junction–to–Case θJC 5.0 °C/W
Case 936 (D2PAK)
Operating Junction Temperature Range TJ – 40 to +125 °C
ELECTRICAL CHARACTERISTICS (VI–VO = 5.0 V; IO = 0.5 A for D2T and T packages; TJ = Tlow to Thigh [Note 1]; Imax and Pmax
[Note 2]; unless otherwise noted.)
Line Regulation (Note 3), TA = +25°C, 3.0 V ≤ VI–VO ≤ 40 V 1 Regline – 0.01 0.04 %/V
Load Regulation (Note 3), TA = +25°C, 10 mA ≤ IO ≤ Imax 2 Regload
VO ≤ 5.0 V – 5.0 25 mV
VO ≥ 5.0 V – 0.1 0.5 % VO
Thermal Regulation, TA = +25°C (Note 6), 20 ms Pulse Regtherm – 0.03 0.07 % VO/W
Adjustment Pin Current 3 IAdj – 50 100 µA
Adjustment Pin Current Change, 2.5 V ≤ VI–VO ≤ 40 V, 1, 2 ∆IAdj – 0.2 5.0 µA
10 mA ≤ IL ≤ Imax, PD ≤ Pmax
Reference Voltage, 3.0 V ≤ VI–VO ≤ 40 V, 3 Vref 1.2 1.25 1.3 V

10 mA ≤ IO ≤ Imax, PD ≤ Pmax
Line Regulation (Note 3), 3.0 V ≤ VI–VO ≤ 40 V 1 Regline – 0.02 0.07 %V

Load Regulation (Note 3), 10 mA ≤ IO ≤ Imax 2 Regload
VO ≤ 5.0 V – 20 70 mV
VO ≥ 5.0 V – 0.3 1.5 % VO
Temperature Stability (Tlow ≤ TJ ≤ Thigh) 3 TS – 0.7 – % VO
Minimum Load Current to Maintain Regulation (VI–VO = 40 V) 3 ILmin – 3.5 10 mA
Maximum Output Current 3 Imax A
VI–VO ≤ 15 V, PD ≤ Pmax, T Package 1.5 2.2 –
VI–VO = 40 V, PD ≤ Pmax, TA = +25°C, T Package 0.15 0.4 –
RMS Noise, % of VO, TA = +25°C, 10 Hz ≤ f ≤ 10 kHz N – 0.003 – % VO
Ripple Rejection, VO = 10 V, f = 120 Hz (Note 4) 4 RR dB
Without CAdj – 65 –
CAdj = 10 µF 66 80 –
Long–Term Stability, TJ = Thigh (Note 5), TA = +25°C for 3 S – 0.3 1.0 %/1.0 k
Endpoint Measurements Hrs.
Thermal Resistance Junction to Case, T Package RθJC – 5.0 – °C/W

NOTES: 1. Tlow to Thigh = 0° to +125°C, for LM317T, D2T. Tlow to Thigh = – 40° to +125°C, for LM317BT, BD2T.
2. Imax = 1.5 A, Pmax = 20 W
3. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately.
Pulse testing with low duty cycle is used.
4. CAdj, when used, is connected between the adjustment pin and ground.
5. Since Long–Term Stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability
from lot to lot.
6. Power dissipation within an IC voltage regulator produces a temperature gradient on the die, affecting individual IC components on the die. These
effects can be minimized by proper integrated circuit design and layout techniques. Thermal Regulation is the effect of these temperature gradients
on the output voltage and is expressed in percentage of output change per watt of power change in a specified time.

LM317
Vin
31 310 230 120 5.6k
0 6.3V
170
160
6.7k 12k
5.0pF
125k 200 13k
12.4k 510
6.8k
135
6.3V
30 30
pF pF 2.4k 105
6.3V
190 3.6k 5.8k 110 5.1k 12.5k 4.0
0.1
Vout
Adjust
Figure 1. Line Regulation and ∆IAdj/Line Test Circuit

VCC
ń +
|V –V |
VIH OH OL VOH
* Line Regulation (% V) x 100
VIL |V | VOL
OL
Vin Vout
LM317
* Pulse testing required. Adjust

* 1% Duty Cycle R1 240 +
* is suggested. 1%
Cin 0.1 µF IAdj CO 1.0 µF RL
R2
1%

LM317
Figure 2. Load Regulation and ∆IAdj/Load Test Circuit
VI Vin Vout
LM317 IL
VO (min Load)
RL VO (max Load)
(max Load)
Adjust 240 RL
R1 1% *
(min Load)
+
Cin 0.1 µF IAdj CO 1.0 µF
* Pulse testing required.

R2 * 1% Duty Cycle is suggested.
1%
VO (min Load) – VO (max Load)

Load Regulation (mV) = VO (min Load) – VO (max Load) Load Regulation (% VO) = x 100
VO (min Load)
Figure 3. Standard Test Circuit
Vin Vout
LM317 IL
Adjust
240
VI R1 1% Vref RL
IAdj +
Cin 0.1 µF CO 1.0 µF VO
ISET
R2
1%
* Pulse testing required. To Calculate R2: Vout = ISET R2 + 1.250 V

* 1% Duty Cycle is suggested. To Calculate R2: Assume ISET = 5.25 mA
Figure 4. Ripple Rejection Test Circuit

24 V
Vin Vout
14 V LM317
f = 120 Hz
D1*
Adjust R1 240 RL
1% 1N4002 Vout = 10 V
+
+
1.65 k CAdj 10 µF
R2 1%
* D1 Discharges CAdj if output is shorted to Ground.

LM317
Figure 5. Load Regulation Figure 6. Current Limit

4.0
∆Vout, OUTPUT VOLTAGE CHANGE (%)
0.4
I out , OUTPUT CURRENT (A)

0.2 3.0
0 IL = 0.5 A TJ = 25°C
–0.2 2.0
IL = 1.5 A 150°C
–0.4
Vin = 15 V
–0.6 Vout = 10 V 1.0 55°C
–0.8
–1.0 0
–50 –25 0 25 50 75 100 125 150 0 10 20 30 40
TJ, JUNCTION TEMPERATURE (°C) Vin–Vout, INPUT–OUTPUT VOLTAGE DIFFERENTIAL (Vdc)
Figure 7. Adjustment Pin Current Figure 8. Dropout Voltage

3.0
I Adj, ADJUSTMENT PIN CURRENT ( µA)
V in–Vout, INPUT–OUTPUT VOLTAGE

70 ∆Vout = 100 mV
IL = 1.5 A
65 DIFFERENTIAL (Vdc) 2.5
60
1.0 A
55 2.0
50
500 mA
45 1.5
200 mA
40
20 mA
35 1.0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Temperature Stability Figure 10. Minimum Operating Current

1.26 5.0
4.5
IB, QUIESCENT CURRENT (mA)
Vref, REFERENCE VOLTAGE (V)
TJ = –55°C
4.0
1.25 +25°C
3.5
+150°C
3.0
1.24 2.5
2.0
1.5
1.23
1.0
0.5
1.22 0
–50 –25 0 25 50 75 100 125 150 0 10 20 30 40

LM317
Figure 12. Ripple Rejection versus

Figure 11. Ripple Rejection versus Output Voltage Output Current
100
CAdj = 10 µF
120
RR, RIPPLE REJECTION (dB)
80

100
Without CAdj
60 CAdj = 10 µF
80
Without CAdj
40 60
Vin – Vout = 5 V 40
IL = 500 mA Vin = 15 V
20 f = 120 Hz Vout = 10 V
20 f = 120 Hz
TJ = 25°C
TJ = 25°C
0 0
0 5.0 10 15 20 25 30 35 0.01 0.1 1.0 10
Vout, OUTPUT VOLTAGE (V) IO, OUTPUT CURRENT (A)
Figure 13. Ripple Rejection versus Frequency Figure 14. Output Impedance
100 101
Z O, OUTPUT IMPEDANCE ( Ω )
80 IL = 500 mA Vin = 15 V
Vin = 15 V 100
Vout = 10 V
Vout = 10 V IL = 500 mA
60 TJ = 25°C TJ = 25°C
10–1
40 Without CAdj
10–2
20
CAdj = 10 µF CAdj = 10 µF
Without CAdj
0 10–3
10 100 1.0 k 10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k 1.0 M
VOLTAGE DEVIATION (V)
Figure 15. Line Transient Response Figure 16. Load Transient Response
∆Vout , OUTPUT
3.0
∆Vout , OUTPUT
1.5 2.0
1.0 1.0 CL = 1.0 µF;
CL = 1.0 µF; CAdj = 10 µF
0.5 CAdj = 10 µF 0
0 –1.0
Vin = 15 V
–0.5 –2.0 Vout = 10 V
Vout = 10 V CL = 0;
–1.0 –3.0 INL = 50 mA
VOTLAGE CHANGE (V)
IL = 50 mA Without CAdj
CL = 0; TJ = 25°C
–1.5 TJ = 25°C
∆V in , INPUT
1.5
CURRENT (A)
Without CAdj
IL , LOAD
1.0 1.0
Vin IL
0.5 0.5
0 0
0 10 20 30 40 0 10 20 30 40
t, TIME (µs) t, TIME (µs)

LM317
Basic Circuit Operation External Capacitors
The LM317 is a 3–terminal floating regulator. In operation, A 0.1 µF disc or 1.0 µF tantalum input bypass capacitor
the LM317 develops and maintains a nominal 1.25 V (Cin) is recommended to reduce the sensitivity to input line
reference (Vref) between its output and adjustment terminals. impedance.
This reference voltage is converted to a programming current The adjustment terminal may be bypassed to ground to
(IPROG) by R1 (see Figure 17), and this constant current flows improve ripple rejection. This capacitor (CAdj) prevents ripple
ǒ Ǔ
through R2 to ground. from being amplified as the output voltage is increased. A
The regulated output voltage is given by: 10 µF capacitor should improve ripple rejection about 15 dB
at 120 Hz in a 10 V application.
V out + Vref 1 ) RR2 ) IAdj R2 Although the LM317 is stable with no output capacitance,
1 like any feedback circuit, certain values of external
Since the current from the adjustment terminal (IAdj) capacitance can cause excessive ringing. An output
represents an error term in the equation, the LM317 was capacitance (CO) in the form of a 1.0 µF tantalum or 25 µF
designed to control IAdj to less than 100 µA and keep it aluminum electrolytic capacitor on the output swamps this
constant. To do this, all quiescent operating current is effect and insures stability.
returned to the output terminal. This imposes the requirement Protection Diodes
for a minimum load current. If the load current is less than this When external capacitors are used with any IC regulator it
minimum, the output voltage will rise. is sometimes necessary to add protection diodes to prevent
Since the LM317 is a floating regulator, it is only the the capacitors from discharging through low current points
voltage differential across the circuit which is important to into the regulator.
performance, and operation at high voltages with respect to Figure 18 shows the LM317 with the recommended
ground is possible. protection diodes for output voltages in excess of 25 V or high
Figure 17. Basic Circuit Configuration capacitance values (CO > 25 µF, CAdj > 10 µF). Diode D1
prevents CO from discharging thru the IC during an input
Vin Vout
Vout
short circuit. Diode D2 protects against capacitor CAdj
LM317
+ discharging through the IC during an output short circuit. The
R1 combination of diodes D1 and D2 prevents CAdj from
Vref discharging through the IC during an input short circuit.
Adjust IPROG
Figure 18. Voltage Regulator with Protection Diodes
D1
IAdj
R2
Vout 1N4002
Vref = 1.25 V Typical Vin Vout
Load Regulation LM317
+
The LM317 is capable of providing extremely good load Cin R1 CO
regulation, but a few precautions are needed to obtain D2
maximum performance. For best performance, the Adjust 1N4002
programming resistor (R1) should be connected as close to
the regulator as possible to minimize line drops which R2 CAdj
effectively appear in series with the reference, thereby
degrading regulation. The ground end of R2 can be returned
near the load ground to provide remote ground sensing and
improve load regulation.
Figure 19. D2PAK Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length
80 3.5
PD, MAXIMUM POWER DISSIPATION (W)
PD(max) for TA = +50°C

R θ JA, THERMAL RESISTANCE
70 Free Air 3.0

JUNCTION-TO-AIR (°C/W)
Mounted
Vertically 2.0 oz. Copper
ÎÎÎÎ
60 2.5
L
50 Minimum
ÎÎÎÎ 2.0
ÎÎÎÎ
Size Pad L
40 1.5
RθJA
30 1.0
0 5.0 10 15 20 25 30
L, LENGTH OF COPPER (mm)

LM317
Figure 20. ‘‘Laboratory’’ Power Supply with Adjustable Current Limit and Output Voltage
D6*
1N4002
Vout1 RSC Vin2 Iout
Vout 2
Vin LM317 LM317 Vout
32 V to 40 V Vin1 (1) (2)
+
0.1 µF 240 D5
1.0 µF
D1 IN4001 Tantalum
Adjust 1
1N4001 Adjust 2 +
Current 1.0K D2 5.0 k Voltage 10 µF
Limit 1N4001 Adjust
Adjust 1N4001
Q1
2N3822 D3
* Diodes D1 and D2 and transistor Q2 are added to Output Range: 0 ≤ VO ≤ 25 V
* allow adjustment of output voltage to 0 V. D4 Output Range: 0 ≤ IO ≤ 1.5 A
* D6 protects both LM317’s during an input short circuit. –10 V

Q2 IN4001
2N5640
–10 V
Figure 21. Adjustable Current Limiter Figure 22. 5.0 V Electronic Shutdown Regulator
+25 V Vout R1 D1*

LM317 Iout
Vin 1.25 1N4002
Vin Vout
Adjust D1 LM317
R2 1N4001 +
120 1.0 µF
100 D2
1N4001 Adjust
* To provide current limiting of IO to the system MPS2222
* ground, the source of the FET must be tied to a 720 TTL
* negative voltage below – 1.25 V. 1.0 k Control
2N5640
Vref Vref
R1 = R2 ≤
IOmax + IDSS IDDS Minimum Vout = 1.25 V
VSS*
VO < BVDSS + 1.25 V + VSS,
ILmin – IDSS < IO < 1.5 A. * D1 protects the device during an input short circuit.
As shown 0 < IO < 1.0 A.
Figure 23. Slow Turn–On Regulator Figure 24. Current Regulator
Iout
Vin Vout Vin Vout R1
LM317 LM317
240 1N4001
ǒǓ
IAdj
Adjust 50 k Adjust
R2 MPS2907 +
10 µF
I out + ref
R1
V
I )
Adj
+
1.25 V
R1
10 mA ≤ Iout ≤ 1.5 A

LM317L
Output Positive Voltage LOW CURRENT
Regulator THREE–TERMINAL
The LM317L is an adjustable 3–terminal positive voltage regulator ADJUSTABLE POSITIVE
capable of supplying in excess of 100 mA over an output voltage range of VOLTAGE REGULATOR
1.2 V to 37 V. This voltage regulator is exceptionally easy to use and
requires only two external resistors to set the output voltage. Further, it SEMICONDUCTOR
employs internal current limiting, thermal shutdown and safe area TECHNICAL DATA
compensation, making them essentially blow–out proof.
The LM317L serves a wide variety of applications including local, on card
regulation. This device can also be used to make a programmable output
regulator, or by connecting a fixed resistor between the adjustment and Z SUFFIX
output, the LM317L can be used as a precision current regulator. PLASTIC PACKAGE
• Output Current in Excess of 100 mA CASE 29
• Output Adjustable Between 1.2 V and 37 V

Pin 1. Adjust
• Internal Thermal Overload Protection 2. Vout 1
2
• 3. Vin 3
Internal Short Circuit Current Limiting
• Floating Operation for High Voltage Applications D SUFFIX Pin 1. Vin
• Standard 3–Lead Transistor Package PLASTIC PACKAGE 2. Vout
• Eliminates Stocking Many Fixed Voltages
CASE 751
(SOP–8*)
3.
4.
Vout
Adjust
5. N.C.
6. Vout
7. Vout
8
8. N.C.
1
* SOP–8 is an internally modified SO–8 pack-

age. Pins 2, 3, 6 and 7 are electrically common
to the die attach flag. This internal lead frame
Simplified Application modification decreases package thermal resis-
tance and increases power dissipation capabili-
ty when appropriately mounted on a printed cir-
Vin Vout cuit board. SOP–8 conforms to all external di-
LM317L mensions of the standard SO–8 package.
R1
240
IAdj
Cin* Adjust + C **
O
0.1µF 1.0µF
R2
* Cin is required if regulator is located an appreciable ORDERING INFORMATION

** distance from power supply filter.
** CO is not needed for stability, however, Operating
ǒ Ǔ
** it does improve transient response. Device Temperature Range Package
LM317LD SOP–8
Vout + 1.25 V 1 ) RR21 ) IAdj R2 LM317LZ
TJ = 0° to +125°C
Plastic
LM317LBD SOP–8
Since IAdj is controlled to less than 100 µA, the error TJ = –40° to +125°C
associated with this term is negligible in most applications. LM317LBZ Plastic

LM317L
MAXIMUM RATINGS
Power Dissipation PD Internally Limited W
Operating Junction Temperature Range TJ –40 to +125 °C
ELECTRICAL CHARACTERISTICS (VI–VO = 5.0 V; IO = 40 mA; TJ = Tlow to Thigh [Note 1]; Imax and Pmax [Note 2];
unless otherwise noted.)
LM317L, LB
Line Regulation (Note 3) 1 Regline – 0.01 0.04 %/V
TA = 25°C, 3.0 V ≤ VI – VO ≤ 40 V
Load Regulation (Note 3), TA = 25°C 2 Regload

10 mA ≤ IO ≤ Imax – LM317L
VO ≤ 5.0 V – 5.0 25 mV
VO ≥ 5.0 V – 0.1 0.5 % VO
Adjustment Pin Current Change 1, 2 ∆IAdj – 0.2 5.0 µA
2.5 V ≤ VI – VO ≤ 40 V, PD ≤ Pmax
Reference Voltage 3 Vref 1.20 1.25 1.30 V
3.0 V ≤ VI – VO ≤ 40 V, PD ≤ Pmax
3.0 V ≤ VI – VO ≤ 40 V
Load Regulation (Note 3) 2 Regload

VO ≤ 5.0 V – 20 70 mV
VO ≥ 5.0 V – 0.3 1.5 % VO
Minimum Load Current to Maintain Regulation (VI – VO = 40 V) 3 ILmin – 3.5 10 mA
Maximum Output Current 3 Imax mA
VI – VO ≤ 6.25 V, PD ≤ Pmax, Z Package 100 200 –
VI – VO ≤ 40 V, PD ≤ Pmax, TA = 25°C, Z Package – 20 –
RMS Noise, % of VO N – 0.003 – % VO
TA = 25°C, 10 Hz ≤ f ≤ 10 kHz
Ripple Rejection (Note 4) 4 RR dB

VO = 1.2 V, f = 120 Hz 60 80 –
CAdj = 10 µF, VO = 10.0 V – 80 –
Long Term Stability, TJ = Thigh (Note 5) 3 S – 0.3 1.0 %/1.0 k
TA = 25°C for Endpoint Measurements Hrs.
Thermal Resistance, Junction–to–Case RθJC – 83 – °C/W

Z Package
Thermal Resistance, Junction–to–Air RθJA – 160 – °C/W

Z Package
NOTES: 1. Tlow to Thigh = 0° to +125°C for LM317L –40° to +125°C for LM317LB
2. Imax = 100 mA Pmax = 625 mW
from lot to lot.

LM317L
Vin
300 300 300 3.0k 30 70 6.8V

0
6.8V
350
18k
8.67k 500
130
40
5.1k 0
200
k
180 180 2.0k 6.0k 10 60 2.5

6.3V pF 10
pF
Vout
2.4k
12.8k 5
0 Adjust
VCC
VOH – VOL
Line Regulation (%/V) = x 100
* VOL
VIH VOH
VIL Vin Vout VOL
LM317L
Adjust R1 240 RL
1%
+
Cin 0.1µF IAdj CO 1µF
* Pulse Testing Required: R2

1% Duty Cycle is suggested. 1
%

LM317L
Load Regulation (mV) = VO (min Load) –VO (max Load)

Load Regulation (% VO) = X
VO (min Load) VO (min Load)
100
VO (max Load)
Vin* Vin Vout
LM317L IL
RL
(max Load)
Adjust 240 RL
R1 1% *
(min Load)
+
Cin 0.1µF IAdj CO 1.0µF
R2
1%
* Pulse Testing Required:

1% Duty Cycle is suggested.
Vin Vout
LM317L IL
Adjust
240
R1 1% Vref RL
IAdj +
VI Cin 0.1µF CO 1µF VO
ISET
R2
1%
To Calculate R2:
Pulse Testing Required: Vout = ISET R2 + 1.250 V
1% Duty Cycle is suggested. Assume ISET = 5.25 mA

14.30V
Vin Vout Vout = 1.25 V

4.30V
LM317L
f = 120 Hz
D1 *
Adjust R1 240 RL
1% 1N4002
+
Cin 0.1µF CO 1µF VO
+
1.65K 10µF
R2 1% **
* D1 Discharges CAdj if Output is Shorted to Ground. **CAdj provides an AC ground to the adjust pin.

LM317L
∆ V out, OUTPUT VOLTAGE CHANGE (%) Figure 5. Load Regulation Figure 6. Ripple Rejection
0.4 Vin = 45 V

Vout = 5.0 V
0.2 IL = 5.0 mA to 40 mA 80
0
–0.2 70
Vin = 10 V IL = 40 mA
–0.4 Vout = 5.0 V f = 120 Hz
–0.6 IL = 5.0 mA to 100 mA 60 Vout = 10 V
Vin = 14 V to 24 V
–0.8
–1.0 50
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
Figure 7. Current Limit Figure 8. Dropout Voltage

0.50 2.5
V in –Vout , INPUT–OUTPUT VOLTAGE
TJ = 25°C
IO, OUTPUT CURRENT (A)
0.40
2.0
IL = 100 mA
DIFFERENTIAL (V)
0.30
1.5
0.20 TJ = 150°C
IL = 5.0 mA
1.0
0.10
0 0.5
0 10 20 30 40 50 –50 –25 0 25 50 75 100 125 150
Vin–Vout, INPUT–OUTPUT VOLTAGE DIFFERENTIAL (V) TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Minimum Operating Current Figure 10. Ripple Rejection versus Frequency
5.0 100
4.5 90
IB , QUIESCENT CURRENT (mA)
4.0 TJ = 55°C IL = 40 mA
80
TJ = 25°C Vin = 5.0 V ± 1.0 VPP
3.5 TJ = 150°C 70 Vout = 1.25 V
3.0 60
2.5 50
2.0 40
1.5 30
1.0 20
0.5 10
0 10 20 30 40 10 100 1.0 k 10 k 100 k 1.0 M

Vin–Vout, INPUT–OUTPUT VOLTAGE DIFFERENTIAL (V) f, FREQUENCY (Hz)

LM317L
Figure 11. Temperature Stability Figure 12. Adjustment Pin Current

1.260 80
IAdj, ADJUSTMENT PIN CURRENT ( µA)

70 Vin = 6.25 V
V ref , REFERENCE VOLTAGE (V)
Vout = Vref
1.250 65 IL = 10 mA
IL = 100 mA
60
1.240 55
50
Vin = 4.2 V
1.230 Vout = Vref 45
IL = 5.0 mA
40
1.220 35
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
Figure 13. Line Regulation Figure 14. Output Noise

∆ Vout , OUTPUT VOLTAGE CHANGE (%)
0.4 Vin = 4.25 V to 41.25 V

Vout = Vref Bandwidth 100 Hz to 10 kHz
0.2 IL = 5 mA
NOISE VOLTAGE ( µV) 10
0
–0.2 8.0
–0.4
–0.6 6.0
–0.8
–1.0 4.0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
∆ Vout , OUTPUT VOLTAGE
DEVIATION (V)
DEVIATION (V)
1.5 0.3
1.0 0.2 CL = 1 µF; CAdj = 10 µF
0.5 CL = 1 µF 0.1
0 0 Vin = 15 V
Vout = 10 V
–0.5 –0.1 INL = 50 mA
Vout = 1.25 V CL = 0.3 µF; CAdj = 10 µF
–1.0 –0.2 TJ = 25°C
∆ Vin , INPUT VOLTAGE
IL = 20 mA
–1.5 TJ = 25°C CL = 0 –0.3
CURRENT (mA)
CHANGE (V)
I L , LOAD
1.0 100
Vin IL
0.5 50
0 0
0 10 20 30 40 0 10 20 30 40

LM317L
The LM317L is a 3–terminal floating regulator. In A 0.1 µF disc or 1.0 µF tantalum input bypass capacitor
operation, the LM317L develops and maintains a nominal (Cin) is recommended to reduce the sensitivity to input line
1.25 V reference (Vref) between its output and adjustment impedance.
terminals. This reference voltage is converted to a The adjustment terminal may be bypassed to ground to
programming current (IPROG) by R1 (see Figure 13), and this improve ripple rejection. This capacitor (CAdj) prevents ripple
constant current flows through R2 to ground. The regulated from being amplified as the output voltage is increased. A
output voltage is given by: 10 µF capacitor should improve ripple rejection about 15 dB
R2 at 120 Hz in a 10 V application.
Vout = Vref (1 + ) + IAdj R2 Although the LM317L is stable with no output capacitance,
R1
like any feedback circuit, certain values of external
Since the current from the adjustment terminal (IAdj) capacitance can cause excessive ringing. An output
represents an error term in the equation, the LM317L was capacitance (CO) in the form of a 1.0 µF tantalum or 25 µF
designed to control IAdj to less than 100 µA and keep it aluminum electrolytic capacitor on the output swamps this
constant. To do this, all quiescent operating current is effect and insures stability.
returned to the output terminal. This imposes the requirement
for a minimum load current. If the load current is less than this Protection Diodes
minimum, the output voltage will rise. When external capacitors are used with any IC regulator it
Since the LM317L is a floating regulator, it is only the is sometimes necessary to add protection diodes to prevent
voltage differential across the circuit which is important to the capacitors from discharging through low current points
performance, and operation at high voltages with respect to into the regulator.
ground is possible. Figure 14 shows the LM317L with the recommended
protection diodes for output voltages in excess of 25 V or high
capacitance values (CO > 10 µF, CAdj > 5.0 µF). Diode D1
Figure 17. Basic Circuit Configuration
Vin Vout
LM317L
discharging through the IC during an output short circuit. The
+ combination of diodes D1 and D2 prevents CAdj from
R1 discharging through the IC during an input short circuit.
Vref
Adjust IPROG
Vout Figure 18. Voltage Regulator with
Protection Diodes
IAdj
R2 D1
Vref = 1.25 V Typical 1N4002

Vin Vout
LM317L
Load Regulation +
The LM317L is capable of providing extremely good load Cin R1 D2 CO
regulation, but a few precautions are needed to obtain Adjust
maximum performance. For best performance, the 1N4002
programming resistor (R1) should be connected as close to R2 CAdj
the regulator as possible to minimize line drops which

LM317L
Figure 19. Adjustable Current Limiter Figure 20. 5 V Electronic Shutdown Regulator
+25V Vout R1 VO IO D1
LM317L
Vin 1.25k 1N4002
Vin Vout
LM317L
Adjust D1
R2 1N914 +
120 1.0µF
* To provide current limiting of IO 500 D2
to the system ground, the source of 1N914 Adjust
the current limiting diode must be tied to MPS2222
a negative voltage below – 7.25 V. 720 TTL
1.0k Control
1N5314
Vref
R2 ≥
IDSS Minimum Vout = 1.25 V
Vref VSS*
R1 =
IOmax + IDSS
D1 protects the device during an input short circuit.
VO < POV + 1.25 V + VSS
ILmin – IP < IO < 100 mA – IP
As shown O < IO < 95 mA
Vin Vout Iout

LM317L Vin R1 R2
LM317L
240 1N4002 Vout
Adjust 50k Adjust IAdj
R2 MPS2907 +
10µF
Ioutmax =
Vref
R1
+ IAdj ^ 1.25R1 V
Ioutmax =
Vref
R1 + R2
+ IAdj ^ R1.25 V
1 + R2
5.0 mA < Iout < 100 mA

LM317M
Regulator MEDIUM CURRENT
THREE–TERMINAL
The LM317M is an adjustable three–terminal positive voltage regulator ADJUSTABLE POSITIVE
capable of supplying in excess of 500 mA over an output voltage range of
1.2 V to 37 V. This voltage regulator is exceptionally easy to use and requires VOLTAGE REGULATOR
only two external resistors to set the output voltage. Further, it employs SEMICONDUCTOR
internal current limiting, thermal shutdown and safe area compensation, TECHNICAL DATA
making it essentially blow–out proof.
The LM317M serves a wide variety of applications including local,
on–card regulation. This device also makes an especially simple adjustable T SUFFIX
switching regulator, a programmable output regulator, or by connecting a PLASTIC PACKAGE
fixed resistor between the adjustment and output, the LM317M can be used CASE 221A
as a precision current regulator.
• Output Current in Excess of 500 mA Heatsink surface
• Output Adjustable between 1.2 V and 37 V connected to Pin 2
• Internal Thermal Overload Protection 1

• Internal Short Circuit Current Limiting
2
3

•
(All 3 Packages)
Floating Operation for High Voltage Applications Pin 1. Adjust
• Eliminates Stocking Many Fixed Voltages 2. Vout
3. Vin
DT–1 SUFFIX
PLASTIC PACKAGE
CASE 369
1
2 (DPAK)
3
Simplified Application
DT SUFFIX
Vin Vout PLASTIC PACKAGE
Vin LM317M Vout 1 CASE 369A
3 (DPAK)
R1
240
IAdj Adjust Heatsink Surface (shown as terminal 4 in
* **
Cin +C case outline drawing) is connected to Pin 2.
O
0.1µF 1.0µF
R2
Operating
LM317MT TJ = 0° to +125°C Plastic Power

* = Cin is required if regulator is located an appreciable distance from power supply filter. LM317MBT# TJ = –40° to +125°C Plastic Power
ǒ ) Ǔ)
** = CO is not needed for stability, however, it does improve transient response.
LM317MDT
TJ = 0° to 125°C DPAK
Vout + 1.25 V 1
R2
R1
IAdj R2
LM317MDT–1
# Automotive temperature range selections are
# available with special test conditions and additional
Since IAdj is controlled to less than 100 µA, the error associated with this # tests. Contact your local Motorola sales office for
term is negligible in most applications. # information.

LM317M
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Power Dissipation (Package Limitation) (Note 1)
Plastic Package, T Suffix
TA = 25°C PD Internally Limited
Thermal Resistance, Junction–to–Air θJA 70 °C/W
Plastic Package, DT Suffix
NOTE: 1. Figure 23 provides thermal resistance versus pc board pad size.
ELECTRICAL CHARACTERISTICS (VI–VO = 5.0 V; IO = 0.1 A, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
TA = 25°C, 3.0 V ≤ VI–VO ≤ 40 V

TA = 25°C, 10 mA ≤ IO ≤ 0.5 A
VO ≤ 5.0 V – 5.0 25 mV
VO ≥ 5.0 V – 0.1 0.5 % VO
Adjustment Pin Current Change 1,2 ∆IAdj – 0.2 5.0 µA
2.5 V ≤ VI–VO ≤ 40 V, 10 mA ≤ IL ≤ 0.5 A, PD ≤ Pmax

3.0 V ≤ VI–VO ≤ 40 V, 10 mA ≤ IO ≤ 0.5 A, PD ≤ Pmax

3.0 V ≤ VI–VO ≤ 40 V

10 mA ≤ IO ≤ 0.5 A
VO ≤ 5.0 V – 20 70 mV
VO ≥ 5.0 V – 0.3 1.5 % VO
Minimum Load Current to Maintain Regulation 3 ILmin – 3.5 10 mA
(VI–VO = 40 V)

VI–VO ≤ 15 V, PD ≤ Pmax 0.5 0.9 –
VI–VO = 40 V, PD ≤ Pmax, TA = 25°C 0.15 0.25 –
RMS Noise, % of VO – N – 0.003 – % VO
TA= 25°C, 10 Hz ≤ f ≤ 10 kHz

CAdj = 10 µF 66 80 –
Long–Term Stability, TJ = Thigh (Note 4) 3 S – 0.3 1.0 %/1.0 k
TA= 25°C for Endpoint Measurements Hrs.
NOTES: 1. Tlow to Thigh = 0° to +125°C; Pmax = 7.5 W for LM317M Tlow to Thigh = – 40° to +125°C; Pmax = 7.5 W for LM317MB
from lot to lot.

LM317M
Vin
300 300 300 3.0k 300 70 6.8V
6.8V
350
18k
8.67k 500
130
400
5.1k
200k
180 180 2.0k 6.0k 10 60 1.25

6.3V pF 10
pF
Vout
2.4k
12.8k 50
Adjust
VCC
VOH – VOL
* VOL
VIH VOH
VIL Vin Vout VOL
LM317M
Adjust R1 240 RL
1%
+

1% Duty Cycle is suggested. 1%

LM317M
Load Regulation (mV) = VO (min Load) –VO (max Load)

Load Regulation (% VO) = X 100
VO (min Load) VO (min Load)
VO (max Load)
Vin Vin Vout
LM317M IL
RL
(max Load)
Adjust 240 RL
R1 1% *
(min Load)
+
R2
1%

Vin Vout
LM317M IL
Adjust
240
VI R1 1% Vref RL
IAdj +
Cin 0.1µF CO 1µF VO
ISET
R2
1%
To Calculate R2:
*Pulse Testing Required: Vout = ISET R2 + 1.250 V

24V
Vin Vout Vout = 10 V
14V LM317M
f = 120 Hz
D1 *
Adjust R1 240 RL
1% 1N4002
+
Cin 0.1µF CO 1.0µF VO
** +
1.65K CAdj 10µF
R2 1%
* D1 Discharges CAdj if Output is Shorted to Ground.

**CAdj provides an AC ground to the adjust pin.

LM317M
Figure 5. Load Regulation Figure 6. Ripple Rejection

90
∆ V out , OUTPUT VOLTAGE CHANGE (%)
0.4 Vin = 45 V

Vout = 5.0 V
0.2 80
IL = 5.0 mA to 40 mA Without CAdj = 10 µF
0
–0.2 70
Vin = 10 V
–0.4 Vout = 5.0 V
–0.6 IL = 5.0 mA to 100 mA 60 IL = 100 mA Without CAdj
f = 120 Hz
–0.8 Vout = 10 V
Vin = 14 V to 24 V
–1.0 50
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
Figure 7. Current Limit Figure 8. Dropout Voltage

1.0 V in –Vout , INPUT–OUTPUT VOLTAGE 2.5
0.80 IL = 500 mA
Iout , OUTPUT CURRENT (A)
2.0
DIFFERENTIAL (V)
0.60 IL = 100 mA
1.5
TJ = 25°C
0.40
1.0
0.20 TJ = 125°C
0 0.5
0 10 20 30 40 50 –50 –25 0 25 50 75 100 125 150
Vin–Vout, INPUT–OUTPUT VOLTAGE DIFFERENTIAL (V) TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Minimum Operating Current Figure 10. Ripple Rejection versus Frequency
5.0 100
4.5 90
4.0 IL = 40 mA
80
Vin = 5.0 V ± 1.0 VPP
3.5 70 Vout = 1.25 V
3.0 TJ = 25°C 60
2.5 50
2.0 TJ = 125°C 40
1.5 30
1.0 20
0.5 10
0 10 20 30 40 10 100 1.0 k 10 k 100 k 1.0 M

Vin–Vout, INPUT–OUTPUT VOLTAGE DIFFERENTIAL (Vdc) f, FREQUENCY (Hz)

LM317M
Figure 11. Temperature Stability Figure 12. Adjustment Pin Current

1.260 80

70 Vin = 6.25 V
Vout = Vref
1.250 65 IL = 10 mA
IL = 100 mA
60
1.240 55
50
1.230 Vin = 4.2 V 45

Vout = Vref
IL = 5.0 mA 40
1.220 35
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
Figure 13. Line Regulation Figure 14. Output Noise

∆ Vout , OUTPUT VOLTAGE CHANGE (%)
0.4 Vin = 4.25 V to 41.25 V

Vout = Vref Bandwidth 100 Hz to 10 kHz
0.2 10
NOISE VOLTAGE ( µV)
IL = 5.0 mA
0
–0.2 8.0
–0.4
–0.6 6.0
–0.8
–1.0 4.0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
3
DEVIATION (V)
1.5 2
DEVIATION (V)
1.0 1 CL = 1.0 µF; CAdj = 10 µF

0.5 CL = 1.0 µF 0
0 –1 Vin = 15 V
Vout = 10 V
–0.5 –2 INL = 50 mA
Vout = 10 V CL = 0.3 µF; CAdj = 10 µF
–1.0 –3 TJ = 25°C
IL = 50 mA
–1.5 1.5
CURRENT (A)
TJ = 25°C CL = 0
CHANGE (V)
I L , LOAD
1.0 1.0
Vin IL
0.5 0.5
0 0
0 10 20 30 40 0 10 20 30 40

LM317M
The LM317M is a three–terminal floating regulator. In A 0.1 µF disc or 1.0 µF tantalum input bypass capacitor
operation, the LM317M develops and maintains a nominal (Cin) is recommended to reduce the sensitivity to input line
1.25 V reference (Vref) between its output and adjustment impedance.
terminals. This reference voltage is converted to a The adjustment terminal may be bypassed to ground to
programming current (IPROG) by R1 (see Figure 17), and this improve ripple rejection. This capacitor (CAdj) prevents ripple
constant current flows through R2 to ground. The regulated from being amplified as the output voltage is increased. A
output voltage is given by: 10 µF capacitor should improve ripple rejection about 15 dB
Vout ǒ Ǔ
+ Vref 1 ) RR21 ) IAdj R2
Although the LM317M is stable with no output
capacitance, like any feedback circuit, certain values of
external capacitance can cause excessive ringing. An output
Since the current from the terminal (IAdj) represents an capacitance (CO) in the form of a 1.0 µF tantalum or 25 µF
error term in the equation, the LM317M was designed to aluminum electrolytic capacitor on the output swamps this
control IAdj to less than 100 µA and keep it constant. To do effect and insures stability.
this, all quiescent operating current is returned to the output
terminal. This imposes the requirement for a minimum load Protection Diodes
current. If the load current is less than this minimum, the When external capacitors are used with any IC regulator it
output voltage will rise. is sometimes necessary to add protection diodes to prevent
Since the LM317M is a floating regulator, it is only the the capacitors from discharging through low current points
voltage differential across the circuit which is important to into the regulator.
performance, and operation at high voltages with respect to Figure 18 shows the LM317M with the recommended
ground is possible. protection diodes for output voltages in excess of 25 V or high
capacitance values (CO > 25 µF, CAdj > 5.0 µF). Diode D1
Figure 17. Basic Circuit Configuration prevents CO from discharging thru the IC during an input
Vin Vout discharging through the IC during an output short circuit. The
LM317M combination of diodes D1 and D2 prevents CAdj from
+
discharging through the IC during an input short circuit.
R1
Vref
Adjust IPROG Figure 18. Voltage Regulator with
Vout Protection Diodes
IAdj D1
R2
1N4002
Vref = –1.25 V Typical Vin Vout
LM317M Vout
Load Regulation +
The LM317M is capable of providing extremely good load Cin R1 D2 CO
regulation, but a few precautions are needed to obtain Adjust
maximum performance. For best performance, the 1N4002
programming resistor (R1) should be connected as close to R2 CAdj

LM317M
Figure 19. Adjustable Current Limiter Figure 20. 5 V Electronic Shutdown Regulator
+25V Vout R1 VO IO D1
LM317M
Vin 1.25k 1N4002
Vin Vout
Vin LM317M Vout
Adjust D1
R2 1N914 +
120 1.0µF
the current limiting diode must be tied to MPS2222
a negative voltage below – 7.25 V. 720 TTL
1.0k Control
1N5314
Vref
R2 ≥
IDSS Minimum Vout = 1.25 V
Vref VSS*
R1 =
IOmax + IDSS
VO < POV + 1.25 V + VSS
ILmin – IP < IO < 500 mA – IP
As shown O < IO < 495 mA
Vout Iout
Vin LM317M Vout R1 R2
Vin LM317M
240 1N4001 Vout
Adjust 50k Adjust IAdj
R2 MPS2907 +
10µF
Ioutmax =
Vref
R1
+ IAdj ^ 1.25 V
R1
Ioutmax =
Vref
R1 + R2
+ IAdj ^ R1.25 V
1 + R2
5.0 mA < Iout < 100 mA
Figure 23. DPAK Thermal Resistance and Maximum

100 2.4
PD(max) for TA = 50°C

Free Air
90 Mounted 2.0
JUNCTION–TO–AIR (°C/W)
ÎÎÎ
Vertically
2.0 oz. Copper
80 1.6
ÎÎÎ
L
Minimum
ÎÎÎ
70 Size Pad L 1.2
60
50
ÎÎÎ 0.8
0.4
RθJA
40 0
0 5.0 10 15 20 25 30

LM323, A
Positive Voltage Regulators

The LM323,A are monolithic integrated circuits which supply a fixed
positive 5.0 V output with a load driving capability in excess of 3.0 A. These
three–terminal regulators employ internal current limiting, thermal shutdown,
3–AMPERE, 5 VOLT
and safe–area compensation. The A–suffix is an improved device with POSITIVE
superior electrical characteristics and a 2% output voltage tolerance. These
regulators are offered with a 0° to +125°C temperature range in a low cost
VOLTAGE REGULATORS
plastic power package. SEMICONDUCTOR
Although designed primarily as a fixed voltage regulator, these devices TECHNICAL DATA
can be used with external components to obtain adjustable voltages and
currents. These devices can be used with a series pass transistor to supply
up to 15 A at 5.0 V.
• Available with 2% Output Voltage Tolerance
T SUFFIX
PLASTIC PACKAGE
• No External Components Required CASE 221A
• Output Transistor Safe–Area Compensation Pin 1. Input
2. Ground
• Thermal Regulation and Ripple Rejection Have Specified Limits 3. Output 1
2
3
Heatsink surface is connected to Pin 2.
Input LM323, A Output
Cin*
CO**
0.33µF
A common ground is required between the input and the output voltages. The input
voltage must remain typically 2.5 V above the output voltage even during the low point
on the input ripple voltage.
Output Operating
* Cin is required if regulator is located an appreciable
Voltage Temperature
* distance from power supply filter. (See Applications
Device Tolerance Range Package
* Information for details.)
** CO is not needed for stability; however, it does LM323T 4% Plastic
** improve transient response. TJ = 0° to +125°C
LM323AT 2% Power

LM323, A
MAXIMUM RATINGS
Input Voltage Vin 20 Vdc
Operating Junction Temperature Range TJ 0 to +125 °C
Lead Temperature (Soldering, 10 s) Tsolder 300 °C
ELECTRICAL CHARACTERISTICS (TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
LM323A LM323
Output Voltage VO 4.9 5.0 5.1 4.8 5.0 5.2 V
(Vin = 7.5 V, 0 ≤ Iout ≤ 3.0 A, TJ = 25°C)
Output Voltage VO 4.8 5.0 5.2 4.75 5.0 5.25 V

(7.5 V ≤ Vin ≤ 15 V, 0 ≤ Iout ≤ 3.0 A,
P ≤ Pmax) (Note 2)
Line Regulation Regline – 1.0 15 – 1.0 25 mV
(7.5 V ≤ Vin ≤ 15 V, TJ = 25°C) (Note 3)
Load Regulation Regload – 10 50 – 10 100 mV

(Vin = 7.5 V, 0 ≤ Iout ≤ 3.0 A, TJ = 25°C)
(Note 3)
Thermal Regulation Regtherm – 0.001 0.01 – 0.002 0.03 %VO/W
(Pulse = 10 ms, P = 20 W, TA = 25°C)
Quiescent Current IB – 3.5 10 – 3.5 20 mA

(7.5 V ≤ Vin ≤ 15 V, 0 ≤ Iout ≤ 3.0 A)
Output Noise Voltage VN – 40 – – 40 – µVrms

(10 Hz ≤ f ≤ 100 kHz, TJ = 25°C)
Ripple Rejection RR 66 75 – 62 75 – dB
(8.0 V ≤ Vin ≤ 18 V, Iout = 2.0A,
f = 120 Hz, TJ = 25°C)
Short Circuit Current Limit ISC A
(Vin = 15 V, TJ = 25°C) – 4.5 – – 4.5 –
(Vin = 7.5 V, TJ = 25°C) – 5.5 – – 5.5 –
Long Term Stability S – – 35 – – 35 mV
Thermal Resistance, Junction–to–Case (Note 4) RΘJC – 2.0 – – 2.0 – °C/W
NOTES: 1. Tlow to Thigh = 0° to +125°C
2. Although power dissipation is internally limited, specifications apply only for P ≤ Pmax = 25 W.
3. Load and line regulation are specified at constant junction temperature. Pulse testing is required with a pulse width ≤ 1.0 ms and a duty cycle ≤ 5%.
4. Without a heatsink, the thermal resistance (RθJA is 65°C/W). With a heatsink, the effective thermal resistance can approach the specified values of
2.0°C/W, depending on the efficiency of the heatsink.

LM323, A
2 Input
1.0k 1.0k
210
Q2 Q21
Q1 Q20 Q22
6.7V
16k 100
Q25
Q8
Q9 1.0k Q24 200
Q27
300
Q26
3.0k 10pF
Q3 10k Q19
Q4 300
5.6k Q23
Q5 Q16 13 0.12
Q10
520 50 200
Q12 Output
2.6k 40pF 7.2k 840
6.0k
2.0k 3.9k Q17 Q18

Q6 Q7
Q13 Q15 1.7k
Q11
6.0k Q14 2.8k
Gnd
VOLTAGE REGULATOR PERFORMANCE

The performance of a voltage regulator is specified by its be caused by a change in either input voltage or the load
immunity to changes in load, input voltage, power dissipation, current. Thermal regulation is a function of IC layout and die
and temperature. Line and load regulation are tested with a attach techniques, and usually occurs within 10 ms of a
pulse of short duration (< 100 µs) and are strictly a function of change in power dissipation. After 10 ms, additional changes
electrical gain. However, pulse widths of longer duration in the output voltage are due to the temperature coefficient of
(> 1.0 ms) are sufficient to affect temperature gradients the device.
across the die. These temperature gradients can cause a Figure 1 shows the line and thermal regulation response of
change in the output voltage, in addition to changes by line a typical LM323A to a 20 W input pulse. The variation of the
and load regulation. Longer pulse widths and thermal output voltage due to line regulation is labeled À and the
gradients make it desirable to specify thermal regulation. thermal regulation component is labeled Á. Figure 2 shows
Thermal regulation is defined as the change in output the load and thermal regulation response of a typical LM323A
voltage caused by a change in dissipated power for a to a 20 W load pulse. The output voltage variation due to load
specified time, and is expressed as a percentage output regulation is labeled À and the thermal regulation component
voltage change per watt. The change in dissipated power can is labeled Á.
Figure 1. Line and Thermal Regulation Figure 2. Load and Thermal Regulation
2 2
∆ Vout , OUTPUT
∆ Vout , OUTPUT
(2.0 mV/DIV)
(2.0 mV/DIV)
2 1
1 2
18 V
Iout , OUTPUT
CURRENT (A)
2.0
VOLTAGE (V)
Vin , INPUT
8.0 V 0
t, TIME (2.0 ms/DIV) t, TIME (2.0 ms/DIV)

Vout = 5.0 V Vout = 5.0 V
1 = Regline = 2.4 mV 1 = Regline = 5.4 mV
Vin = 8.0 V → 18 V → 8.0 V Vin = 15 V
Iout = 2.0 A 2 = Regtherm = 0.0015% VO/W Iout = 0 A → 2.0 A → 0 A 2 = Regtherm = 0.0015% VO/W

LM323, A
Figure 3. Temperature Stability Figure 4. Output Impedance

5.1 10
Vout , OUTPUT VOLTAGE (Vdc)
Vin = 10 V 10–1
Iout = 100 mA
Vin = 7.5 V
Iout = 1.0 A
10–2 CO = 0
5.0
TJ = 25°C
10–3
4.9 10–4
–90 –50 –10 30 70 110 150 190 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
TJ, JUNCTION TEMPERATURE (°C) f, FREQUENCY (Hz)
Figure 5. Ripple Rejection versus Frequency Figure 6. Ripple Rejection versus Output Current
100 100
Iout = 50 mA
80
80
Iout = 3.0 A
60
60 Vin = 10 V
Vin = 10 V CO = 0
CO = 0 f = 120 Hz
40 TJ = 25°C TJ = 25°C
40
20 30
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M 0.01 0.1 1.0 10
f, FREQUENCY (Hz) Iout, OUTPUT CURRENT (A)
Figure 7. Quiescent Current versus Figure 8. Quiescent Current versus

Input Voltage Output Current
4.0 5.0
TJ = 55°C
TJ = –55°C
TJ = 25°C 4.0
3.0
TJ = 150°C TJ = 25°C
3.0
2.0 TJ = 150°C
TJ = 150°C
Iout = 2.0 A 2.0
1.0 TJ = 55°C
1.0 Vin = 10 V
TJ = 25°C
0 0
0 5.0 10 15 20 0.01 0.1 1.0 10
Vin, INPUT VOLTAGE (Vdc) Iout, OUTPUT CURRENT (A)

LM323, A
Figure 9. Dropout Voltage Figure 10. Short Circuit Current

2.5 8.0
ISC , SHORT CIRCUIT CURRENT AT

VOLTAGE DIFFERENTIAL (Vdc)
V in –Vout , INPUT TO OUTPUT
Iout = 3.0 A
2.0 6.0
ZERO VOLTS (A)

1.5 Iout = 1.0 A 4.0 TJ = 0°C
TJ = 25°C
Iout = 0.5 A TJ = 125°C
1.0 2.0
∆Vout = 50 mV
0.5 0
–90 –50 –10 30 70 110 150 190 5.0 10 15 20 25
TJ, JUNCTION TEMPERATURE (°C) Vin, INPUT VOLTAGE (Vdc)

0.8 0.3
Iout = 150 mA Vin = 10 V
DEVIATION (V)
0.6 0.2
DEVIATION (V)
CO = 0 CO = 0
0.4 TJ = 25°C 0.1 TJ = 25°C
0.2 0
0 –0.1
–0.2 –0.2
–0.4 –0.3
–0.6 1.5
Iout , OUTPUT
CURRENT (A)
CHANGE (V)
1.0 1.0
0.5 0.5
0 0
0 10 20 30 40 0 10 20 30 40
Design Considerations regulator is connected to the power supply filter with long wire
The LM323,A series of fixed voltage regulators are lengths, or if the output load capacitance is large. An input
designed with Thermal Overload Protection that shuts down bypass capacitor should be selected to provide good
the circuit when subjected to an excessive power overload high–frequency characteristics to insure stable operation
condition, Internal Short Circuit Protection that limits the under all load conditions. A 0.33 µF or larger tantalum, mylar,
maximum current the circuit will pass, and Output Transistor or other capacitor having low internal impedance at high
Safe–Area Compensation that reduces the output short frequencies should be chosen. The bypass capacitor should
circuit current as the voltage across the pass transistor is be mounted with the shortest possible leads directly across
increased. the regulator’s input terminals. Normally good construction
In many low current applications, compensation techniques should be used to minimize ground loops and
capacitors are not required. However, it is recommended that lead resistance drops since the regulator has no external
the regulator input be bypassed with a capacitor if the sense lead.

LM323, A
Figure 13. Current Regulator Figure 14. Adjustable Output Regulator
Input LM323, A Output

LM323, A
0.33µF R Input
Constant
Current to
IO Grounded Load 7 2
–
0.33µF 6 0.1µF
MC1741
The LM323,A regulator can also be used as a current source when 3
+ 10k
connected as above. Resistor R determines the current as follows: 1.0k 4
IO = 5.0 V + IB
R
∆IB ^ 0.7 mA over line, load and temperature changes VO, 8.0 V to 20 V Vin – VO ≥ 2.5 V
IB ^ 3.5 mA
For example, a 2.0 A current source would require R to be a 2.5 Ω,
The addition of an operational amplifier allows adjustment to higher or
15 W resistor and the output voltage compliance would be the input
intermediate values while retaining regulation characteristics. The
voltage less 7.5 V.
minimum voltage obtainable with this arrangement is 3.0 V greater
than the regulator voltage.
Figure 16. Current Boost with

Figure 15. Current Boost Regulator Short Circuit Protection
2N4398
2N4398 or Equiv or Equiv.
Input Rsc
R
LM323, A Output MJ2955
or Equiv.
R
LM323, A
1.0µF 0.1µF Output
1.0µF
The LM323, A series can be current boosted with a PNP transistor. The The circuit of Figure 16 can be modified to provide supply protection
2N4398 provides current to 15 A. Resistor R in conjuction with the VBE of against short circuits by adding a short circuit sense resistor, RSC, and
the PNP determines when the pass transistor begins conducting; this an additional PNP transistor. The current sensing PNP must be able to
circuit is not short circuit proof. Input–output differential voltage handle the short circuit current of the three–terminal regulator.
minimum is increased by the VBE of the pass transistor. Therefore, an 8.0 A power transistor is specified.

LM337
Output Negative Voltage
Regulator
THREE–TERMINAL
The LM337 is an adjustable 3–terminal negative voltage regulator
capable of supplying in excess of 1.5 A over an output voltage range of ADJUSTABLE NEGATIVE
–1.2 V to – 37 V. This voltage regulator is exceptionally easy to use and VOLTAGE REGULATOR
requires only two external resistors to set the output voltage. Further, it
employs internal current limiting, thermal shutdown and safe area
compensation, making it essentially blow–out proof.
The LM337 serves a wide variety of applications including local, on card SEMICONDUCTOR
regulation. This device can also be used to make a programmable output TECHNICAL DATA
regulator, or by connecting a fixed resistor between the adjustment and
output, the LM337 can be used as a precision current regulator.
• Output Adjustable between –1.2 V and – 37 V
• Internal Short Circuit Current Limiting Constant with Temperature
• Output Transistor Safe–Area Compensation T SUFFIX
PLASTIC PACKAGE
• Floating Operation for High Voltage Applications CASE 221A
• Eliminates Stocking many Fixed Voltages
• Available in Surface Mount D2PAK and Standard 3–Lead Transistor
Heatsink surface
connected to Pin 2.
Package 1
2
3
Pin 1. Adjust
2. Vin
Standard Application 3. Vout
IPROG
D2T SUFFIX
+ R2 +
Cin* CO** PLASTIC PACKAGE
1.0 µF R1 1.0 µF CASE 936
2
120 (D2PAK) 1
3
IAdj

Vin Vout case outline drawing) is connected to Pin 2.
–Vin LM337 –Vout
* Cin is required if regulator is located more than 4 inches from power supply filter. Operating
* A 1.0 µF solid tantalum or 10 µF aluminum electrolytic is recommended. Device Temperature Range Package
ǒ Ǔ
** CO is necessary for stability. A 1.0 µF solid tantalum or 10 µF aluminum electrolytic LM337BD2T Surface Mount
** is recommeded. TJ = – 40° to +125°C
LM337BT Insertion Mount
V out + –1.25 V 1 ) R R2 LM337D2T

TJ = 0° to +125°C
Surface Mount
1 LM337T Insertion Mount

LM337
MAXIMUM RATINGS
Power Dissipation
Case 221A
Case 936 (D2PAK)
ELECTRICAL CHARACTERISTICS (|VI–VO| = 5.0 V; IO = 0.5 A for T package; TJ = Tlow to Thigh [Note 1]; Imax and Pmax [Note 2].)
Line Regulation (Note 3), TA = +25°C, 3.0 V ≤ |VI–VO| ≤ 40 V 1 Regline – 0.01 0.04 %/V
Load Regulation (Note 3), TA = +25°C, 10 mA ≤ IO ≤ Imax 2 Regload
|VO| ≤ 5.0 V – 15 50 mV
|VO| ≥ 5.0 V – 0.3 1.0 % VO
Thermal Regulation, TA = +25°C (Note 6), 10 ms Pulse Regtherm – 0.003 0.04 % VO/W
Adjustment Pin Current Change, 2.5 V ≤ |VI–VO| ≤ 40 V, 1, 2 ∆IAdj – 2.0 5.0 µA
10 mA ≤ IL ≤ Imax, PD ≤ Pmax, TA = +25°C
Reference Voltage, TA = +25°C, 3.0 V ≤ |VI–VO| ≤ 40 V, 3 Vref –1.213 –1.250 –1.287 V
10 mA ≤ IO ≤ Imax, PD ≤ Pmax, TJ = Tlow to Thigh –1.20 –1.25 –1.30
Line Regulation (Note 3), 3.0 V ≤ |VI–VO| ≤ 40 V 1 Regline – 0.02 0.07 %/V
Load Regulation (Note 3), 10 mA ≤ IO ≤ Imax 2 Regload
|VO| ≤ 5.0 V – 20 70 mV
|VO| ≥ 5.0 V – 0.3 1.5 % VO
Minimum Load Current to Maintain Regulation 3 ILmin mA
(|VI–VO| ≤ 10 V) – 1.5 6.0
(|VI–VO| ≤ 40 V) – 2.5 10
|VI–VO| ≤ 15 V, PD ≤ Pmax, T Package – 1.5 2.2
|VI–VO| ≤ 40 V, PD ≤ Pmax, TJ = +25°C, T Package – 0.15 0.4
RMS Noise, % of VO, TA = +25°C, 10 Hz ≤ f ≤ 10 kHz N – 0.003 – % VO
Ripple Rejection, VO = –10 V, f = 120 Hz (Note 4) 4 RR dB
CAdj = 10 µF 66 77 –
Long–Term Stability, TJ = Thigh (Note 5), TA = +25°C for 3 S – 0.3 1.0 %/1.0 k
Endpoint Measurements Hrs.
Thermal Resistance Junction–to–Case, T Package RθJC – 4.0 – °C/W
NOTES: 1. Tlow to Thigh = 0° to +125°C, for LM337T, D2T. Tlow to Thigh = – 40° to +125°C, for LM337BT, BD2T.
2. Imax = 1.5 A, Pmax = 20 W
3. Load and line regulation are specified at constant junction temperature. Change in VO because of heating effects is covered under the Thermal
Regulation specification. Pulse testing with a low duty cycle is used.
5. Since Long Term Stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from
lot to lot.
6. Power dissipation within an IC voltage regulator produces a temperature gradient on the die, affecting individual IC components on the die. These
effects can be minimized by proper integrated circuit design and layout techniques. Thermal Regulation is the effect of these temperature gradients
on the output voltage and is expressed in percentage of output change per watt of power change in a specified time.

LM337
Adjust
100 60
2.0k
2.5k
810
21k
Vout
10k 800
15pF 25pF
5.0k 220
75 60k 100k 800 15pF 2.0k

0
18k
4.0k
6.0k
100
1.0k
3.0k 2.2k 18k

9.6k 30k
270 2.0
100pF 5.0pF 240 pF 250
20k
8.0k 5.0k
0.2
600 100k
15
2.9k
4.0k 155
500 2.4k 15 500 0.05
Vin
R2 1%
+
Cin 1.0 µF IAdj CO 1.0 µF
120
R1 1%
* Pulse testing required. Adjust RL
1% Duty Cycle
is suggested. Vin Vout
LM337
VIH VOH
VIL VOL
*
ń +
|V –V |
OL OH
VEE Line Regulation (% V) x 100
|V |
OH

LM337
* Pulse testing required.

R2 1% 1% Duty Cycle is suggested.
CO +
Cin 1.0 µF 1.0 µF
IAdj R1 120
Adjust * RL
(max
Vin Vout Load) –VO (min Load)
–VI LM337 IL –VO (max Load)

Load Regulation (mV) = VO (min Load) – VO (max Load) Load Regulation (% VO) = x 100
VO (min Load)
R2 1%
+
Cin 1.0 µF CO 1.0 µF
VI VO
RL
IAdj Vref
R1 120
Adjust
Vin Vout
LM337 IL
VO
To Calculate R2: R2 = – 1 R1
Vref * Pulse testing required.
This assumes IAdj is negligible. * 1% Duty Cycle is suggested.
+
R2 1% CAdj 10µF
+
RL
Adjust D1* 1N4002
R1 120
Vin Vout
LM337
Vout = –1.25 V
14.3 V
4.3 V * D1 Discharges CAdj if output is shorted to Ground.

f = 120 Hz

LM337

0.2 4.0
∆V out , OUTPUT VOLTAGE CHANGE (%)
0
IL = 0.5 A

–0.2 3.0
–0.4
–0.6 2.0
–0.8 TJ = 25°C
Vin = –15 V IL = 1.5 A
–1.0 Vout = –10 V 1.0
–1.2
–1.4 0
–50 –25 0 25 50 75 100 125 150 0 10 20 30 40
TJ, JUNCTION TEMPERATURE (°C) Vin–Vout , INPUT–OUTPUT VOLTAGE DIFFERENTIAL (Vdc)

80 3.0
V in – Vout , INPUT–OUTPUT VOLTAGE

IAdj, ADJUSTMENT CURRENT (µA)
75 Vout = –5.0 V
∆VO = 100 mV
70 DIFFERENTIAL (Vdc) 2.5
IL = 1.5 A
65
60 2.0
1.0 A
55
50 1.5 500 mA
45 200 mA
20 mA
40 1.0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150

1.27
1.8
I B , QUIESCENT CURRENT (mA)
V ref , REFERENCE VOLTAGE (V)
1.6
1.26
1.4
1.2
1.25 1.0 TJ = 25°C
0.8
0.6
1.24
0.4
0.2
1.23 0
–50 –25 0 25 50 75 100 125 150 0 10 20 30 40
TJ, JUNCTION TEMPERATURE (°C) Vin–Vout , INPUT–OUTPUT VOLTAGE DIFFERENTIAL (Vdc)

LM337
Figure 11. Ripple Rejection versus Output Voltage Figure 12. Ripple Rejection versus Output Current
100 100
CAdj = 10 µF
CAdj = 10 µF

80 80
Without CAdj
60 60
Without CAdj
40 40
Vin – Vout = 5.0 V Vin = –15 V
IL = 500 mA Vout = –10 V
20 20 f = 120 Hz
f = 120 Hz
TJ = 25°C TJ = 25°C
0 0
0 –5.0 –10 –15 –20 –25 –30 –35 –40 0.01 0.1 1.0 10
Vout, OUTPUT VOLTAGE (V) IO, OUTPUT CURRENT (A)
100 101
Vin = –15 V Vin = –15 V
80 Vout = –10 V Z O , OUTPUT IMPEDANCE ( Ω ) Vout = –10 V

IL = 500 mA 100 IL = 500 mA
CAdj =10 µF TJ = 25°C CL = 1.0 µF
60 TJ = 25°C
10–1
Without CAdj
40 Without CAdj
10–2 CAdj = 10 µF
20
0 10–3
10 100 1.0 k 10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k 1.0 M
Figure 15. Line Transient Response Figure 16. Load Transient Reponse
VOLTAGE CHANGE (V) VOLTAGE DEVIATION (V)
0.6
∆V out , OUTPUT
∆V out , OUTPUT
0.8 0.4
0.6 0.2 Without CAdj
0.4 0
0.2 Without CAdj –0.2 CAdj = 10 µF
0 –0.4
–0.2 CAdj = 10 µF –0.6
–0.4 0 Vin = –15 V
CURRENT (A)
∆V in, INPUT
Vout = –10 V Vout = –10 V

I L , LOAD
0 IL = 50 mA –0.5 IL = 50 mA
TJ = 25°C TJ = 25°C
–0.5 –1.0 CL = 1.0 µF
CL = 1.0 µF
–1.0 –1.5
0 10 20 30 40 0 10 20 30 40

LM337
Basic Circuit Operation
The LM337 is a 3–terminal floating regulator. In operation, degrading regulation. The ground end of R2 can be returned
the LM337 develops and maintains a nominal –1.25 V near the load ground to provide remote ground sensing and
reference (Vref) between its output and adjustment terminals. improve load regulation.
This reference voltage is converted to a programming current
External Capacitors
(IPROG) by R1 (see Figure 17), and this constant current flows
A 1.0 µF tantalum input bypass capacitor (Cin) is
ǒ Ǔ
through R2 from ground.
The regulated output voltage is given by: recommended to reduce the sensitivity to input line
impedance.
V out + Vref 1 ) RR2 ) IAdj R2 The adjustment terminal may be bypassed to ground to
improve ripple rejection. This capacitor (CAdj) prevents ripple
1
from being amplified as the output voltage is increased. A
Since the current into the adjustment terminal (IAdj) 10 µF capacitor should improve ripple rejection about 15 dB
represents an error term in the equation, the LM337 was at 120 Hz in a 10 V application.
designed to control IAdj to less than 100 µA and keep it An output capacitance (CO) in the form of a 1.0 µF
constant. To do this, all quiescent operating current is tantalum or 10 µF aluminum electrolytic capacitor is required
returned to the output terminal. This imposes the requirement for stability.
for a minimum load current. If the load current is less than this
minimum, the output voltage will rise. Protection Diodes
Since the LM337 is a floating regulator, it is only the When external capacitors are used with any IC regulator it
voltage differential across the circuit which is important to is sometimes necessary to add protection diodes to prevent
performance, and operation at high voltages with respect to the capacitors from discharging through low current points
ground is possible. into the regulator.
Figure 17. Basic Circuit Configuration Figure 18 shows the LM337 with the recommended
protection diodes for output voltages in excess of –25 V or
+ Vout
high capacitance values (CO > 25 µF, CAdj > 10 µF). Diode D1
R2 prevents CO from discharging thru the IC during an input
IAdj IPROG short circuit. Diode D2 protects against capacitor CAdj
CO combination of diodes D1 and D2 prevents CAdj from the
Adjust Vref R1 discharging through the IC during an input short circuit.
Figure 18. Voltage Regulator with Protection Diodes
Vin LM337 – Vout + Vout
Vout +
R2 CAdj
+ +
Vref = –1.25 V Typical Cin CO
Adjust R1 D2
Load Regulation
The LM337 is capable of providing extremely good load 1N4002
–Vin LM337 – Vout
regulation, but a few precautions are needed to obtain Vin Vout
maximum performance. For best performance, the
programming resistor (R1) should be connected as close to D1
the regulator as possible to minimize line drops which 1N4002

80 3.5

70 Free Air 3.0

Mounted
ÎÎÎÎ
60 2.5
ÎÎÎÎ
L
ÎÎÎÎ
50 Minimum 2.0
Size Pad L
40
RθJA
ÎÎÎÎ 1.5
30 1.0
0 5.0 10 15 20 25 30

LM337M
Output Negative Voltage
Regulator MEDIUM CURRENT
THREE–TERMINAL
The LM337M is an adjustable three–terminal negative voltage regulator ADJUSTABLE NEGATIVE
capable of supplying in excess of 500 mA over an output voltage range of
–1.2 V to –37 V. This voltage regulator is exceptionally easy to use and VOLTAGE REGULATOR
requires only two external resistors to set the output voltage. Further, it SEMICONDUCTOR
employs internal current limiting, thermal shutdown and safe area TECHNICAL DATA
compensation, making it essentially blow–out proof.
The LM337M serves a wide variety of applications including local,
on–card regulation. This device can also be used to make a programmable
output regulator or by connecting a fixed resistor between the adjustment
and output. The LM337M can be used as a precision current regulator.
T SUFFIX
• Output Current in Excess of 500 mA PLASTIC PACKAGE
• Output Adjustable Between –1.2 V and –37 V CASE 221A
Pin 1. Adjust
2. Vin 1
• Floating Operation for High Voltage Applications 3. Vout 2
3
• Standard 3–Lead Transistor Packages
IPROG
+ R2 +
Cin * 1.0µF CO ** 1.0µF
R1
120
IAdj
Adjust
Vin Vout
–Vin LM337M –Vout
*Cin is required if regulator is located more than 4″ from power supply filter.
**A 1.0 µF solid tantalum or 10 µF aluminum electrolytic is recommended. ORDERING INFORMATION
**CO is necessary for stability. A 1.0 µF solid tantalum or 10 µF aluminum
ǒ Ǔ
**electrolytic is recommeded. Operating
Vout + –1.25 V 1 ) R2
R1 LM337MT TJ = 0° to +125°C Plastic Power

LM337M
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (|VI – VO| = 5.0 V, IO = 0.1; TJ = Tlow to Thigh [Note 1], Pmax per Note 2, unless otherwise noted.)
TA = 25°C, 3.0 V ≤ |VI–VO| ≤ 40 V

TA = 25°C, 10 mA ≤ IO ≤ 0.5 A
|VO| ≤ 5.0V – 15 15 mV
|VO| ≥ 5.0V – 0.3 1.0 %/VO
Thermal Regulation – Regtherm – 0.03 0.04 % VO/W
10 ms Pulse, TA = 25°C

Adjustment Pin Current Change 1, 2 ∆IAdj – 2.0 5.0 µA
2.5 V ≤ |VI–VO| ≤ 40 V, 10 mA ≤ IL ≤ 0.5 A,
PD ≤ Pmax, TA = 25°C
Reference Voltage 3 Vref V
3.0 V ≤ |VI–VO| ≤ 40 V, 10 mA ≤ IO ≤ 0.5 A,
PD ≤ Pmax, TA = 25°C –1.213 –1.250 –1.287
Tlow to Thigh –1.20 –1.25 –1.30
3.0 V ≤ |VI–VO| ≤ 40 V

10 mA ≤ IO ≤ 0.5 A mV
|VO| ≤ 5.0 V – 20 70 %/VO
|VO| ≥ 5.0 V – 0.3 1.5
Temperature Stability (Tlow ≤ TJ ≤ Thigh) 3 TS – 0.6 – %/VO
Minimum Load Current to Maintain Regulation 3 ILmin mA
(|VI–VO| ≤ 10 V) – 1.5 6.0
(|VI–VO| ≤ 40 V) – 2.5 10
|VI–VO| ≤ 15 V, PD ≤ Pmax 0.5 0.9 –
|VI–VO| ≤ 40 V, PD ≤ Pmax, TJ = 25°C 0.1 0.25 –
RMS Noise, % of VO – N – 0.003 – %/VO
TA = 25°C, 10 Hz ≤ f ≤ 10 kHz
Ripple Rejection, VO = –10 V, f = 120 Hz (Note 4) 4 RR dB

CAdj = 10 µF 66 77 –
TA = 25°C for Endpoint Measurements Hrs
Thermal Resistance, Junction–to–Case – RΘJC – 7.0 – °C/W

2. Pmax = 7.5 W
3 Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately.
5. Since Long Term Stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability
from lot to lot.

LM337M
Schematic Diagram
Adjust
100 60
2.0k
2.5k
810
21k
Vout
800
10k 220
25pF
15pF
50k
750 60k 100k 15pF 2.0k

800
18k
4.0k
6.0k
100
1.0k
3.0k 2.2k 18k
9.6k
30k
270
2.0
250
100pF 5.0pF 240 pF
20k
5.0k
8.0k
0.2
100k
15
2.9k
4.0k
155
600 500 2.4k 15 500 0.1
Vin
R2 1%
+
120
R1 1%
* Pulse Testing Required: Adjust RL
Vin Vout
LM337M VOH
VIH
VOL
VIL
* |VOL – VOH|
Line Regulation (%/VO) = x 100
|VOH|
VEE

LM337M
* Pulse Testing required:

R2 1% 1% Duty Cycle is suggested.
CO +
Cin 1.0µF 1.0µF
IAdj 120
R1
1%
*
Adjust RL
(max –VO (min Load)
Vin Vout Load)
–Vin LM33M IL VO (max Load)
VO (min Load) – VO(max Load)

Load Regulation (mV) = VO (min Load) – VO (max Load) Load Regulation (%/VO) = x 100
VO (min Load)
R2 1%
+
Cin 1.0µF CO 1.0µF
VI VO
RL
IAdj Vref
R1 120
Adjust
Vin Vout
LM337M IL
To Calculate R2:
VO
R2 = – 1 R1
Vref
Pulse Testing Required: 1% Duty Cycle is suggested.
This assumes IAdj is negligible.
+
R2 1% CAdj 10µF
+
RL
Adjust D1 * 1N4002
R1 120
Vin Vout
LM337M
Vout = –1.25 V
14.3V
4.3V *D1 Discharges CAdj if Output is shorted to Ground.

f = 120 Hz

LM337M

0.2 4
∆ V O , OUTPUT VOLTAGE CHANGE (%)
0
IL = 0.5 A
IO, OUTPUT CURRENT (A)

–0.2 3
–0.4 TJ = 25°C
–0.6 2
–0.8 TJ = 150°C TJ = 55°C

Vin = –15 V
–1.0 Vout = –10 V 1
–1.2
–1.4 0
–50 –25 0 25 50 75 100 125 150 0 10 20 30 40
TJ, JUNCTION TEMPERATURE (°C) VI – VO, INPUT VOLTAGE DIFFERENTIAL (Vdc)

80 3.0
Vout = –5.0 V
IAdj, ADJUSTMENT CURRENT ( µ A)
75 ∆Vout = 100 mV
70 2.5
DIFFERENTIAL (Vdc)
65
60 2.0
55
IL = 500 mA
50 1.5 IL = 200 mA
45
IL = 20 mA
40 1.0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150

1.270
1.8
TJ = –55°C
1.6
1.260 TJ = 25°C
1.4
1.2 TJ = 150°C
1.250 1.0
0.8
0.6
1.240
0.4
0.2
1.230 0
–50 –25 0 25 50 75 100 125 150 0 10 20 30 40

LM337M
100 100
CAdj = 10 µF
CAdj = 10 µF

80 80
Without CAdj
60 Without CAdj 60
40 40
Vin – Vout = 5.0 V Vin = –15 V
IL = 500 mA Vout = –10 V
20 f = 120 Hz 20 f = 120 Hz
TJ = 25°C TJ = 25°C
0 0
0 –5 –10 –15 –20 –25 –30 –35 –40 0.01 0.1 1.0 10
VO, OUTPUT VOLTAGE (V) IO, OUTPUT CURRENT (A)
100 101
Vin = –15 V
Z O , OUTPUT IMPEDANCE ( Ω ) Vout = –10 V

80 IL = 500 mA
100
CAdj = 10 µF CL = 1.0 µF
TJ = 25°C
60
10–1 Without CAdj
40 Without CAdj
Vin = –15 V 10–2 CAdj = 10µF

20 Vout = –10 V
IL = 500 mA
TJ = 25°C
0 10–3
10 100 1.0 k 10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k 1M
Figure 15. Line Transient Response Figure 16. Load Transient Reponse
0.6
DEVIATION (V)
0.8 0.4
Without CAdj
DEVIATION (V)
0.6 0.2
0.4 0
0.2 Without CAdj –0.2 CAdj = 10 µF
0 –0.4
–0.2 CAdj = 10 µF –0.6
Vin = –15 V
–0.4 Vout = –10 V 0
CURRENT (A)
Vout = –10 V
CHANGE (V)
I L , LOAD
0 IL = 50 mA –0.5 INL = 50 mA
TJ = 25°C TJ = 25°C
–0.5 CL = 1.0 µF –1.0 CL = 1.0 µF
–1.0 –1.5
0 10 20 30 40 0 10 20 30 40

LM337M
Basic Circuit Operation degrading regulation. The ground end of R2 can be returned
The LM337M is a three–terminal floating regulator. In near the load ground to provide remote ground sensing and
operation, the LM337M develops and maintains a nominal improve load regulation.
–1.25 V reference (Vref) between its output and adjustment
terminals. This reference voltage is converted to a External Capacitors
programming current (IPROG) by R1 (see Figure 17), and this A 1.0 µF tantalum input bypass capacitor (Cin) is
constant current flows through R2 to ground. The regulated recommended to reduce the sensitivity to input line
output voltage is given by: impedance.
The adjustment terminal may be bypassed to ground to
R2
Vout = Vref (1 + ) + IAdj R2 from being amplified as the output voltage is increased. A
R1 10 µF capacitor should improve ripple rejection about 15 dB
Since the current into the adjustment terminal (IAdj) at 120 Hz in a 10 V application.
represents an error term in the equation, the LM337M was An output capacitance (CO) in the form of a 1.0 µF
designed to control IAdj to less than 100 µA and keep it tantalum or 10 µF aluminum electrolytic capacitor is required
constant. To do this, all quiescent operating current is for stability.
returned to the output terminal. This imposes the requirement
for a minimum load current. If the load current is less than this Protection Diodes
minimum, the output voltage will rise. When external capacitors are used with any IC regulator it
Since the LM337M is a floating regulator, it is only the is sometimes necessary to add protection diodes to prevent
voltage differential across the circuit which is important to the capacitors from discharging through low current points
performance, and operation at high voltages with respect to into the regulator.
ground is possible. Figure 18 shows the LM337M with the recommended
protection diodes for output voltages in excess of –25 V or
high capacitance values (CO > 25 µF, CAdj > 10 µF). Diode D1
Figure 17. Basic Circuit Configuration prevents CO from discharging thru the IC during an input
combination of diodes D1 and D2 prevents CAdj from
R2 discharging through the IC during an input short circuit.
IAdj IPRONG
+
CO Vout
Adjust Vref R1
Figure 18. Voltage Regulator with
Protection Diodes
Vin LM337M –
Vout +
+
R2 CAdj
Vref = –1.25 V Typically
+ +
Cin CO Vout
Load Regulation Adjust R1 D2
The LM337M is capable of providing extremely good load
regulation, but a few precautions are needed to obtain –Vin LM337M –
maximum performance. For best performance, the Vin Vout 1N4002
the regulator as possible to minimize line drops which D1
effectively appear in series with the reference, thereby 1N4002

LM340, A
Series
Three-Terminal Positive
Fixed Voltage Regulators
This family of fixed voltage regulators are monolithic integrated circuits THREE–TERMINAL
capable of driving loads in excess of 1.0 A. These three–terminal regulators POSITIVE FIXED
employ internal current limiting, thermal shutdown, and safe–area
compensation. Devices are available with improved specifications, including VOLTAGE REGULATORS
a 2% output voltage tolerance, on A–suffix 5.0, 12 and 15 V device types. SEMICONDUCTOR
Although designed primarily as a fixed voltage regulator, these devices
TECHNICAL DATA
can be used with external components to obtain adjustable voltages and
currents. This series of devices can be used with a series–pass transistor to
boost output current capability at the nominal output voltage.
• No External Components Required T SUFFIX
PLASTIC PACKAGE
• Output Voltage Offered in 2% and 4% Tolerance* CASE 221A
Pin 1. Input 1
2. Ground 2
3
3. Output
Heatsink surface is connected to Pin 2.
Input LM340–XX Output

Cin*
CO**
Output Voltage Operating 0.33µF
Device and Tolerance Temperature Range Package
LM340T–5.0 5.0 V ± 4%
LM340AT–5.0 5.0 V ± 2%
A common ground is required between the input and
LM340T–6.0 6.0 V ± 4% the output voltages. The input voltage must remain
typically 1.7 V above the output voltage even during
LM340T–8.0 8.0 V ± 4% the low point on the input ripple voltage.
LM340T–12 12 V ± 4%
TJ = 0° to +125°C Plastic Power XX these two digits of the type number indicate
LM340AT–12 12 V ± 2%
voltage.
LM340T–15 15 V ± 4% * Cin is required if regulator is located an
appreciable distance from power supply filter.
LM340AT–15 15 V ± 2% ** CO is not needed for stability; however, it does
improve transient response. If needed, use a
LM340T–18 18 V ± 4%
0.1 µF ceramic disc.
LM340T–24 24 V ± 4%
* 2% regulators are available in 5, 12 and 15 V devices.

LM340, A Series
MAXIMUM RATINGS (TA = +25°C unless otherwise noted.)
Input Voltage (5.0 V – 18 V) Vin 35 Vdc
Input Voltage (24 V) 40

Plastic Package
Derate above TA = +25°C 1/θJA 15.4 mW/°C
TC= +25°C PD Internally Limited W

Derate above TC = +75°C (See Figure 1) 1/θJA 200 mW/°C
1.0k 1.0k Input

210
6.7V
16k
100
1.0k 200
300
3.0k
3.6k
10pF
5.6k 300
6.4k 13 0.12
50 200
520 Output
40
pF
2.6k
6.0k
2.0k 3.9k
6.0k 2.8k Gnd

LM340, A Series
LM340–5.0
ELECTRICAL CHARACTERISTICS (Vin = 10 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
Output Voltage (TJ = +25°C) VO 4.8 5.0 5.2 Vdc
IO = 5.0 mA to 1.0 A
Line Regulation (Note 2) Regline mV

8.0 Vdc to 20 Vdc – – 50
7.0 Vdc to 25 Vdc (TJ = +25°C) – – 50
8.0 Vdc to 12 Vdc, IO = 1.0 A – – 25
7.3 Vdc to 20 Vdc, IO = 1.0 A (TJ = +25°C) – – 50
Load Regulation (Note 2) Regload mV
5.0 mA ≤ IO ≤ 1.0 A – – 50
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – – 50
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 25
Output Voltage VO 4.75 – 5.25 Vdc
7.0 ≤ Vin ≤ 20 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W
Quiescent Current IB mA
IO = 1.0 A – – 8.5
TJ = +25°C – 4.0 8.0
Quiescent Current Change ∆IB mA
7.0 ≤ Vin ≤ 25 Vdc, IO = 500 mA – – 1.0
5.0 mA ≤ IO ≤ 1.0 A, Vin = 10 V – – 0.5
7.5 ≤ Vin ≤ 20 Vdc, IO = 1.0 A – – 1.0
Ripple Rejection RR 62 80 – dB
IO = 1.0 A (TJ = +25°C)
Dropout Voltage VI – VO – 1.7 – Vdc

Output Resistance (f = 1.0 kHz) rO – 2.0 – mΩ
Short Circuit Current Limit (TJ = +25°C) ISC – 2.0 – A
Output Noise Voltage (TA = +25°C) Vn – 40 – µV
10 Hz ≤ f ≤ 100 kHz
Average Temperature Coefficient of Output Voltage TCVO – ±0.6 – mV/°C

IO = 5.0 mA
Peak Output Current (TJ = +25°C) IO – 2.4 – A

Input Voltage to Maintain Line Regulation (TJ = +25°C) 7.3 – – Vdc
IO = 1.0 A
DEFINITIONS
Line Regulation – The change in output voltage for a Maximum Power Dissipation – The maximum total device
change in the input voltage. The measurement is made dissipation for which the regulator will operate within
under conditions of low dissipation or by using pulse specifications.
techniques such that the average chip temperature is not
Quiescent Current – That part of the input current that is not
significantly affected.
delivered to the load.
Load Regulation – The change in output voltage for a
Output Noise Voltage – The rms AC voltage at the output,
change in load current at constant chip temperature.
with constant load and no input ripple, measured over a
specified frequency range.

LM340, A Series
LM340A–5.0
ELECTRICAL CHARACTERISTICS (Vin = 10 V, IO = 1.0 A, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
IO = 5.0 mA to 1.0 A
Line Regulation Regline mV

7.5 Vdc to 20 Vdc, IO = 500 mA – – 10
7.3 Vdc to 25 Vdc (TJ = +25°C) – 3.0 10
8.0 Vdc to 12 Vdc – – 12
8.0 Vdc to 12 Vdc (TJ = +25°C) – – 4.0
Load Regulation Regload mV
5.0 mA ≤ IO ≤ 1.0 A – – 25
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – – 25
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 15
7.5 ≤ Vin ≤ 20 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W
Quiescent Current IB – – 6.5 mA

TJ = +25°C – 3.5 6.0

5.0 mA ≤ IO ≤ 1.0 A, Vin = 10 V – – 0.5
8.0 ≤ Vin ≤ 25 Vdc, IO = 500 mA – – 0.8
7.5 ≤ Vin ≤ 20 Vdc, IO = 1.0 A (TJ = +25°C) – – 0.8
Ripple Rejection RR dB
8.0 ≤ Vin ≤ 18 Vdc, f = 120 Hz
IO = 500 mA 68 – –
IO = 1.0 A (TJ = +25°C) 68 80 –
10 Hz ≤ f ≤ 100 kHz

IO = 5.0 mA

IO = 1.0 A
NOTE: 1. Tlow to Thigh = 0° to +125°C

LM340, A Series
LM340–6.0
IO = 5.0 mA to 1.0 A

9.0 Vdc to 21 Vdc – – 60
8.0 Vdc to 25 Vdc (TJ = +25°C) – – 60
9.0 Vdc to 13 Vdc, IO = 1.0 A – – 30
8.3 Vdc to 21 Vdc, IO = 1.0 A (TJ = +25°C) – – 60
5.0 mA ≤ IO ≤ 1.0 A – – 60
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – – 60
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 30
8.0 ≤ Vin ≤ 21 Vdc, 6.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W
IO = 1.0 A – – 8.5
TJ = +25°C – 4.0 8.0
8.0 ≤ Vin ≤ 25 Vdc, IO = 500 mA – – 1.0
5.0 mA ≤ IO ≤ 1.0 A, Vin = 11 V – – 0.5
8.6 ≤ Vin ≤ 21 Vdc, IO = 1.0 A – – 1.0
IO = 1.0 A (TJ = +25°C)

10 Hz ≤ f ≤ 100 kHz

IO = 5.0 mA

IO = 1.0 A

LM340, A Series
LM340–8.0
IO = 5.0 mA to 1.0 A

11 Vdc to 23 Vdc – – 80
10.5 Vdc to 25 Vdc (TJ = +25°C) – – 80
11 Vdc to 17 Vdc, IO = 1.0 A – – 40
10.5 Vdc to 23 Vdc, IO = 1.0 A (TJ = +25°C) – – 80
5.0 mA ≤ IO ≤ 1.0 A – – 80
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – – 80
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 40
10.5 ≤ Vin ≤ 23 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W
IO = 1.0 A – – 8.5
TJ = +25°C – 4.0 8.0
10.5 ≤ Vin ≤ 25 Vdc, IO = 500 mA – – 1.0
5.0 mA ≤ IO ≤ 1.0 A, Vin = 14 V – – 0.5
10.6 ≤ Vin ≤ 23 Vdc, IO = 1.0 A – – 1.0
IO = 1.0 A (TJ = +25°C)

10 Hz ≤ f ≤ 100 kHz

IO = 5.0 mA

IO = 1.0 A

LM340, A Series
LM340–12
Output Voltage (TJ = +25°C) VO 11.5 12 12.5 Vdc
IO = 5.0 mA to 1.0 A

15 Vdc to 27 Vdc – – 120
14.6 Vdc to 30 Vdc (TJ = +25°C) – – 120
16 Vdc to 22 Vdc, IO = 1.0 A – – 60
14.6 Vdc to 27 Vdc, IO = 1.0 A (TJ = +25°C) – – 120
5.0 mA ≤ IO ≤ 1.0 A – – 120
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – – 120
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 60
14.5 ≤ Vin ≤ 27 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W
IO = 1.0 A – – 8.5
TJ = +25°C – 4.0 8.0
14.5 ≤ Vin ≤ 30 Vdc, IO = 500 mA – – 1.0
5.0 mA ≤ IO ≤ 1.0 A, Vin = 19 V – – 0.5
14.8 ≤ Vin ≤ 27 Vdc, IO = 1.0 A – – 1.0
IO = 1.0 A (TJ = +25°C)

10 Hz ≤ f ≤ 100 kHz

IO = 5.0 mA

IO = 1.0 A

LM340, A Series
LM340A–12
ELECTRICAL CHARACTERISTICS (Vin = 19 V, IO = 1.0 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
IO = 5.0 mA to 1.0 A

14.8 Vdc to 27 Vdc, IO = 500 mA – – 18
14.5 Vdc to 30 Vdc (TJ = +25°C) – 4.0 18
16 Vdc to 22 Vdc – – 30
16 Vdc to 22 Vdc (TJ = +25°C) – – 9.0
5.0 mA ≤ IO ≤ 1.0 A – – 60
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – – 32
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 19
14.8 ≤ Vin ≤ 27 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W

TJ = +25°C – 3.5 6.0

5.0 mA ≤ IO ≤ 1.0 A, Vin = 19 V – – 0.5
15 ≤ Vin ≤ 30 Vdc, IO = 500 mA – – 0.8
14.8 ≤ Vin ≤ 27 Vdc, IO = 1.0 A(TJ = +25°C) – – 0.8
15 ≤ Vin ≤ 25 Vdc, f = 120 Hz
IO = 500 mA 61 – –
IO = 1.0 A (TJ = +25°C) 61 72 –
10 Hz ≤ f ≤ 100 kHz

IO = 5.0 mA


LM340, A Series
LM340–15
IO = 5.0 mA to 1.0 A

18.5 Vdc to 30 Vdc – – 150
17.5 Vdc to 30 Vdc (TJ = +25°C) – – 150
20 Vdc to 26 Vdc, IO = 1.0 A – – 75
17.7 Vdc to 30 Vdc, IO = 1.0 A (TJ = +25°C) – – 150

5.0 mA ≤ IO ≤ 1.0 A – – 150
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – – 150
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 75
17.5 ≤ Vin ≤ 30 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W
IO = 1.0 A – – 8.5
TJ = +25°C – 4.0 8.0
17.5 ≤ Vin ≤ 30 Vdc, IO = 500 mA – – 1.0
5.0 mA ≤ IO ≤ 1.0 A, Vin = 23 V – – 0.5
17.9 ≤ Vin ≤ 30 Vdc, IO = 1.0 A – – 1.0
IO = 1.0 mA (TJ = +25°C)

Short Circuit Current Limit (TJ = +25°C) ISC – 800 – A
10 Hz ≤ f ≤ 100 kHz

IO = 5.0 mA

IO = 1.0 A

LM340, A Series
LM340A–15
ELECTRICAL CHARACTERISTICS (Vin = 23 V, IO = 1.0 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
IO = 5.0 mA to 1.0 A

17.9 Vdc to 30 Vdc, IO = 500 mA – – 22
17.5 Vdc to 30 Vdc (TJ = +25°C) – 4.0 22
20 Vdc to 26 Vdc, IO = 1.0 A – – 30
20 Vdc to 26 Vdc, IO = 1.0 A (TJ = +25°C) – – 10
5.0 mA ≤ IO ≤ 1.0 A – – 75
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – 12 35
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 21
17.9 ≤ Vin ≤ 30 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W

TJ = +25°C – 3.5 6.0

5.0 mA ≤ IO ≤ 1.0 A, Vin = 23 V – – 0.5
17.9 ≤ Vin ≤ 30 Vdc, IO = 500 mA – – 0.8
17.9 ≤ Vin ≤ 30 Vdc, IO = 1.0 A (TJ = +25°C) – – 0.8
18.5 ≤ Vin ≤ 28.5 Vdc, f = 120 Hz
IO = 500 mA 60 – –
IO = 1.0 A (TJ = +25°C) 60 70 –
10 Hz ≤ f ≤ 100 kHz

IO = 5.0 mA


LM340, A Series
LM340–18
IO = 5.0 mA to 1.0 A

21.5 Vdc to 33 Vdc – – 180
21 Vdc to 33 Vdc (TJ = +25°C) – – 180
24 Vdc to 30 Vdc, IO = 1.0 A – – 90
21 Vdc to 33 Vdc, IO = 1.0 A (TJ = +25°C) – – 180
5.0 mA ≤ IO ≤ 1.0 A – – 180
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – – 180
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 90
21 ≤ Vin ≤ 33 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W
IO = 1.0 A – – 8.5
TJ = +25°C – 4.0 8.0
21 ≤ Vin ≤ 33 Vdc, IO = 500 mA – – 1.0
5.0 mA ≤ IO ≤ 1.0 A, Vin = 27 V – – 0.5
21 ≤ Vin ≤ 33 Vdc, IO = 1.0 A – – 1.0
IO = 1.0 mA (TJ = +25°C)

10 Hz ≤ f ≤ 100 kHz

IO = 5.0 mA

Input Voltage to Maintain Line Regulation (TJ = +25°C) 21 – – Vdc
IO = 1.0 A

LM340, A Series
LM340–24
Output Voltage (TJ = +25°C) VO 23 24 25 Vdc
IO = 5.0 mA to 1.0 A

28 Vdc to 38 Vdc – – 240
27 Vdc to 38 Vdc (TJ = +25°C) – – 240
30 Vdc to 36 Vdc, IO = 1.0 A – – 120
27.1 Vdc to 38 Vdc, IO = 1.0 A (TJ = +25°C) – – 240
5.0 mA ≤ IO ≤ 1.0 A – – 240
5.0 mA ≤ IO ≤ 1.5 A (TJ = +25°C) – – 240
250 mA ≤ IO ≤ 750 mA (TJ = +25°C) – – 120
27 ≤ Vin ≤ 38 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, PD ≤ 15 W
IO = 1.0 A – – 8.5
TJ = +25°C – 4.0 8.0
27 ≤ Vin ≤ 38 Vdc, IO = 500 mA – – 1.0
5.0 mA ≤ IO ≤ 1.0 A, Vin = 33 V – – 0.5
27.3 ≤ Vin ≤ 38 Vdc, IO = 1.0 A – – 1.0
IO = 1.0 mA (TJ = +25°C)

10 Hz ≤ f ≤ 100 kHz

IO = 5.0 mA

IO = 1.0 A

LM340, A Series
The performance of a voltage regulator is specified by its be caused by a change in either input voltage or the load
immunity to changes in load, input voltage, power dissipation, current. Thermal regulation is a function of IC layout and die
and temperature. Line and load regulation are tested with a attach techniques, and usually occurs within 10 ms of a
pulse of short duration (< 100 µs) and are strictly a function of change in power dissipation. After 10 ms, additional changes
electrical gain. However, pulse widths of longer duration in the output voltage are due to the temperature coefficient of
(> 1.0 ms) are sufficient to affect temperature gradients the device.
across the die. These temperature gradients can cause a Figure 1 shows the line and thermal regulation response of
change in the output voltage, in addition to changes caused a typical LM340AT–5.0 to a 10 W input pulse. The variation of
by line and load regulation. Longer pulse widths and thermal the output voltage due to line regulation is labeled À and the
gradients make it desirable to specify thermal regulation. thermal regulation component is labeled Á. Figure 2 shows
Thermal regulation is defined as the change in output the load and thermal regulation response of a typical
voltage caused by a change in dissipated power for a LM340AT–5.0 to a 15 W load pulse. The output voltage
specified time, and is expressed as a percentage output variation due to load regulation is labeled À and the thermal
voltage change per watt. The change in dissipated power can regulation component is labeled Á.
Figure 1. Line and Thermal Regulation Figure 2. Load and Thermal Regulation

Vin , INPUT VOLTAGE DEVIATION (V)
∆ Vout , OUTPUT
2
∆ Vout , OUTPUT
(2.0 mV/DIV)
(2.0 mV/DIV)
2
1
1 2
18 V
VOLTAGE (V)
Iout , OUTPUT
CURRENT (A)
2.0
8.0 V 0

LM340AT–5.0 LM340AT–5.0
Vin = 8.0 V → 18 V → 8.0 V Vin = 15 V
Iout = 1.0 A 2 = Regtherm = 0.0030% VO/W Iout = 0 A → 1.5 A → 0 A 2 = Regtherm = 0.0020% VO/W

1.02 100
NORMALIZED OUTPUT VOLTAGE
1.01 Vin – Vout = 5.0 V 10–1

Iout = 100 mA
Vout = 5.0 V
Vin = 7.5 V
1.00 10–2 Iout = 1.0 A
CO = 0
TJ = 25°C
0.99 10–3
0.98 10–4
–90 –50 –10 30 70 110 150 190 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M

LM340, A Series
100 100
Iout = 50 mA

80
80
Iout = 1.5 A
60 Vout = 5.0 V Vout = 5.0 V
Vin = 10 V 60 Vin = 10 V
CO = 0 Vin = 10 V
TJ = 25°C CO = 0
40 f = 120 Hz
TJ = 25°C
40
20 30
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M 0.01 0.1 1.0 10

4.0 5.0
4.0
3.0
3.0 TJ = 25°C
TJ = 25°C
2.0 Vout = 5.0 V Vin – Vout = 5.0 V
Iout = 1.0 A
2.0
1.0
1.0
0 0
0 10 20 30 40 0.01 0.1 1.0 10
Figure 9. Dropout Voltage Figure 10. Peak Output Current

2.5 4.0
∆Vout = 100 mV
Iout , OUTPUT CURRENT (A)
2.0 IO = 1.0 A 3.0

DIFFERENTIAL (V)
1.5 IO = 500 mA
2.0
1.0
IO = 10 mA
1.0 TJ = 25°C
0.5
0 0
–75 –50 –25 0 25 50 75 100 125 0 10 20 30 40
TA, AMBIENT TEMPERATURE (°C) Vin–Vout, INPUT–OUTPUT VOLTAGE DIFFERENTIAL (V)

LM340, A Series

0.8 0.3
DEVIATION (V)
0.6 Vout = 5.0 V 0.2
DEVIATION (V)
Iout = 150 mA
0.4 CO = 0 0.1
0.2 TJ = 25°C 0
0 –0.1
Vout = 5.0 V
–0.2 –0.2 Vin = 10 V
–0.4 –0.3 CO = 0
–0.6 1.5 TJ = 25°C
CURRENT (A)
Iout , OUTPUT
1.0 1.0
CHANGE (V)
0.5 0.5
0 0
0 10 20 30 40 0 10 20 30 40
Figure 13. Worst Case Power Dissipation

versus Ambient Temperature (Case 221A)
20
θJC = 5°C/W
θJA = 65°C/W
PD , POWER DISSIPATION (W)
16 θHS = 0°C/W
TJ(max) = 150°C
θHS = 5°C/W
12
8.0 θHS = 15°C/W
4.0
No Heatsink
0
–50 –25 0 25 50 75 100 125 150

LM340, A Series
The LM340, A series of fixed voltage regulators are lengths, or if the output load capacitance is large. An input
designed with Thermal Overload Protection that shuts down bypass capacitor should be selected to provide good
condition, Internal Short Circuit Protection that limits the under all load conditions. A 0.33 µF or larger tantalum, mylar,
maximum current the circuit will pass, and Output Transistor or other capacitor having low internal impedance at high
Safe–Area Compensation that reduces the output short frequencies should be chosen. The bypass capacitor should
circuit current as the voltage across the pass transistor is be mounted with the shortest possible leads directly across
increased. the regulators input terminals. Normally good construction
In many low current applications, compensation techniques should be used to minimize ground loops and
capacitors are not required. However, it is recommended that lead resistance drops since the regulator has no external
the regulator input be bypassed with a capacitor if the sense lead.
Input LM340–5.0 Output

LM340–5.0
0.33µF R Input
Constant
Current to
IO Grounded Load 7 2
–
0.33µF 6 0.1µF
These regulators can also be used as a current source when
connected as above. In order to minimize dissipation the LM340–5.0 3
+ 10k
is chosen in this application. Resistor R determines the current as 1k
follows: 4
MC1741G
5.0 V
IO = + IQ
R
Vout, 7.0 V to 20 V
IQ ^ 1.5 mA over line and load changes Vin – VO ≥ 2.0 V
For example, a 1 A current source would require R to be a 5 Ω,

10 W resistor and the output voltage compliance would be the input
intermediate values while retaining regulation characteristics. The
voltage less 7.0 V.
Figure 16. Current Boost Regulator Figure 17. Short Circuit Protection
MJ2955
MJ2955 or Equiv or Equiv.
Input RSC
Input
R
LM340 Output 2N6049
or Equiv.
R
LM340
1.0µF
The LM340, A series can be current boosted with a PNP transistor. The The circuit of Figure 17 can be modified to provide supply protection
MJ2955 provides current to 5.0 A. Resistor R in conjuction with the VBE against short circuits by adding a short circuit sense resistor, RSC, and
of the PNP determines when the pass transistor begins conducting; this an additional PNP transistor. The current sensing PNP must be able to
circuit is not short circuit proof. Input–output differential voltage handle the short circuit current of the three–terminal regulator.
minimum is increased by VBE of the pass transistor. Therefore, 4.0 A plastic power transistor is specified.

LM350
Regulator THREE–TERMINAL
ADJUSTABLE POSITIVE
The LM350 is an adjustable three–terminal positive voltage regulator
capable of supplying in excess of 3.0 A over an output voltage range of 1.2 V VOLTAGE REGULATOR
to 33 V. This voltage regulator is exceptionally easy to use and requires only
SEMICONDUCTOR
two external resistors to set the output voltage. Further, it employs internal
TECHNICAL DATA
current limiting, thermal shutdown and safe area compensation, making it
essentially blow–out proof.
The LM350 serves a wide variety of applications including local, on card
regulation. This device also makes an especially simple adjustable switching
T SUFFIX
regulator, a programmable output regulator, or by connecting a fixed resistor PLASTIC PACKAGE
between the adjustment and output, the LM350 can be used as a precision CASE 221A
current regulator.
• Guaranteed 3.0 A Output Current
• Output Adjustable between 1.2 V and 33 V Pin 1. Adjust
• Load Regulation Typically 0.1%
2. Vout
3. Vin
• Line Regulation Typically 0.005%/V
1
• Internal Short Circuit Current Limiting Constant with Temperature 2
3
• Output Transistor Safe Area Compensation
• Floating Operation for High Voltage Applications Heatsink surface is connected to Pin 2.
• Standard 3–lead Transistor Package

Vin vout
LM350
R1
240
IAdj Adjust
Cin* + C **
O
0.1µF 1µF
R2
Operating
* = Cin is required if regulator is located an appreciable distance from power supply filter.
LM350T TJ = 0° to +125°C Plastic Power
ǒ Ǔ
** = CO is not needed for stability, however, it does improve transient response.
LM350BT# TJ = –40° to +125°C Plastic Power
Vout + 1.25 V 1 ) RR21 ) IAdj R2 # Automotive temperature range selections are
available with special test conditions and additional
Since IAdj is controlled to less than 100 µA, the error associated with tests. Contact your local Motorola sales office for
this term is negligible in most applications. information.

LM350
MAXIMUM RATINGS
Soldering Lead Temperature (10 seconds) Tsolder 300 °C
ELECTRICAL CHARACTERISTICS (VI–VO = 5.0 V; IL = 1.5 A; TJ = Tlow to Thigh; Pmax [Note 1], unless otherwise noted.)
TA = 25°C, 3.0 V ≤ VI–VO ≤ 35 V

TA = 25°C, 10 mA ≤ Il ≤ 3.0 A
VO ≤ 5.0 V – 5.0 25 mV
VO ≥ 5.0 V – 0.1 0.5 % VO
Thermal Regulation, Pulse = 20 ms, Regtherm – 0.002 – % VO/W
(TA = +25°C)

Adjustment Pin Current Change 1,2 ∆IAdj – 0.2 5.0 µA
3.0 V ≤ VI–VO ≤ 35 V
10 mA ≤ IL ≤ 3.0 A, PD ≤ Pmax
3.0 V ≤ VI–VO ≤ 35 V
10 mA ≤ IO ≤ 3.0 A, PD ≤ Pmax
3.0 V ≤ VI–VO ≤ 35 V

10 mA ≤ IL ≤ 3.0 A
VO ≤ 5.0 V – 20 70 mV
VO ≥ 5.0 V – 0.3 1.5 % VO
Minimum Load Current to 3 ILmin – 3.5 10 mA
Maintain Regulation (VI–VO = 35 V)

VI–VO ≤ 10 V, PD ≤ Pmax 3.0 4.5 –
VI–VO = 30 V, PD ≤ Pmax, TA = 25°C 0.25 1.0 –
RMS Noise, % of VO N – 0.003 – % VO
TA= 25°C, 10 Hz ≤ f ≤ 10 kHz

CAdj = 10 µF 66 80 –
TA= 25°C for Endpoint Measurements Hrs.
Thermal Resistance, Junction–to–Case RθJC °C/W

Peak (Note 5) – 2.3 –
Average (Note 6) – – 1.5
NOTES: 1. Tlow to Thigh = 0° to +125°C; Pmax = 25 W for LM350T; Tlow to Thigh = – 40° to +125°C; Pmax = 25 W for LM350BT
from lot to lot.
5. Thermal Resistance evaluated measuring the hottest temperature on the die using an infrared scanner. This method of evaluation yields very
accurate thermal resistance values which are conservative when compared to the other measurement techniques.
6. The average die temperature is used to derive the value of thermal resistance junction to case (average).

LM350
Vin
310 310 230 120 5.6K
6.3V
170
160
6.7K
12K
5.0pF
13K
125K
200
12.4K
510
6.8K
135
6.3V
6.3V
30 30
pF pF 2.4K 105
5.1K
3.6K
5.8K
110
190 12.5K 4
0.45
Vout
Adjust
VCC
VOH – VOL
* VOL
VIH VOH
VIL Vin Vout VOL
LM350 IL
Adjust R1 240 RL
1%
+
Cin 0.1µF IAdj CO 1µF

1% Duty Cycle is suggested. 1%

LM350

Load Regulation (% VO) = X 100
VO (min Load)
Load Regulation (mV) = VO (min Load) –VO (max Load) VO (min Load)
VO (max Load)
Vin Vin Vout
LM350 IL
RL
(max Load)
Adjust 240 RL
R1 1% *
(min Load)
+
R2
1%

Vin Vout
LM350 IL
Adjust
240
VI R1 1% Vref RL
IAdj +
ISET
R2
1%
To Calculate R2:
Pulse Testing Required: Vout = ISET R2 + 1.250 V

24V
Vin Vout Vout = 10 V
14V LM350 IL
f = 120 Hz
D1 *
Adjust R1 240 RL
1% 1N4002
+
** +
1.65K CAdj 10µF
R2 1%
* D1 Discharges CAdj if Output is Shorted to Ground.

**CAdj provides an AC ground to the adjust pin.

LM350
∆ Vout , OUTPUT VOLTAGE CHANGE (%) Figure 5. Load Regulation Figure 6. Current Limit
0.4 7

0.2 TJ = 55°C
0 IL = 0.5 A 5
TJ = 25°C
–0.2
IL = 1.5 A
–0.4 3 TJ = 150°C
Vin = 15 V
–0.6 Vout = 10 V
–0.8 1
–1.0 0
–75 –50 –25 0 25 50 75 100 125 150 0 10 20 30 40
TJ, JUNCTION TEMPERATURE (°C) Vin–Vout, INPUT VOLTAGE DIFFERENTIAL (Vdc)

3.0
∆V0 = 100 mV

70
IL = 3.0 A
65 2.5
DIFFERENTIAL (Vdc)
IL = 2.0 A
60
55 2.0
50 IL = 500 mA
45 1.5
40
IL = 20 mA IL = 200 mA
35 1.0
–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150

1.260 5.0
4.5
TJ = –55°C
4.0
1.250 TJ = 25°C
3.5
3.0 TJ = 150°C
1.240 2.5
2.0
1.5
1.230
1.0
0.5
1.220 0
–75 –50 –25 0 25 50 75 100 125 150 0 10 20 30 40

LM350
100 140
CAdj = 10 µF
120

80
100
Without CAdj CAdj = 10 µF
60
80
40 60 Without CAdj
Vin – Vout = 5 V
IL = 500 mA 40 Vin – Vout = 5 V
f = 120 Hz IL = 500 mA
20
TJ = 25°C 20 f = 120 Hz
TJ = 25°C
0 0
0 5 10 15 20 25 30 35 0.01 0.1 1 10
Vout, OUTPUT VOLTAGE (V) Iout, OUTPUT CURRENT (A)
100 101
Vin = 15 V
80 IL = 500 mA Vout = 10 V
Vin = 15 V 100 IL = 500 mA
Vout = 10 V TJ = 25°C
60 TJ = 25°C
10–1
40 Without CAdj
CAdj = 10 µF
10–2
20 Without CAdj CAdj = 10 µF
0 10–3
10 100 1.0 k 10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k 1.0 M
3
DEVIATION (V)
1.5 2
DEVIATION (V)
1.0 1 CL = 1.0 µF; CAdj = 10 µF

0.5 CL = 1.0 µF; CAdj = 10 µF 0
0 –1 Vin = 15 V
Vout = 10 V
–0.5 –2 INL = 50 mA
Vout = 10 V CL = 0; Without CAdj
–1.0 –3 TJ = 25°C
IL = 50 mA
–1.5 TJ = 25°C CL = 0; Without CAdj 1.5
CURRENT (A)
CHANGE (V)
I L , LOAD
1.0 1.0
Vin IL
0.5 0.5
0 0
0 10 20 30 40 0 10 20 30 40

LM350
Basic Circuit Operation
External Capacitors
The LM350 is a three–terminal floating regulator. In
A 0.1 µF disc or 1 µF tantalum input bypass capacitor (Cin)
operation, the LM350 develops and maintains a nominal
is recommended to reduce the sensitivity to input line
1.25 V reference (Vref) between its output and adjustment
impedance.
terminals. This reference voltage is converted to a
The adjustment terminal may be bypassed to ground to
programming current (IPROG) by R1 (see Figure 17), and this
constant current flows through R2 to ground. The regulated
from being amplified as the output voltage is increased. A
output voltage is given by:
10 µF capacitor should improve ripple rejection about 15 dB
R2 Although the LM350 is stable with no output capacitance,
Vout = Vref (1 + ) + IAdj R2 like any feedback circuit, certain values of external
R1
capacitance can cause excessive ringing. An output
Since the current from the terminal (IAdj) represents an capacitance (CO) in the form of a 1 µF tantalum or 25 µF
error term in the equation, the LM350 was designed to control aluminum electrolytic capacitor on the output swamps this
IAdj to less than 100 µA and keep it constant. To do this, all effect and insures stability.
quiescent operating current is returned to the output terminal.
Protection Diodes
This imposes the requirement for a minimum load current. If
When external capacitors are used with any IC regulator, it
the load current is less than this minimum, the output voltage
is sometimes necessary to add protection diodes to prevent
will rise.
the capacitors from discharging through low current points
Since the LM350 is a floating regulator, it is only the
into the regulator.
voltage differential across the circuit which is important to
Figure 18 shows the LM350 with the recommended
performance, and operation at high voltages with respect to
protection diodes for output voltages in excess of 25 V or high
ground is possible.
capacitance values (CO > 25 µF, CAdj > 10 µF). Diode D1
Figure 17. Basic Circuit Configuration discharging through the IC during an output short circuit. The
combination of diodes D1 and D2 prevents CAdj from
Vin Vout discharging through the IC during an input short circuit.
LM350
+
R1
Vref Figure 18. Voltage Regulator with
Adjust IPROG
Protection Diodes
Vout
D1
IAdj
R2
1N4002
Vref = 1.25 V Typical Vin Vout
LM350
+
Load Regulation Cin R1 CO
D2
The LM350 is capable of providing extremely good load
Adjust 1N4002
regulation, but a few precautions are needed to obtain
maximum performance. For best performance, the
R2 CAdj

LM350
Figure 19. “Laboratory” Power Supply with Adjustable Current Limit and Output Voltage
D6
1N4002
Vout1 RSC Vin2 IO
Vout 2
Vin LM350 LM350
VO
32V Vin1 (1) (2)
+
0.1µF 240 D5
1.0µF
D1 IN4001 Tantalum
Adjust 1
1N4001 Adjust 2 +
Current 1K 1N4001 5.0K Voltage 10µF
Limit D2 Adjust
Adjust
1N4001
Q1
2N3822 D3
D4 Output Range:
0 ≤ VO ≤ 25 V
–10V
Q2 1N4001 0 ≤ IO ≤ 1.5 A
Diodes D1 and D2 and transistor Q2 are added to allow adjustment 2N5640
of output voltage to 0 V.
D6 protects both LM350’s during an input short circuit. –10V
Figure 20. Adjustable Current Limiter Figure 21. 5.0 V Electronic Shutdown Regulator
+25V Vout R1 Vout Iout D1

LM350
Vin 620 1N4002
Vin Vout
LM350
Adjust D1
R2 1N4001 +
120 1.0µF
the FET must be tied to a negative MPS2222
voltage below –1.25 V. 720 TTL
1.0k Control
Vref 2N5640
R2 ≤
IDSS
Vref Minimum Vout = 1.25 V
R1 = VSS*
IOmax + IDSS
VO < V(BR)DSS + 1.25 V + VSS
ILmin – IDSS < IO < 3.0 A
As shown O < IO < 1.0 A

Iout
Vin Vout Vin Vout R1
LM350 LM350
240 1N4001
IAdj
ǒ Ǔ)
Adjust 50k Adjust
R2 MPS2907 + Iout + Vref

R1
IAdj
10µF
^ 1.25 V
R1
10 mA ≤ Iout ≤ 3.0 A

LM2575
Advance Information EASY SWITCHER

Easy Switcher 1.0 A 1.0 A STEP–DOWN
Step-Down Voltage Regulator VOLTAGE REGULATOR
The LM2575 series of regulators are monolithic integrated circuits ideally SEMICONDUCTOR
suited for easy and convenient design of a step–down switching regulator TECHNICAL DATA
(buck converter). All circuits of this series are capable of driving a 1.0 A load
with excellent line and load regulation. These devices are available in fixed
output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output version.
These regulators were designed to minimize the number of external
components to simplify the power supply design. Standard series of
T SUFFIX
inductors optimised for use with the LM2575 are offered by several different
PLASTIC PACKAGE
inductor manufacturers. CASE 314D
1
Since the LM2575 converter is a switch–mode power supply, its efficiency
is significantly higher in comparison with popular three–terminal linear 5
regulators, especially with higher input voltages. In many cases, the power Pin 1. Vin
dissipated by the LM2575 regulator is so low, that no heatsink is required or 2. Output
its size could be reduced dramatically. 3. Ground
4. Feedback
The LM2575 features include a guaranteed ±4% tolerance on output 5. ON/OFF
voltage within specified input voltages and output load conditions, and ±10%
on the oscillator frequency (±2% over 0°C to 125°C). External shutdown is
included, featuring 80 µA typical standby current. The output switch includes
cycle–by–cycle current limiting, as well as thermal shutdown for full TV SUFFIX 1
protection under fault conditions. PLASTIC PACKAGE
CASE 314B
Features 5
• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions Heatsink surface

•
connected to Pin 3.
Adjustable Version Output Voltage Range of 1.23 V to 37 V ±4%
Maximum Over Line and Load Conditions
• Guaranteed 1.0 A Output Current D2T SUFFIX
• Wide Input Voltage Range: 4.75 V to 40 V PLASTIC PACKAGE
• CASE 936A 1
Requires Only 4 External Components (D2PAK) 5
• 52 kHz Fixed Frequency Internal Oscillator
• TTL Shutdown Capability, Low Power Standby Mode
• High Efficiency
Heatsink surface (shown as terminal 6 in case outline
drawing) is connected to Pin 3.
• Uses Readily Available Standard Inductors
• Thermal Shutdown and Current Limit Protection
DEVICE TYPE/NOMINAL OUTPUT VOLTAGE
Applications
LM2575–3.3 3.3 V
• Simple and High–Efficiency Step–Down (Buck) Regulators LM2575–5 5.0 V
• Efficient Pre–Regulator for Linear Regulators
LM2575–12
LM2575–15
12 V
15 V
• On–Card Switching Regulators LM2575–Adj 1.23 V to 37 V
• Positive to Negative Converters (Buck–Boost)
• Negative Step–Up Converters
• Power Supply for Battery Chargers

Device
Operating
Temperature Range Package
LM2575T–** Straight Lead
LM2575TV–** TJ = –40° to +125°C Vertical Mount
LM2575D2T–** Surface Mount
** = Voltage Option, ie. 3.3, 5.0, 12, 15 V and
** =\Adjustable Output.

LM2575
Figure 1. Block Diagram and Typical Application
Typical Application (Fixed Output Voltage Versions)

Feedback
7.0 V – 40 V +Vin 4 L1
LM2575 330 µH
Unregulated
DC Input 1 Output 5.0 V Regulated
Cin Output 1.0 A Load
100 µF 2 D1
3 Gnd 5 ON/OFF 1N5819 Cout
330 µF
Representative Block Diagram and Typical Application
Unregulated +Vin 3.1 V Internal ON/OFF

ON/OFF Output R2
DC Input Regulator Voltage Versions (Ω)
1 5
Cin 3.3 V 1.7 k
4 5.0 V 3.1 k
12 V 8.84 k
Feedback 15 V 11.3 k
Current
R2 Fixed Gain Limit For adjustable version
Error Amplifier Comparator R1 = open, R2 = 0 Ω
Driver Regulated
R1
Freq Latch Output
1.0 k L1
Shift Output Vout
18 kHz
1.0 Amp 2
1.235 V Switch Gnd D1 Cout
Band–Gap 52 kHz Thermal
Reference Reset 3 Load
Oscillator Shutdown
ABSOLUTE MAXIMUM RATINGS (Absolute Maximum Ratings indicate limits beyond

which damage to the device may occur.)
Maximum Supply Voltage Vin 45 V
ON/OFF Pin Input Voltage – –0.3 V ≤ V ≤ +Vin V
Output Voltage to Ground (Steady–State) – –1.0 V
Power Dissipation
Case 314B and 314D (TO–220, 5–Lead) PD Internally Limited W
Thermal Resistance, Junction–to–Ambient RθJA 65 °C/W
Thermal Resistance, Junction–to–Case RθJC 5.0 °C/W
Case 936A (D2PAK) PD Internally Limited W
(Figure 34)
Minimum ESD Rating (Human Body Model: C – 3.0 kV
= 100 pF, R = 1.5 kΩ)
Lead Temperature (Soldering, 10 s) – 260 °C

Maximum Junction Temperature TJ 150 °C
NOTE: ESD data available upon request.

LM2575
OPERATING RATINGS (Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see the Electrical Characteristics.)
Supply Voltage Vin 40 V
SYSTEM PARAMETERS ([Note 1] Test Circuit Figure 14)

ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for
the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 200 mA. For typical values TJ = 25°C, for min/max values TJ is the operating
junction temperature range that applies [Note 2], unless otherwise noted.)
LM2575–3.3 ([Note 1] Test Circuit Figure 14)

Output Voltage (Vin = 12 V, ILoad = 0.2 A, TJ = 25°C) Vout 3.234 3.3 3.366 V
Output Voltage (4.75 V ≤ Vin ≤ 40 V, 0.2 A ≤ ILoad ≤ 1.0 A) Vout V
TJ = 25°C 3.168 3.3 3.432
TJ = –40 to +125°C 3.135 – 3.465
Efficiency (Vin = 12 V, ILoad = 1.0 A) η – 75 – %
LM2575–5 ([Note 1] Test Circuit Figure 14)

Output Voltage (Vin = 12 V, ILoad = 0.2 A, TJ = 25°C) Vout 4.9 5.0 5.1 V
Output Voltage (8.0 V ≤ Vin ≤ 40 V, 0.2 A ≤ ILoad ≤ 1.0 A) Vout V
TJ = 25°C 4.8 5.0 5.2
TJ = –40 to +125°C 4.75 – 5.25

Output Voltage (Vin = 25 V, ILoad = 0.2 A, TJ = 25°C) Vout 11.76 12 12.24 V
Output Voltage (15 V ≤ Vin ≤ 40 V, 0.2 A ≤ ILoad ≤ 1.0 A) Vout V
TJ = 25°C 11.52 12 12.48
TJ = –40 to +125°C 11.4 – 12.6
Efficiency (Vin = 15V, ILoad = 1.0 A) η – 88 – %

Output Voltage (Vin = 30 V, ILoad = 0.2 A, TJ = 25°C) Vout 14.7 15 15.3 V
Output Voltage (18 V ≤ Vin ≤ 40 V, 0.2 A ≤ ILoad ≤ 1.0 A) Vout V
TJ = 25°C 14.4 15 15.6
TJ = –40 to +125°C 14.25 – 15.75
LM2575 ADJUSTABLE VERSION ([Note 1] Test Circuit Figure 14)

Feedback Voltage (Vin = 12 V, ILoad = 0.2 A, Vout = 5.0 V, TJ = 25°C) VFB 1.217 1.23 1.243 V
Feedback Voltage (8.0 V ≤ Vin ≤ 40 V, 0.2 A ≤ ILoad ≤ 1.0 A, Vout = 5.0 V) VFB V
TJ = 25°C 1.193 1.23 1.267
TJ = –40 to +125°C 1.18 – 1.28
Efficiency (Vin = 12 V, ILoad = 1.0 A, Vout = 5.0 V) η – 77 – %
NOTES: 1. External components such as the catch diode, inductor, input and output capacitors can affect switching regulator system performance. When the
LM2575 is used as shown in the Figure 14 test circuit, system performance will be as shown in system parameters section.
2. Tested junction temperature range for the LM2575: Tlow = –40°C Thigh = +125°C

LM2575
DEVICE PARAMETERS
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for
the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 200 mA. For typical values TJ = 25°C, for min/max values TJ is the operating
junction temperature range that applies [Note 2], unless otherwise noted.)
ALL OUTPUT VOLTAGE VERSIONS
Feedback Bias Current (Vout = 5.0 V [Adjustable Version Only]) Ib nA
TJ = 25°C – 25 100
TJ = –40 to +125°C – – 200
Oscillator Frequency [Note 3] fosc kHz
TJ = 25°C – 52 –
TJ = 0 to +125°C 47 – 58
TJ = –40 to +125°C 42 – 63
Saturation Voltage (Iout = 1.0 A [Note 4]) Vsat V
TJ = 25°C – 1.0 1.2
TJ = –40 to +125°C – – 1.3
Max Duty Cycle (“on”) [Note 5] DC 94 98 – %
Current Limit (Peak Current [Notes 4 and 3]) ICL A
TJ = 25°C 1.7 2.3 3.0
TJ = –40 to +125°C 1.4 – 3.2
Output Leakage Current [Notes 6 and 7], TJ = 25°C IL mA
Output = 0 V – 0.8 2.0
Output = –1.0 V – 6.0 20
Quiescent Current [Note 6] IQ mA
TJ = 25°C – 5.0 9.0
TJ = –40 to +125°C – – 11
Standby Quiescent Current (ON/OFF Pin = 5.0 V (“off”)) Istby µA
TJ = 25°C – 80 200
TJ = –40 to +125°C – – 400
ON/OFF Pin Logic Input Level (Test Circuit Figure 14) V
Vout = 0 V VIH
TJ = 25°C 2.2 1.4 –
TJ = –40 to +125°C 2.4 – –
Vout = Nominal Output Voltage VIL
TJ = 25°C – 1.2 1.0
TJ = –40 to +125°C – – 0.8
ON/OFF Pin Input Current (Test Circuit Figure 14) µA
ON/OFF Pin = 5.0 V (“off”), TJ = 25°C IIH – 15 30
ON/OFF Pin = 0 V (“on”), TJ = 25°C IIL – 0 5.0
NOTES: 3. The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which causes the regulated output voltage to
drop approximately 40% from the nominal output voltage. This self protection feature lowers the average dissipation of the IC by lowering the
minimum duty cycle from 5% down to approximately 2%.
4. Output (Pin 2) sourcing current. No diode, inductor or capacitor connected to output pin.
5. Feedback (Pin 4) removed from output and connected to 0 V.
6. Feedback (Pin 4) removed from output and connected to +12 V for the Adjustable, 3.3 V, and 5.0 V versions, and +25 V for the 12 V and 15 V
versions, to force the output transistor “off”.
7. Vin = 40 V.

LM2575
TYPICAL PERFORMANCE CHARACTERISTICS (Circuit of Figure 14)
Figure 2. Normalized Output Voltage Figure 3. Line Regulation

0.6 1.0
Vin = 20 V
Vout , OUTPUT VOLTAGE CHANGE (%)
Vout , OUTPUT VOLTAGE CHANGE (%)

ILoad = 200 mA
ILoad = 200 mA TJ = 25°C
0.4 0.8
Normalized at
TJ = 25°C
0.2 0.6 3.3 V, 5.0 V and Adj
0 0.4
–0.2 0.2
–0.4 0 12 V and 15 V
–0.6 –0.2
–50 –25 0 25 50 75 100 125 0 5.0 10 15 20 25 30 35 40
TJ, JUNCTION TEMPERATURE (°C) Vin, INPUT VOLTAGE (V)
Figure 4. Switch Saturation Voltage Figure 5. Current Limit

1.2 3.0
1.1
Vsat , SATURATION VOLTAGE (V)
2.5
IO , OUTPUT CURRENT (A)
1.0
2.0
0.9
–40°C
0.8 1.5
0.7 25°C
1.0
0.6
125°C 0.5
0.5
Vin = 25 V
0.4 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 –50 –25 0 25 50 75 100 125
SWITCH CURRENT (A) TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Dropout Voltage Figure 7. Quiescent Current

2.0 20
∆Vout = 5% Vout = 5.0 V
INPUT–OUTPUT DIFFERENTIAL (V)
Rind = 0.2 Ω
IQ , QUIESCENT CURRENT (mA)
1.8 18 Measured at
ILoad = 1.0 A Ground Pin
1.6 16 TJ = 25°C
1.4 14
ILoad = 1.0 A
1.2 12
1.0 ILoad = 200 mA 10

0.8 8.0 ILoad = 200 mA
0.6 6.0
0.4 4.0
–50 –25 0 25 50 75 100 125 0 5.0 10 15 20 25 30 35 40
TJ, JUNCTION TEMPERATURE (°C) Vin, INPUT VOLTAGE (V)

LM2575
Figure 8. Standby Quiescent Current Figure 9. Standby Quiescent Current

Istby , STANDBY QUIESCENT CURRENT (µ A)
Istby , STANDBY QUIESCENT CURRENT (µ A)

120 120
TJ = 25°C Vin = 12 V
VON/OFF = 5.0 V
100 100
80 80
60 60
40 40
20 20
0 0
0 5.0 10 15 20 25 30 35 40 –50 –25 0 25 50 75 100 125
Vin, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Oscillator Frequency Figure 11. Feedback Pin Current

2.0 40
Vin = 12 V Adjustable
IFB , FEEDBACK PIN CURRENT (nA)

NORMALIZED FREQUENCY (%)
Normalized at 25°C Version Only

0
20
–2.0
–4.0 0
–6.0
–20
–8.0
–10 –40
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
I Load, LOAD CURRENT (A) Vout , OUTPUT VOLTAGE
Figure 12. Switching Waveforms Figure 13. Load Transient Response

CHANGE (mV)
OUTPUT 10 V 100
PIN
VOLTAGE 0 0
OUTPUT 1.0 A –100

PIN
CURRENT 0
INDUCTOR 1.0 A 1.0

CURRENT 0.5 A 0.5
OUTPUT 0 0
RIPPLE 20 mV
VOLTAGE /DIV
5.0 µs/DIV 100 µs/DIV

LM2575
Figure 14. Typical Test Circuit
5.0 Output Voltage Versions
Feedback
4
+Vin Vout
LM2575–5 L1
1 330 µH Regulated
Output Output
2
Vin 3 Gnd 5 ON/OFF
Unregulated Cin 100 µF, 50 V, Aluminium Electrolytic
Cin Cout
Cout 330 µF, 16 V, Aluminium Electrolytic
DC Input 100 µF/50 V D1 330 µF D1 Schottky, 1N5819
8.0 V – 40 V /16 V Load
1N5819 L1 330 µF, PE–52627 (for 5.0 V in, 3.3 V out,
use 100 µH, PE–92108)
ǒ Ǔ
Adjustable Output Voltage Versions
+ Vref 1 ) R2
ǒ Ǔ
Feedback V out
R1
4
+Vin Vout
+ R1
LM2575 L1 V out
1 Adjustable 330 µH Regulated R2 –1
Output Output V
ref
2
3 Gnd 5 ON/OFF Where Vref = 1.23 V, R1
Unregulated R2 between 1.0 kΩ and 5.0 kΩ
Cin Cout
DC Input 100 µF/50 V 330 µF
8.0 V – 40 V D1 Load
1N5819 /16 V
R1
PCB LAYOUT GUIDELINES

As in any switching regulator, the layout of the printed On the other hand, the PCB area connected to the Pin 2
circuit board is very important. Rapidly switching currents (emitter of the internal switch) of the LM2575 should be kept
associated with wiring inductance, stray capacitance and to a minimum in order to minimize coupling to sensitive
parasitic inductance of the printed circuit board traces can circuitry.
generate voltage transients which can generate Another sensitive part of the circuit is the feedback. It is
electromagnetic interferences (EMI) and affect the desired important to keep the sensitive feedback wiring short. To
operation. As indicated in the Figure 14, to minimize assure this, physically locate the programming resistors near
inductance and ground loops, the length of the leads to the regulator, when using the adjustable version of the
indicated by heavy lines should be kept as short as possible. LM2575 regulator.
For best results, single–point grounding (as indicated) or
ground plane construction should be used.

LM2575
PIN FUNCTION DESCRIPTION

Pin Symbol Description (Refer to Figure 1)
1 Vin This pin is the positive input supply for the LM2575 step–down switching regulator. In order to minimize
voltage transients and to supply the switching currents needed by the regulator, a suitable input bypass
capacitor must be present (Cin in Figure 1).
2 Output This is the emitter of the internal switch. The saturation voltage Vsat of this output switch is typically 1.0 V.
It should be kept in mind that the PCB area connected to this pin should be kept to a minimum in order to
minimize coupling to sensitive circuitry.
3 Gnd Circuit ground pin. See the information about the printed circuit board layout.
4 Feedback This pin senses regulated output voltage to complete the feedback loop. The signal is divided by the
internal resistor divider network R2, R1 and applied to the non–inverting input of the internal error amplifier.
In the Adjustable version of the LM2575 switching regulator this pin is the direct input of the error amplifier
and the resistor network R2, R1 is connected externally to allow programming of the output voltage.
5 ON/OFF It allows the switching regulator circuit to be shut down using logic level signals, thus dropping the total
input supply current to approximately 80 µA. The input threshold voltage is typically 1.4 V. Applying a
voltage above this value (up to +Vin) shuts the regulator off. If the voltage applied to this pin is lower than
1.4 V or if this pin is connected to ground, the regulator will be in the “on” condition.
DESIGN PROCEDURE
Buck Converter Basics
The LM2575 is a “Buck” or Step–Down Converter which is I
t
off
+
ǒ V out – V
D
Ǔ
the most elementary forward–mode converter. Its basic L L(off)
schematic can be seen in Figure 15. This period ends when the power switch is once again
The operation of this regulator topology has two distinct turned on. Regulation of the converter is accomplished by
time periods. The first one occurs when the series switch is varying the duty cycle of the power switch. It is possible to
on, the input voltage is connected to the input of the inductor. describe the duty cycle as follows:
The output of the inductor is the output voltage, and the
rectifier (or catch diode) is reverse biased. During this period,
d
t on
T
+
, where T is the period of switching.
since there is a constant voltage source connected across For the buck converter with ideal components, the duty
the inductor, the inductor current begins to linearly ramp cycle can also be described as:
ǒ Ǔ +
upwards, as described by the following equation: V out
d
+
V
– V out t on V
in in
I
L(on) L Figure 16 shows the buck converter idealized waveforms
During this “on” period, energy is stored within the core of the catch diode voltage and the inductor current.
material in the form of magnetic flux. If the inductor is properly
designed, there is sufficient energy stored to carry the Figure 16. Buck Converter Idealized Waveforms
requirements of the load during the “off” period.
Von(SW)
Figure 15. Basic Buck Converter
Power
Diode Voltage
L Power Power Power

Switch Vout Switch Switch Switch
Off Power Off On
Switch
On
Vin D1 Cout RLoad Time
VD(FWD)
Inductor Current
The next period is the “off” period of the power switch. Ipk
When the power switch turns off, the voltage across the ILoad(AV)
inductor reverses its polarity and is clamped at one diode Imin Power Power
voltage drop below ground by catch dioded. Current now Diode Switch Diode Switch
flows through the catch diode thus maintaining the load Time
current loop. This removes the stored energy from the
inductor. The inductor current during this time is:

LM2575
Procedure (Fixed Output Voltage Version) In order to simplify the switching regulator design, a step–by–step
design procedure and example is provided.
Procedure Example
Given Parameters: Given Parameters:
Vout = Regulated Output Voltage (3.3 V, 5.0 V, 12 V or 15 V) Vout = 5.0 V
Vin(max) = Maximum DC Input Voltage Vin(max) = 20 V
ILoad(max) = Maximum Load Current ILoad(max) = 0.8 A
1. Controller IC Selection 1. Controller IC Selection
According to the required input voltage, output voltage and According to the required input voltage, output voltage, current
current, select the appropriate type of the controller IC output polarity and current value, use the LM2575–5 controller IC
voltage version.
2. Input Capacitor Selection (Cin) 2. Input Capacitor Selection (Cin)
To prevent large voltage transients from appearing at the input A 47 µF, 25 V aluminium electrolytic capacitor located near to
and for stable operation of the converter, an aluminium or the input and ground pins provides sufficient bypassing.
tantalum electrolytic bypass capacitor is needed between the
input pin +Vin and ground pin Gnd. This capacitor should be
located close to the IC using short leads. This capacitor should
have a low ESR (Equivalent Series Resistance) value.
3. Catch Diode Selection (D1)
3. Catch Diode Selection (D1)
A. For this example the current rating of the diode is 1.0 A.
A. Since the diode maximum peak current exceeds the
regulator maximum load current the catch diode current
rating must be at least 1.2 times greater than the maximum
load current. For a robust design the diode should have a
current rating equal to the maximum current limit of the
LM2575 to be able to withstand a continuous output short
B. Use a 30 V 1N5818 Schottky diode, or any of the suggested
B. The reverse voltage rating of the diode should be at least
fast recovery diodes shown in the Table 4.
1.25 times the maximum input voltage.
4. Inductor Selection (L1) 4. Inductor Selection (L1)
A. According to the required working conditions, select the A. Use the inductor selection guide shown in Figures 17 to 21.
correct inductor value using the selection guide from
Figures 17 to 21.
B. From the appropriate inductor selection guide, identify the B. From the selection guide, the inductance area intersected
inductance region intersected by the Maximum Input by the 20 V line and 0.8 A line is L330.
Voltage line and the Maximum Load Current line. Each
region is identified by an inductance value and an inductor
code.
C. Select an appropriate inductor from the several different C. Inductor value required is 330 µH. From the Table 1 or
manufacturers part numbers listed in Table 1 or Table 2. Table 2, choose an inductor from any of the listed
When using Table 2 for selecting the right inductor the manufacturers.
designer must realize that the inductor current rating must
be higher than the maximum peak current flowing through
ǒ Ǔ
the inductor. This maximum peak current can be calculated
as follows:
)
V –V out t on
I +I
p(max) Load(max)
in
2L
where ton is the “on” time of the power switch and
V
ton + out x 1
V fosc
in
For additional information about the inductor, see the
inductor section in the “External Components” section of
this data sheet.

LM2575
Procedure (Fixed Output Voltage Version) (continued)In order to simplify the switching regulator design, a step–by–step
design procedure and example is provided.
Procedure Example
5. Output Capacitor Selection (Cout) 5. Output Capacitor Selection (Cout)
A. Since the LM2575 is a forward–mode switching regulator A. Cout = 100 µF to 470 µF standard aluminium electrolytic.
with voltage mode control, its open loop 2–pole–2–zero
frequency characteristic has the dominant pole–pair
determined by the output capacitor and inductor values. For
stable operation and an acceptable ripple voltage,
(approximately 1% of the output voltage) a value between
100 µF and 470 µF is recommended.
B. Due to the fact that the higher voltage electrolytic capacitors B. Capacitor voltage rating = 16 V.
generally have lower ESR (Equivalent Series Resistance)
numbers, the output capacitor’s voltage rating should be at
least 1.5 times greater than the output voltage. For a 5.0 V
regulator, a rating at least 8V is appropriate, and a 10 V or
16 V rating is recommended.
Procedure (Adjustable Output Version: LM2575–Adj)

Procedure Example
Given Parameters: Given Parameters:
Vout = Regulated Output Voltage Vout = 8.0 V
Vin(max) = Maximum DC Input Voltage Vin(max) = 12 V
ILoad(max) = Maximum Load Current ILoad(max) = 1.0 A
1. Programming Output Voltage 1. Programming Output Voltage (selecting R1 and R2)
ǒ Ǔ
To select the right programming resistor R1 and R2 value (see Select R1 and R2:
ǒ Ǔ
ǒ Ǔ
+ 1.23 1 ) R2
Figure 14) use the following formula:
V out Select R1 = 1.8 kΩ
+ Vref 1 )
ǒ Ǔ
R2 R1
V out where Vref = 1.23 V
R1
+ R1 * 1 + 1.8 k 1.23 *1
V out 8.0 V
ǒ Ǔ
Resistor R1 can be between 1.0 k and 5.0 kΩ. (For best R2
V V
temperature coefficient and stability with time, use 1% metal ref
film resistors). R2 = 9.91 kΩ, choose a 9.88 k metal film resistor.
+
V out
R2 R1 – 1
V
ref
2. Input Capacitor Selection (Cin) 2. Input Capacitor Selection (Cin)

To prevent large voltage transients from appearing at the input A 100 µF aluminium electrolytic capacitor located near the
and for stable operation of the converter, an aluminium or input and ground pin provides sufficient bypassing.
tantalum electrolytic bypass capacitor is needed between the
input pin +Vin and ground pin Gnd This capacitor should be
located close to the IC using short leads. This capacitor should
have a low ESR (Equivalent Series Resistance) value.
For additional information see input capacitor section in the
“External Components” section of this data sheet.
3. Catch Diode Selection (D1) 3. Catch Diode Selection (D1)
A. Since the diode maximum peak current exceeds the A. For this example, a 3.0 A current rating is adequate.
regulator maximum load current the catch diode current
rating must be at least 1.2 times greater than the maximum
load current. For a robust design, the diode should have a
current rating equal to the maximum current limit of the
LM2575 to be able to withstand a continuous output short.
B. The reverse voltage rating of the diode should be at least B. Use a 20 V 1N5820 or MBR320 Schottky diode or any
1.25 times the maximum input voltage. suggested fast recovery diode in the Table 4.

LM2575
Procedure (Adjustable Output Version: LM2575–Adj) (continued)
Procedure Example
4. Inductor Selection (L1) 4. Inductor Selection (L1)
A. Use the following formula to calculate the inductor Volt x A. Calculate E x T [V x µs] constant:
microsecond [V x µs] constant:
E x T + ǒ
V – V out
in
V out
V on
Ǔx 10
6
F[Hz]
[V x ms] E x T + (12 – 8.0) x 8.0
12
x 1000
52
+ 51 [V x ms]
B. Match the calculated E x T value with the corresponding B. E x T = 51 [V x µs]
number on the vertical axis of the Inductor Value Selection
Guide shown in Figure 21. This E x T constant is a measure
of the energy handling capability of an inductor and is
dependent upon the type of core, the core area, the number
of turns, and the duty cycle.
C. Next step is to identify the inductance region intersected by C. ILoad(max) = 1.0 A
the E x T value and the maximum load current value on the Inductance Region = L220
horizontal axis shown in Figure 21.
D. From the inductor code, identify the inductor value. Then D. Proper inductor value = 220 µH
select an appropriate inductor from the Table 1 or Table 2. Choose the inductor from the Table 1 or Table 2.
The inductor chosen must be rated for a switching
frequency of 52 kHz and for a current rating of 1.15 x IIoad.
The inductor current rating can also be determined by
ǒ Ǔ
calculating the inductor peak current:
+ ILoad(max) )
V – V out ton
in
I
p(max) 2L
where ton is the “on” time of the power switch and
t on + VVout x f 1
in osc
For additional information about the inductor, see the
inductor section in the “External Components” section of
this data sheet.
5. Output Capacitor Selection (Cout) 5. Output Capacitor Selection (Cout)
w +
A. Since the LM2575 is a forward–mode switching regulator A.
with voltage mode control, its open loop 2–pole–2–zero Cout 7.785 12 53 µF
8.220
frequency characteristic has the dominant pole–pair
determined by the output capacitor and inductor values. To achieve an acceptable ripple voltage, select
Cout = 100 µF electrolytic capacitor.
For stable operation, the capacitor must satisfy the
following requirement:
w
V
in(max)
Cout 7.785 [µF]
V out x L [µH]
B. Capacitor values between 10 µF and 2000 µF will satisfy

the loop requirements for stable operation. To achieve an
acceptable output ripple voltage and transient response, the
output capacitor may need to be several times larger than
the above formula yields.
C. Due to the fact that the higher voltage electrolytic capacitors
generally have lower ESR (Equivalent Series Resistance)
numbers, the output capacitor’s voltage rating should be at
least 1.5 times greater than the output voltage. For a 5.0 V
regulator, a rating of at least 8V is appropriate, and a 10 V
or 16 V rating is recommended.

LM2575
INDUCTOR VALUE SELECTION GUIDE
Figure 17. LM2575–3.3 Figure 18. LM2575–5.0

60 60
H1000 40 H1500
20
Vin , MAXIMUM INPUT VOLTAGE (V)

25
15 L680 20
H1000 L680
10 L470 15
8.0
L330 12 L470
7.0
L220 10 L330
6.0 L150 9.0
L220
L100 8.0
L150
5.0 7.0
0.2 0.3 0.4 0.5 0.6 0.8 1.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IL, MAXIMUM LOAD CURRENT (A) IL, MAXIMUM LOAD CURRENT (A)
Figure 19. LM2575–12 Figure 20. LM2575–15

60 60
H2200
40 H2200 H1500 Vin , MAXIMUM INPUT VOLTAGE (V) 40

30 35 H1500
H1000 30
25 H680 H1000
H470 25 H680
20 H470
22
18
17 L680 20
16 L470 19 L680
L330 L470 L330
15 18 L220
L220
14 17
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IL, MAXIMUM LOAD CURRENT (A) IL, MAXIMUM LOAD CURRENT (A)
Figure 21. LM2575–Adj

200
150 H2200 H1500

125 H1000
ET, VOLTAGE TIME (Vµ s)
100 H680 H470

80
70
60 L680
50 L470
40 L330
L220
30
L150
L100
20
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IL, MAXIMUM LOAD CURRENT (A)
NOTE: This Inductor Value Selection Guide is applicable for continuous mode only.

LM2575
Table 1. Inductor Selection Guide

Inductor Inductor
Code Value Pulse Eng Renco AIE Tech 39
L100 100 µH PE–92108 RL2444 415–0930 77 308 BV
L150 150 µH PE–53113 RL1954 415–0953 77 358 BV
L220 220 µH PE–52626 RL1953 415–0922 77 408 BV
L330 330 µH PE–52627 RL1952 415–0926 77 458 BV
L470 470 µH PE–53114 RL1951 415–0927 –
L680 680 µH PE–52629 RL1950 415–0928 77 508 BV
H150 150 µH PE–53115 RL2445 415–0936 77 368 BV
H220 220 µH PE–53116 RL2446 430–0636 77 410 BV
H330 330 µH PE–53117 RL2447 430–0635 77 460 BV
H470 470 µH PE–53118 RL1961 430–0634 –
H680 680 µH PE–53119 RL1960 415–0935 77 510 BV
H1000 1000 µH PE–53120 RL1959 415–0934 77 558 BV
H1500 1500 µH PE–53121 RL1958 415–0933 –
H2200 2200 µH PE–53122 RL2448 415–0945 77 610 BV
Table 2. Inductor Selection Guide

Inductance Current Schott Renco Pulse Engineering Coilcraft
(µH) (A) THT SMT THT SMT THT SMT SMT
0.32 67143940 67144310 RL–1284–68–43 RL1500–68 PE–53804 PE–53804–S DO1608–68
0.58 67143990 67144360 RL–5470–6 RL1500–68 PE–53812 PE–53812–S DO3308–683
68
0.99 67144070 67144450 RL–5471–5 RL1500–68 PE–53821 PE–53821–S DO3316–683
1.78 67144140 67144520 RL–5471–5 – PE–53830 PE–53830–S DO5022P–683
0.48 67143980 67144350 RL–5470–5 RL1500–100 PE–53811 PE–53811–S DO3308–104
100 0.82 67144060 67144440 RL–5471–4 RL1500–100 PE–53820 PE–53820–S DO3316–104
1.47 67144130 67144510 RL–5471–4 – PE–53829 PE–53829–S DO5022P–104
0.39 – 67144340 RL–5470–4 RL1500–150 PE–53810 PE–53810–S DO3308–154
150 0.66 67144050 67144430 RL–5471–3 RL1500–150 PE–53819 PE–53819–S DO3316–154
1.20 67144120 67144500 RL–5471–3 – PE–53828 PE–53828–S DO5022P–154
0.32 67143960 67144330 RL–5470–3 RL1500–220 PE–53809 PE–53809–S DO3308–224
220 0.55 67144040 67144420 RL–5471–2 RL1500–220 PE–53818 PE–53818–S DO3316–224
1.00 67144110 67144490 RL–5471–2 – PE–53827 PE–53827–S DO5022P–224
0.42 67144030 67144410 RL–5471–1 RL1500–330 PE–53817 PE–53817–S DO3316–334
330
0.80 67144100 67144480 RL–5471–1 – PE–53826 PE–53826–S DO5022P–334
NOTE: Table 1 and Table 2 of this Indicator Selection Guide shows some examples of different manufacturer products suitable for design with the LM2575.

LM2575
Table 3. Example of Several Inductor Manufacturers Phone/Fax Numbers

Phone + 1–619–674–8100
Pulse Engineering Inc.
Fax + 1–619–674–8262
Phone + 353 93 24 107

Pulse Engineering Inc. Europe
Fax + 353 93 24 459
Phone + 1–516–645–5828
Renco Electronics Inc.
Fax + 1–516–586–5562
Phone + 1–813–347–2181
AIE Magnetics
Fax
Phone + 1–708–322–2645
Coilcraft Inc.
Fax + 1–708–639–1469
Phone + 44 1236 730 595

Coilcraft Inc., Europe
Fax + 44 1236 730 627
Phone + 33 8425 2626

Tech 39
Fax + 33 8425 2610
Phone + 1–612–475–1173
Schott Corp.
Fax + 1–612–475–1786
Table 4. Diode Selection Guide gives an overview about both surface–mount and through–hole diodes for an
effective design. Device listed in bold are available from Motorola.
Schottky Ultra–Fast Recovery
1.0 A 3.0 A 1.0 A 3.0 A
VR SMT THT SMT THT SMT THT SMT THT
20 V SK12 1N5817 SK32 1N5820
SR102 MBRD320 MBR320
SR302
30 V MBRS130LT3 1N5818 SK33 1N5821 MURS320T3
SK13 SR103 MBRD330 MBR330 MURS120T3 MUR120
11DQ03 SR303 11DF1
31DQ03 HER102
40 V MBRS140T3 1N5819 MBRS340T3 1N5822 10BF10 MURD320 MUR320
SK14 SR104 MBRD340 MBR340 30WF10
10BQ040 11DQ04 30WQ04 SR304 MUR420
10MQ040 SK34 31DQ04
50 V MBRS150 MBR150 MBRD350 MBR350 31DF1
10BQ050 SR105 SK35 SR305 HER302
11DQ05 30WQ05 11DQ05

LM2575
EXTERNAL COMPONENTS
Input Capacitor (Cin) At Low Temperatures, Put in Parallel Aluminium

The Input Capacitor Should Have a Low ESR Electrolytic Capacitors with Tantalum Capacitors
For stable operation of the switch mode converter a low Electrolytic capacitors are not recommended for
ESR (Equivalent Series Resistance) aluminium or solid temperatures below –25°C. The ESR rises dramatically at
tantalum bypass capacitor is needed between the input pin cold temperatures and typically rises 3 times at –25°C and as
and the ground pin to prevent large voltage transients from much as 10 times at –40°C. Solid tantalum capacitors have
appearing at the input. It must be located near the regulator much better ESR spec at cold temperatures and are
and use short leads. With most electrolytic capacitors, the recommended for temperatures below –25°C. They can be
capacitance value decreases and the ESR increases with also used in parallel with aluminium electrolytics. The value
lower temperatures. For reliable operation in temperatures of the tantalum capacitor should be about 10% or 20% of the
below –25°C larger values of the input capacitor may be total capacitance. The output capacitor should have at least
needed. Also paralleling a ceramic or solid tantalum 50% higher RMS ripple current rating at 52 kHz than the
capacitor will increase the regulator stability at cold peak–to–peak inductor ripple current.
temperatures. Catch Diode
RMS Current Rating of Cin Locate the Catch Diode Close to the LM2575
The important parameter of the input capacitor is the RMS The LM2575 is a step–down buck converter; it requires a
current rating. Capacitors that are physically large and have fast diode to provide a return path for the inductor current
large surface area will typically have higher RMS current when the switch turns off. This diode must be located close to
ratings. For a given capacitor value, a higher voltage the LM2575 using short leads and short printed circuit traces
electrolytic capacitor will be physically larger than a lower to avoid EMI problems.
voltage capacitor, and thus be able to dissipate more heat to
Use a Schottky or a Soft Switching
the surrounding air, and therefore will have a higher RMS
Ultra–Fast Recovery Diode
current rating. The consequence of operating an electrolytic
Since the rectifier diodes are very significant source of
capacitor above the RMS current rating is a shortened
losses within switching power supplies, choosing the rectifier
operating life. In order to assure maximum capacitor
that best fits into the converter design is an important
operating lifetime, the capacitor’s RMS ripple current rating
process. Schottky diodes provide the best performance
should be:
because of their fast switching speed and low forward
Irms > 1.2 x d x ILoad
voltage drop.
where d is the duty cycle, for a buck regulator They provide the best efficiency especially in low output
d+ + t on
T
V out
V
voltage applications (5.0 V and lower). Another choice could
be Fast–Recovery, or Ultra–Fast Recovery diodes. It has to
in
and d + + t on
T
|V out|
|V out|) V
*
for a buck boost regulator.
be noted, that some types of these diodes with an abrupt
turnoff characteristic may cause instability or EMI troubles.
in A fast–recovery diode with soft recovery characteristics
Output Capacitor (Cout) can better fulfill a quality, low noise design requirements.
For low output ripple voltage and good stability, low ESR Table 4 provides a list of suitable diodes for the LM2575
output capacitors are recommended. An output capacitor has regulator. Standard 50/60 Hz rectifier diodes such as the
two main functions: it filters the output and provides regulator 1N4001 series or 1N5400 series are NOT suitable.
loop stability. The ESR of the output capacitor and the Inductor
peak–to–peak value of the inductor ripple current are the The magnetic components are the cornerstone of all
main factors contributing to the output ripple voltage switching power supply designs. The style of the core and
value.Standard aluminium electrolytics could be adequate for the winding technique used in the magnetic component’s
some applications but for quality design low ESR types are design has a great influence on the reliability of the overall
recommended. power supply.
An aluminium electrolytic capacitor’s ESR value is related Using an improper or poorly designed inductor can cause
to many factors such as the capacitance value, the voltage high voltage spikes generated by the rate of transitions in
rating, the physical size and the type of construction. In most current within the switching power supply, and the possibility
cases, the higher voltage electrolytic capacitors have lower of core saturation can arise during an abnormal operational
ESR value. Often capacitors with much higher voltage mode. Voltage spikes can cause the semiconductors to enter
ratings may be needed to provide low ESR values that are avalanche breakdown and the part can instantly fail if enough
required for low output ripple voltage. energy is applied. It can also cause significant RFI (Radio
The Output Capacitor Requires an ESR Value Frequency Interference) and EMI (Electro–Magnetic
That Has an Upper and Lower Limit Interference) problems.
As mentioned above, a low ESR value is needed for low Continuous and Discontinuous Mode of Operation
output ripple voltage, typically 1% to 2% of the output voltage. The LM2575 step–down converter can operate in both the
But if the selected capacitor’s ESR is extremely low (below continuous and the discontinuous modes of operation. The
0.05 Ω), there is a possibility of an unstable feedback loop, regulator works in the continuous mode when loads are
resulting in oscillation at the output. This situation can occur relatively heavy, the current flows through the inductor
when a tantalum capacitor, that can have a very low ESR, is continuously and never falls to zero. Under light load
used as the only output capacitor.

LM2575
conditions, the circuit will be forced to the discontinuous toroid and bobbin core, as well as different core materials
mode when inductor current falls to zero for certain period of such as ferrites and powdered iron from different
time (see Figure 22 and Figure 23). Each mode has manufacturers.
distinctively different operating characteristics, which can For high quality design regulators the toroid core seems to
affect the regulator performance and requirements. In many be the best choice. Since the magnetic flux is completely
cases the preferred mode of operation is the continuous contained within the core, it generates less EMI, reducing
mode. It offers greater output power, lower peak currents in noise problems in sensitive circuits. The least expensive is
the switch, inductor and diode, and can have a lower output the bobbin core type, which consists of wire wound on a
ripple voltage. On the other hand it does require larger ferrite rod core. This type of inductor generates more EMI
inductor values to keep the inductor current flowing due to the fact that its core is open, and the magnetic flux is
continuously, especially at low output load currents and/or not completely contained within the core.
high input voltages. When multiple switching regulators are located on the
To simplify the inductor selection process, an inductor same printed circuit board, open core magnetics can cause
selection guide for the LM2575 regulator was added to this interference between two or more of the regulator circuits,
data sheet (Figures 17 through 21). This guide assumes that especially at high currents due to mutual coupling. A toroid,
the regulator is operating in the continuous mode, and pot core or E–core (closed magnetic structure) should be
selects an inductor that will allow a peak–to–peak inductor used in such applications.
ripple current to be a certain percentage of the maximum
Do Not Operate an Inductor Beyond its
design load current. This percentage is allowed to change as
Maximum Rated Current
different design load currents are selected. For light loads
Exceeding an inductor’s maximum current rating may
(less than approximately 200 mA) it may be desirable to
cause the inductor to overheat because of the copper wire
operate the regulator in the discontinuous mode, because
losses, or the core may saturate. Core saturation occurs
the inductor value and size can be kept relatively low.
when the flux density is too high and consequently the cross
Consequently, the percentage of inductor peak–to–peak
sectional area of the core can no longer support additional
current increases. This discontinuous mode of operation is
lines of magnetic flux.
perfectly acceptable for this type of switching converter. Any
This causes the permeability of the core to drop, the
buck regulator will be forced to enter discontinuous mode if
inductance value decreases rapidly and the inductor begins
the load current is light enough.
to look mainly resistive. It has only the dc resistance of the
winding. This can cause the switch current to rise very rapidly
Figure 22. Continuous Mode Switching
and force the LM2575 internal switch into cycle–by–cycle
Current Waveforms current limit, thus reducing the dc output load current. This
can also result in overheating of the inductor and/or the
POWER SWITCH
CURRENT (A)
1.0 LM2575. Different inductor types have different saturation

characteristics, and this should be kept in mind when
selecting an inductor.
0
Figure 23. Discontinuous Mode Switching
Current Waveforms
CURRENT (A)
1.0
INDUCTOR
POWER SWITCH
CURRENT (A)
0 0.1
0
HORTIZONTAL TIME BASE: 5.0 µs/DIV
Selecting the Right Inductor Style

Some important considerations when selecting a core
CURRENT (A)
INDUCTOR
type are core material, cost, the output power of the power 0.1
supply, the physical volume the inductor must fit within, and
the amount of EMI (Electro–Magnetic Interference) shielding 0
that the core must provide. The inductor selection guide
covers different styles of inductors, such as pot core, E–core, HORTIZONTAL TIME BASE: 5.0 µs/DIV

LM2575
GENERAL RECOMMENDATIONS
a heatsink for ambient temperatures up to approximately
Output Voltage Ripple and Transients
50°C (depending on the output voltage and load current).
Source of the Output Ripple
Higher ambient temperatures require some heatsinking,
Since the LM2575 is a switch mode power supply
either to the printed circuit (PC) board or an external heatsink.
regulator, its output voltage, if left unfiltered, will contain a
sawtooth ripple voltage at the switching frequency. The The Surface Mount Package D 2PAK and its Heatsinking
output ripple voltage value ranges from 0.5% to 3% of the The other type of package, the surface mount D2PAK, is
output voltage. It is caused mainly by the inductor sawtooth designed to be soldered to the copper on the PC board. The
ripple current multiplied by the ESR of the output capacitor. copper and the board are the heatsink for this package and
the other heat producing components, such as the catch
Short Voltage Spikes and How to Reduce Them
diode and inductor. The PC board copper area that the
The regulator output voltage may also contain short
package is soldered to should be at least 0.4 in2 (or
voltage spikes at the peaks of the sawtooth waveform (see
100 mm2) and ideally should have 2 or more square inches
Figure 24). These voltage spikes are present because of the
(1300 mm2) of 0.0028 inch copper. Additional increasing of
fast switching action of the output switch, and the parasitic
copper area beyond approximately 3.0 in2 (2000 mm2) will
inductance of the output filter capacitor. There are some
not improve heat dissipation significantly. If further thermal
other important factors such as wiring inductance, stray
improvements are needed, double sided or multilayer PC
capacitance, as well as the scope probe used to evaluate
boards with large copper areas should be considered.
these transients, all these contribute to the amplitude of these
spikes. To minimise these voltage spikes, low inductance Thermal Analysis and Design
capacitors should be used, and their lead lengths must be The following procedure must be performed to determine
kept short. The importance of quality printed circuit board whether or not a heatsink will be required. First determine:
layout design should also be highlighted. 1. PD(max) maximum regulator power dissipation in the
application.
Figure 24. Output Ripple Voltage Waveforms 2. TA(max) maximum ambient temperature in the
application.
Voltage spikes caused by switching action of the output
switch and the parasitic inductance of the output capacitor 3. TJ(max) maximum allowed junction temperature
(125°C for the LM2575). For a conservative
design, the maximum junction temperature
should not exceed 110°C to assure safe
UNFILITERED
OUTPUT operation. For every additional 10°C
VOLTAGE temperature rise that the junction must
withstand, the estimated operating lifetime of
VERTICAL the component is halved.
RESOLUTION:
20 mV/DIV 4. RθJC package thermal resistance junction–case.
5. RθJA package thermal resistance junction–ambient.
FILITERED
OUTPUT (Refer to Absolute Maximum Ratings in this data sheet or
VOLTAGE RθJC and RθJA values).
The following formula is to calculate the total power
HORTIZONTAL TIME BASE: 10 µs/DIV dissipated by the LM2575:
PD = (Vin x IQ) + d x ILoad x Vsat
Minimizing the Output Ripple
where d is the duty cycle and for buck converter
In order to minimise the output ripple voltage it is possible
to enlarge the inductance value of the inductor L1 and/or to
use a larger value output capacitor. There is also another way
d + +
t on
T
V
V
O,
in
to smooth the output by means of an additional LC filter IQ (quiescent current) and Vsat can be found in the
(20 µH, 100 µF), that can be added to the output (see LM2575 data sheet,
Figure 33) to further reduce the amount of output ripple and Vin is minimum input voltage applied,
transients. With such a filter it is possible to reduce the VO is the regulator output voltage,
output ripple voltage transients 10 times or more. Figure 24 ILoad is the load current.
shows the difference between filtered and unfiltered output
waveforms of the regulator shown in Figure 33. The dynamic switching losses during turn–on and turn–off
The upper waveform is from the normal unfiltered output of can be neglected if proper type catch diode is used.
the converter, while the lower waveform shows the output Packages Not on a Heatsink (Free–Standing)
ripple voltage filtered by an additional LC filter. For a free–standing application when no heatsink is used,
Heatsinking and Thermal Considerations the junction temperature can be determined by the following
The Through–Hole Package TO–220 expression:
The LM2575 is available in two packages, a 5–pin TJ = (RθJA) (PD) + TA
TO–220(T, TV) and a 5–pin surface mount D2PAK(D2T). where (RθJA)(PD) represents the junction temperature rise
There are many applications that require no heatsink to keep caused by the dissipated power and TA is the maximum
the LM2575 junction temperature within the allowed ambient temperature.
operating range. The TO–220 package can be used without

LM2575
Packages on a Heatsink cannot exceed +28 V because the maximum voltage

If the actual operating junction temperature is greater than appearing across the regulator is the absolute sum of the
the selected safe operating junction temperature determined input and output voltages and this must be limited to a
in step 3, than a heatsink is required. The junction maximum of 40 V.
temperature will be calculated as follows: This circuit configuration is able to deliver approximately
0.35 A to the output when the input voltage is 12 V or higher.
TJ = PD (RθJA + RθCS + RθSA) + TA
At lighter loads the minimum input voltage required drops to
where RθJC is the thermal resistance junction–case, approximately 4.7 V, because the buck–boost regulator
RθCS is the thermal resistance case–heatsink, topology can produce an output voltage that, in its absolute
RθSA is the thermal resistance heatsink–ambient. value, is either greater or less than the input voltage.
Since the switch currents in this buck–boost configuration
If the actual operating temperature is greater than the
are higher than in the standard buck converter topology, the
selected safe operating junction temperature, then a larger
available output current is lower.
heatsink is required.
This type of buck–boost inverting regulator can also
Some Aspects That can Influence Thermal Design require a larger amount of startup input current, even for light
It should be noted that the package thermal resistance and loads. This may overload an input power source with a
the junction temperature rise numbers are all approximate, current limit less than 1.5 A.
and there are many factors that will affect these numbers, Such an amount of input startup current is needed for at
such as PC board size, shape, thickness, physical position, least 2.0 ms or more. The actual time depends on the output
location, board temperature, as well as whether the voltage and size of the output capacitor.
surrounding air is moving or still. Because of the relatively high startup currents required by
Other factors are trace width, total printed circuit copper this inverting regulator topology, the use of a delayed startup
area, copper thickness, single– or double–sided, multilayer or an undervoltage lockout circuit is recommended.
board, the amount of solder on the board or even colour of Using a delayed startup arrangement, the input capacitor
the traces. can charge up to a higher voltage before the switch–mode
The size, quantity and spacing of other components on regulator begins to operate.
the board can also influence its effectiveness to dissipate The high input current needed for startup is now partially
the heat. supplied by the input capacitor Cin.
Design Recommendations:
Figure 25. Inverting Buck–Boost Regulator Using the
The inverting regulator operates in a different manner than
LM2575–12 Develops –12 V @ 0.35 A
the buck converter and so a different design procedure has to
Unregulated be used to select the inductor L1 or the output capacitor Cout.
Feedback
DC Input The output capacitor values must be larger than is
12 V to 25 V +Vin 4 L1 normally required for buck converter designs. Low input
LM2575–12 100 µH
1 Output voltages or high output currents require a large value output
Cin
100 µF 2 capacitor (in the range of thousands of µF).
/50 V 3 Gnd 5 ON/OFF D1 Cout The recommended range of inductor values for the
1800 µF
1N5819
/16 V
inverting converter design is between 68 µH and 220 µH. To
select an inductor with an appropriate current rating, the
Regulated inductor peak current has to be calculated.
Output The following formula is used to obtain the peak inductor
–12 V @ 0.35 A current:
ADDITIONAL APPLICATIONS I [ I (V
Load in
) O )
|V |) V x t on
in
peak V 2L 1
Inverting Regulator in
An inverting buck–boost regulator using the LM2575–12 is
shown in Figure 25. This circuit converts a positive input
where t on + V )
|V |
O
|V |
x 1 , and f osc
f osc
+ 52 kHz.
in O
voltage to a negative output voltage with a common ground Under normal continuous inductor current operating
by bootstrapping the regulators ground to the negative output conditions, the worst case occurs when Vin is minimal.
voltage. By grounding the feedback pin, the regulator senses Note that the voltage appearing across the regulator is the
the inverted output voltage and regulates it. absolute sum of the input and output voltage, and must not
In this example the LM2575–12 is used to generate a exceed 40 V.
–12 V output. The maximum input voltage in this case

LM2575
Figure 26. Inverting Buck–Boost Figure 28. Inverting Buck–Boost Regulator Shut Down
Regulator with Delayed Startup Circuit Using a PNP Transistor
Unregulated +V Shutdown
DC Input Feedback Off Input
12 V to 25 V +Vin 4 L1 0
LM2575–12 100 µH On
Cin 1 Output R2
100 µF C1 2 5.6 k
/50 V 0.1 µF 5 ON/OFF 3 Gnd +Vin +Vin
D1 Cout
1
R1
1N5819 1800 µF LM2575–XX
47 k /16 V Cin
R2
47 k 100 µF
Q1
2N3906 5 ON/OFF 3 Gnd
Regulated
Output
–12 V @ 0.35 A R1
12 k –Vout
It has been already mentioned above, that in some
situations, the delayed startup or the undervoltage lockout
features could be very useful. A delayed startup circuit NOTE: This picture does not show the complete circuit.
applied to a buck–boost converter is shown in Figure 26.
Negative Boost Regulator
Figure 31 in the “Undervoltage Lockout” section describes an
This example is a variation of the buck–boost topology and
undervoltage lockout feature for the same converter
is called a negative boost regulator. This regulator
topology.
experiences relatively high switch current, especially at low
input voltages. The internal switch current limiting results in
Figure 27. Inverting Buck–Boost Regulator Shut Down
lower output load current capability.
Circuit Using an Optocoupler
The circuit in Figure 29 shows the negative boost
configuration. The input voltage in this application ranges
+Vin +Vin from –5.0 V to –12 V and provides a regulated –12 V output.
LM2575–XX If the input voltage is greater than –12 V, the output will rise
1
above –12 V accordingly, but will not damage the regulator.
Cin R1
100 µF 47 k Figure 29. Negative Boost Regulator
Shutdown 5 ON/OFF 3 Gnd
Input
5.0 V
Off
0 R3
On 470 Cout
R2
47 k 4 1000 µF
–Vout +Vin /16 V
LM2575–12 Feedback
1 Output D1
MOC8101
Cin 2
100 µF 3 Gnd 5 ON/OFF 1N5817 Regulated
NOTE: This picture does not show the complete circuit. /50 V Output
Vout = –12 V
With the inverting configuration, the use of the ON/OFF pin
requires some level shifting techniques. This is caused by the Load Current from
L1 200 mA for Vin = –5.2 V
fact, that the ground pin of the converter IC is no longer at
to 500 mA for Vin = –7.0 V
ground. Now, the ON/OFF pin threshold voltage (1.4 V 150 µH
approximately) has to be related to the negative output Unregulated
DC Input
voltage level. There are many different possible shut down –Vin = –5.0 V to –12 V
methods, two of them are shown in Figures 27 and 28.

LM2575
Design Recommendations: shown in Figure 32. Resistor R3 pulls the ON/OFF pin high
The same design rules as for the previous inverting and keeps the regulator off until the input voltage reaches a
buck–boost converter can be applied. The output capacitor predetermined threshold level, which is determined by the
Cout must be chosen larger than would be required for a
standard buck converter. Low input voltages or high output
currents require a large value output capacitor (in the range
following expression:
V
th
V [
Z1
1 R2 V
R1
ǒ Ǔ
) ) BE
(Q1)
of thousands of µF). The recommended range of inductor
values for the negative boost regulator is the same as for Figure 31. Undervoltage Lockout Circuit for
inverting converter design. Buck Converter
Another important point is that these negative boost
converters cannot provide current limiting load protection in
the event of a short in the output so some other means, such +Vin +Vin
as a fuse, may be necessary to provide the load protection. LM2575–5.0
1
Delayed Startup
There are some applications, like the inverting regulator R2 R3 Cin
10 k 47 k 100 µF 5 ON/OFF 3 Gnd
already mentioned above, which require a higher amount of
startup current. In such cases, if the input power source is
limited, this delayed startup feature becomes very useful. Z1
To provide a time delay between the time the input voltage 1N5242B
is applied and the time when the output voltage comes up,
the circuit in Figure 30 can be used. As the input voltage is Q1
2N3904
applied, the capacitor C1 charges up, and the voltage across
the resistor R2 falls down. When the voltage on the ON/OFF R1 Vth ≈ 13 V
10 k
pin falls below the threshold value 1.4 V, the regulator starts
up. Resistor R1 is included to limit the maximum voltage
applied to the ON/OFF pin, reduces the power supply noise NOTE: This picture does not show the complete circuit.
sensitivity, and also limits the capacitor C1 discharge current,
but its use is not mandatory. Figure 32. Undervoltage Lockout Circuit for
When a high 50 Hz or 60 Hz (100 Hz or 120 Hz Buck–Boost Converter
respectively) ripple voltage exists, a long delay time can
cause some problems by coupling the ripple into the ON/OFF
pin, the regulator could be switched periodically on and off +Vin +Vin
with the line (or double) frequency. LM2575–5.0
1
Figure 30. Delayed Startup Circuitry Cin
R2 R3
15 k 68 k 100 µF 5 ON/OFF 3 Gnd
+Vin +Vin
LM2575–XX Z1
1
1N5242B
Vth ≈ 13 V
C1 Q1
0.1 µF 5 ON/OFF 3 Gnd 2N3904
Cin R1
100 µF 15 k
R1 Vout = –5.0 V
47 k R2
47 k
NOTE: This picture does not show the complete circuit.
Adjustable Output, Low–Ripple Power Supply

NOTE: This picture does not show the complete circuit. A 1.0 A output current capability power supply that
features an adjustable output voltage is shown in Figure 33.
Undervoltage Lockout This regulator delivers 1.0 A into 1.2 V to 35 V output. The
Some applications require the regulator to remain off until input voltage ranges from roughly 8.0 V to 40 V. In order to
the input voltage reaches a certain threshold level. Figure 31 achieve a 10 or more times reduction of output ripple, an
shows an undervoltage lockout circuit applied to a buck additional L–C filter is included in this circuit.
regulator. A version of this circuit for buck–boost converter is

LM2575
Figure 33. Adjustable Power Supply with Low Ripple Voltage
Feedback
Unregulated
4
DC Input +Vin
+ LM2575–Adj L1 L2 Regulated
1 150 µH 20 µH
Output Output Voltage
2 1.2 V to 35 V @1.0 A
3 Gnd 5 ON/OFF R2
50 k
C1
Cin 100 µF
100 µF D1
Cout
/50 V 2200 µF R1
1N5819
/16 V 1.1 k
Optional Output
Ripple Filter

80 3.5

70 Free Air 3.0

Mounted
ÎÎÎÎ
60 2.5
L
50 Minimum
ÎÎÎÎ 2.0
ÎÎÎÎ
Size Pad L
40 1.5
RθJA
30 1.0
0 5.0 10 15 20 25 30

LM2575
THE LM2575–5.0 STEP–DOWN VOLTAGE REGULATOR WITH 5.0 V @ 1.0 A OUTPUT POWER CAPABILITY.
TYPICAL APPLICATION WITH THROUGH–HOLE PC BOARD LAYOUT
Figure 35. Schematic Diagram of the LM2575–5.0 Step–Down Converter
Feedback
4
Unregulated +Vin
LM2575–5.0 L1
DC Input
1 330 µH
+Vin = +7.0 V to +40 V Output Regulated Output
+Vout1 = 5.0 V @ 1.0 A
2
3 Gnd 5 ON/OFF
C1
100 µF J1
D1 Cout
/50 V 1N5819 330 µF
/16 V
Gndin Gndout
C1 – 100 µF, 50 V, Aluminium Electrolytic

D1 – 1.0 A, 40 V, Schottky Rectifier, 1N5819
L1 – 330 µH, Tech 39: 77 458 BV, Toroid Core, Through–Hole, Pin 3 = Start, Pin 7 = Finish
Figure 36. Printed Circuit Board Figure 37. Printed Circuit Board
Component Side Copper Side
Gndin Gndout
U1 LM2575
C1
J1 C2
D1
L1
DC–DC Converter
+Vin +Vout1
NOTE: Not to scale. NOTE: Not to scale.

LM2575
THE LM2575–ADJ STEP–DOWN VOLTAGE REGULATOR WITH 8.0 V @ 1.0 A OUTPUT POWER
CAPABILITY. TYPICAL APPLICATION WITH THROUGH–HOLE PC BOARD LAYOUT
Figure 38. Schematic Diagram of the 8.0 V @ 1.0 V Step–Down Converter Using the LM2575–Adj
(An additional LC filter is included to achieve low output ripple voltage)
Regulated
Output Unfiltered
Vout1 = 8.0 V @1.0 A

4 Feedback
Unregulated
DC Input +Vin
LM2575–Adj L1 L2 Regulated
+Vin = +10 V to + 40 V 1 330 µH 25 µH
Output Output Filtered
2 Vout2 = 8.0 V @1.0 A

3 Gnd 5 ON/OFF
R2
10 k C3
C1 100 µF
100 µF D1 C2 /16 V
/50 V 1N5819 330 µF R1
/16 V 1.8 k
V
out
Vref = 1.23 V
ǒ Ǔ
+ Vref ) 1 ) R2
R1
C1 – 100 µF, 50 V, Aluminium Electrolytic R1 is between 1.0 k and 5.0 k
D1 – 1.0 A, 40 V, Schottky Rectifier, 1N5819
L1 – 330 µH, Tech 39: 77 458 BV, Toroid Core, Through–Hole, Pin 3 = Start, Pin 7 = Finish
L2 – 25 µH, TDK: SFT52501, Toroid Core, Through–Hole
R1 – 1.8 k
R2 – 10 k
Figure 39. PC Board Component Side Figure 40. PC Board Copper Side
Gndin U1 LM2575 Gndout

C3
C1
C2
L1 D1 J1
L2
+Vout2
+Vin
+Vout1
R2 R1 MOTOROLA
NOTE: Not to scale. NOTE: Not to scale.
References
• National Semiconductor LM2575 Data Sheet and Application Note
• National Semiconductor LM2595 Data Sheet and Application Note
• Marty Brown “Pratical Switching Power Supply Design”, Academic Press, Inc., San Diego 1990
• Ray Ridley “High Frequency Magnetics Design”, Ridley Engineering, Inc. 1995

LM2931
Series
Low Dropout
Voltage Regulators LOW DROPOUT
The LM2931 series consists of positive fixed and adjustable output VOLTAGE REGULATORS
voltage regulators that are specifically designed to maintain proper
regulation with an extremely low input–to–output voltage differential. These
devices are capable of supplying output currents in excess of 100 mA and
feature a low bias current of 0.4 mA at 10 mA output. FIXED OUTPUT VOLTAGE
Designed primarily to survive in the harsh automotive environment, these
devices will protect all external load circuitry from input fault conditions
Z SUFFIX
caused by reverse battery connection, two battery jump starts, and
PLASTIC PACKAGE
excessive line transients during load dump. This series also includes internal Pin 1. Output
CASE 29
current limiting, thermal shutdown, and additionally, is able to withstand 2. Ground
1
2 3. Input
temporary power–up with mirror–image insertion. 3
Due to the low dropout voltage and bias current specifications, the
LM2931 series is ideally suited for battery powered industrial and consumer
equipment where an extension of useful battery life is desirable. The ‘C’ T SUFFIX
suffix adjustable output regulators feature an output inhibit pin which is PLASTIC PACKAGE
extremely useful in microprocessor–based systems. CASE 221A
• Input–to–Output Voltage Differential of < 0.6 V @ 100 mA Heatsink surface
Pin 1. Input
• Output Current in Excess of 100 mA connected to Pin 2. 1
2. Ground
3. Output
• Low Bias Current
2
3
• 60 V Load Dump Protection

• – 50 V Reverse Transient Protection 1
• Internal Current Limiting with Thermal Shutdown 3
1
•
2
3
Temporary Mirror–Image Protection
• Ideally Suited for Battery Powered Equipment
DT SUFFIX
PLASTIC PACKAGE
DT–1 SUFFIX
PLASTIC PACKAGE
• Economical 5–Lead TO–220 Package with Two Optional Leadforms CASE 369A CASE 369
• Available in Surface Mount SOP–8, D2PAK and DPAK Packages
(DPAK) (DPAK)
D2T SUFFIX
PLASTIC PACKAGE
CASE 936
2
(D2PAK) 1
3

(See Following Page for Ordering Information.) case outline drawing) is connected to Pin 2.
FIXED ADJUSTABLE OUTPUT VOLTAGE

Pin 1. Adjust
N.C. 5 4 N.C.
2. Output Inhibit
Gnd Gnd TH SUFFIX 3. Ground
Input 8 1 Output PLASTIC PACKAGE 4. Input
8 CASE 314A 5. Output
1
(Top View) 1
5
D SUFFIX
PLASTIC PACKAGE TV SUFFIX 1
1
CASE 751 PLASTIC PACKAGE 5
ADJUSTABLE (SOP–8) CASE 314B
5
D2T SUFFIX
Output
5 4 Adjust PLASTIC PACKAGE
Inhibit
CASE 936A
Gnd Gnd T SUFFIX (D2PAK)
Input 8 1 Output PLASTC PACKAGE
CASE 314D 1 Heatsink surface (shown as
(Top View) terminal 6 in case outline
5
Heatsink surface connected to Pin 3. drawing) is connected to Pin 3.

LM2931 Series
Output
Device Voltage Tolerance Case Package
LM2931AD–5.0 751 SOP–8 Surface Mount
LM2931ADT–5.0 369A Surface Mount DPAK
LM2931ADT–1–5.0 369 DPAK
± 3.8%
3 8%
LM2931AD2T–5.0 936 Surface Mount D2PAK
LM2931AT–5.0 221A TO–220 Type
LM2931AZ–5.0 29 TO–92 Type
50V
5.0
LM2931D–5.0 751 SOP–8 Surface Mount
LM2931D2T–5.0 936 Surface Mount D2PAK
LM2931DT–5.0 369A Surface Mount DPAK
LM2931DT–1–5.0 369 DPAK
LM2931T–5.0 221A TO–220 Type
LM2931Z–5.0 ± 5.0% 29 TO–92 Type
LM2931CD 751 SOP–8 Surface Mount
LM2931CD2T 936A Surface Mount D2PAK
LM2931CT Adjustable 314D 5–Pin TO–220 Type
LM2931CTH 314A 5–Pin Horizontal Leadform
LM2931CTV 314B 5–Pin Vertical Leadform
MAXIMUM RATINGS
Input Voltage Continuous VI 40 Vdc
Transient Input Voltage (τ ≤ 100 ms) VI(τ) 60 Vpk
Transient Reverse Polarity Input Voltage –VI(τ) – 50– Vpk
1.0% Duty Cycle, τ ≤ 100 ms
Power Dissipation
Case 29 (TO–92 Type)
TA = 25°C PD Internally Limited W
Thermal Resistance, Junction–to–Case RθJC 83 °C/W
Case 221A, 314A, 314B and 314D (TO–220 Type)
Case 369 and 369A (DPAK) [Note 1]
Case 751 (SOP–8) [Note 2]
Case 936 and 936A (D2PAK) [Note 3]
Tested Operating Junction Temperature Range TJ – 40 to +125 °C
NOTES: 1. DPAK Junction–to–Ambient Thermal Resistance is for vertical mounting. Refer to Figure 23 for
board mounted Thermal Resistance.
2. SOP–8 Junction–to–Ambient Thermal Resistance is for minimum recommended pad size. Refer
to Figure 23 for Thermal Resistance variation versus pad size.
3. D2PAK Junction–to–Ambient Thermal Resistance is for vertical mounting. Refer to Figure 25 for
board mounted Thermal Resistance.

LM2931 Series
Input
6.0
30 k
6.0 k
6.8 V
350
500
Output
Output Inhibit
30 k 30 k 50 k
30 k * 48 k 180 k 184 k 5.8 V
3.94 k
Adjust EPI
3.0 k Bias
92.8 k *
11.5 k 35 k 10 k
Ground
*Deleted on Adjustable Regulators This device contains 26 active transistors.
ELECTRICAL CHARACTERISTICS (Vin = 14 V, IO = 10 mA, CO = 100 µF, CO(ESR) = 0.3 Ω, TJ = 25°C [Note 4].)
LM2931–5.0 LM2931A–5.0
FIXED OUTPUT
Output Voltage VO V
Vin = 14 V, IO = 10 mA, TJ = 25°C 4.75 5.0 5.25 4.81 5.0 5.19
Vin = 6.0 V to 26 V, IO ≤ 100 mA, TJ = – 40° to +125°C 4.50 – 5.50 4.75 – 5.25
Vin = 9.0 V to 16 V – 2.0 10 – 2.0 10
Vin = 6.0 V to 26 V – 4.0 30 – 4.0 30
Load Regulation (IO = 5.0 mA to 100 mA) Regload – 14 50 – 14 50 mV
Output Impedance ZO mΩ
IO = 10 mA, ∆IO = 1.0 mA, f = 100 Hz to 10 kHz – 200 – – 200 –
Bias Current IB mA
Vin = 14 V, IO = 100 mA, TJ = 25°C – 5.8 30 – 5.8 30
Vin = 6.0 V to 26 V, IO = 10 mA, TJ = – 40° to +125°C – 0.4 1.0 – 0.4 1.0
Output Noise Voltage (f = 10 Hz to 100 kHz) Vn – 700 – – 700 – µVrms
Long Term Stability S – 20 – – 20 – mV/kHR
Ripple Rejection (f = 120 Hz) RR 60 90 – 60 90 – dB
Dropout Voltage VI–VO V
IO = 10 mA – 0.015 0.2 – 0.015 0.2
IO = 100 mA – 0.16 0.6 – 0.16 0.6
Over–Voltage Shutdown Threshold Vth(OV) 26 29.5 40 26 29.5 40 V
Output Voltage with Reverse Polarity Input (Vin = –15 V) –VO – 0.3 0 – – 0.3 0 – V
NOTE: 4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

LM2931 Series
ELECTRICAL CHARACTERISTICS (Vin = 14 V, VO = 3.0 V, IO = 10 mA, R1 = 27 k, CO = 100 µF, CO(ESR) = 0.3 Ω, TJ = 25°C [Note 4].)
LM2931C
ADJUSTABLE OUTPUT
Reference Voltage (Note 5, Figure 18) Vref V
IO = 10 mA, TJ = 25°C 1.14 1.20 1.26
IO ≤ 100 mA, TJ = – 40 to +125°C 1.08 – 1.32
Output Voltage Range VO range 3.0 to 24 2.7 to 29.5 – V
Line Regulation (Vin = VO + 0.6 V to 26 V) Regline – 0.2 1.5 mV/V
Load Regulation (IO = 5.0 mA to 100 mA) Regload – 0.3 1.0 %/V
Output Impedance ZO mΩ/V
IO = 10 mA, ∆IO = 1.0 mA, f = 10 Hz to 10 kHz – 40 –
Bias Current IB mA
IO = 100 mA – 6.0 –
IO = 10 mA – 0.4 1.0
Output Inhibited (Vth(OI) = 2.5 V) – 0.2 1.0
Adjustment Pin Current IAdj – 0.2 – µA
Output Noise Voltage (f = 10 Hz to 100 kHz) Vn – 140 – µVrms/V
Long–Term Stability S – 0.4 – %/kHR
Ripple Rejection (f = 120 Hz) RR 0.10 0.003 – %/V
IO = 10 mA – 0.015 0.2
IO = 100 mA – 0.16 0.6
Over–Voltage Shutdown Threshold Vth(OV) 26 29.5 40 V
Output Voltage with Reverse Polarity Input (Vin = –15 V) –VO – 0.3 0 – V
Output Inhibit Threshold Voltages Vth(OI) V
Output “On”: TJ = 25°C – 2.15 1.90
TJ = – 40° to +125°C – – 1.20
Output “Off”: TJ = 25°C 2.50 2.26 –
TJ = – 40° to +125°C 3.25 – –
Output Inhibit Threshold Current (Vth(OI) = 2.5 V) Ith(OI) – 30 50 µA
NOTES: 4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
5. The reference voltage on the adjustable device is measured from the output to the adjust pin across R1.

LM2931 Series
Figure 2. Dropout Voltage versus

Figure 1. Dropout Voltage versus Output Current Junction Temperature
200 300
Vin –VO , DROPOUT VOLTAGE (mV)
Vin –VO , DROPOUT VOLTAGE (mV)

Vin = 14 V
160 Vin = 14 V ∆Vout = 100 mV
∆Vout = 100 mV IO = 100 mA
TJ = 25°C 200
120
80
100
40 IO = 50 mA
IO = 10 mA
0 0
0 20 40 60 80 100 0 25 50 75 100 125
IO, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Peak Output Current versus Input Voltage Figure 4. Output Voltage versus Input Voltage
350 6.0
Vout = 5.0 V
I O, OUTPUT CURRENT (mA)
5.0 TA = 25°C
TJ = –40°C VO , OUTPUT VOLTAGE (V)
TJ = 25°C
250 4.0
TJ = 85°C
3.0
150 2.0
Dashed lines below Vin = 5.0 V RL = 50 Ω IO = 100 mA
are for Adjustable output devices only. 1.0
50 0
0 5.0 10 15 20 25 30 0 1.0 2.0 3.0 4.0 5.0 6.0
Vin, INPUT VOLTAGE (V) Vin, INPUT VOLTAGE (V)
Figure 5. Output Voltage versus Input Voltage Figure 6. Load Dump Characteristics
6.0
Vin , INPUT VOLTAGE
Vout = 5.0 V
VCC = 15 V RL = 50 Ω
(10 V/DIV)
5.0
VFB1 = 5.05 V CO = 100 µF
τ = 150 ms
4.0 TA = 25°C
3.0
0
VO , OUTPUT VOLTAGE
2.0
Vout = 5.0 V
RL = 500 Ω
(5.0 V/DIV)
1.0 TA = 25°C 0
0
–20 –10 0 10 20 30 40 50 60
t, TIME (50 ms/DIV)
Vin, INPUT VOLTAGE (V)

LM2931 Series
Figure 7. Bias Current versus Input Voltage Figure 8. Bias Current versus Output Current
12 8.0
Vout = 5.0 V
10 Vin = 14 V
TJ = 25°C
IB, BIAS CURRENT (mA)
I B, BIAS CURRENT (mA)

6.0 Vout = 5.0 V
8.0 TJ = 25°C
6.0 RL = 50 Ω 4.0
4.0
RL = 100 Ω 2.0
2.0
RL = 500 Ω
0 0
–20 –10 0 10 20 30 40 50 60 0 20 40 60 80 100
Vin, INPUT VOLTAGE (V) IO, OUTPUT CURRENT (mA)
Figure 9. Bias Current versus Junction Temperature Figure 10. Output Impedance versus Frequency
8.0 2.0
Vin = 14 V Vin = 14 V
IO = 100 mA IO , OUTPUT IMPEDANCE (Ω ) 1.6 IO = 10 mA
IB, BIAS CURRENT (mA)
6.0 DIO = 1.0 mA

CO = 100 µF
1.2 TJ = 25°C
4.0
0.8
CO(ESR) = 0.15 Ω
IO = 50 mA
CO(ESR) = 0.3 Ω Tantulum
2.0 Electrolytic
0.4
IO = 0 mA
0 0
–55 –25 0 25 50 75 100 125 10 100 1.0 k 10 k 100 k 1.0 M 10 M
95 95
RR, RIPPLE REJECTION RATIO (dB)
85
CO(ESR) = 0.15 Ω 85
Tantulum
Vin = 14 V
75 Vout = 5.0 V
DVin = 100 mV Vin = 14 V
RL = 500 Ω 75
Vout = 5.0 V
CO = 100 µF f = 120 Hz
65 TJ = 25°C
TJ = 25°C
CO(ESR) = 0.3 Ω
Electrolytic
55 65
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 20 40 60 80 100
f, FREQUENCY (Hz) IO, OUTPUT CURRENT (mA)

LM2931 Series
OUTPUT VOLTAGE DEVIATION,
OUTPUT CURRENT, OUTPUT VOLTAGE DEVIATION,

Figure 13. Line Regulation Figure 14. Load Regulation
∆ VO , (2.0 mV/DIV)
∆ VO , (2.0 mV/DIV)
Vin = 14 V
RL = 500 Ω Cin = 1000 µF
18.5 CO = 100 µF
CO(ESR) = 0.3 Ω 100 CO = 100 µF
TA = 25°C CO(ESR) = 0.3 Ω
INPUT VOLTAGE,
TA = 25°C
I out (mA)
V in, (V)
14 0
t, TIME (10 µs/DIV) t, TIME (10 µs/DIV)
Figure 16. Output Inhibit–Thresholds

Figure 15. Reference Voltage versus Output Voltage versus Output Voltage
V th(on/off), OUTPUT INHIBIT-THRESHOLDS (V)

1.240 2.6
LM2931C Adjustable LM2931C Adjustable
IO = 10 mA IO = 10 mA
2.5
Vin = Vout + 1.0 V Vin = Vout + 1.0 V
1.220 Output “Off”
TA = 25°C TA = 25°C
2.4
1.200 2.3
2.2
1.180
2.1 Output “On”
1.160 2.0
0 3.0 6.0 9.0 12 15 18 21 24 0 3.0 6.0 9.0 12 15 18 21 24
VO, OUTPUT VOLTAGE (V) VO, OUTPUT VOLTAGE (V)
The LM2931 series regulators are designed with many With economical electrolytic capacitors, cold temperature
protection features making them essentially blow–out proof. operation can pose a serious stability problem. As the
These features include internal current limiting, thermal electrolyte freezes, around – 30°C, the capacitance will
shutdown, overvoltage and reverse polarity input protection, decrease and the equivalent series resistance (ESR) will
and the capability to withstand temporary power–up with increase drastically, causing the circuit to oscillate. Quality
mirror–image insertion. Typical application circuits for the electrolytic capacitors with extended temperature ranges of
fixed and adjustable output device are shown in Figures 17 – 40° to +85°C and – 55° to +105°C are readily available.
and 18. Solid tantalum capacitors may be a better choice if small size
The input bypass capacitor Cin is recommended if the is a requirement, however, the maximum ZO limit over
regulator is located an appreciable distance (≥ 4″) from the temperature must be observed.
supply input filter. This will reduce the circuit’s sensitivity to Note that in the stable region, the output noise voltage is
the input line impedance at high frequencies. linearly proportional to ZO. In effect, CO dictates the high
This regulator series is not internally compensated and frequency roll–off point of the circuit. Operation in the area
thus requires an external output capacitor for stability. The titled “Marginally Stable” will cause the output of the regulator
capacitance value required is dependent upon the load to exhibit random bursts of oscillation that decay in an
current, output voltage for the adjustable regulator, and the under–damped fashion. Continuous oscillation occurs when
type of capacitor selected. The least stable condition is operating in the area titled “Unstable”. It is suggested that
encountered at maximum load current and minimum output oven testing of the entire circuit be performed with maximum
voltage. Figure 22 shows that for operation in the “Stable” load, minimum input voltage, and minimum ambient
region, under the conditions specified, the magnitude of the temperature.
output capacitor impedance |ZO| must not exceed 0.4 Ω. This
limit must be observed over the entire operating temperature
range of the regulator circuit.

LM2931 Series
Figure 17. Fixed Output Regulator Figure 18. Adjustable Output Regulator
Input Output
Input LM2931–5.0 Output Vin Vout
Vin Fixed Vout LM2931C
Output 51 k R1
Output Adjustable
2 Inhibit Output Adjust
Cin Cin
Gnd CO CO
0.1 IB 0.1
1 IAdj
Gnd R2
IB
ǒ Ǔ
Switch Position 1 = Output “On”, 2 = Output “Off”
V out + Vref 1 ) RR2 ) IAdj R2 22.5 k w R R1)R2R

1 1 2
Figure 19. (5.0 A) Low Differential Figure 20. Current Boost Regulator with
Voltage Regulator Short Circuit Projection
D45VH7 RSC
Input Input
≥ 6.0 V
68 R R
5.0 V @ 5.0 A Output
LM2931–5.0 LM2931–5.0
+ + Output
100 100 + +
100 100
The LM2931 series can be current boosted with a PNP transistor. The The circuit of Figure 19 can be modified to provide supply protection against
D45VH7, on a heatsink, will provide an output current of 5.0 A with an input short circuits by adding the current sense resistor RSC and an additional PNP
to output voltage differential of approximately 1.0 V. Resistor R in transistor. The current sensing PNP must be capable of handling the short
conjunction with the VBE of the PNP determines when the pass transistor circuit current of the LM2931. Safe operating area of both transistors must be
begins conducting. This circuit is not short circuit proof. considered under worst case conditions.
Figure 22. Output Noise Voltage versus

Figure 21. Constant Intensity Lamp Flasher Output Capacitor Impedance
100
Vn , OUTPUT NOISE VOLTAGE (mVrms)
Input Vin = 5.6 V

6.4 V to 30 V Vout = 5.0 V
LM2931C 2.0 k +
IO = 100 mA Unstable
100 10 Vnrms 10 Hz to 10 MHz
|ZO| @ 40 kHz
TA = 25°C Marginally
8.2 k Stable
CM 1.0
#345
+ 33 k 0.1
100 6.2 V Stable
0
fosc = 2.2 Hz 0.01
10 100 1.0 k 10 k
|ZO|, MAGNITUDE OF CAPACITOR IMPEDANCE (mΩ)

LM2931 Series
Figure 23. SOP–8 Thermal Resistance and Maximum

170 3.2

150 2.8

130 2.4
110
ÎÎÎ ÎÎÎ
Graph represents symmetrical layout
ÎÎÎ
2.0
90
ÎÎÎ ÎÎÎ 2.0 oz. 1.6
ÎÎÎ ÎÎÎ
L
Copper
70 1.2
L 3.0 mm
50 0.8
RθJA
30 0.4
0 10 20 30 40 50

100 2.4

Free Air
90 Mounted 2.0
Vertically
2.0 oz. Copper
ÎÎÎ
80 L 1.6
ÎÎÎ
Minimum
70 Size Pad 1.2
ÎÎÎ
L
60 0.8
50 0.4
RθJA
40 0
0 5.0 10 15 20 25 30
Figure 25. 3–Pin and 5–Pin D2PAK

Thermal Resistance and Maximum Power
Dissipation versus P.C.B. Copper Length
80 3.5

70 Free Air 3.0

Mounted
ÎÎÎÎ
60 2.5
ÎÎÎÎ
L
ÎÎÎÎ
50 Minimum 2.0
Size Pad
ÎÎÎÎ
L
40 1.5
RθJA
30 1.0
0 5.0 10 15 20 25 30

LM2931 Series
DEFINITIONS
Dropout Voltage – The input/output voltage differential at Maximum Power Dissipation – The maximum total
which the regulator output no longer maintains regulation device dissipation for which the regulator will operate within
against further reductions in input voltage. Measured when specifications.
the output decreases 100 mV from nominal value at 14 V Bias Current – That part of the input current that is not
input, dropout voltage is affected by junction temperature and delivered to the load.
load current. Output Noise Voltage – The rms AC voltage at the
Line Regulation – The change in output voltage for a output, with constant load and no input ripple, measured over
change in the input voltage. The measurement is made under a specified frequency range.
conditions of low dissipation or by using pulse techniques Long–Term Stabliity – Output voltage stability under
such that the average chip temperature is not significantly accelerated life test conditions with the maximum rated
affected. voltage listed in the devices electrical characteristics and
Load Regulation – The change in output voltage for a maximum power dissipation.

LM2935
Low Dropout
Dual Voltage Regulator
The LM2935 is a dual positive 5.0 V low dropout voltage regulator,
designed for standby power systems. The main output is capable of LOW DROPOUT
supplying 750 mA for microprocessor power, and can be turned “on” and DUAL VOLTAGE REGULATOR
“off” by the switch/reset input. The other output is dedicated for standby
operation of volatile memory, and is capable of supplying up to 10 mA loads.
The total device features a low quiescent current of 3.0 mA or less when SEMICONDUCTOR
supplying 10 mA from the standby output. TECHNICAL DATA
This part was designed for harsh automotive environments and is
therefore immune to many input supply voltage problems such as reverse
battery (–12 V), double battery (+24 V), and load dump transients (+60 V).
• Two Regulated 5.0 V Outputs
• Main Output Current in Excess of 750 mA
TH SUFFIX
• On/Off Control of Main Output PLASTIC PACKAGE
• Standby Output Current in Excess of 10 mA CASE 314A
• Low Input/Output Differential of Less than 0.6 V at 500 mA

1
• Short Circuit Current Limiting 5

• Low Voltage Indicator Output
• Designed for Automotive Environment Including TV SUFFIX
• Reverse Battery Protection 1 PLASTIC PACKAGE
• Double Battery Protection CASE 314B
5
• Load Dump Protection
• Reverse Transient Protection
• Economical 5–Lead TO–220 Package with Two Optional Leadforms Heatsink surface connected to Pin 3.
• Also Available in Surface Mount D2PAK Package
T SUFFIX
PLASTIC PACKAGE
CASE 314D
1
5
Pin 1. Input Voltage/VCC

2. Main Output
ORDERING INFORMATION 3. Ground
4. Switch/Reset
Operating 5. Standby/Output
LM2935D2T Surface Mount
LM2935T Plastic Power D2T SUFFIX
TJ = –40° to +125°C PLASTIC PACKAGE
LM2935TH Horizontal Mount
CASE 936A
LM2935TV Vertical Mount 1
(D2PAK)
5
Heatsink surface (shown as terminal 6

in case outline drawing) is connected to Pin 3.

LM2935
Typical Application Circuit
Main
Input Output
Vin 1 2 5.0 V/750 mA
+
S1* 0.1 10
*The main output LM2935

is “Off” with switch 20 k
S1 open. Standby
4 5 5.0 V/10 mA
Switch/ 3 +
Reset 10
Gnd
An input bypass capacitor is recommended if the regulator is located more than 4″ from the supply
input filter. The LM2935 is not internally compensated and thus requires an external output capacitor
for stability. A minimum capacitance of 10 µF is recommended. The actual capacitance value is
dependent upon load current, temperature, and the capacitor’s equivalent series resistance (ESR).
The least stable condition is encountered at maximum load current and minimum ambient
temperature.
MAXIMUM RATINGS
Input Voltage Continuous VI 60 Vdc
Transient Reverse Polarity Input Voltage –VI(τ) – 50 Vpk
1.0% Duty Cycle, τ ≤ 100 ms
Switch/Reset Input Current Iin 5.0 mA

Power Dissipation
Case 314A, 314B and 314D (TO–220 Type)
Case 936A (D2PAK)
Thermal Resistance, Junction–to–Ambient RθJA Per Figure 1 °C/W
ELECTRICAL CHARACTERISTICS (Vin = 14 V, IO = 500 mA, Istby = 0 mA, CO = 10 µF, Cstby = 10 µF, TJ = 25°C [Note 1].)
MAIN OUTPUT
Output Voltage (Vin = 6.0 V to 26 V, IO = 5.0 mA to 500 mA, TJ = – 40 to +125°C) VO 4.75 5.0 5.25 V
Vin = 9.0 V to 16 V, IO = 5.0 mA – 4.0 25
Vin = 6.0 V to 26 V, IO = 5.0 mA – 10 50
Load Regulation (IO = 5.0 mA to 500 mA) Regload – 10 50 mV
Output Impedance ZO mΩ
IO = 500 mAdc and 10 mArms, f = 100 Hz to 10 kHz – 200 –
Output Noise Voltage (f = 10 Hz to 100 kHz) Vn – 100 – µVrms

Long Term Stability S – 20 – mV/kHR

LM2935
MAIN OUTPUT (continued)

Ripple Rejection (f = 120 Hz) RR – 66 – dB
IO = 500 mA – 0.45 0.6
IO = 750 mA – 0.82 –
Short Circuit Current Limit ISC 0.75 1.2 – A
Over–Voltage Shutdown Threshold Vth(OV) 26 31 – V
SWITCH/RESET
Output Sink Current (VOL = 1.2 V) ISink – 5.0 – mA
Output Voltage (Ron/off = 20 kΩ) V
Low State, Vin = 4.0 V VOL – 0.9 1.2
High State, Vin = 14 V VOH 4.5 5.0 6.0
Output Pull–Up Resistor, “On”/“Off” (Note 2) Ron/off – 20 30 kΩ
Output Voltage with Reverse Polarity Input (Vin = –15 V, RL = 10 Ω) –VO – 0.6 0 – V
STANDBY OUTPUT
Output Voltage (Vin = 6.0 V to 26 V, Istby = 1.0 mA to 10 mA, TJ = –40 to +125°C) VO(stby) 4.75 5.0 5.25 V
Tracking Voltage VO–VO(stby) – 200 0 200 mV
Line Regulation (Vin = 6.0 V to 26 V) Regline – 4.0 50 mV
Load Regulation (Istby = 1.0 mA to 10 mA) Regload – 10 50 mV
Output Impedance ZO(stby) Ω
I(stby) = 10 mAdc and 1.0 mArms, f = 100 Hz to 10 kHz – 1.0 –
Output Noise Voltage (f = 10 Hz to 100 kHz) Vn – 300 – µVrms

Long Term Stability S – 20 – mV/kHR
Ripple Rejection (f = 120 Hz) RR – 66 – dB
Dropout Voltage (Istby = 10 mA) VI–VO(stby) – 0.55 0.7 V
Short Circuit Current Limit ISC 25 70 – mA
Output Voltage with Reverse Polarity Input –VO V
Vin = –15 V, RL = 510 Ω – 0.3 0 –
Output Voltage with Maximum Positive Input VO(max) V

Vin = 60 V, RL = 510 Ω – 5.0 6.0
TOTAL DEVICE
Bias Current IB mA
IO = 10 mA, Istby = 0 mA – 3.0 –
IO = 500 mA, Istby = 0 mA – 40 100
IO = 750 mA, Istby = 0 mA – 90 –
Main Output “Off”, Istby = 10 mA – 2.0 3.0
NOTES: 1. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
2. The maximum switch/reset current must not exceed 5.0 mA.

LM2935
TYPICAL CIRCUIT WAVEFORMS
60 V
26 V
Vin, Input Voltage 14 V 14 V 14 V
(Pin 1) 3.0 V
9.0 V
Open
S1, “On”/“Off” Switch Closed Open
5.0 V 5.0 V 5.0 V 5.0 V 5.0 V
VO, Main Output Voltage 2.4 V 0V
(Pin 2)
5.0 V
0V
Reset (Pin 4)
Vstby, Standby Voltage 5.0 V 5.0 V
(Pin 5) Main 2.4 V Main Main
Output Low Input Output Output
Turn “On” Voltage Short Turn “Off”
Input
Circuit
Load Voltage Thermal
Dump Line Noise Shutdown

80 3.5

70 Free Air 3.0

JUNCTION–TO–AIR ( °C/W)
Mounted
ÎÎÎÎ
60 2.5
L
ÎÎÎÎ
ÎÎÎÎ
50 Minimum 2.0
Size Pad L
40
RθJA ÎÎÎÎ 1.5
30 1.0
0 5.0 10 15 20 25 30

LP2950
LP2951
Micropower Voltage Regulators MICROPOWER

The LP2950 and LP2951 are micropower voltage regulators that are LOW DROPOUT
specifically designed to maintain proper regulation with an extremely low VOLTAGE REGULATORS
input–to–output voltage differential. These devices feature a very low
quiescent bias current of 75 µA and are capable of supplying output currents
in excess of 100 mA. Internal current and thermal limiting protection is
provided.
The LP2951 has three additional features. The first is the Error Output Z SUFFIX
that can be used to signal external circuitry of an out of regulation condition, PLASTIC PACKAGE
CASE 29
or as a microprocessor power–on reset. The second feature allows the
(TO–226AA/TO–92)
output voltage to be preset to 5.0 V, 3.3 V or 3.0 V output (depending on the Pin: 1. Output
1
version) or programmed from 1.25 V to 29 V. It consists of a pinned out 2
2. Ground
3
resistor divider along with direct access to the Error Amplifier feedback input. 3. Input
The third feature is a Shutdown input that allows a logic level signal to
turn–off or turn–on the regulator output.
DT SUFFIX
Due to the low input–to–output voltage differential and bias current PLASTIC PACKAGE
1
specifications, these devices are ideally suited for battery powered CASE 369A
(DPAK) 3
computer, consumer, and industrial equipment where an extension of
useful battery life is desirable. The LP2950 is available in the three pin case
29 and DPAK packages, and the LP2951 is available in the eight pin
dual–in–line, SO–8 and Micro–8 surface mount packages. The ‘A’ suffix
Pin: 1. Input
devices feature an initial output voltage tolerance ± 0.5%. 2. Ground
1 2 3
3. Output
LP2950 and LP2951 Features:
• Low Quiescent Bias Current of 75 µA (Top View)
• Low Input–to–Output Voltage Differential of 50 mV at 100 µA and Heatsink surface (shown as terminal 4 in
380 mV at 100 mA case outline drawing) is connected to Pin 2.
• 5.0 V, 3.3 V or 3.0 V ± 0.5% Allows Use as a Regulator or Reference

• Extremely Tight Line and Load Regulation D SUFFIX
PLASTIC PACKAGE 8
• Requires Only a 1.0 µF Output Capacitor for Stability CASE 751 1
(SO–8)
• Internal Current and Thermal Limiting
LP2951 Additional Features: N SUFFIX

• Error Output Signals an Out of Regulation Condition PLASTIC PACKAGE
CASE 626 8
• Output Programmable from 1.25 V to 29 V 1
• Logic Level Shutdown Input

DM SUFFIX
PLASTIC PACKAGE 8
CASE 846A 1
(Micro–8)
Output 1 8 Input
Sense 2 7 Feedback
Shutdown 3 6 VO Tap
Gnd 4 5 Error Output
(See Following Page for Ordering Information.) (Top View)

LP2950 LP2951
Operating
Device Type Temperature Range Package
LP2950CZ–**
TO–92/TO–226AA
LP2950ACZ–** Fixed Voltageg
LP2950CDT–**
LP2950CDT– (3.0, 3.3 or 5.0 V)
DPAK
LP2950ACDT–**
LP2950ACDT **
LP2951CD Adjustable or
LP2951ACD 5.0 V Fixed
SO 8
SO–8
LP2951CD–**
LP2951CD– Adjustable or Fixed
LP2951ACD–**
LP2951ACD ** (3.0,
(3 0 33.3
3 V)
40° to +125°C
TJ = –40°
LP2951CN Adjustable or
LP2951ACN 5.0 V Fixed
Plastic
LP2951CN–**
LP2951CN– Adjustable or Fixed
LP2951ACN–**
LP2951ACN ** (3.0,
(3 0 33.3
3 V)
LP2951CDM Adjustable or
LP2951ACDM 5.0 V Fixed
Micro 8
Micro–8
LP2951CDM–**
LP2951CDM– Adjustable or Fixed
LP2951ACDM–**
LP2951ACDM ** (3.0,
(3 0 33.3
3 V)
** = Voltage option of 3.0, 3.3 or 5.0 V.

Device No. (±1%) Device No. (±0.5%) Nominal Voltage
LP2950CX–5.0 LP2950ACX–5.0 5.0
LP2950CX–3.3 LP2950ACX–3.3 3.3
LP2950CX–3.0 LP2950ACX–3.0 3.0
LP2951CX LP2951ACX Adjustable or 5.0
LP2950CX–3.3 LP2951ACX–3.3 Adjustable or 3.3
LP2951CX–3.0 LP2951ACX–3.0 Adjustable or 3.0
X = Package suffix.
Representative Block Diagrams
Input Output
5.0 V/100 mA
3 1
Battery or 1.0 µF
182 k
Unregulated DC
Error Amplifier 60 k
1.23 V
Reference
LP2950CZ–5.0
Gnd 2
5.0 V/100 mA
Input 8 Output 1 Sense 2
Battery or 1.0 µF
Unregulated DC
182 k
VO Tap
6
60 k
7 330 k
Error Feedback
Amplifier
Shutdown
From 3 60 k 75 mV/
CMOS/TTL 50 k Error
60 mV
Output
To CMOS/TTL
5
1.23 V Error Detection
Reference Comparator
LP2951CD or CN
Gnd 4

LP2950 LP2951
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ
Input Voltage
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Rating Symbol
VCC
Value
30
Unit
Vdc
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Maximum Power Dissipation
Case 751(SO–8) D Suffix
PD Internally Limited W

Case 369A (DPAK) DT Suffix [Note 1]
Case 29 (TO–226AA/TO–92) Z Suffix
Case 626 N Suffix
Case 846A (Micro–8) DM Suffix
ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Thermal Resistance, Junction–to–Ambient
ÁÁÁÁÁ
ÁÁÁ
Feedback Input Voltage
RθJA
Vfb
240
–1.5 to +30
°C/W
Vdc
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Shutdown Input Voltage Vsd –0.3 to +30 Vdc
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Error Comparator Output Voltage Verr –0.3 to +30 Vdc
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Operating Junction Temperature TJ –40 to +125 °C
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
NOTE: 1. The Junction–to–Ambient Thermal Resistance is determined by PC board copper area
per Figure 26.
ELECTRICAL CHARACTERISTICS (Vin = VO + 1.0 V, IO = 100 µA, CO = 1.0 µF, TJ = 25°C [Note 1], unless otherwise
noted.)
Output Voltage, 5.0 V Versions VO V
Vin = 6.0 V, IO = 100 µA, TJ = 25°C
LP2950C–5.0/LP2951C 4.950 5.000 5.050
LP2950AC–5.0/LP2951AC 4.975 5.000 5.025
TJ = – 40 to +125°C
LP2950C–5.0/LP2951C 4.900 – 5.100
LP2950AC–5.0/LP2951AC 4.940 – 5.060
Vin = 6.0 to 30 V, IO = 100 µA to 100 mA, TJ = – 40 to +125°C
LP2950C–5.0/LP2951C 4.880 – 5.120
LP2950AC–5.0/LP2951AC 4.925 – 5.075
Vin = 4.3 V, IO = 100 µA, TJ = 25°C
LP2950C–3.3/LP2951C–3.3 3.267 3.300 3.333
LP2950AC–3.3/LP2951AC–3.3 3.284 3.300 3.317
TJ = – 40 to +125°C
LP2950C–3.3/LP2951C–3.3 3.234 – 3.366
LP2950AC–3.3/LP2951AC–3.3 3.260 – 3.340
LP2950C–3.3/LP2951C–3.3 3.221 – 3.379
LP2950AC–3.3/LP2951AC–3.3 3.254 – 3.346
Vin = 4.0 V, IO = 100 µA, TJ = 25°C
LP2950C–3.0/LP2951C–3.0 2.970 3.000 3.030
LP2950AC–3.0/LP2951AC–3.0 2.985 3.000 3.015
TJ = – 40 to +125°C
LP2950C–3.0/LP2951C–3.0 2.940 – 3.060
LP2950AC–3.0/LP2951AC–3.0 2.964 – 3.036
LP2950C–3.0/LP2951C–3.0 2.928 – 3.072
LP2950AC–3.0/LP2951AC–3.0 2.958 – 3.042

LP2950 LP2951
ELECTRICAL CHARACTERISTICS (continued) (Vin = VO + 1.0 V, IO = 100 µA, CO = 1.0 µF, TJ = 25°C [Note 1], unless otherwise
noted.)
Line Regulation (Vin = VO(nom) +1.0 V to 30 V) [Note 2] Regline %
LP2950C–XX/LP2951C/LP2951C–XX – 0.08 0.20
LP2950AC–XX/LP2951AC/LP2951AC–XX – 0.04 0.10
Load Regulation (IO = 100 µA to 100 mA) Regload %
LP2950C–XX/LP2951C/LP2951C–XX – 0.13 0.20
LP2950AC–XX/LP2951AC/LP2951AC–XX – 0.05 0.10
Dropout Voltage VI – VO mV
IO = 100 µA – 30 80
IO = 100 mA – 350 450
Supply Bias Current ICC
IO = 100 µA – 93 120 µA
IO = 100 mA – 4.0 12 mA
Dropout Supply Bias Current (Vin = VO(nom) – 0.5 V, ICCdropout – 110 170 µA
IO = 100 µA) [Note 2]
Current Limit (VO Shorted to Ground) ILimit – 220 300 mA
Thermal Regulation Regthermal – 0.05 0.20 %/W
Output Noise Voltage (10 Hz to 100 kHz) [Note 3] Vn µVrms
CL = 1.0 µF – 126 –
CL = 100 µF – 56 –
LP2951A/LP2951AC ONLY
Reference Voltage (TJ = 25°C) Vref V
LP2951C/LP2951C–XX 1.210 1.235 1.260
LP2951AC/LP2951AC–XX 1.220 1.235 1.250
Reference Voltage (TJ = – 40 to +125°C) Vref V
LP2951C/LP2951C–XX 1.200 – 1.270
LP2951AC/LP2951AC–XX 1.200 – 1.260
Reference Voltage (TJ = – 40 to +125°C) Vref V
IO = 100 µA to 100 mA, Vin = 23 to 30 V
LP2951C/LP2951C–XX 1.185 – 1.285
LP2951AC/LP2951AC–XX 1.190 – 1.270
Feedback Pin Bias Current IFB – 15 40 nA
ERROR COMPARATOR
Output Leakage Current (VOH = 30 V) Ilkg – 0.01 1.0 µA
Output Low Voltage (Vin = 4.5 V, IOL = 400 µA) VOL – 150 250 mV
Upper Threshold Voltage (Vin = 6.0 V) Vthu 40 45 – mV
Lower Threshold Voltage (Vin = 6.0 V) Vthl – 60 95 mV
Hysteresis (Vin = 6.0 V) Vhy – 15 – mV
SHUTDOWN INPUT
Input Logic Voltage Vshtdn V
Logic “0” (Regulator “On”) 0 – 0.7
Logic “1” (Regulator “Off”) 2.0 – 30
Shutdown Pin Input Current Ishtdn µA
Vshtdn = 2.4 V – 35 50
Vshtdn = 30 V – 450 600
Regulator Output Current in Shutdown Mode Ioff – 3.0 10 µA
(Vin = 30 V, Vshtdn = 2.0 V, VO = 0, Pin 6 Connected to Pin 7)
NOTES: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
2. VO(nom) is the part number voltage option.
3. Noise tests on the LP2951 are made with a 0.01 µF capacitor connected across Pins 7 and 1.

LP2950 LP2951
DEFINITIONS
Dropout Voltage – The input/output voltage differential at Output Noise Voltage – The rms ac voltage at the output,
which the regulator output no longer maintains regulation with constant load and no input ripple, measured over a
against further reductions in input voltage. Measured when specified frequency range.
the output drops 100 mV below its nominal value (which is Leakage Current – Current drawn through a bipolar
measured at 1.0 V differential), dropout voltage is affected by transistor collector–base junction, under a specified collector
junction temperature, load current and minimum input supply voltage, when the transistor is “off”.
requirements. Upper Threshold Voltage – Voltage applied to the
Line Regulation – The change in output voltage for a comparator input terminal, below the reference voltage
change in input voltage. The measurement is made under which is applied to the other comparator input terminal,
conditions of low dissipation or by using pulse techniques which causes the comparator output to change state from a
such that average chip temperature is not significantly logic “0” to “1”.
affected. Lower Threshold Voltage – Voltage applied to the
Load Regulation – The change in output voltage for a comparator input terminal, below the reference voltage
change in load current at constant chip temperature. which is applied to the other comparator input terminal,
Maximum Power Dissipation – The maximum total which causes the comparator output to change state from a
device dissipation for which the regulator will operate within logic “1” to “0”.
specifications. Hysteresis – The difference between Lower Threshold
Bias Current – Current which is used to operate the voltage and Upper Threshold voltage.
regulator chip and is not delivered to the load.
Figure 1. Quiescent Current Figure 2. Dropout Characteristics

10 6.0
LP2950/LP2951 BIAS CURRENT (mA)
LP2951C
5.0 TA = 25°C
Vout , OUTPUT VOLTAGE (V) RL = 50 k
1.0 4.0
3.0
RL = 50 Ω
0.1 2.0
1.0
0.01 0
0.1 1.0 10 100 0 1.0 2.0 3.0 4.0 5.0 6.0
IL, LOAD CURRENT (mA) Vin, INPUT VOLTAGE (V)
Figure 3. Input Current Figure 4. Output Voltage versus Temperature

250 5.00
200 4.99
Vout , OUTPUT VOLTAGE (V)
0.1 mA Load Current

BIAS CURRENT (µ A)
150 4.98
100 4.97
No Load
50 4.96
LP2951C
0 4.95
0 5.0 10 15 20 25 – 50 0 50 100 150
Vin, INPUT VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

LP2950 LP2951

Output Current Figure 6. Dropout Voltage versus Temperature
400 550 55
350
DROPOUT VOLTAGE (mV) R L= 50 k

DROPOUT VOLTAGE (mV) R L= 50
TA = 25°C 500 50
DROPOUT VOLTAGE (mV)
300
250 450 45
RL = 50
200
150 400 40
100
350 35
50 RL = 50 k
0 300 30
0.1 1.0 10 100 – 50 0 50 100 150
IO, OUTPUT CURRENT (mA) T, TEMPERATURE (°C)
Figure 7. Error Comparator Output Figure 8. Line Transient Response

5.0 8.0 4.0
LP2951C Vin
OUTPUT VOLTAGE CHANGE (mV)

RL = 330 k
Vout , OUTPUT VOLTAGE (V)
4.0 TA = 25°C 7.5 2.0

Vin , INPUT VOLTAGE (V)
Vin Decreasing
3.0 7.0 0
Vout
Vin Increasing
2.0 6.5 – 2.0
TA = 25°C
1.0 6.0 CL = 1.0 µF – 4.0
IL = 1.0 mA
VO = 5.0 V
0 5.5 – 6.0
4.70 4.74 4.78 4.82 4.86 4.90 0 100 200 300 400 500 600 700 800
Vin, INPUT VOLTAGE (V) t, TIME (µs)
Figure 9. LP2951 Enable Transient Figure 10. Load Transient Response

7.0 200
SHUTDOWN AND OUTPUT VOLTAGE (V)
CL = 1.0 µF CL = 1.0 µF

6.0 400
Vout = 5.0 V
150 TA = 25°C
5.0
LOAD CURRENT (mA)
200
Vout
4.0 100
CL = 10 µF
3.0 0
TA = 25°C 50
2.0 IL = 10 mA
Vin = 8.0 V – 200
1.0 ILoad
Shutdown Input Vout = 5.0 V 0
0
– 400
–1.0 – 50
–100 0 100 200 300 400 0 50 100 150 200 250 300 350 400
t, TIME (µs) t, TIME (ms)

LP2950 LP2951
Figure 11. Ripple Rejection Figure 12. Output Noise

80 4.0
IL= 100 mA
TA = 25°C
CL = 1.0 µF VO = 5.0 V
VOLTAGE NOISE (µ V/√ Hz)

RIPPLE REJECTION (dB)
60 3.0 LP2951C
IL= 0.1 mA
40 2.0
TA = 25°C
20 1.0 CL = 100 µF
CL = 1.0 µF
Vin = 6.0 V
Vout = 5.0 V
0 0
1.0 10 100 1.0 k 10 k 100 k 100 1.0 k 10 k 100 k
Figure 13. Shutdown Threshold Voltage Figure 14. Maximum Rated

versus Temperature Output Current
1.8 100 4.0
SHUTDOWN THRESHOLD VOLTAGE (V)

TA = 25°C
Vout , OUTPUT CURRENT (mA)
1.6 80 2.0
TA = 75°C
1.4 60 0
Output “Off”
1.2 40 – 2.0
Output “On”
1.0 20 – 4.0
LP2951CN
0.8 0 – 6.0
– 40 – 20 0 20 40 60 80 100 120 140 160 0 5.0 10 15 20 25 30 35 40
t, TEMPERATURE (°C) Vin, INPUT VOLTAGE (V)

LP2950 LP2951
Introduction
The LP2950/LP2951 regulators are designed with When operated in the shutdown mode, the error
internal current limiting and thermal shutdown making them comparator output will go high if it has been pulled up to an
user–friendly. Typical application circuits for the LP2950 and external supply. To avoid this invalid response, the error
LP2951 are shown in Figures 17 through 25. comparator output should be pulled up to Vout (see
These regulators are not internally compensated and thus Figure 15).
require a 1.0 µF (or greater) capacitance between the
LP2950/LP2951 output terminal and ground for stability. Figure 15. ERROR Output Timing
Most types of aluminum, tantalum or multilayer ceramic will
5.0 V
perform adequately. Solid tantalums or appropriate
4.75 V 4.70 V
multilayer ceramic capacitors are recommended for Output
operation below 25°C. Voltage
At lower values of output current, less output capacitance
is required for output stability. The capacitor can be reduced
Pull–Up
to 0.33 µF for currents less than 10 mA, or 0.1 µF for currents to Ext
below 1.0 mA. Using the 8–pin versions at voltages less than Not
ERROR Not Valid
5.0 V operates the error amplifier at lower values of gain, so Valid Pull–Up
that more output capacitance is needed for stability. For the to Vout
worst case operating condition of a 100 mA load at 1.23 V
output (Output Pin 1 connected to the feedback Pin 7) a 4.75 V + Vdropout 4.70 V + Vdropout
minimum capacitance of 3.3 µF is recommended.
The LP2950 will remain stable and in regulation when
Input
operated with no output load. When setting the output voltage Voltage 1.3 V
1.3 V
of the LP2951 with external resistors, the resistance values
should be chosen to draw a minimum of 1.0 µA.
A bypass capacitor is recommended across the Programming the Output Voltage (LP2951)
LP2950/LP2951 input to ground if more than 4 inches of The LP2951CX may be pin–strapped for 5.0 V using its
wire connects the input to either a battery or power supply internal voltage divider by tying Pin 1 (output) to Pin 2 (sense)
filter capacitor. and Pin 7 (feedback) to Pin 6 (5.0 V tap). Alternatively, it may
Input capacitance at the LP2951 Feedback Pin 7 can be programmed for any output voltage between its 1.235
create a pole, causing instability if high value external reference voltage and its 30 V maximum rating. An external
resistors are used to set the output voltage. Adding a 100 pF pair of resistors is required, as shown in Figure 16.
capacitor between the Output Pin 1 and the Feedback Pin 7
and increasing the output filter capacitor to at least 3.3 µF will Figure 16. Adjustable Regulator
stabilize the feedback loop. Vin
Error Detection Comparator
The comparator switches to a positive logic low whenever
the LP2951 output voltage falls more than approximately 100 k 8
5.0% out of regulation. This value is the comparator’s Vin
designed–in offset voltage of 60 mV divided by the 1.235 V Error 5 1
Error Vout
internal reference. As shown in the representative block Output Vout
diagram. This trip level remains 5.0% below normal 2 1.23 to 30 V
SNS NC
regardless of the value of regulated output voltage. For R1
example, the error flag trip level is 4.75 V for a normal 5.0 V Shutdown 3 6 NC 0.01 µF
Input SD VO T 3.3 µF
regulated output, or 9.50 V for a 10 V output voltage.
Figure 1 is a timing diagram which shows the ERROR Gnd FB
signal and the regulated output voltage as the input voltage to 4 7
the LP2951 is ramped up and down. The ERROR signal
becomes valid (low) at about 1.3 V input. It goes high when R2
the input reaches about 5.0 V (Vout exceeds about 4.75 V).
Since the LP2951’s dropout voltage is dependent upon the
load current (refer to the curve in the Typical Performance The complete equation for the output voltage is:
Characteristics), the input voltage trip point will vary with load
current. The output voltage trip point does not vary with load.
V out + Vref (1 ) R1ńR2) ) IFB R1
The error comparator output is an open collector which where Vref is the nominal 1.235 V reference voltage and IFB
requires an external pull–up resistor. This resistor may be is the feedback pin bias current, nominally – 20 nA. The
returned to the output or some other voltage within the minimum recommended load current of 1.0 µA forces an
system. The resistance value should be chosen to be upper limit of 1.2 MΩ on the value of R2, if the regulator must
consistent with the 400 µA sink capability of the error work with no load. IFB will produce a 2% typical error in Vout
comparator. A value between 100 k and 1.0 MΩ is suggested. which may be eliminated at room temperature by adjusting
No pull–up resistance is required if this output is unused. R1. For better accuracy, choosing R2 = 100 k reduces this

LP2950 LP2951
error to 0.17% while increasing the resistor program current
to 12 µA. Since the LP2951 typically draws 75 µA at no load Figure 17. 1.0 A Regulator with 1.2 V Dropout
with Pin 2 open circuited, the extra 12 µA of current drawn is
Unregulated
often a worthwhile tradeoff for eliminating the need to set
Input
output voltage in test. MTB23P06E
1.0 µF 10 k 0.01 µF
Output Noise
In many applications it is desirable to reduce the noise
Vout
present at the output. Reducing the regulator bandwidth by 5.0 V ±1.0%
increasing the size of the output capacitor is the only method 8 0 to 1.0 A
for reducing noise on the 3 lead LP2950. However, Vin
Error 5 Error 1
Vout
increasing the capacitor from 1.0 µF to 220 µF only Output
decreases the noise from 430 µV to 160 µVrms for a 100 kHz 2
SNS
bandwidth at the 5.0 V output. LP2951CN
Noise can be reduced fourfold by a bypass capacitor Shutdown 3 6
SD VO T 220 µF
across R1, since it reduces the high frequency gain from 4 to Input
unity. Pick Gnd FB
C
Bypass
[ 1
2pR1 x 200 Hz
4 7
0.002 µF
or about 0.01 µF. When doing this, the output capacitor 1.0 M
must be increased to 3.3 µF to maintain stability. These 2.0 k
changes reduce the output noise from 430 µV to 126 µVrms
for a 100 kHz bandwidth at 5.0 V output. With bypass
capacitor added, noise no longer scales with output voltage
so that improvements are more dramatic at higher output
voltages.

LP2950 LP2951
TYPICAL APPLICATIONS
Figure 18. Lithium Ion Battery Cell Charger Figure 19. Low Drift Current Sink
+V = 2.0 to 30 V
Unregulated Input
6.0 to 10 Vdc
IL
Load IL = 1.23/R
8
Vin
1 1N4001 4.2 V ± 0.025 V
5 Error Vout
NC
8 0.1 µF
2 2.0 M
SNS NC 330 pF Vin
1.0% Error 5 1
0.1 µF LP2951CN Error Vout
3 6 Output
SD VO T NC
2
806 k SNS
Gnd FB 2.2 µF Lithium Ion LP2951CN
1.0%
4 7 Rechargeable Shutdown 3 6
Cell SD VO T
Input
50 k Gnd FB
4 7
Gnd
R 1.0 µF
Figure 20. Latch Off When Error Flag Occurs Figure 21. 5.0 V Regulator with 2.5 V Sleep Function
+Vin +Vin CMOS

*Sleep Gate
Input
470 k 8
Vin 47 k 8 470 k
5 1
2N3906 Error Vout Vout Vin Vout
1 2N3906
470 k Error 5 Vout
2 Output Error
SNS NC
Reset LP2951CN 2
SNS NC 200 k
3 6 R1 LP2951CN
SD VO T NC
Normally
Shutdown 3
SD VO T
6 NC 3.3 µF
Gnd FB Input
Closed 1.0 µF 100 k 100 pF
4 7 Gnd FB
4 7
R2
100 k
Error flag occurs when Vin is too low to
maintain Vout, or if Vout is reduced by
excessive load current.

LP2950 LP2951
Figure 22. Regulator with Early Warning and Auxiliary Output

+Vin
8
Vin D2
5 1 Memory
Error Vout
V+
D1
2 1.0 µF 20
SNS
LP2951CN 3.6 V
3 #1 6 NiCad
NC SD VO T
Gnd FB
4 7
Early Warning
27 k D3 All diodes are 1N4148.
Reset Early Warning flag on low input voltage.
2.7 M µP
Main output latches off at lower input
Q1 D4 VDD
voltages.
2N3906
8 Battery backup on auxiliary output.
330 k Vin
5 1 Operation: Regulator #1’s Vout is
Error Vout
Main programmed one diode drop above 5.0 V.
2 Output Its error flag becomes active when Vin < 5.7
SNS V. When Vin drops below 5.3 V, the error
LP2951CN flag of regulator #2 becomes active and via
3 #2 6 1.0 µF Q1 latches the main output “off”. When Vin
SD VO T again exceeds 5.7 V, regulator #1 is back in
regulation and the early warning signal
Gnd FB rises, unlatching regulator #2 via D3.
4 7
Figure 23. 2.0 A Low Dropout Regulator

+Vin
Current Limit
Section
680 470 0.05 1000 µF

2N3906
2N3906
MJE2955
10 k .33 µF
4.7 M 8
Vin
Error 5 1
Error Vout
Flag
2 Vout @ 2.0 A
SNS NC 47
LP2951CN
220 3 6
SD VO T NC 4.7 µF
100 µF
Tant
20 k Gnd FB .01 µF R1
4 7
R2
0.033 µF
Vout = 1.25V (1.0 + R1/R2)
For 5.0 V output, use internal resistors. Wire Pin 6 to 7,

and wire Pin 2 to +Vout Bus.

LP2950 LP2951
Figure 24. Open Circuit Detector for
4.0 to 20 mA Current Loop
+ 5.0 V
4.7 k
Output*
1 5
4 20 mA
8
Vin
5 1 2 4
NC Error Vout
2
SNS NC
LP2951CN * High for
NC 3 6 IL < 3.5 mA
SD VO T NC
1N4001 0.1 µF Gnd FB

4 7
1N457
1N457 360
1N457
Figure 25. Low Battery Disconnect
31.6 k 6.0 V Lead–Acid

100 k Battery
2N3906
8
Vin
2 5 1
NC Error Vout Main V+
1
MC34164P–5
2
SNS Memory V+
3 LP2951CN
1.0 µF
3 6 20
SD VO T NC
NiCad Backup
Gnd FB Battery
4 7
NC

100 2.4

Free Air
90 Mounted 2.0
ÎÎÎ
Vertically
2.0 oz. Copper
80 1.6
ÎÎÎ
L
Minimum
ÎÎÎ
70 Size Pad 1.2
L
60
50
ÎÎÎ 0.8
0.4
RθJA
40 0
0 5.0 10 15 20 25 30

MC1723C
Voltage Regulator
The MC1723C is a positive or negative voltage regulator designed to
deliver load current to 150 mAdc. Output current capability can be increased
to several amperes through use of one or more external pass transistors.
MC1723C is specified for operation over the commercial temperature range VOLTAGE REGULATOR
(0° to +70°C).
• Output Voltage Adjustable from 2.0 Vdc to 37 Vdc SEMICONDUCTOR
• Output Current to 150 mAdc Without External Pass Transistors TECHNICAL DATA
• 0.01% Line and 0.03% Load Regulation
• Adjustable Short Circuit Protection
Figure 1. Representative Schematic Diagram P SUFFIX

PLASTIC PACKAGE
VCC VC CASE 646
12 11
500 25k 1.0k 1.0k
6.2V
Vz
9
D SUFFIX
6.2V PLASTIC PACKAGE
15k
CASE 751A
15k
10 (SO–14)
VO
100 13
Compensation
5.0pF
30k 6.2V 2 Current
300 Limit
5.0k 20k 150 Operating
Current Temperature
6 Vref 5 7 VEE 4 3 Sense Device Alternate Range Package
Noninverting Inverting MC1723CD – SO–14

Input Input TA = 0° to +70°C
MC1723CP LM723CN Plastic DIP
µA723PC
Figure 2. Typical Circuit Connection
(7 < VO < 37)

12 10 RSC
Figure 3. Typical NPN Current Boost Connection
Vin VO
11 2
RSC = 0.33
VO = +15Vdc
3 2N3055 or Equiv IL = 2Adc max
MC1723C
6 12 10
R3 R1 Vin = 20Vdc
4 11 2
5 C1 100pF 3
MC1723C
Cref 13
R2 12k
7 0.1µF 6 4
5 C1 100pF
13 10k
VO ^7 R1 + R2
R2
Vsense
ISC =
RSC
=
0.66
RSC
at TJ = + 25°C
7
For best results 10 k < R2 < 100 k

For minimum drift R3 = R1 | | R2

MC1723C
Pulse Voltage from VCC to VEE (50 ms) VI(p) 50 Vpk
Continuous Voltage from VCC to VEE VI 40 Vdc
Maximum Output Current IL 150 mAdc
Current from Vref Iref 15 mAdc
Current from Vz Iz 25 mA
Voltage Between Noninverting Input and VEE Vie 8.0 Vdc
Differential Input Voltage Vid ±5.0 Vdc
TA = +25°C PD 1.25 W
Operating and Storage Junction Temperature Range TJ, Tstg –65 to +175 °C
ELECTRICAL CHARACTERISTICS (TA = +25°C, Vin 12 Vdc, VO = 5.0 Vdc, IL = 1.0 mAdc, RSC = 0, C1 = 100 pF, Cref = 0 and divider
impedance as seen by the error amplifier ≤ 10 kΩ connected as shown in Figure 2, unless otherwise noted.)
Input Voltage Range VI 9.5 – 40 Vdc
Output Voltage Range VO 2.0 – 37 Vdc
Input–Output Voltage Differential VI–VO 3.0 – 38 Vdc
Reference Voltage Vref 6.80 7.15 7.50 Vdc
Standby Current Drain ( IL = 0, Vin = 30 V) IIB – 2.3 4.0 mAdc
Output Noise Voltage (f = 100 Hz to 10 kHz) Vn µV(RMS)
Cref = 0 – 20 –
Cref = 5.0 µF – 2.5 –
Average Temperature Coefficient of Output TCVO – 0.003 0.015 %/°C
Voltage (Tlow < TA < Thigh)
Line Regulation Regline % VO

12 V < Vin < 15 V – 0.01 0.1
(TA = 25°C)
12 V < Vin < 40 V – 0.1 0.5
(Tlow < TA < Thigh)
12 V < Vin < 15 V – – 0.3
Load Regulation (1.0 mA < IL < 50 mA) Regload % VO

TA = 25°C – 0.03 0.2
Tlow < TA < Thigh – – 0.6
Ripple Rejection (f = 50 Hz to 10 kHz) RR dB
Cref = 0 – 74 –
Cref = 5.0 µF – 86 –
Short Circuit Current Limit (RSC = 10 Ω, VO = 0) ISC – 65 – mAdc
Long Term Stability ^VO/^t – 0.1 – %/1000 Hr.
NOTE: Tlow to Thigh = 0° to +70°C

MC1723C
Figure 4. Maximum Load Current as a Function Figure 5. Load Regulation Characteristics

of Input–Output Voltage Differential Without Current Limiting
200 0.05
TJmax = 150°C
Reg load , LOAD REGULATION (%VO )

I L (max), LOAD CURRENT (mA)
RTH = 150°C/W
160 PSTANDBY 60 mW
(No heatsink) 0
120
TA = + 25°C
TA = + 25°C –0.05
80 TA = –55°C
–0.1
40 TA = + 75°C TA = + 125°C
TA = + 125°C
0 –0.15
0 10 20 30 40 0 20 40 60 80 100
Vin–Vout, INPUT–OUTPUT VOLTAGE (V) IO, OUTPUT CURRENT (mA)
Figure 6. Load Regulation Characteristics Figure 7. Load Regulation Characteristics

With Current Limiting With Current Limiting
0.05 0.1

0 0
TA = –55°C
–0.05 –0.1
TA = + 25°C
TA = –55°C
–0.1 –0.2
TA = + 125°C RSC = 10 Ω
TA = + 25°C
–0.15 RSC = 10 Ω
–0.3
TA = + 125°C
–0.2 –0.4
0 5.0 10 15 20 25 30 0 20 40 60 80
IO, OUTPUT CURRENT (mA) IO, OUTPUT CURRENT (mA)
Figure 9. Current Limiting Characteristics

Figure 8. Current Limiting Characteristics as a Function of Junction Temperature
1.2 0.8 200
RSC = 10 Ω
CURRENT LIMIT SENSE VOLTAGE (V)
RELATIVE OUTPUT VOLTAGE (V)
1.0
LIMITING CURRENT (mA)
0.7 Sense Voltage 160

0.8
0.6 0.6 Limit Current RSC = 5.0 Ω 120
0.4 TA = + 125°C
TA=+25°C 0.5 80
0.2
TA = –55°C Limit Current RSC = 10 Ω
0 0.4 40
0 20 40 60 80 100 –50 0 50 100 150
IO, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (°C)

MC1723C
Figure 10. Line Regulation as a Function Figure 11. Load Regulation as a Function
of Input–Output Voltage Differential of Input–Output Voltage Differential
0.2 0.1
∆Vin = +3 V IL = 1.0 to IL = 50 mA

Reg in , LINE REGULATION (%VO )
0.1 0
0 –0.1
–0.1 –0.2
5.0 15 25 35 0 10 20 30 40 50
Vin–Vout, INPUT–OUTPUT VOLTAGE (V) Vin–Vout, INPUT–OUTPUT VOLTAGE (V)
Figure 12. Standby Current Drain as a

Function of Input Voltage Figure 13. Line Transient Response
4.0 4.0
OUTPUT VOLTAGE DEVIATION (mV) Input Voltage
VO = Vref
IL = 0
INPUT VOLTAGE DEVIATION (V)

TA = –55°C
STANDBY CURRENT (mA)
3.0 2.0
2.0 2.0 0
TA = +25°C
Output Voltage
1.0 0
TA = +125°C
0 –2.0
10 20 30 40 –5.0 0 10 20 30 40 45
Vin, INPUT VOLTAGE (V) t, TIME (µs)
Figure 15. Output Impedance as

Figure 14. Load Transient Response Function of Frequency
10 10
Load Current IL = 40 mA
IL = 50 mA
OUTPUT VOLTAGE DEVIATION (mV)
CI = 0
0
LOAD DEVIATION (mA)
1.0
2.0
CI = 1.0 µF
0
Output Voltage 0.1

–4.0
–8.0 0.01
–5.0 0 10 20 30 40 45 100 1.0 k 10 k 100 k 1M
t, TIME (µs) f, FREQUENCY (Hz)

MC1723C
Figure 16. Typical Connection for 2 < VO < 7 Figure 17. Foldback Connection
12 10 RSC 12 10 RSC
+Vin Vout + Vin Vout
11 2 11
RA
3 2
MC1723C R1
6 6 10k
R1 R3
4 MC1723C
4
5
5 13 100pF
13
Cref R2 1000pF
7
R2
Vout 3
7
VO ^7 R2
R1 + R2 ISC =
Vsense
RSC
^ 0.66
RSC at TJ = + 25°C
a Vsense Iknee
ISC Iknee RA = 10 kΩ where a = –1
For best results 10 k < R1 +R2 < 100 k 1–a VO ISC
For minimum drift R3 = R1 R2 IL
Vsense
RSC = (1– ) I
a SC
Figure 18. +5.0 V, 1.0 A Switching Regulator Figure 19. +5.0 V, 1.0 A High Efficiency Regulator
Vin1 Vout
2N4918 or Equiv 1mH
+6.5V
0.33 +5.0V
1N4001 0.1µF
11 or Equiv Vin2 12
+10V
100 12 Vout 10
Vin
+10V 10 10 +5V 11 2
6
MC1723C 6 MC1723C 3
2 2.0k
1.0M 3 4
2.2k +
100µF 5
1.0k 4 –
5.1k 13
5
7 1000pF
0.1µF 5.1k 7
Figure 20. +15 V, 1.0 A Regulator with Remote Sense Figure 21. –15 V Negative Regulator
0.33
12 10
2N3055 or Equiv
11
Vin 12 10
+20V 4 12k
11 2
6 MC1723C +
3 +
100pF Vref 10µF
MC1723C –
5
0.1µF 6 4 12k + Sense Vout
+ 13 10k
5 100pF +15V Vref 7
– –
13 10k Load Vout = –15 V
7 V2 = 14V
2N3055
– Sense
Vin = –20 V or Equiv

MC1723C
Figure 22. +12V, 1.0 A Regulator

(Using PNP Current Boost)
2N3791
or Equiv
Vin
+18V Vout = +12 V
0.33
11
100 10
12 2
MC1723C 3
6 4 10k
100pF
5 13 12k

MC3423
Overvoltage Crowbar
Sensing Circuit
This overvoltage protection circuit (OVP) protects sensitive electronic OVERVOLTAGE
circuitry from overvoltage transients or regulator failures when used in SENSING CIRCUIT
conjunction with an external “crowbar” SCR. The device senses the
overvoltage condition and quickly “crowbars” or short circuits the supply,
forcing the supply into current limiting or opening the fuse or circuit breaker. SEMICONDUCTOR
The protection voltage threshold is adjustable and the MC3423 can be TECHNICAL DATA
programmed for minimum duration of overvoltage condition before tripping,
thus supplying noise immunity.
The MC3423 is essentially a “two terminal” system, therefore it can be
used with either positive or negative supplies.
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
8
MAXIMUM RATINGS 1

Differential Power Supply Voltage VCC–VEE 40 Vdc
Sense Voltage (1) VSense1 6.5 Vdc D SUFFIX
Sense Voltage (2) VSense2 6.5 Vdc PLASTIC PACKAGE
8 CASE 751
Remote Activation Input Voltage Vact 7.0 Vdc 1 (SOP–8)
Output Current IO 300 mA
PIN CONNECTIONS
Drive
VCC 1 8
Output
Sense 1 2 7 VEE
Indicator
Sense 2 3 6
Output
Current Remote
4 5
Vout Source Activation
Vin
Current (Top View)

Limited +
Cout O. V. P.
DC
MC3423
Power
Supply
Operating
MC3423D SO–8
TA = 0° to +70°C
MC3423P1 Plastic DIP

MC3423
ELECTRICAL CHARACTERISTICS (5.0 V ≤ VCC – VEE ≤ 36 V, Tlow < TA , Thigh, unless otherwise noted.)
Supply Voltage Range VCC–VEE 4.5 – 40 Vdc
Output Voltage VO VCC–2.2 VCC–1.8 – Vdc
(IO = 100 mA)
Indicator Output Voltage VOL(Ind) – 0.1 0.4 Vdc

(IO(Ind) = 1.6 mA)
Sense Trip Voltage VSense1, 2.45 2.6 2.75 Vdc

(TA = 25°C) VSense2
Temperature Coefficient of VSense1 TCVS1 – 0.06 – %/°C

(Figure 2)
Remote Activation Input Current µA

(VIH = 2.0 V, VCC – VEE = 5.0 V) IIH – 5.0 40
(VIL = 0.8 V, VCC – VEE = 5.0 V) IIL – –120 –180
Source Current ISource 0.1 0.2 0.3 mA
Output Current Risetime tr – 400 – mA/µs
(TA = 25°C)
Propagation Delay Time tpd – 0.5 – µs

(TA = 25°C)
Supply Current ID – 6.0 10 mA

NOTES: Tlow to Thigh = 0° to +70°C
Figure 1. Representative Block Diagram
VCC 1
ISource
4 Current
Source
2
Sense 1 – +
+ –
Vref
2.6V 8
+ Output
–
7 VEE 3 Sense 2 5 6 Indicator

Remote Output
Activation
Figure 2. Sense Voltage Test Circuit

VCC
Switch 1 1
2
(A)
Switch 1 Switch 2
3 8
(B) MC3423 VSense 1 Position A Closed
Switch 2 VSense 2 Position B Open
4
VI 7 5 V
Ramp VI until output goes high; this is
the VSense threshold.

MC3423
Figure 3. Basic Circuit Configuration
ǒ Ǔ ǒ Ǔ
* +
F1 (+ Sense
R1
Lead) Vtrip + Vref 1 ) R1
R2
[ 2.6 V 1 ) R1
R2
1
R2 ≤ 10 kΩ for minimum drift
Power 2 8
Supply MC3423 To
3 RG Load
For minimum value of RG, see Figure 9.
R2 4 7 5
S1* *See text for explanation.
(– Sense Lead)
–
Figure 4. Circuit Configuration for Supply Voltage Above 36 V
+ RS
C1 > (R1 + R2) 10µF
ǒ Ǔ
(+ Sense R1R2
Lead)
+ VS 25– 10 kW
RS
ǒ Ǔ ǒ Ǔ
RS
R1
Vtrip + Vref 1 ) R1 [ 2.6 V 1 ) R1
1 Q1
R2 R2
8
To *R2 ≤ 10 kΩ
Load
Power 1N4740 2
MC3423 VS
Supply 10V 3 Q1: VS ≤ 50 V; 2N6504 or equivalent
+ C1 Q1: VS ≤ 100 V; 2N6505 or equivalent
10µF 4 Q1: VS ≤ 200 V; 2N6506 or equivalent
15V *R2 Q1: VS ≤ 400 V; 2N6507 or equivalent
7 5
(– Sense Q1: VS ≤ 600 V; 2N6508 or equivalent
Lead) Q1: VS ≤ 800 V; 2N6509 or equivalent
–
Figure 5. Basic Configuration for Programmable Duration

of Overvoltage Condition Before Trip
VCC
Vtrip
+VCC
0
R3
R1 V10 VC
1 6 Vref
Indication
Power 2 8 Out
Supply MC3423 0
RG
4 3 5 7 VO
R2 VO
VC C
0
td
VIO
Vtrip
R3 ≥
10 mA Vref
td = × C ≈ [12 × 103] C (See Figure 10)
Isource

MC3423
Basic Circuit Configuration Figure 6. Configuration for Programmable
The basic circuit configuration of the MC3423 OVP is Duration of Overvoltage Condition Before
shown in Figure 3 for supply voltages from 4.5 V to 36 V, and Trip/With Immediate Trip at
in Figure 4 for trip voltages above 36 V. The threshold or trip High Overvoltages
voltage at which the MC3423 will trigger and supply gate
drive to the crowbar SCR, Q1, is determined by the selection (+ Sense +
of R1 and R2. Their values can be determined by the Lead)
equation given in Figures 3 and 4, or by the graph shown in
Figure 8. The minimum value of the gate current limiting 1
resistor, RG, is given in Figure 9. Using this value of RG, the R1
2
SCR, Q1, will receive the greatest gate current possible Z1
3 RG
without damaging the MC3423. If lower output currents are R2 MC3423
Power 5
required, RG can be increased in value. The switch, S1, Supply
shown in Figure 3 may be used to reset the crowbar.
Otherwise, the power supply, across which the SCR is 4 3 7
connected, must be shut down to reset the crowbar. If a non
1k
current–limited supply is used, a fuse or circuit breaker, F1, C
should be used to protect the SCR and/or the load.
The circuit configurations shown in Figures 3 and 4 will (– Sense Lead)
have a typical propogation delay of 1.0 µs. If faster operation –
is desired, Pin 3 may be connected to Pin 2 with Pin 4 left
floating. This will result in decreasing the propogation delay to
Additional Features
approximately 0.5 µs at the expense of a slightly increased
1. Activation Indication Output
TC for the trip voltage value.
An additional output for use as an indicator of OVP
Configuration for Programmable Minimum Duration activation is provided by the MC3423. This output is an
of Overvoltage Condition Before Tripping open collector transistor which saturates when the OVP is
activated. In addition, it can be used to clock an edge
In many instances, the MC3423 OVP will be used in a
triggered flip–flop whose output inhibits or shuts down the
noise environment. To prevent false tripping of the OVP
power supply when the OVP trips. This reduces or
circuit by noise which would not normally harm the load,
eliminates the heatsinking requirements for the
MC3423 has a programmable delay feature. To implement
crowbar SCR.
this feature, the circuit configuration of Figure 5 is used. In
this configuration, a capacitor is connected from Pin 3 to VEE. 2. Remote Activation Input
The value of this capacitor determines the minimum duration Another feature of the MC3423 is its remote activation
of the overvoltage condition which is necessary to trip the input, Pin 5. If the voltage on this CMOS/TTL compatible
OVP. The value of C can be found from Figure 10. The circuit input is held below 0.8 V, the MC3423 operates normally.
operates in the following manner: When VCC rises above the However, if it is raised to a voltage above 2.0 V, the OVP
trip point set by R1 and R2, an internal current source (Pin 4) output is activated independent of whether or not an
begins charging the capacitor, C, connected to Pin 3. If the overvoltage condition is present. It should be noted that Pin
overvoltage condition disappears before this occurs, the 5 has an internal pull–up current source. This feature can
capacitor is discharged at a rate ≅ 10 times faster than the be used to accomplish an orderly and sequenced
charging rate, resetting the timing feature until the next shutdown of system power supplies during a system fault
overvoltage condition occurs. condition. In addition, the activation indication output of one
Occasionally, it is desired that immediate crowbarring of MC3423 can be used to activate another MC3423 if a single
the supply occur when a high overvoltage condition occurs, transistor inverter is used to interface the former’s indication
while retaining the false tripping immunity of Figure 5. In this output to the latter’s remote activation input, as shown in
case, the circuit of Figure 6 can be used. The circuit will Figure 7. In this circuit, the indication output (Pin 6) of the
operate as previously described for small overvoltages, but MC3423 on power supply 1 is used to activate the MC3423
will immediately trip if the power supply voltage exceeds associated with power supply 2. Q1 is any small PNP with
VZ1 + 1.4 V. adequate voltage rating.

MC3423
Figure 7. Circuit Configuration for Figure 8. R1 versus Trip Voltage

Activating One MC3423 from Another 30
+ Typ
1 Max
R2 = 2.7 k
R1, RESISTANCE (k Ω )
Power 6 20
Supply Min
#1
7
–
10
R1 10k
+
1
0
Q1 0 5.0 10 15 20 25 30
Power 5
Supply VT, TRIP VOLTAGE (V)
#2
1.0k
7
–
Figure 9. Minimum RG versus Supply Voltage
35
Note that both supplies have their negative output leads
tied together (i.e., both are positive supplies). If their
RG(min) = 0
positive leads are common (two negative supplies) the
VCC , SUPPLY VOLTAGE (V)

30 if VCC < 11 V
emitter of Q1 would be moved to the positive lead of supply
1 and R1 would therefore have to be resized to deliver the
25
appropriate drive to Q1.
Crowbar SCR Considerations 20

Referring to Figure 11, it can be seen that the crowbar
SCR, when activated, is subject to a large current surge from 15
the output capacitance, Cout. This capacitance consists of
the power supply output caps, the load’s decoupling caps,
and in the case of Figure 11A, the supply’s input filter caps. 10
0 10 20 30 40 50 60 70 80
This surge current is illustrated in Figure 12, and can cause
RG, GATE CURRENT LIMITING RESISTOR (Ω)
SCR failure or degradation by any one of three mechanisms:
di/dt, absolute peak surge, or I2t. The interrelationship of
these failure methods and the breadth of the applications
make specification of the SCR by the semiconductor Figure 10. Capacitance versus
manufacturer difficult and expensive. Therefore, the designer Minimum Overvoltage Duration
must empirically determine the SCR and circuit elements 1 2 3 57 1
which result in reliable and effective OVP operation. 1.0
However, an understanding of the factors which influence the
SCR’s di/dt and surge capabilities simplifies this task.
C, CAPACITANCE ( µ F)
0.1
di/dt
As the gate region of the SCR is driven on, its area of
conduction takes a finite amount of time to grow, starting as a 0.01
very small region and gradually spreading. Since the anode
current flows through this turned–on gate region, very high
current densities can occur in the gate region if high anode 0.001 1
currents appear quickly (di/dt). This can result in immediate 5
destruction of the SCR or gradual degradation of its forward 2
blocking voltage capabilities – depending on the severity of 0.0001 1
0.001 0.01 0.1 1.0 10
the occasion.
td, DELAY TIME (ms)

MC3423
will be the case, though this is difficult to guarantee. Of

Figure 11. Typical Crowbar OVP Circuit course, a sufficiently high surge will cause an open. These
Configurations comments also apply to the fuse in Figure 11B.
The value of di/dt that an SCR can safely handle is
(11A) influenced by its construction and the characteristics of the
Vin Vout gate drive signal. A center–gate–fire SCR has more di/dt
DC capability than a corner–gate–fire type, and heavily
+ OV
Power Cout overdriving (3 to 5 times IGT) the SCR gate with a fast < 1.0 µs
Sense
Supply rise time signal will maximize its di/dt capability. A typical
maximum number in phase control SCRs of less than 50
A(RMS) rating might be 200 A/µs, assuming a gate current of
(11B) five times IGT and < 1.0 µs rise time. If having done this, a
Vin Vout di/dt problem is seen to still exist, the designer can also
*
DC decrease the di/dt of the current waveform by adding
+ OV
Power Cout inductance in series with the SCR, as shown in Figure 13. Of
Sense
Supply course, this reduces the circuit’s ability to rapidly reduce the
DC bus voltage and a tradeoff must be made between
*Needed if supply not current limited speedy voltage reduction and di/dt.
Surge Current
If the peak current and/or the duration of the surge is
Figure 12. Crowbar SCR Surge Current excessive, immediate destruction due to device overheating
Waveform will result. The surge capability of the SCR is directly
proportional to its die area. If the surge current cannot be
l reduced (by adding series resistance – see Figure 13) to a
lpk
safe level which is consistent with the systems requirements
for speedy bus voltage reduction, the designer must use a
di
higher current SCR. This may result in the average current
dt
Surge Due to capability of the SCR exceeding the steady state current
Output Capacitor requirements imposed by the DC power supply.
Current Limited A WORD ABOUT FUSING

Supply Output Before leaving the subject of the crowbar SCR, a few
words about fuse protection are in order. Referring back to
Figure 11A, it will be seen that a fuse is necessary if the power
t supply to be protected is not output current limited. This fuse
is not meant to prevent SCR failure but rather to prevent a fire!
In order to protect the SCR, the fuse would have to
possess an I2t rating less than that of the SCR and yet have
Figure 13. Circuit Elements Affecting
a high enough continuous current rating to survive normal
SCR Surge and di/dt
supply output currents. In addition, it must be capable of
successfully clearing the high short circuit currents from the
RLead LLead supply. Such a fuse as this is quite expensive, and may not
ESR R even be available.
Output CROWBAR SCR SELECTION GUIDE

ESL L
Cap As an aid in selecting an SCR for crowbar use, the
following selection guide is presented.
To
MC3423
Device IRMS IFSM Package
2N6400 Series 16 A 160 A TO–220 Plastic
R & L EMPIRICALLY DETERMINED! 2N6504 Series 25 A 160 A TO–220 Plastic
2N1842 Series 16 A 125 A Metal Stud
The usual design compromise then is to use a garden 2N2573 Series 25 A 260 A Metal TO–3 Type
variety fuse (3AG or 3AB style) which cannot be relied on to 2N681 Series 25 A 200 A Metal Stud
blow before the thyristor does, and trust that if the SCR does MCR3935–1 Series 35 A 350 A Metal Stud
fail, it will fail short circuit. In the majority of the designs, this MCR81–5 Series 80 A 1000 A Metal Stud

MC3425
Power Supply Supervisory/

Over and Undervoltage
POWER SUPPLY SUPERVISORY/
Protection Circuit
OVER AND UNDERVOLTAGE
The MC3425 is a power supply supervisory circuit containing all the
necessary functions required to monitor over and undervoltage fault
PROTECTION CIRCUIT
conditions. These integrated circuits contain dedicated over and SEMICONDUCTOR
undervoltage sensing channels with independently programmable time TECHNICAL DATA
delays. The overvoltage channel has a high current Drive Output for use in
conjunction with an external SCR Crowbar for shutdown. The undervoltage
channel input comparator has hysteresis which is externally programmable,
and an open–collector output for fault indication.
• Dedicated Over and Undervoltage Sensing
• Programmable Hysteresis of Undervoltage Comparator
• Internal 2.5 V Reference
• 300 mA Overvoltage Drive Output
•
8
30 mA Undervoltage Indicator Output 1
• Programmable Time Delays
P1 SUFFIX
• 4.5 V to 40 V Operation PLASTIC PACKAGE
CASE 626
MAXIMUM RATINGS
Power Supply Voltage VCC 40 Vdc
Comparator Input Voltage Range (Note 1) VIR –0.3 to +40 Vdc
Drive Output Short Circuit Current IOS(DRV) Internally mA
Limited
Indicator Output Voltage VIND 0 to 40 Vdc
Indicator Output Sink Current IIND 30 mA
PIN CONNECTIONS
Maximum Power Dissipation @ TA = 70°C PD 1000 mW
Thermal Resistance, Junction–to–Air RθJA 80 °C/W
Operating Junction Temperature TJ +150 °C O.V. DRV
1 8 VCC
Output
Storage Temperature Range Tstg –55 to +150 °C O.V. DLY 2 7 Gnd
NOTE: 1. The input signal voltage should not be allowed to go negative by more than 300 mV U.V. IND
NOTE: 1. or positive by more than 40 V, independent of VCC, without device destruction.
O.V. Sense 3 6 Output
U.V. Sense 4 5 U.V. DLY
(Top View)
Overvoltage Crowbar Protection, Undervoltage Indication
Vin Vout
DC
Power + MC3425 Undervoltage ORDERING INFORMATION
Supply Indication
Cout
Operating
MC3425P1 TA = 0° to +70°C Plastic DIP

MC3425
ELECTRICAL CHARACTERISTICS (4.5 V ≤ VCC ≤ 40 V; TA = Tlow to Thigh [Note 2], unless otherwise noted.)
REFERENCE SECTION
Sense Trip Voltage (Referenced Voltage) VSense Vdc
VCC = 15 V
TA= 25°C 2.4 2.5 2.6
Tlow to Thigh (Note 2) 2.33 2.5 2.63
Line Regulation of VSense Regline – 7.0 15 mV
4.5 V ≤ VCC ≤ 40 V; TJ = 25°C
Power Supply Voltage Operating Range VCC 4.5 – 40 Vdc

Power Supply Current
VCC = 40 V; TA = 25°C; No Output Loads
O.V. Sense (Pin 3) = 0 V; ICC(off) – 8.5 10 mA
U.V. Sense (Pin 4) = VCC
O.V. Sense (Pin 3) = VCC; ICC(on) – 16.5 19 mA
U.V. Sense (Pin 4) = 0 V
INPUT SECTION
Input Bias Current, O.V. and U.V. Sense IIB – 1.0 2.0 µA
Hysteresis Activation Voltage, U.V. Sense VH(act) V
VCC = 15 V; TA = 25°C;
IH = 10% – 0.6 –
IH = 90% – 0.8 –
Hysteresis Current, U.V. Sense IH 9.0 12.5 16 µA
VCC = 15 V; TA = 25°C; U.V. Sense (Pin 4) = 2.5 V
Delay Pin Voltage (IDLY = 0 mA) V

Low State VOL(DLY) – 0.2 0.5
High State VOH(DLY) VCC–0.5 VCC–0.15 –
Delay Pin Source Current IDLY(source) 140 200 260 µA
VCC = 15 V; VDLY = 0 V
Delay Pin Sink Current IDLY(sink) 1.8 3.0 – mA

VCC = 15 V; VDLY = 2.5V
OUTPUT SECTION
Drive Output Peak Current (TA = 25°C) IDRV(peak) 200 300 – mA
Drive Output Voltage VOH(DRV) VCC–2.5 VCC–2.0 – V
IDRV = 100 mA; TA = 25° C
Drive Output Leakage Current IDRV(leak) – 15 200 nA

VDRV = 0 V
Drive Output Current Slew Rate (TA = 25°C) di/dt – 2.0 – A/µs
Drive Output VCC Transient Rejection IDRV(trans) – 1.0 – mA
VCC = 0 V to 15 V at dV/dt = 200 V µs; (Peak)
O.V. Sense (Pin 3) = 0 V; TA = 25°C
Indicator Output Saturation Voltage VIND(sat) – 560 800 mV
IIND = 30 mA; TA = 25°C
Indicator Output Leakage Current IIND(leak) – 25 200 nA

VOH(IND) = 40 V
Output Comparator Threshold Voltage (Note 3) Vth(OC) 2.33 2.5 2.63 V

Propagation Delay Time
(VCC = 15 V; TA = 25°C)
Input to Drive Output or Indicator Output tPLH(IN/OUT) – 1.7 – µs
100 mV Overdrive, CDLY = 0 µF
Input to Delay tPLH(IN//DLY) – 700 – ns
2.5 V Overdrive (0 V to 5.0 V Step)
3. The Vth(OC) limits are approximately the VSense limits over the applicable temperature range.

MC3425
Figure 1. Hysteresis Current versus Figure 2. Hysteresis Activation Voltage

Hysteresis Activation Voltage versus Temperature
V H(act) , HYSTERESIS ACTIVATION VOLTAGE (V)

14 1.2
VH(act) = Voltage Level at
IH, HYSTERESIS CURRENT (µA)
12 TA = 25°C VCC = 5.0 V which Hysteresis Current

1.0
(IH) is 90% of full value.
10
0.8 VCC = 15 V
8.0 VCC = 40 V
0.6 VCC = 40 V
6.0
VCC
= 15 V 0.4
4.0 VCC = 5.0 V
2.0 0.2
0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –55 –25 0 25 50 75 100 125
VH(act), HYSTERESIS ACTIVATION VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 3. Hysteresis Current Figure 4. Sense Trip Voltage Change

∆ V Sense , SENSE TRIP VOLTAGE CHANGE (mW)

15.0
VSense* = 2.400 V * = 2.500 V * = 2.600 V
0
U.V. Sense = 2.5 V
IH, HYSTERESIS CURRENT (µA)
14.0
–10
13.0 –20
VCC = 15 V
12.0 –30 *VSense at TA = 25°C
–40
11.0
–50
10.0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
Figure 5. Output Delay Time versus Figure 6. Delay Pin Source Current
Delay Capacitance versus Temperature
IDLY(source), DELAY PIN SOURCE CURRENT ( µ A)
100 260
VCC = 15 V
t DLY , OUTPUT DELAY TIME (mS)
TA = 25°C
10 240 VCC = 40 V
1.0 220
VCC = 15 V
0.1 200
2.5 CDLY
tDLY =
200 µA
0.01 180 VCC = 5.0 V
0.001 160
0.0001 0.001 0.01 0.1 1.0 10 –55 –25 0 25 50 75 100 125
CDLY, DELAY PIN CAPACITANCE (µF) TA, AMBIENT TEMPERATURE (°C)

MC3425
Figure 7. Drive Output Saturation Voltage Figure 8. Indicator Output Saturation Voltage
V OH(DRV), DRIVE OUTPUT SATURATION VOLTAGE (V)
V IND(sat) , INDICATOR OUTPUT SATURATION VOLTAGE (V)

versus Output Peak Current versus Output Sink Current
5.0 0.4
4.0 VCC = 15 V
1.0% Duty Cycle @ 300 Hz 0.3
TA = 25°C
3.0
0.2
2.0 VCC = 15 V
TA = 25°C
0.1
1.0
0 0
0 100 200 300 400 0 10 20 30 40
IDRV(peak), DRIVE OUTPUT PEAK CURRENT (mA) IIND, INDICATOR OUTPUT SINK CURRENT (mA)
Figure 9. Drive Output Saturation Voltage Figure 10. Power Supply Current
V OH(DRV), DRIVE OUTPUT SATURATION VOTLAGE (V)
versus Temperature versus Voltage

2.500 28
I CC, POWER SUPPLY CURRENT (mA) Curve O.V. Sense U.V. Sense
VCC = 15 V
IDRV(peak) = 200 mA 24 A VCC Gnd
2.460 1.0% Duty Cycle @ 300 Hz B Gnd VCC
20 A
2.420 16
12
2.380
B
8.0
2.340
4.0 TA = 25°C
2.300 0
–55 –25 0 25 50 75 100 125 0 5.0 10 15 20 25 30 35 40
TA, AMBIENT TEMPERATURE (°C) VCC, POWER SUPPLY VOLTAGE (V)

MC3425
Figure 11. Overvoltage Protection and Figure 12. Overvoltage Protection of 5.0 V
Undervoltage Fault Indication with Supply with Line Loss Detector
Programmable Delay
VO = 5.0 V
+VO Vin +5.0V VO(trip) = 6.25 V
Power
Supply
8
VCC 1.0k
R1A R1B 15k
4 U.V. U.V. 6 Line Loss

8 Sense IND Output
+ VCC AC Line
Power U.V. Fault MC3425
Supply Indicator
4 U.V. U.V. 6 3 O.V. O.V. 1
4.5V to 40V Sense IND Sense DRV
– IH
MC3425
10k O.V. U.V.
3 O.V. O.V. 1 DLY Gnd DLY
Sense DRV
100 2 7 5
O.V. U.V. 0.33µF
DLY Gnd DLY 0.01µF
R2A R2B 2 7 5
CDLY CDLY U.V. Sense
Gnd 2.5V
Pin 4
U.V. DLY 2.5V
R1B R2B R1A Pin 5
U.V. Hysteresis = IH , VO(trip) – 2.5 V 1+
R1B + R2B R2A U.V. IND OFF
tDLY = 12500 CDLY Pin 6 ON
Figure 13. Overvoltage Audio Alarm Circuit Figure 14. Programmable Frequency Switch
12V
+VO Input Signal 5.0µF
8
8 Output Pulse when:
VCC
12k Alarm On when: I.V. p–p 1
VCC 10k f(input) <
VO = 13.6 V 3 O.V. 1 25000 CDLY
O.V.
3 O.V. O.V. 1 Sense DRV
+ Sense DRV
10k MC3425 1.0k
12V 2.7k MC3425
Power 4 U.V.
4 U.V. 100Ω
Supply Sense
Sense U.V. O.V.
82k U.V. O.V. DLY Gnd DLY
DLY DLY Gnd 5 7 2
6.8k 5 2 7
0.1µF CDLY
0.1µF
Gnd
O.V. Sense
Pin 3 2.5V
O.V. DLY 2.5V

Pin 2
ON
O.V. DRV
OFF
Pin 1

MC3425
CIRCUIT DESCRIPTION
The MC3425 is a power supply supervisory circuit source, IDLY(source), charging the external delay capacitor
containing all the necessary functions required to monitor (CDLY) to 2.5 V.
over and undervoltage fault conditions. The block diagram
is shown below in Figure 15. The Overvoltage (O.V.) and
Undervoltage (U.V.) Input Comparators are both Vref CDLY 2.5 CDLY
tDLY = = = 12500 CDLY
referenced to an internal 2.5 V regulator. The U.V. Input IDLY(source) 200 µA
Comparator has a feedback activated 12.5 µA current sink
(IH) which is used for programming the input hysteresis Figure 5 provides CDLY values for a wide range of time
voltage (VH). The source resistance feeding this input (RH) delays. The Delay pins are pulled low when the respective
determines the amount of hysteresis voltage by VH = IHRH input comparator’s noninverting input is less than the
= 12.5 × 10–6 RH. inverting input. The sink current, IDLY(sink), capability of the
Separate Delay pins (O.V. DLY, U.V. DLY.) are provided for Delay pins is ≥ 1.8 mA and is much greater than the typical
each channel to independently delay the Drive and Indicator 200 µA source current, thus enabling a relatively fast delay
outputs, thus providing greater input noise immunity. The two capacitor discharge time.
Delay pins are essentially the outputs of the respective input The Overvoltage Drive Output is a current–limited
comparators, and provide a constant current source, emitter–follower capable of sourcing 300 mA at a turn–on
IDLY(source), of typically 200 µA when the noninverting input slew rate at 2.0 A/µs, ideal for driving “Crowbar” SCR’s. The
voltage is greater than the inverting input level. A capacitor Undervoltage Indicator Output is an open–collector, NPN
connected from these Delay pins to ground, will establish a transistor, capable of sinking 30 mA to provide sufficient drive
predictable delay time (tDLY) for the Drive and Indicator for LED’s, small relays or shut–down circuitry. These current
outputs. The Delay pins are internally connected to the capabilities apply to both channels operating simultaneously,
noninverting inputs of the O.V. and U.V. Output Comparators, providing device power dissipation limits are not exceeded.
which are referenced to the internal 2.5 V regulator. The MC3425 has an internal 2.5 V bandgap reference
Therefore, delay time (tDLY) is based on the constant current regulator with an accuracy of ± 4.0% for the basic device.
VCC
8
+
+
O.V.
Sense 200µA
+
+ Input +Output
3 Comparator Comparator
– O.V. – O.V.
O.V.
+ 1 DRV
–
Output U.V.
200µA 6 IND
Comparator
U.V. + Input + U.V.
Sense Comparator +
– U.V.
4
2.5V
IH Reference
Regulator
12.5µA
5 2 7
Input Section U.V. O.V. Gnd Output Section
DLY DLY
Note: All voltages and currents are nominal.

MC3425
CROWBAR SCR CONSIDERATIONS
Referring to Figure 16, it can be seen that the crowbar current flows through this turned–on gate region, very high
SCR, when activated, is subject to a large current surge from current densities can occur in the gate region if high anode
the output capacitance, Cout. This capacitance consists of currents appear quickly (di/dt). This can result in immediate
the power supply output capacitors, the load’s decoupling destruction of the SCR or gradual degradation of its forward
capacitors, and in the case of Figure 16A, the supply’s input blocking voltage capabilities – depending on the severity of
filter capacitors. This surge current is illustrated in Figure 17, the occasion.
and can cause SCR failure or degradation by any one of The value of di/dt that an SCR can safely handle is
three mechanisms: di/dt, absolute peak surge, or I2t. The influenced by its construction and the characteristics of the
interrelationship of these failure methods and the breadth of gate drive signal. A center–gate–fire SCR has more di/dt
the applications make specification of the SCR by the capability than a corner–gate–fire type, and heavily
semiconductor manufacturer difficult and expensive. overdriving ( 3 to 5 times IGT) the SCR gate with a fast < 1.0
Therefore, the designer must empirically determine the SCR µs rise time signal will maximize its di/dt capability. A typical
and circuit elements which result in reliable and effective OVP maximum number in phase control SCRs of less than 50
operation. However, an understanding of the factors which A(RMS) rating might be 200 A/µs, assuming a gate current of
influence the SCR’s di/dt and surge capabilities simplifies five times IGT and < 1.0 µs rise time. If having done this, a di/dt
this task. problem is seen to still exist, the designer can also decrease
the di/dt of the current waveform by adding inductance in
1. di/dt series with the SCR, as shown in Figure 18. Of course, this
As the gate region of the SCR is driven on, its area of reduces the circuit’s ability to rapidly reduce the dc bus
conduction takes a finite amount of time to grow, starting as a voltage and a tradeoff must be made between speedy
very small region and gradually spreading. Since the anode voltage reduction and di/dt.
Figure 16. Typical Crowbar Circuit Configurations
(A) SCR Across Input of Regulator
Series
Vin Regulator Vout
MC3425
+ +
Cin Cout
(B) SCR Across Output of Regulator
Series *
Vin Vout
Regulator
+ +
Cin Cout MC3425
*Needed if supply is not current limited.

MC3425
Figure 17. Crowbar SCR Surge Current Waveform A WORD ABOUT FUSING
Before leaving the subject of the crowbar SCR, a few
l words about fuse protection are in order. Referring back to
lpk Figure 16A, it will be seen that a fuse is necessary if the
power supply to be protected is not output current limited.
di This fuse is not meant to prevent SCR failure but rather to
dt prevent a fire!
Surge Due to In order to protect the SCR, the fuse would have to
Output Capacitor
possess an I2t rating less than that of the SCR and yet have
Current Limited a high enough continuous current rating to survive normal
Supply Output supply output currents. In addition, it must be capable of
successfully clearing the high short circuit currents from the
supply. Such a fuse as this is quite expensive, and may not
t even be available.
The usual design compromise then is to use a garden
2. Surge Current variety fuse (3AG or 3AB style) which cannot be relied on to
If the peak current and/or the duration of the surge is blow before the thyristor does, and trust that if the SCR does
excessive, immediate destruction due to device overheating fail, it will fail short circuit. In the majority of the designs, this
will result. The surge capability of the SCR is directly will be the case, though this is difficult to guarantee. Of
proportional to its die area. If the surge current cannot be course, a sufficiently high surge will cause an open. These
reduced (by adding series resistance – see Figure 18) to a comments also apply to the fuse in Figure 16B.
safe level which is consistent with the system’s requirements
for speedy bus voltage reduction, the designer must use a CROWBAR SCR SELECTION GUIDE
higher current SCR. This may result in the average current As an aid in selecting an SCR for crowbar use, the
capability of the SCR exceeding the steady state current following selection guide is presented.
requirements imposed by the DC power supply.
Figure 18. Circuit Elements Affecting Device IRMS ITSM

SCR Surge & di/dt
MCR310 Series 10 A 100 A
RLead LLead MCR25 Series 25 A 300 A
R 2N6501 Series 25 A 300 A
ESR
Output MCR264 Series 40 A 400 A
ESL L
Cap MCR265 Series 55 A 550 A
To
MC3423
R & L EMPIRICALLY DETERMINED!
UNDERVOLTAGE SENSING
An undervoltage sense circuit with hysteresis may be
designed, as shown in Figure 11, using the following
equations:
R1 +
V
CCU
* VCC1
12.5 mA
R2 +
V CC1 * 2.5
2.5 R1
where: VCCU is the designed upper trip point

(output indicator goes off)
VCC1 is the lower trip point
(output indicator goes on)

MC7800
Series
Three-Terminal Positive THREE–TERMINAL

Voltage Regulators POSITIVE FIXED
These voltage regulators are monolithic integrated circuits designed as VOLTAGE REGULATORS
fixed–voltage regulators for a wide variety of applications including local,
SEMICONDUCTOR
on–card regulation. These regulators employ internal current limiting,
thermal shutdown, and safe–area compensation. With adequate heatsinking TECHNICAL DATA
they can deliver output currents in excess of 1.0 A. Although designed
primarily as a fixed voltage regulator, these devices can be used with
external components to obtain adjustable voltages and currents.
• No External Components Required T SUFFIX
• Internal Thermal Overload Protection PLASTIC PACKAGE
CASE 221A
• Output Transistor Safe–Area Compensation Heatsink surface
connected to Pin 2.
• Output Voltage Offered in 2% and 4% Tolerance
• Available in Surface Mount D2PAK and Standard 3–Lead Transistor 1
2
Packages 3
Pin 1. Input
2. Ground
3. Output
D2T SUFFIX
PLASTIC PACKAGE
CASE 936
(D2PAK) 1 2
3

DEVICE TYPE/NOMINAL OUTPUT VOLTAGE STANDARD APPLICATION

MC7805 5.0 V MC7812 12 V
MC7806 6.0 V MC7815 15 V
Input MC78XX Output
MC7808 8.0 V MC7818 18 V
MC7809 9.0 V MC7824 24 V Cin*
CO**
0.33 µF
A common ground is required between the input
Output Voltage Operating and the output voltages. The input voltage must
Device Tolerance Temperature Range Package remain typically 2.0 V above the output voltage
MC78XXACT Insertion Mount even during the low point on the input ripple
2% voltage.
MC78XXACD2T Surface Mount
TJ = 0° to +125°C XX, These two digits of the type number
MC78XXCT Insertion Mount indicate nominal voltage.
MC78XXCD2T Surface Mount * Cin is required if regulator is located an
4% appreciable distance from power supply
MC78XXBT Insertion Mount filter.
TJ = – 40° to +125°C
MC78XXBD2T Surface Mount ** CO is not needed for stability; however,
it does improve transient response. Values
XX indicates nominal voltage. of less than 0.1 µF could cause instability.

MC7800 Series
MAXIMUM RATINGS (TA = 25°C unless otherwise noted.)

Input Voltage (5.0 – 18 V) VI 35 Vdc
Power Dissipation
Case 221A
Case 936 (D2PAK)
Thermal Resistance, Junction–to–Ambient RθJA See Figure 13 °C/W
Thermal Resistance, Junction–to–Case RθJA 5.0 °C/W
Storage Junction Temperature Range Tstg – 65 to +150 °C
Vin
MC7800
R24
50 D2
Zener
LAT LAT 3A
Q18 R19
Q17 27.5 k
Q19
QNPN Q20
QNPN
C3 1.0P
R14
1.0 k
Q10
QNPN
R15
R18 R21 680 R23
100 k R22 600 0.2
100
Vout
Q7 5.01
QNPN Q5
QNPN 2 R30
R17 Q12 18 k
9.0 k Q9 QNPN Sense
QNPN 2 R12 R29
D1 Q6 R11 3.0 k 9.0 k
Zener 15 k Q15
QNPN
QNPN R25 R28
R1
10.66 k 6.0 k 9.0 k
R16 R10
R20 3340–(3316ACT)
600 R26 R27
17500
Q8 3.0 k 9.0 k
QNPN
R2
1.56 k
R9
R5 R13
3.0 k
4.5 k SUB 11660
Q14 Q11 2
QNPN Q1 C1
C2 N+ 30P
3.0P QNPN 6
Q4
QNPN
Q13 Q3
QNPN QNPN
Q2 Q16
R6 QNPN 4
1.0 k
Diode
R7 R3 R8
14 k 1.8 k 5.0 k

MC7800 Series
MC7805B MC7805C
Output Voltage (TJ = 25°C) VO 4.8 5.0 5.2 4.8 5.0 5.2 Vdc
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W)
7.0 Vdc ≤ Vin ≤ 20 Vdc – – – 4.75 5.0 5.25
8.0 Vdc ≤ Vin ≤ 20 Vdc 4.75 5.0 5.25 – – –
Line Regulation, TJ = 25°C (Note 2) Regline mV
7.0 Vdc ≤ Vin ≤ 25 Vdc – 5.0 100 – 5.0 100
8.0 Vdc ≤ Vin ≤ 12 Vdc – 1.3 50 – 1.3 50
Load Regulation, TJ = 25°C (Note 2) Regload mV
5.0 mA ≤ IO ≤ 1.5 A – 1.3 100 – 1.3 100
250 mA ≤ IO ≤ 750 mA – 0.15 50 – 0.15 50
Quiescent Current (TJ = 25°C) IB – 3.2 8.0 – 3.2 8.0 mA
7.0 Vdc ≤ Vin ≤ 25 Vdc – – – – – 1.3
8.0 Vdc ≤ Vin ≤ 25 Vdc – – 1.3 – – –
5.0 mA ≤ IO ≤ 1.0 A – – 0.5 – – 0.5
8.0 Vdc ≤ Vin ≤ 18 Vdc, f = 120 Hz – 68 – – 68 –
Dropout Voltage (IO = 1.0 A, TJ = 25°C) VI – VO – 2.0 – – 2.0 – Vdc

Output Noise Voltage (TA = 25°C) Vn µV/VO
10 Hz ≤ f ≤ 100 kHz – 10 – – 10 –
Output Resistance f = 1.0 kHz rO – 0.9 – – 0.9 – mΩ

Short Circuit Current Limit (TA = 25°C) ISC A
Vin = 35 Vdc – 0.2 – – 0.2 –
Peak Output Current (TJ = 25°C) Imax – 2.2 – – 2.2 – A

Average Temperature Coefficient of Output Voltage TCVO – – 0.3 – – – 0.3 – mV/°C
MC7805AC
Output Voltage (TJ = 25°C) VO 4.9 5.0 5.1 Vdc
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W) 4.8 5.0 5.2
7.5 Vdc ≤ Vin ≤ 20 Vdc
7.5 Vdc ≤ Vin ≤ 25 Vdc, IO = 500 mA – 5.0 50
8.0 Vdc ≤ Vin ≤ 12 Vdc – 1.3 50
8.0 Vdc ≤ Vin ≤ 12 Vdc, TJ = 25°C – 1.3 25
7.3 Vdc ≤ Vin ≤ 20 Vdc, TJ = 25°C – 4.5 50
5.0 mA ≤ IO ≤ 1.5 A, TJ = 25°C – 1.3 100
5.0 mA ≤ IO ≤ 1.0 A – 0.8 100
250 mA ≤ IO ≤ 750 mA – 0.15 50
(TJ = 25°C) – 3.2 6.0

8.0 Vdc ≤ Vin ≤ 25 Vdc, IO = 500 mA – – 0.8
7.5 Vdc ≤ Vin ≤ 20 Vdc, TJ = 25°C – – 0.8
5.0 mA ≤ IO ≤ 1.0 A – – 0.5
NOTES: 1. Tlow = 0°C for MC78XXAC, C Thigh = +125°C for MC78XXAC, C, B
Tlow = – 40°C for MC78XXB
2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account
separately. Pulse testing with low duty cycle is used.

MC7800 Series
ELECTRICAL CHARACTERISTICS (continued) (Vin = 10 V, IO = 1.0 A, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
MC7805AC
8.0 Vdc ≤ Vin ≤ 18 Vdc, f = 120 Hz, IO = 500 mA – 68 –
Dropout Voltage (IO = 1.0 A, TJ = 25°C) VI – VO – 2.0 – Vdc

10 Hz ≤ f ≤ 100 kHz – 10 –

Vin = 35 Vdc – 0.2 –
Peak Output Current (TJ = 25°C) Imax – 2.2 – A

Average Temperature Coefficient of Output Voltage TCVO – – 0.3 – mV/°C
MC7806B MC7806C
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W)
8.0 Vdc ≤ Vin ≤ 21 Vdc – – – 5.7 6.0 6.3
9.0 Vdc ≤ Vin ≤ 21 Vdc 5.7 6.0 6.3 – – –
8.0 Vdc ≤ Vin ≤ 25 Vdc – 5.5 120 – 5.5 120
9.0 Vdc ≤ Vin ≤ 13 Vdc – 1.4 60 – 1.4 60
5.0 mA ≤ IO ≤ 1.5 A – 1.3 120 – 1.3 120
250 mA ≤ IO ≤ 750 mA – 0.2 60 – 0.2 60
8.0 Vdc ≤ Vin ≤ 25 Vdc – – – – – 1.3
9.0 Vdc ≤ Vin ≤ 25 Vdc – – 1.3 – – –
5.0 mA ≤ IO ≤ 1.0 A – – 0.5 – – 0.5
9.0 Vdc ≤ Vin ≤ 19 Vdc, f = 120 Hz – 65 – – 65 –

10 Hz ≤ f ≤ 100 kHz – 10 – – 10 –

Vin = 35 Vdc – 0.2 – – 0.2 –


MC7800 Series
MC7806AC
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W) 5.76 6.0 6.24
8.6 Vdc ≤ Vin ≤ 21 Vdc
8.6 Vdc ≤ Vin ≤ 25 Vdc, IO = 500 mA – 5.0 60
9.0 Vdc ≤ Vin ≤ 13 Vdc – 1.4 60
9.0 Vdc ≤ Vin ≤ 13 Vdc, TJ = 25°C – 1.4 30
8.3 Vdc ≤ Vin ≤ 21 Vdc, TJ = 25°C – 4.5 60
5.0 mA ≤ IO ≤ 1.5 A, TJ = 25°C – 1.3 100
5.0 mA ≤ IO ≤ 1.0 A – 0.9 100
250 mA ≤ IO ≤ 750 mA – 0.2 50
TJ = 25°C – 3.3 6.0

9.0 Vdc ≤ Vin ≤ 25 Vdc, IO = 500 mA – – 0.8
8.6 Vdc ≤ Vin ≤ 21 Vdc, TJ = 25°C – – 0.8
5.0 mA ≤ IO ≤ 1.0 A – – 0.5
9.0 Vdc ≤ Vin ≤ 19 Vdc, f = 120 Hz, IO = 500 mA – 65 –

10 Hz ≤ f ≤ 100 kHz – 10 –

Vin = 35 Vdc – 0.2 –

MC7808B MC7808C
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W)
10.5 Vdc ≤ Vin ≤ 23 Vdc – – – 7.6 8.0 8.4
11.5 Vdc ≤ Vin ≤ 23 Vdc 7.6 8.0 8.4 – – –
Line Regulation, TJ = 25°C, (Note 2) Regline mV
10.5 Vdc ≤ Vin ≤ 25 Vdc – 6.0 160 – 6.0 160
11 Vdc ≤ Vin ≤ 17 Vdc – 1.7 80 – 1.7 80
5.0 mA ≤ IO ≤ 1.5 A – 1.4 160 – 1.4 160
250 mA ≤ IO ≤ 750 mA – .22 80 – .22 80

MC7800 Series
ELECTRICAL CHARACTERISTICS (continued) (Vin = 14 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
MC7808B MC7808C
10.5 Vdc ≤ Vin ≤ 25 Vdc – – – – – 1.0
11.5 Vdc ≤ Vin ≤ 25 Vdc – – 1.0 – – –
5.0 mA ≤ IO ≤ 1.0 A – – 0.5 – – 0.5
11.5 Vdc ≤ Vin ≤ 18 Vdc, f = 120 Hz – 62 – – 62 –

10 Hz ≤ f ≤ 100 kHz – 10 – – 10 –

Vin = 35 Vdc – 0.2 – – 0.2 –

MC7808AC
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W) 7.7 8.0 8.3
10.6 Vdc ≤ Vin ≤ 23 Vdc
10.6 Vdc ≤ Vin ≤ 25 Vdc, IO = 500 mA – 6.0 80
11 Vdc ≤ Vin ≤ 17 Vdc – 1.7 80
11 Vdc ≤ Vin ≤ 17 Vdc, TJ = 25°C – 1.7 40
10.4 Vdc ≤ Vin ≤ 23 Vdc, TJ = 25°C – 5.0 80
5.0 mA ≤ IO ≤ 1.5 A, TJ = 25°C – 1.4 100
5.0 mA ≤ IO ≤ 1.0 A – 1.0 100
250 mA ≤ IO ≤ 750 mA – .22 50
TJ = 25°C – 3.3 6.0

11 Vdc ≤ Vin ≤ 25 Vdc, IO = 500 mA – – 0.8
10.6 Vdc ≤ Vin ≤ 20 Vdc, TJ = 25°C – – 0.8
5.0 mA ≤ IO ≤ 1.0 A – – 0.5
11.5 Vdc ≤ Vin ≤ 21.5 Vdc, f = 120 Hz, IO = 500 mA – 62 –

10 Hz ≤ f ≤ 100 kHz – 10 –
Output Resistance f = 1.0 kHz rO – 0.9 – mΩ

Vin = 35 Vdc – 0.2 –


MC7800 Series
MC7809CT
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W) 8.55 9.0 9.45
11.5 Vdc ≤ Vin ≤ 24 Vdc
11.5 Vdc ≤ Vin ≤ 26 Vdc – 6.2 50
11.5 Vdc ≤ Vin ≤ 17 Vdc – 1.8 25
5.0 mA ≤ IO ≤ 1.5 A – 1.5 50
250 mA ≤ IO ≤ 750 mA – 0.3 25
Quiescent Current (TJ = 25°C) IB – 3.4 8.0 mA
11.5 Vdc ≤ Vin ≤ 26 Vdc – – 1.0
5.0 mA ≤ IO ≤ 1.0 A – – 0.5
11.5 Vdc ≤ Vin ≤ 21.5 Vdc, f = 120 Hz – 61 –

10 Hz ≤ f ≤ 100 kHz – 10 –

Vin = 35 Vdc – 0.2 –

MC7812B MC7812C
Output Voltage (TJ = 25°C) VO 11.5 12 12.5 11.5 12 12.5 Vdc
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W)
14.5 Vdc ≤ Vin ≤ 27 Vdc – – – 11.4 12 12.6
15.5 Vdc ≤ Vin ≤ 27 Vdc 11.4 12 12.6 – – –
14.5 Vdc ≤ Vin ≤ 30 Vdc – 7.5 240 – 7.5 240
16 Vdc ≤ Vin ≤ 22 Vdc – 2.2 120 – 2.2 120
5.0 mA ≤ IO ≤ 1.5 A – 1.6 240 – 1.6 240
250 mA ≤ IO ≤ 750 mA – 1.0 120 – 1.0 120
14.5 Vdc ≤ Vin ≤ 30 Vdc – – – – – 1.0
15 Vdc ≤ Vin ≤ 30 Vdc – – 1.0 – – –
5.0 mA ≤ IO ≤ 1.0 A – – 0.5 – – 0.5
15 Vdc ≤ Vin ≤ 25 Vdc, f = 120 Hz – 60 – – 60 –


MC7800 Series
MC7812B MC7812C
10 Hz ≤ f ≤ 100 kHz – 10 – – 10 –

Vin = 35 Vdc – 0.2 – – 0.2 –

ELECTRICAL CHARACTERISTICS (Vin = 19 V, IO = 10 A, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
MC7812AC
Output Voltage (TJ = 25°C) VO 11.75 12 12.25 Vdc
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W) 11.5 12 12.5
14.8 Vdc ≤ Vin ≤ 27 Vdc
14.8 Vdc ≤ Vin ≤ 30 Vdc, IO = 500 mA – 7.5 120
16 Vdc ≤ Vin ≤ 22 Vdc – 2.2 120
16 Vdc ≤ Vin ≤ 22 Vdc, TJ = 25°C – 2.2 60
14.5 Vdc ≤ Vin ≤ 27 Vdc, TJ = 25°C – 6.0 120
5.0 mA ≤ IO ≤ 1.5 A, TJ = 25°C – 1.6 100
5.0 mA ≤ IO ≤ 1.0 A – 1.2 100
250 mA ≤ IO ≤ 750 mA – 1.0 50
TJ = 25°C – 3.4 6.0

15 Vdc ≤ Vin ≤ 30 Vdc, IO = 500 mA – – 0.8
14.8 Vdc ≤ Vin ≤ 27 Vdc, TJ = 25°C – – 0.8
5.0 mA ≤ IO ≤ 1.0 A – – 0.5
15 Vdc ≤ Vin ≤ 25 Vdc, f = 120 Hz, IO = 500 mA – 60 –

10 Hz ≤ f ≤ 100 kHz – 10 –

Vin = 35 Vdc – 0.2 –


MC7800 Series
MC7815B MC7815C
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W)
17.5 Vdc ≤ Vin ≤ 30 Vdc – – – 14.25 15 15.75
18.5 Vdc ≤ Vin ≤ 30 Vdc 14.25 15 15.75 – – –
17.5 Vdc ≤ Vin ≤ 30 Vdc – 8.5 300 – 8.5 300
20 Vdc ≤ Vin ≤ 26 Vdc – 3.0 150 – 3.0 150
5.0 mA ≤ IO ≤ 1.5 A – 1.8 300 – 1.8 300
250 mA ≤ IO ≤ 750 mA – 1.2 150 – 1.2 150
17.5 Vdc ≤ Vin ≤ 30 Vdc – – – – – 1.0
18.5 Vdc ≤ Vin ≤ 30 Vdc – – 1.0 – – –
5.0 mA ≤ IO ≤ 1.0 A – – 0.5 – – 0.5
18.5 Vdc ≤ Vin ≤ 28.5 Vdc, f = 120 Hz – 58 – – 58 –

10 Hz ≤ f ≤ 100 kHz – 10 – – 10 –

Vin = 35 Vdc – 0.2 – – 0.2 –

Average Temperature Coefficient of Output Voltage TCVO – –1.0 – – –1.0 – mV/°C
MC7815AC
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W) 14.4 15 15.6
17.9 Vdc ≤ Vin ≤ 30 Vdc
17.9 Vdc ≤ Vin ≤ 30 Vdc, IO = 500 mA – 8.5 150
20 Vdc ≤ Vin ≤ 26 Vdc – 3.0 150
20 Vdc ≤ Vin ≤ 26 Vdc, TJ = 25°C – 3.0 75
17.5 Vdc ≤ Vin ≤ 30 Vdc, TJ = 25°C – 7.0 150
5.0 mA ≤ IO ≤ 1.5 A, TJ = 25°C – 1.8 100
5.0 mA ≤ IO ≤ 1.0 A – 1.5 100
250 mA ≤ IO ≤ 750 mA – 1.2 50
TJ = 25°C – 3.5 6.0

17.5 Vdc ≤ Vin ≤ 30 Vdc, IO = 500 mA – – 0.8
17.5 Vdc ≤ Vin ≤ 30 Vdc, TJ = 25°C – – 0.8
5.0 mA ≤ IO ≤ 1.0 A – – 0.5

MC7800 Series
ELECTRICAL CHARACTERISTICS (continued) (Vin = 23 V, IO = 1.0 A, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
MC7815AC
18.5 Vdc ≤ Vin ≤ 28.5 Vdc, f = 120 Hz, IO = 500 mA – 58 –

10 Hz ≤ f ≤ 100 kHz – 10 –

Vin = 35 Vdc – 0.2 –

Average Temperature Coefficient of Output Voltage TCVO – –1.0 – mV/°C
MC7818B MC7818C
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W)
21 Vdc ≤ Vin ≤ 33 Vdc – – – 17.1 18 18.9
22 Vdc ≤ Vin ≤ 33 Vdc 17.1 18 18.9 – – –
21 Vdc ≤ Vin ≤ 33 Vdc – 9.5 360 – 9.5 360
24 Vdc ≤ Vin ≤ 30 Vdc – 3.2 180 – 3.2 180
5.0 mA ≤ IO ≤ 1.5 A – 2.0 360 – 2.0 360
250 mA ≤ IO ≤ 750 mA – 1.5 180 – 1.5 180
21 Vdc ≤ Vin ≤ 33 Vdc – – – – – 1.0
22 Vdc ≤ Vin ≤ 33 Vdc – – 1.0 – – –
5.0 mA ≤ IO ≤ 1.0 A – – 0.5 – – 0.5
22 Vdc ≤ Vin ≤ 33 Vdc, f = 120 Hz – 57 – – 57 –
Dropout Voltage (IO = 1.0 A, TJ = 25°C) ViI – VO – 2.0 – – 2.0 – Vdc

10 Hz ≤ f ≤ 100 kHz – 10 – – 10 –

Vin = 35 Vdc – 0.2 – – 0.2 –

Average Temperature Coefficient of Output Voltage TCVO – –1.5 – – –1.5 – mV/°C

MC7800 Series
ELECTRICAL CHARACTERISTICS (Vin = 27 V, IO = 10 A, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)
MC7818AC
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W) 17.3 18 18.7
21 Vdc ≤ Vin ≤ 33 Vdc
21 Vdc ≤ Vin ≤ 33 Vdc, IO = 500 mA – 9.5 180
24 Vdc ≤ Vin ≤ 30 Vdc – 3.2 180
24 Vdc ≤ Vin ≤ 30 Vdc, TJ = 25°C – 3.2 90
20.6 Vdc ≤ Vin ≤ 33 Vdc, TJ = 25°C – 8.0 180
5.0 mA ≤ IO ≤ 1.5 A, TJ = 25°C – 2.0 100
5.0 mA ≤ IO ≤ 1.0 A – 1.8 100
250 mA ≤ IO ≤ 750 mA – 1.5 50
TJ = 25°C – 3.5 6.0

21 Vdc ≤ Vin ≤ 33 Vdc, IO = 500 mA – – 0.8
21 Vdc ≤ Vin ≤ 33 Vdc, TJ = 25°C – – 0.8
5.0 mA ≤ IO ≤ 1.0 A – – 0.5

10 Hz ≤ f ≤ 100 kHz – 10 –

Vin = 35 Vdc – 0.2 –

Average Temperature Coefficient of Output Voltage TCVO – –1.5 – mV/°C
MC7824B MC7824C
Output Voltage (TJ = 25°C) VO 23 24 25 23 24 25 Vdc
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W)
27 Vdc ≤ Vin ≤ 38 Vdc – – – 22.8 24 25.2
28 Vdc ≤ Vin ≤ 38 Vdc 22.8 24 25.2 – – –
27 Vdc ≤ Vin ≤ 38 Vdc – 11.5 480 – 11.5 480
30 Vdc ≤ Vin ≤ 36 Vdc – 3.8 240 – 3.8 240
5.0 mA ≤ IO ≤ 1.5 A – 2.1 480 – 2.1 480
250 mA ≤ IO ≤ 750 mA – 1.8 240 – 1.8 240

MC7800 Series
MC7824B MC7824C
27 Vdc ≤ Vin ≤ 38 Vdc – – – – – 1.0
28 Vdc ≤ Vin ≤ 38 Vdc – – 1.0 – – –
5.0 mA ≤ IO ≤ 1.0 A – – 0.5 – – 0.5
28 Vdc ≤ Vin ≤ 38 Vdc, f = 120 Hz – 54 – – 54 –

10 Hz ≤ f ≤ 100 kHz – 10 – – 10 –

Vin = 35 Vdc – 0.2 – – 0.2 –

MC7824AC
(5.0 mA ≤ IO ≤ 1.0 A, PD ≤15 W) 23 24 25
27.3 Vdc ≤ Vin ≤ 38 Vdc
27 Vdc ≤ Vin ≤ 38 Vdc, IO = 500 mA – 11.5 240
30 Vdc ≤ Vin ≤ 36 Vdc – 3.8 240
30 Vdc ≤ Vin ≤ 36 Vdc, TJ = 25°C – 3.8 120
26.7 Vdc ≤ Vin ≤ 38 Vdc, TJ = 25°C – 10 240
5.0 mA ≤ IO ≤ 1.5 A, TJ = 25°C – 2.1 100
5.0 mA ≤ IO ≤ 1.0 A – 2.0 100
250 mA ≤ IO ≤ 750 mA – 1.8 50
TJ = 25°C – 3.6 6.0

27.3 Vdc ≤ Vin ≤ 38 Vdc, IO = 500 mA – – 0.8
27.3 Vdc ≤ Vin ≤ 38 Vdc, TJ = 25°C – – 0.8
5.0 mA ≤ IO ≤ 1.0 A – – 0.5

10 Hz ≤ f ≤ 100 kHz – 10 –

Vin = 35 Vdc – 0.2 –


MC7800 Series
Figure 1. Peak Output Current as a Function of Figure 2. Ripple Rejection as a Function of

Input/Output Differential Voltage (MC78XXC, AC, B) Output Voltages (MC78XXC, AC)
3.0 80
TJ = – 40°C
2.5
I O , OUTPUT CURRENT (A)
TJ = 0°C

70
2.0 TJ = 25°C f = 120 Hz
PART # Vin IO = 20 mA
MC7805C = 10 V ∆Vin = 1.0 V(RMS)
1.5 60 MC7806C = 11 V
TJ = 85°C MC7808C = 14 V
1.0 MC7812C = 19 V
MC7815C = 23 V
50
TJ = 125°C MC7818C = 27 V
0.5 MC7824C = 33 V
0 40
4.0 6.0 8.0 10 12 15 20 25 30 35 40 4.0 6.0 8.0 10 12 14 16 18 20 22 24
Vin–Vout, INPUT/OUPUT VOLTAGE DIFFERENTIAL (V) VO, OUTPUT VOLTAGE (V)
Figure 3. Ripple Rejection as a Function of Figure 4. Output Voltage as a Function of

Frequency (MC78XXC, AC) Junction Temperature (MC7805C, AC, B)
80
Vin = 20 V

70 5.0
IO = 5.0 mA
MC78XXB, C, AC
60
Vin = 8.0 V to 18 V
IO = 500 mA
50 f = 120 Hz 4.9
TA = 25°C
40
30 4.8
0.01 0.1 1.0 10 – 60 – 20 20 60 100 140 180
f, FREQUENCY (kHz) TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Output Impedance as a Function of Figure 6. Quiescent Current as a Function of

Output Voltage (MC78XXC, AC) Temperature (MC78XXC, AC, B)
10 6.0
Vin = 10 V
Z O , OUTPUT IMPEDANCE (mΩ )
5.0 VO = 5.0 V
f = 120 Hz 4.0
3.0 IL = 20 mA
IO = 500 mA
2.0 CL = 0 µF
3.0
1.0
2.0
0.5
0.3
1.0
0.2
0.1 0
4.0 8.0 12 16 20 24 –75 –50 –25 0 25 50 75 100 125
VO, OUTPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)

MC7800 Series
Design Considerations
The MC7800 Series of fixed voltage regulators are wire lengths, or if the output load capacitance is large. An
designed with Thermal Overload Protection that shuts down input bypass capacitor should be selected to provide good
condition, Internal Short Circuit Protection that limits the under all load conditions. A 0.33 µF or larger tantalum,
maximum current the circuit will pass, and Output Transistor mylar, or other capacitor having low internal impedance at
Safe–Area Compensation that reduces the output short high frequencies should be chosen. The bypass capacitor
circuit current as the voltage across the pass transistor is should be mounted with the shortest possible leads directly
increased. across the regulators input terminals. Normally good
In many low current applications, compensation construction techniques should be used to minimize ground
capacitors are not required. However, it is recommended loops and lead resistance drops since the regulator has no
that the regulator input be bypassed with a capacitor if the external sense lead.
regulator is connected to the power supply filter with long
Input MC7805
Output
R MC7805
0.33 µF Constant Input
Current to
Grounded
IO Load 7 2
0.33 µF 6 0.1 µF
The MC7800 regulators can also be used as a current source when 3
10 k
connected as above. In order to minimize dissipation the MC7805C is 1.0 k 4
chosen in this application. Resistor R determines the current as follows: MC1741G
5.0 V
IO = + IB
R
VO = 7.0 V to 20 V
IB ^ 3.2 mA over line and load changes. VIN = VO ≥ 2.0 V

For example, a 1.0 A current source would require R to be a 5.0 Ω, intermediate values while retaining regulation characteristics. The
10 W resistor and the output voltage compliance would be the input minimum voltage obtainable with this arrangement is 2.0 V greater than the
voltage less 7.0 V. regulator voltage.
Figure 9. Current Boost Regulator Figure 10. Short Circuit Protection

MJ2955
MJ2955 or Equiv. or Equiv.
RSource RSource RSC
Input Input
0.33 µF 0.33 µF
R
MC78XX Output 2N6049
or Equiv.
R
MC78XX
≥ 10 µF 1.0 µF 1.0 µF Output
≥ 10 µF 1.0 µF
XX = 2 digits of type number indicating voltage. XX = 2 digits of type number indicating voltage.
The MC7800 series can be current boosted with a PNP transistor. The The circuit of Figure 9 can be modified to provide supply protection against
MJ2955 provides current to 5.0 A. Resistor R in conjunction with the VBE short circuits by adding a short circuit sense resistor, Rsc, and an additional
of the PNP determines when the pass transistor begins conducting; this PNP transistor. The current sensing PNP must be able to handle the short
circuit is not short circuit proof. Input/output differential voltage minimum is circuit current of the three–terminal regulator. Therefore, a four–ampere
increased by VBE of the pass transistor. plastic power transistor is specified.

MC7800 Series
Figure 11. Worst Case Power Dissipation versus Figure 12. Input Output Differential as a Function
Ambient Temperature (Case 221A) of Junction Temperature (MC78XXC, AC, B)
20 2.5
θJC = 5°C/W IO = 1.0 A
V in – V out , INPUT–OUTPUT VOLTAGE

θJA = 65°C/W
P D , POWER DISSIPATION (W)
IO = 500 mA
16 θHS = 0°C/W TJ(max) = 150°C 2.0
IO = 200 mA
DIFFERENTIAL (V)
12 θHS = 5°C/W 1.5 IO = 20 mA
IO = 0 mA
8.0 θHS = 15°C/W 1.0
4.0 0.5 ∆VO = 2% of VO

No Heatsink
– – – Extended Curve for MC78XXB
0 0
–50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

80 3.5

70 Free Air 3.0

Mounted
Vertically
ÎÎÎÎ
60 2.0 oz. Copper 2.5
L
Minimum
ÎÎÎÎ
ÎÎÎÎ
50 2.0
Size Pad L
40
30
RθJA ÎÎÎÎ 1.5
1.0
0 5.0 10 15 20 25 30
DEFINITIONS
Line Regulation – The change in output voltage for a Quiescent Current – That part of the input current that is
change in the input voltage. The measurement is made under not delivered to the load.
conditions of low dissipation or by using pulse techniques such Output Noise Voltage – The rms AC voltage at the
that the average chip temperature is not significantly affected. output, with constant load and no input ripple, measured over
Load Regulation – The change in output voltage for a a specified frequency range.
change in load current at constant chip temperature. Long Term Stability – Output voltage stability under
Maximum Power Dissipation – The maximum total accelerated life test conditions with the maximum rated
device dissipation for which the regulator will operate within voltage listed in the devices’ electrical characteristics and
specifications. maximum power dissipation.

MC78L00, A
Series
Three-Terminal Low Current
Positive Voltage Regulators
The MC78L00, A Series of positive voltage regulators are inexpensive, P SUFFIX
easy–to–use devices suitable for a multitude of applications that require a CASE 29
regulated supply of up to 100 mA. Like their higher powered MC7800 and
MC78M00 Series cousins, these regulators feature internal current limiting
and thermal shutdown making them remarkably rugged. No external Pin 1. Output
components are required with the MC78L00 devices in many applications. 2. GND
3. Input 1
These devices offer a substantial performance advantage over the 2
3
traditional zener diode–resistor combination, as output impedance and
quiescent current are substantially reduced.
• Wide Range of Available, Fixed Output Voltages D SUFFIX
PLASTIC PACKAGE
• Low Cost
8
CASE 751
• Internal Short Circuit Current Limiting 1 (SOP–8)*
• Internal Thermal Overload Protection Pin 1. Vout 5. NC

• No External Components Required 2. GND 6. GND
•
3. GND 7. GND
Complementary Negative Regulators Offered (MC79L00 Series) 4. NC 8. Vin
• Available in either ±5% (AC) or ±10% (C) Selections
* SOP–8 is an internally modified SO–8 package.
Pins 2, 3, 6, and 7 are electrically common to the die
attach flag. This internal lead frame modification
Representative Schematic Diagram decreases package thermal resistance and
increases power dissipation capability when
appropriately mounted on a printed circuit board.
Input SOP–8 conforms to all external dimensions of the
15k Q3 Q5 Q11
standard SO–8 package.
Q12
Q1
Q10
5.0k 3.0 Output Standard Application
3.8k
Q4 Q6
0–25k Input MC78LXX Output
Cin*
CO**
1.9k 19k 2.2k 0.33µF
1.2k
C Q9
Q2 Q8 A common ground is required between the input

Z1 2.85k and the output voltages. The input voltage must
Q7 remain typically 2.0 V above the output voltage even
420 during the low point on the input ripple voltage.
1.0k Ground *Cin is required if regulator is located an
*appreciable distance from power supply filter.
**CO is not needed for stability; however, it does
*improve transient response.
Operating
Device Temperature Range Package DEVICE TYPE/NOMINAL VOLTAGE
MC78LXXACD* SOP–8 10% 5% Voltage
MC78LXXACP TJ = 0° to +125°C Plastic Power MC78L05C MC78L05AC 5.0
MC78L08C MC78L08AC 8.0
MC78LXXCP Plastic Power MC78L09C MC78L09AC 9.0
MC78LXXABD* SOP–8 MC78L12C MC78L12AC 12
TJ = –40° to +125°C MC78L15C MC78L15AC 15
MC78LXXABP* Plastic Power MC78L18C MC78L18AC 18
XX indicates nominal voltage MC78L24C MC78L24AC 24
*Available in 5, 8, 9, 12 and 15 V devices.

MC78L00, A Series
Input Voltage (2.6 V–8.0 V) VI 30 Vdc
Input Voltage (12 V–18 V) 35
ELECTRICAL CHARACTERISTICS (VI = 10 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, – 40°C < TJ < +125°C (for MC78LXXAB),
0°C < TJ < +125°C (for MC78LXXAC), unless otherwise noted.)
MC78L05AC, AB MC78L05C
Output Voltage (TJ = +25°C) VO 4.8 5.0 5.2 4.6 5.0 5.4 Vdc
(TJ = +25°C, IO = 40 mA)
7.0 Vdc ≤ VI ≤ 20 Vdc – 55 150 – 55 200
8.0 Vdc ≤ VI ≤ 20 Vdc – 45 100 – 45 150
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) – 11 60 – 11 60
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) – 5.0 30 – 5.0 30
(7.0 Vdc ≤ VI ≤ 20 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 4.75 – 5.25 4.5 – 5.5
(VI = 10 V, 1.0 mA ≤ IO ≤ 70 mA) 4.75 – 5.25 4.5 – 5.5
Input Bias Current IIB mA
(TJ = +25°C) – 3.8 6.0 – 3.8 6.0
(TJ = +125°C) – – 5.5 – – 5.5
Input Bias Current Change ∆IIB mA
(8.0 Vdc ≤ VI ≤ 20 Vdc) – – 1.5 – – 1.5
(1.0 mA ≤ IO ≤ 40 mA) – – 0.1 – – 0.2
Output Noise Voltage Vn – 40 – – 40 – µV
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
Ripple Rejection (IO = 40 mA, RR 41 49 – 40 49 – dB
f = 120 Hz, 8.0 Vdc ≤ VI ≤ 18 V, TJ = +25°C)
Dropout Voltage (TJ = +25°C) VI – VO – 1.7 – – 1.7 – Vdc
(TJ = +25°C, IO = 40 mA)
10.5 Vdc ≤ VI ≤ 23 Vdc – 20 175 – 20 200
11 Vdc ≤ VI ≤ 23 Vdc – 12 125 – 12 150
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) – 15 80 – 15 80
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) – 8.0 40 – 6.0 40
(10.5 Vdc ≤ VI ≤ 23 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 7.6 – 8.4 7.2 – 8.8
(VI = 14 V, 1.0 mA ≤ IO ≤ 70 mA) 7.6 – 8.4 7.2 – 8.8
(TJ = +25°C) – 3.0 6.0 – 3.0 6.0
(TJ = +125°C) – – 5.5 – – 5.5
(11 Vdc ≤ VI ≤ 23 Vdc) – – 1.5 – – 1.5
(1.0 mA ≤ IO ≤ 40 mA) – – 0.1 – – 0.2
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
f = 120 Hz, 12 V ≤ VI ≤ 23 V, TJ = +25°C)
Dropout Voltage (TJ = +25°C) VI – VO – 1.7 – – 1.7 – Vdc

MC78L00, A Series
(TJ = +25°C, IO = 40 mA)
11.5 Vdc ≤ VI ≤ 24 Vdc – 20 175 – 20 200
12 Vdc ≤ VI ≤ 24 Vdc – 12 125 – 12 150
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) – 15 90 – 15 90
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) – 8.0 40 – 6.0 40
(11.5 Vdc ≤ VI ≤ 24 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 8.5 – 9.5 8.1 – 9.9
(VI = 15 V, 1.0 mA ≤ IO ≤ 70 mA) 8.5 – 9.5 8.1 – 9.9
(TJ = +25°C) – 3.0 6.0 – 3.0 6.0
(TJ = +125°C) – – 5.5 – – 5.5
(11 Vdc ≤ VI ≤ 23 Vdc) – – 1.5 – – 1.5
(1.0 mA ≤ IO ≤ 40 mA) – – 0.1 – – 0.2
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)

f = 120 Hz, 13 V ≤ VI ≤ 24 V, TJ = +25°C)
Dropout Voltage VI – VO – 1.7 – – 1.7 – Vdc

(TJ = +25°C)
Output Voltage (TJ = +25°C) VO 11.5 12 12.5 11.1 12 12.9 Vdc
(TJ = +25°C, IO = 40 mA)
14.5 Vdc ≤ VI ≤ 27 Vdc – 120 250 – 120 250
16 Vdc ≤ VI ≤ 27 Vdc – 100 200 – 100 200
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) – 20 100 – 20 100
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) – 10 50 – 10 50
(14.5 Vdc ≤ VI ≤ 27 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 11.4 – 12.6 10.8 – 13.2
(VI = 19 V, 1.0 mA ≤ IO ≤ 70 mA) 11.4 – 12.6 10.8 – 13.2
(TJ = +25°C) – 4.2 6.5 – 4.2 6.5
(TJ = +125°C) – – 6.0 – – 6.0
(16 Vdc ≤ VI ≤ 27 Vdc) – – 1.5 – – 1.5
(1.0 mA ≤ IO ≤ 40 mA) – – 0.1 – – 0.2
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)

f = 120 Hz, 15 V ≤ VI ≤ 25 V, TJ = +25°C)

(TJ = +25°C)

MC78L00, A Series
S 0°C < TJ < +125°C (for MC78LXXAC), unless otherwise noted.)
(TJ = +25°C, IO = 40 mA)
17.5 Vdc ≤ VI ≤ 30 Vdc – 130 300 – 130 300
20 Vdc ≤ VI ≤ 30 Vdc – 110 250 – 110 250
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) – 25 150 – 25 150
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) – 12 75 – 12 75
(17.5 Vdc ≤ VI ≤ 30 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 14.25 – 15.75 13.5 – 16.5
(VI = 23 V, 1.0 mA ≤ IO ≤ 70 mA) 14.25 – 15.75 13.5 – 16.5
(TJ = +25°C) – 4.4 6.5 – 4.4 6.5
(TJ = +125°C) – – 6.0 – – 6.0
(20 Vdc ≤ VI ≤ 30 Vdc) – – 1.5 – – 1.5
(1.0 mA ≤ IO ≤ 40 mA) – – 0.1 – – 0.2
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
f = 120 Hz, 18.5 V ≤ VI ≤ 28.5 V, TJ = +25°C)
(TJ = +25°C)
ELECTRICAL CHARACTERISTICS (VI = 27 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, 0°C < TJ < +125°C, unless otherwise noted.)
MC78L18AC MC78L18C
Line Regulation
(TJ = +25°C, IO = 40 mA)
21.4 Vdc ≤ VI ≤ 33 Vdc –
Regline 32 325 mV
20.7 Vdc ≤ VI ≤ 33 Vdc – 45 325
22 Vdc ≤ VI ≤ 33 Vdc –
27 275
21 Vdc ≤ VI ≤ 33 Vdc – 35 275
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) – 30 170 – 30 170
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) – 15 85 – 15 85
(21.4 Vdc ≤ VI ≤ 33 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 16.2 – 19.8
(20.7 Vdc ≤ VI ≤ 33 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 17.1 – 18.9
(VI = 27 V, 1.0 mA ≤ IO ≤ 70 mA) 16.2 – 19.8
(VI = 27 V, 1.0 mA ≤ IO ≤ 70 mA) 17.1 – 18.9
(TJ = +25°C) – 3.1 6.5 – 3.1 6.5
(TJ = +125°C) – – 6.0 – – 6.0
(22 Vdc ≤ VI ≤ 33 Vdc) – – 1.5
(21 Vdc ≤ VI ≤ 33 Vdc) – – 1.5
(1.0 mA ≤ IO ≤ 40 mA) – – 0.1 – – 0.2
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
f = 120 Hz, 23 V ≤ VI ≤ 33 V, TJ = +25°C)
(TJ = +25°C)

MC78L00, A Series
ELECTRICAL CHARACTERISTICS (VI = 33 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, 0°C < TJ < +125°C, unless otherwise noted.)
MC78L24AC MC78L24C
Output Voltage (TJ = +25°C) VO 23 24 25 22.1 24 25.9 Vdc
(TJ = +25°C, IO = 40 mA)
27.5 Vdc ≤ VI ≤ 38 Vdc – – – – 35 350
28 Vdc ≤ VI ≤ 80 Vdc – 50 300 – 30 300
27 Vdc ≤ VI ≤ 38 Vdc – 60 350 – – –
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) – 40 200 – 40 200
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) – 20 100 – 20 100
(28 Vdc ≤ VI ≤ 38 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 21.6 – 26.4
(27 Vdc ≤ VI ≤ 38 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 22.8 – 25.2
(28 Vdc ≤ VI = 33 Vdc, 1.0 mA ≤ IO ≤ 70 mA) 21.6 – 26.4
(27 Vdc ≤ VI ≤ 33 Vdc, 1.0 mA ≤ IO ≤ 70 mA) 22.8 – 25.2
(TJ = +25°C) – 3.1 6.5 – 3.1 6.5
(TJ = +125°C) – – 6.0 – – 6.0
(28 Vdc ≤ VI ≤ 38 Vdc) – – 1.5 – – 1.5
(1.0 mA ≤ IO ≤ 40 mA) – – 0.1 – – 0.2
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)

f = 120 Hz, 29 V ≤ VI ≤ 35 V, TJ = +25°C)

(TJ = +25°C)

MC78L00, A Series

Figure 1. Dropout Characteristics Junction Temperature
V I –V O , INPUT/OUTPUT DIFFERENTIAL VOLTAGE (V)

8.0 2.5
MC78L05C IO = 70 mA
Vout = 5.0 V
2.0
6.0 TJ = 25°C
1.5
IO = 1.0 mA
4.0
1.0 IO = 40 mA
IO = 40 mA IO = 100 mA IO = 1.0 mA
2.0 Dropout of Regulation is
0.5 defined as when
VO = 2% of VO
0 0
0 2.0 4.0 6.0 8.0 10 0 25 50 75 100 125
VI, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)

Ambient Temperature versus Input Voltage
4.2 5.0
I IB , INPUT BIAS CURRENT (mA)
4.0 I IB , INPUT BIAS CURRENT (mA)

4.0
3.8
3.0 MC78L05C
3.6
Vout = 5.0 V
IO = 40 mA
3.4 2.0 TJ = 25°C
3.2 MC78L05C
VI = 10 V 1.0
3.0 VO= 5.0 V
IO = 40 mA
0 0
0 25 50 75 100 125 0 5.0 10 15 20 25 30 35 40
TA, AMBIENT TEMPERATURE (°C) VI, INPUT VOLTAGE (V)
Figure 6. SOP–8 Thermal Resistance and Maximum

Figure 5. Maximum Average Power Dissipation versus
Ambient Temperature – TO–92 Type Package
10,000 170 3.2
150 2.8 PD, MAXIMUM POWER DISSIPATION (W)

PD, POWER DISSIPATION (mW)

No Heatsink 130 2.4

1000
ÎÎÎ ÎÎÎ
110 Graph represents symmetrical layout 2.0
90
ÎÎÎ
ÎÎÎ ÎÎÎ
2.0 oz. 1.6
ÎÎÎ ÎÎÎ
L
Copper
100 70 1.2
L 3.0 mm
RθJA = 200°C/W 50 0.8
PD(max) to 25°C = 625 mW RθJA
10 30 0.4
25 50 75 100 125 150 0 10 20 30 40 50
TA, AMBIENT TEMPERATURE (°C) L, LENGTH OF COPPER (mm)

MC78L00, A Series
Design Considerations bypass capacitor should be selected to provide good
The MC78L00 Series of fixed voltage regulators are high–frequency characteristics to insure stable operation
designed with Thermal Overload Protection that shuts down under all load conditions. A 0.33 µF or larger tantalum, mylar,
the circuit when subjected to an excessive power overload or other capacitor having low internal impedance at high
condition. Internal Short Circuit Protection limits the frequencies should be chosen.The bypass capacitor should
maximum current the circuit will pass. be mounted with the shortest possible leads directly across
In many low current applications, compensation the regulators input terminals. Good construction techniques
capacitors are not required. However, it is recommended that should be used to minimize ground loops and lead resistance
the regulator input be bypassed with a capacitor if the drops since the regulator has no external sense lead.
regulator is connected to the power supply filter with long wire Bypassing the output is also recommended.
lengths, or if the output load capacitance is large. The input
Figure 7. Current Regulator Figure 8. ± 15 V Tracking Voltage Regulator
+20V MC78L15 +VO

Input MC78L05
0.33µF 10k
7 2
R –
0.33µF Constant 6
Current to MC1741
3
Grounded Load +
IO 4
10k
0.33µF
MPS A70
The MC78L00 regulators can also be used as a current source 6.5
when connected as above. In order to minimize dissipation the 20V –VO
MPS U55
MC78L05C is chosen in this application. Resistor R determines
the current as follows:
5.0 V
IO = + IB
R
Figure 9. Positive and Negative Regulator
IIB = 3.8 mA over line and load changes
+VI MC78LXX +VO
For example, a 100 mA current source would require R to be a 0.33µF 0.1µF
50 Ω, 1/2 W resistor and the output voltage compliance would be
the input voltage less 7 V. –VI MC79LXX
0.33µF 0.1µF
–VO

MC78M00
Series
Three-Terminal
Medium Current Positive
Voltage Regulators THREE–TERMINAL MEDIUM
CURRENT POSITIVE FIXED
The MC78M00 Series positive voltage regulators are identical to the
popular MC7800 Series devices, except that they are specified for only half VOLTAGE REGULATORS
the output current. Like the MC7800 devices, the MC78M00 three–terminal
regulators are intended for local, on–card voltage regulation. SEMICONDUCTOR
Internal current limiting, thermal shutdown circuitry and safe–area TECHNICAL DATA
compensation for the internal pass transistor combine to make these devices
remarkably rugged under most operating conditions. Maximum output
current, with adequate heatsinking is 500 mA.
• No External Components Required
• Internal Thermal Overload Protection T SUFFIX
PLASTIC PACKAGE
• Internal Short Circuit Current Limiting CASE 221A
• Output Transistor Safe–Area Compensation (TO–220)
Heatsink surface
connected to Pin 2.
1
2
3
Pin 1. Input
2. Ground
Input 3. Output
1.0 k 1.0 k
210
6.7
V 16 k
100
1 1
300 1.0 k 200 2
3 3
3.6
k 3.0 k DT SUFFIX DT–1 SUFFIX
300 PLASTIC PACKAGE PLASTIC PACKAGE
10 pF
6.4
k 5.6 k CASE 369A CASE 369
0.24 (DPAK) (DPAK)
13
50 200
520
Output Heatsink surface (shown as terminal 4 in

40 case outline drawing) is connected to Pin 2.
pF
6.0 k
2.6 k
2.0 k 3.9 k ORDERING INFORMATION

Operating
6.0 2.8 k
k Gnd MC78MXXCDT*
DPAK
MC78MXXCDT–1* TJ = 0° to +125°C
This device contains 28 active transistors. MC78MXXCT
TO–220
MC78MXXBT#
TJ = – 40° to +125°C
MC78MXXBDT# DPAK
DEVICE TYPE/NOMINAL OUTPUT VOLTAGE XX Indicates nominal voltage.
MC78M05B,C 5.0 V MC78M09B,C 9.0 V MC78M18B,C 18 V * Available in 5, 8, 12 and 15 V devices.
MC78M06B,C 6.0 V MC78M12B,C 12 V MC78M20B,C 20 V
# Automotive temperature range selections are
MC78M08B,C 8.0 V MC78M15B,C 15 V MC78M24B,C 24 V available with special test conditions and
additional tests. Contact your local Motorola

MC78M00 Series

Input Voltage (5.0 V–18 V) VI 35 Vdc
Input Voltage (20 V–24V) 40
Power Dissipation (Package Limitation)

Plastic Package, T Suffix
Plastic Package, DT Suffix
Operating Junction Temperature Range TJ +150 °C
MC78M05B,C ELECTRICAL CHARACTERISTICS (VI = 10 V, IO = 350 mA, 0°C < TJ < +125°C, PD ≤ 5.0 W, unless otherwise noted.)
Line Regulation Regline – 3.0 50 mV
(TJ = 25°C, 7.0 Vdc ≤ VI ≤ 25 Vdc, IO = 200 mA)

(TJ = 25°C, 5.0 mA ≤ IO ≤ 500 mA) – 20 100
(TJ = 25°C, 5.0 mA ≤ IO ≤ 200 mA) – 10 50
(7.0 Vdc ≤ VI ≤ 25 Vdc, 5.0 mA ≤ IO ≤ 200 mA)
(7.0 Vdc ≤ VI ≤ 20 Vdc, 5.0 mA ≤ IO ≤ 350 mA)
Input Bias Current (TJ = 25°C) IIB – 3.2 6.0 mA
Quiescent Current Change ∆IIB mA
(8.0 Vdc ≤ VI ≤ 25 Vdc, IO = 200 mA) – – 0.8
(5.0 mA ≤ IO ≤ 350 mA) – – 0.5
Output Noise Voltage (TA = 25°C, 10 Hz ≤ f ≤ 100 kHz) Vn – 40 – µV
(IO = 100 mA, f = 120 Hz, 8.0 V ≤ VI ≤ 18 V) 62 – –
(IO = 300 mA, f = 120 Hz, 8.0 ≤ VI ≤ 18 V, TJ = 25°C) 62 80 –
Dropout Voltage VI–VO – 2.0 – Vdc
(TJ = 25°C)
Short Circuit Current Limit (TJ = 25°C, VI = 35 V) IOS – 50 – mA

Average Temperature Coefficient of Output Voltage ∆VO/∆T – ±0.2 – mV/°C
(IO = 5.0 mA)
Peak Output Current IO – 700 – mA

(TJ = 25°C)

MC78M00 Series

(TJ = 25°C, 5.0 mA ≤ IO ≤ 500 mA) – 20 120
(TJ = 25°C, 5.0 mA ≤ IO ≤ 200 mA) – 10 60
(8.0 Vdc ≤ VI ≤ 25 Vdc, 5.0 mA ≤ IO ≤ 200 mA)
(8.0 Vdc ≤ VI ≤ 21 Vdc, 5.0 mA ≤ IO ≤ 350 mA)
(9.0 Vdc ≤ VI ≤ 25 Vdc, IO = 200 mA) – – 0.8
(5.0 mA ≤ IO ≤ 350 mA) – – 0.5
(IO = 100 mA, f = 120 Hz, 9.0 V ≤ VI ≤ 19 V) 59 – –
(IO = 300 mA, f = 120 Hz, 9.0 V ≤ VI ≤ 19 V, TJ = 25°C) 59 80 –
(TJ = 25°C)

(IO = 5.0 mA)

(TJ = 25°C)

(TJ = 25°C, 5.0 mA ≤ IO ≤ 500 mA) – 25 160
(TJ = 25°C, 5.0 mA ≤ IO ≤ 200 mA) – 10 80
(10.5 Vdc ≤ VI ≤ 25 Vdc, 5.0 mA ≤ IO ≤ 200 mA)
(10.5 Vdc ≤ VI ≤ 23 Vdc, 5.0 mA ≤ IO ≤ 350 mA)
(10.5 Vdc ≤ VI ≤ 25 Vdc, IO = 200 mA) – – 0.8
(5.0 mA ≤ IO ≤ 350 mA) – – 0.5
(IO = 100 mA, f = 120 Hz, 11.5 V ≤VI ≤ 21.5 V) 56 – –
(IO = 300 mA, f = 120 Hz, 11.5 V ≤VI ≤ 21.5 V, TJ = 25°C) 56 80 –
(TJ = 25°C)

(IO = 5.0 mA)

(TJ = 25°C)

MC78M00 Series

(TJ = 25°C, 5.0 mA ≤ IO ≤ 500 mA) – 25 180
(TJ = 25°C, 5.0 mA ≤ IO ≤ 200 mA) – 10 90
(11.5 Vdc ≤ VI ≤ 25 Vdc, 5.0 mA ≤ IO ≤ 200 mA)
(11.5 Vdc ≤ VI ≤ 23 Vdc, 5.0 mA ≤ IO ≤ 350 mA)
(11.5 Vdc ≤ VI ≤ 25 Vdc, IO = 200 mA) – – 0.8
(5.0 mA ≤ IO ≤ 350 mA) – – 0.5
(IO = 100 mA, f = 120 Hz, 12.5 V ≤VI ≤ 22.5 V) 56 – –
(IO = 300 mA, f = 120 Hz, 12.5 V ≤VI ≤ 22.5 V, TJ = 25°C) 56 80 –
(TJ = 25°C)

(IO = 5.0 mA)

(TJ = 25°C)

(TJ = 25°C, 5.0 mA ≤ IO ≤ 500 mA) – 25 240
(TJ = 25°C, 5.0 mA ≤ IO ≤ 200 mA) – 10 120
(14.5 Vdc ≤ VI ≤ 27 Vdc, 5.0 mA ≤ IO ≤ 350 mA)

(14.5 Vdc ≤ VI ≤ 30 Vdc, IO = 200 mA) – – 0.8
(5.0 mA ≤ IO ≤ 350 mA) – – 0.5
(IO = 100 mA, f = 120 Hz, 15 V ≤VI ≤ 25 V) 55 – –
(IO = 300 mA, f = 120 Hz, 15 V ≤VI ≤ 25 V, TJ = 25°C) 55 80 –
(TJ = 25°C)

(IO = 5.0 mA)

(TJ = 25°C)

MC78M00 Series
Input Regulation Regline – 10 50 mV

(TJ = 25°C, 5.0 mA ≤ IO ≤ 500 mA) – 25 300
(TJ = 25°C, 5.0 mA ≤ IO ≤ 200 mA) – 10 150
(17.5 Vdc ≤ VI ≤ 30 Vdc, 5.0 mA ≤ IO ≤ 350 mA)

(17.5 Vdc ≤ VI ≤ 30 Vdc, IO = 200 mA) – – 0.8
(5.0 mA ≤ IO ≤ 350 mA) – – 0.5
(IO = 100 mA, f = 120 Hz, 18.5 V ≤ VI ≤ 28.5 V) 54 – –
(IO = 300 mA, f = 120 Hz, 18.5 V ≤ VI ≤ 28.5 V, TJ = 25°C) 54 70 –
(TJ = 25°C)

(IO = 5.0 mA)

(TJ = 25°C)
Line Regulation Regline – 10 50 mV
(TJ = 25°C, 21 Vdc ≤ VI ≤ 33 Vdc, IO = 200 mA)

(TJ = 25°C, 5.0 mA ≤ IO ≤ 500 mA) – 30 360
(TJ = 25°C, 5.0 mA ≤ IO ≤ 200 mA) – 10 180
(21 Vdc ≤ VI ≤ 33 Vdc, 5.0 mA ≤ IO ≤ 350 mA)

(21 Vdc ≤ VI ≤ 33 Vdc, IO = 200 mA) – – 0.8
(5.0 mA ≤ IO ≤ 350 mA) – – 0.5
(IO = 100 mA, f = 120 Hz, 22 V ≤ VI ≤ 32 V) 53 – –
(IO = 300 mA, f = 120 Hz, 22 V ≤ VI ≤ 32 V, TJ = 25°C) 53 70 –
(TJ = 25°C)

(IO = 5.0 mA)

(TJ = 25°C)

MC78M00 Series

(TJ = 25°C, 5.0 mA ≤ IO ≤ 500 mA) – 30 400
(TJ = 25°C, 5.0 mA ≤ IO ≤ 200 mA) – 10 200
Output Voltage VO 19 – 21 Vdc
(23 Vdc ≤ VI ≤ 35 Vdc, 5.0 mA ≤ IO ≤ 350 mA)

(23 Vdc ≤ VI ≤ 35 Vdc, IO = 200 mA) – – 0.8
(5.0 mA ≤ IO ≤ 350 mA) – – 0.5
(IO = 100 mA, f = 120 Hz, 24 V ≤ VI ≤ 34 V) 52 – –
(IO = 300 mA, f = 120 Hz, 24 V ≤ VI ≤ 34 V, TJ = 25°C) 52 70 –
(TJ = 25°C)

(IO = 5.0 mA)

(TJ = 25°C)
Output Voltage (TJ = 25°C) VO 23 24 25 Vdc

(TJ = 25°C, 5.0 mA ≤ IO ≤ 500 mA) – 30 480
(TJ = 25°C, 5.0 mA ≤ IO ≤ 200 mA) – 10 240
(27 Vdc ≤ VI ≤ 38 Vdc, 5.0 mA ≤ IO ≤ 350 mA)

(27 Vdc ≤ VI ≤ 38 Vdc, IO = 200 mA) – – 0.8
(5.0 mA ≤ IO ≤ 350 mA) – – 0.5
(IO = 100 mA, f = 120 Hz, 28 V ≤ VI ≤ 38 V) 50 – –
(IO = 300 mA, f = 120 Hz, 28 V ≤ VI ≤ 38 V, TJ = 25°C) 50 70 –
(TJ = 25°C)
Short Circuit Current Limit (TJ = 25°C) IOS – 50 – mA

(IO = 5.0 mA)

(TJ = 25°C)

MC78M00 Series
DEFINITIONS
Line Regulation – The change in output voltage for a Input Bias Current – That part of the input current that is
conditions of low dissipation or by using pulse techniques
Output Noise Voltage – The rms AC voltage at the output,
such that the average chip temperature is not significantly
with constant load and no input ripple, measured over a
affected.
specified frequency range.
Load Regulation – The change in output voltage for a
Long Term Stability – Output voltage stability under
accelerated life test conditions with the maximum rated
Maximum Power Dissipation – The maximum total voltage listed in the devices’ electrical characteristics and
device dissipation for which the regulator will operate within maximum power dissipation.
specifications.

100 2.4

Free Air
90 Mounted 2.0
ÎÎÎ
Vertically
2.0 oz. Copper
ÎÎÎ
80 L 1.6
Minimum
ÎÎÎ
70 Size Pad L 1.2
60
50
ÎÎÎ 0.8
0.4
RθJA
40 0
0 5.0 10 15 20 25 30
Figure 2. Worst Case Power Dissipation

versus Ambient Temperature (TO–220)
10
Infinite Heat
θHS = 10°C/W Sink
PD, POWER DISSIPATION (W)
5.0
3.0 θHS = 20°C/W
2.0
No Heat Sink
1.0
0.5
0.3
0.2 θJC = 5°C/W
PD(max) = 7.52 W
0.1
25 50 75 100 125 150

MC78M00 Series
Figure 3. Peak Output Current versus Figure 4. Dropout Voltage versus

Dropout Voltage Junction Temperature
1.0 2.5
0.9
V I –V O , DROPOUT VOLTAGE (V)

2.0
0.8 TJ = 25°C
0.7 IO = 500 mA
0.6 1.5
0.5 IO = 100 mA
0.4 TJ = 125°C 1.0 IO = 10 mA
0.3
0.2 0.5 ∆VO = 100 mV
0.1
0 0
0 5.0 10 15 20 25 30 35 40 0 25 50 75 100 125 150
VI – VO, DROPOUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)

Figure 5. Ripple Rejection versus Frequency Output Current
100 100
Iout = 50 mA
80
80
Iout = 1.5 A
60 Vout = 5.0 V Vout = 5.0 V
Vin = 10 V 60 Vin = 10 V
CO = 0 CO = 0
TJ = 25°C f = 120 Hz
40
TJ = 25°C
40
20 30
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M 0.01 0.1 0.5 1.0 10
f, FREQUENCY (Hz) IO, OUTPUT CURRENT (A)
Figure 7. Bias Current versus Figure 8. Bias Current versus

4.0 5.0
TJ = 25°C
4.0 TJ = 25°C
I B , BIAS CURRENT (mA)
I B , BIAS CURRENT (mA)
3.0
3.0
TJ = 125°C
2.0
2.0
TJ = 25°C TJ = 125°C
VO = 5.0 V
1.0 IO = 0.5 A
TJ = 125°C 1.0 VI–VO = 5.0 V
0 0
0 5.0 10 15 20 25 30 35 40 0.01 0.1 0.5 1.0 10
VI, INPUT VOLTAGE (Vdc) IO, OUTPUT CURRENT (A)

MC78M00 Series
The MC78M00 Series of fixed voltage regulators are regulator is connected to the power supply filter with long wire
designed with Thermal Overload Protection that shuts down lengths, or if the output load capacitance is large. An input
the circuit when subjected to an excessive power overload bypass capacitor should be selected to provide good high
condition, Internal Short Circuit Protection that limits the frequency characteristics to insure stable operation under all
maximum current the circuit will pass, and Output Transistor load conditions. A 0.33 µF or larger tantalum, mylar, or other
Safe–Area Compensation that reduces the output short capacitor having low internal impedance at high frequencies
circuit current as the voltage across the pass transistor is should be chosen. The bypass capacitor should be mounted
increased. with the shortest possible leads directly across the regulator’s
In many low current applications, compensation input terminals. Normally good construction techniques
capacitors are not required. However, it is recommended that should be used to minimize ground loops and lead resistance
the regulator input be bypassed with a capacitor if the drops since the regulator has no external sense lead.
VO, 7.0 V to 20 V
Input MC78M05C Vin–Vout ≥ 2.0 V
R
0.33 µF Constant Output
Current to MC78M05C
Grounded Load Input
IO
7
* 2
)
The MC78M00 regulators can also be used as a current source
0.33 µF 6 0.1 µF
when connected as above. In order to minimize dissipation the
MC78M05C is chosen in this application. Resistor R 3
10 k
determines the current as follows: 1.0 k 4
5.0 V MC1741
IO = + IIB
R
IIB = 1.5 mA over line and load changes.

The addition of an operational amplifier allows adjustment to
For example, a 500 mA current source would require R to be a higher or intermediate values while retaining regulation
5.0 Ω, 10 W resistor and the output voltage compliance would characteristics. The minimum voltage obtainable with this
be the input voltage less 7 V. arrangement is 2.0 V greater than the regulator voltage.
Figure 12. Current Boost with

MJ2955 or Equiv MJ2955

Input or Equiv.
Input RSC
R
MC78MXXC Output
2N6049
or Equiv.
1.0 µF 1.0 µF R
MC78MXXC
Output
XX = 2 digits of type number indicating voltage. 1.0 µF
XX = 2 digits of type number indicating voltage.

The MC78M00 series can be current boosted with a PNP
transistor. The MJ2955 provides current to 5.0 A. Resistor R in
The circuit of Figure 10 can be modified to provide supply
conjunction with the VBE of the PNP determines when the pass
protection against short circuits by adding a short circuit sense
transistor begins conducting; this circuit is not short circuit
resistor, Rsc, and an additional PNP transistor. The current sensing
proof. Input–output differential voltage minimum is increased
PNP must be able to handle the short circuit current of the
by VBE of the pass transistor.
three–terminal regulator .Therefore, a 4 A plastic power transistor
is specified.

MC78T00
Series
Three-Ampere Positive
Voltage Regulators
This family of fixed voltage regulators are monolithic integrated circuits
THREE–AMPERE
capable of driving loads in excess of 3.0 A. These three–terminal regulators
employ internal current limiting, thermal shutdown, and safe–area POSITIVE FIXED
compensation. Devices are available with improved specifications, including VOLTAGE REGULATORS
a 2% output voltage tolerance, on AC–suffix 5.0, 12 and 15 V device types.
Although designed primarily as a fixed voltage regulator, these devices
can be used with external components to obtain adjustable voltages and SEMICONDUCTOR
currents. This series of devices can be used with a series–pass transistor to TECHNICAL DATA
supply up to 15 A at the nominal output voltage.
• Power Dissipation: 25 W
• Output Voltage Offered in 2% and 4% Tolerance*
• Thermal Regulation is Specified T SUFFIX
PLASTIC PACKAGE
• Internal Thermal Overload Protection CASE 221A
Pin 1. Input
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) 2. Ground 1
3. Output 2
Rating Symbol Value Unit 3
Input Voltage (5.0 V – 12 V) VI 35 Vdc

Input Voltage (15 V) 40 Heatsink surface is connected to Pin 2.
Plastic Package (Note 1)
TA = +25°C PD Internally Limited
TC = +25°C PD Internally Limited
Storage Junction Temperature Tstg +150 °C
(MC78T00C, AC)
MC78T05 5.0 V MC78T12 12 V
NOTES: 1. Although power dissipation is internally limited, specifications apply only
MC78T08 8.0 V MC78T15 15 V
for PO ≤ Pmax, Pmax = 25 W.
Simplified Application Operating

VO Temperature
Device Tol. Range Package
Input MC78TXX Output
MC78TXXCT 4% TJ = 0° to Plastic
Cin* +125°C Power
MC78TXXACT 2%*
0.33µF CO**
MC78TXXBT# 4% TJ = – 40° to Plastic
MC78TXXABT# 2%* +125°C Power
A common ground is required between the input and the output voltages. The input voltage must XX Indicates nominal voltage.
remain typically 2.2 V above the output voltage even during the low point on the input ripple voltage. * 2% regulators available in 5, 12 and 15 V devices.
XX these two digits of the type number indicate voltage. # Automotive temperature range selections are avail-
** Cin is required if regulator is located an appreciable distance from power supply filter. able with special test conditions and additional
** (See Applications Information for details.) tests. Contact your local Motorola sales office for
** CO is not needed for stability; however, it does improve transient response. information.

MC78T00 Series
ELECTRICAL CHARACTERISTICS (Vin = 10 V, IO = 3.0 A, 0°C ≤ TJ ≤ 125°C, PO ≤ Pmax [Note 1], unless otherwise noted.)
MC78T05AC MC78T05C
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) 4.9 5.0 5.1 4.8 5.0 5.2
(5.0 mA ≤ IO ≤ 3.0 A; 4.8 5.0 5.2 4.75 5.0 5.25
5.0 mA ≤ IO ≤ 2.0 A, 7.3 Vdc ≤ Vin ≤ 20 Vdc)
Line Regulation (Note 2) Regline – 3.0 25 – 3.0 25 mV
(7.2 Vdc ≤ Vin ≤ 35 Vdc, IO = 5.0 mA, TJ = +25°C;
7.2 Vdc ≤ Vin ≤ 35 Vdc, IO = 1.0 A, TJ = +25°C;
7.5 Vdc ≤ Vin ≤ 20 Vdc, IO = 1.0 A)
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) – 10 30 – 10 30
(5.0 mA ≤ IO ≤ 3.0 A) – 15 80 – 15 80
(Pulse = 10 ms, P = 20 W, TA = +25°C)
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) – 3.5 5.0 – 3.5 5.0
(5.0 mA ≤ IO ≤ 3.0 A) – 4.0 6.0 – 4.0 6.0
Quiescent Current Change ∆IB – 0.3 1.0 – 0.3 1.0 mA
5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C;
7.5 Vdc ≤ Vin ≤ 20 Vdc, IO = 1.0 A)
(8.0 Vdc ≤ Vin ≤ 18 Vdc, f = 120 Hz,
IO = 2.0 A, TJ = 25°C)
Dropout Voltage (IO = 3.0 A, TJ = +25°C) Vin–VO – 2.2 2.5 – 2.2 2.5 Vdc
Output Noise Voltage Vn – 10 – – 10 – µV/VO
(10 Hz ≤ f ≤ 100 kHz, TJ = +25°C)
Output Resistance (f = 1.0 kHz) RO – 2.0 – – 20 – mΩ

Short Circuit Current Limit ISC – 1.5 – – 1.5 – A
(Vin = 35 Vdc, TJ = +25°C)
Peak Output Current (TJ = +25°C) Imax – 5.0 – – 5.0 – A

Average Temperature Coefficient of Output Voltage TCVO – 0.2 – – 0.2 – mV/°C
(IO = 5.0 mA)
NOTES: 1. Although power dissipation is internally limited, specifications apply only for PO ≤ Pmax, Pmax = 25 W.
2. Line and load regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately.

MC78T00 Series
MC78T08C
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) 7.7 8.0 8.3
(5.0 mA ≤ IO ≤ 3.0 A; 7.6 8.0 8.4
5.0 mA ≤ IO ≤ 2.0 A, 10.4 Vdc ≤ Vin ≤ 23 Vdc)
Line Regulation (Note 2) Regline – 4.0 35 mV
(10.3 Vdc ≤ Vin ≤ 35 Vdc, IO = 5.0 mA, TJ = +25°C
10.3 Vdc ≤ Vin ≤ 35 Vdc, IO = 1.0 A, TJ = +25°C
11 Vdc ≤ Vin ≤ 17 Vdc, IO = 3.0 A, TJ = +25°C
10.7 Vdc ≤ Vin ≤ 23 Vdc, IO = 1.0 A)
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) – 10 30
(5.0 mA ≤ IO ≤ 3.0 A) – 15 80
Thermal Regulation Regtherm – 0.002 0.03 %VO/W
(Pulse = 10 ms, P = 20 W, TA = +25°C)
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) – 3.5 5.0
(5.0 mA ≤ IO ≤ 3.0 A) – 4.0 6.0
Quiescent Current Change ∆IB – 0.3 1.0 mA
5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C;
10.7 Vdc ≤ Vin ≤ 23 Vdc, IO = 1.0 A)
(11 Vdc ≤ Vin ≤ 21 Vdc, f = 120 Hz, IO = 2.0 A, TJ = 25°C)
Dropout Voltage (IO = 3.0 A, TJ = +25°C) Vin–VO – 2.2 2.5 Vdc

Output Noise Voltage Vn – 10 – µV/VO
(10 Hz ≤ f ≤ 100 kHz, TJ = +25°C)
Output Resistance (f = 1.0 kHz) RO – 2.0 – mΩ

Short Circuit Current Limit ISC – 1.5 – A
(Vin = 35 Vdc, TJ = +25°C)
Peak Output Current (TJ = +25°C) Imax – 5.0 – A

Average Temperature Coefficient of Output Voltage (IO = 5.0 mA) TCVO – 0.3 – mV/°C

MC78T00 Series
MC78T12AC MC78T12C
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) 11.75 12 12.25 11.5 12 12.5
(5.0 mA ≤ IO ≤ 3.0 A, 11.5 12 12.5 11.4 12 12.6
5.0 mA ≤ IO ≤ 2.0 A, 14.5 Vdc ≤ Vin ≤ 27 Vdc)
16 Vdc ≤ Vin ≤ 22 Vdc, IO = 3.0 A, TJ = +25°C;
14.9 Vdc ≤ Vin ≤ 27 Vdc, IO = 1.0 A)
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) – 10 30 – 10 30
(5.0 mA ≤ IO ≤ 3.0 A) – 15 80 – 15 80
(Pulse = 10 ms, P = 20 W, TA = +25°C)
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) – 3.5 5.0 – 3.5 5.0
(5.0 mA ≤ IO ≤ 3.0 A) – 4.0 6.0 – 4.0 6.0
5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C;
14.9 Vdc ≤ Vin ≤ 27 Vdc, IO = 1.0 A)
(15 Vdc ≤ Vin ≤ 25 Vdc, f = 120 Hz,
IO = 2.0 A, TJ = 25°C)
Dropout Voltage (IO = 3.0 A, TJ = +25°C) Vin – VO – 2.2 2.5 – 2.2 2.5 Vdc
(10 Hz ≤ f ≤ 100 kHz, TJ = +25°C)

(Vin = 35 Vdc, TJ = +25°C)

Average Temperature Coefficient TCVO – 0.5 – – 0.5 – mV/°C
of Output Voltage (IO = 5.0 mA)

MC78T00 Series
MC78T15AC MC78T15C
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) 14.7 15 15.3 14.4 15 15.6
(5.0 mA ≤ IO ≤ 3.0 A; 14.4 15 15.6 14.25 15 15.75
5.0 mA ≤ IO ≤ 2.0 A, 17.5 Vdc ≤ Vin ≤ 30 Vdc)
20 Vdc ≤ Vin ≤ 26 Vdc, IO = 3.0 A, TJ = +25°C;
18 Vdc ≤ Vin ≤ 30 Vdc, IO = 1.0 A)
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) – 10 30 – 10 30
(5.0 mA ≤ IO ≤ 3.0 A) – 15 80 – 15 80
(Pulse = 10 ms, P = 20 W, TA = +25°C)
(5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) – 3.5 5.0 – 3.5 5.0
(5.0 mA ≤ IO ≤ 3.0 A) – 4.0 6.0 – 4.0 6.0
5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C;
18 Vdc ≤ Vin ≤ 30 Vdc, IO = 1.0 A)
(18.5 Vdc ≤ Vin ≤ 28.5 Vdc, f = 120 Hz,
IO = 2.0 A, TJ = 25°C)
Dropout Voltage (IO = 3.0 A, TJ = +25°C) Vin–VO – 2.2 2.5 – 2.2 2.5 Vdc
(10 Hz ≤ f ≤ 100 kHz, TJ = +25°C)

(Vin = 40 Vdc, TJ = +25°C)

Average Temperature Coefficient of Output Voltage TCVO – 0.6 – – 0.6 – mV/°C
(IO = 5.0 mA)

MC78T00 Series
The performance of a voltage regulator is specified by its can be caused by a change in either the input voltage or the
immunity to changes in load, input voltage, power dissipation, load current. Thermal regulation is a function of IC layout and
and temperature. Line and load regulation are tested with a die attach techniques, and usually occurs within 10 ms of a
pulse of short duration (< 100µs) and are strictly a function of change in power dissipation. After 10 ms, additional changes
electrical gain. However, pulse widths of longer duration (> in the output voltage are due to the temperature coefficient of
1.0 ms) are sufficient to affect temperature gradients across the device.
the die. These temperature gradients can cause a change in Figure 1 shows the line and thermal regulation response of
the output voltage, in addition to changes caused by line and a typical MC78T05AC to a 20 W input pulse. The variation of
load regulation. Longer pulse widths and thermal gradients the output voltage due to line regulation is labeled ➀ and the
make it desirable to specify thermal regulation. thermal regulation component is labeled ➁. Figure 2 shows
Thermal regulation is defined as the change in output the load and thermal regulation response of a typical
voltage caused by a change in dissipated power for a MC78T05AC to a 20 W load pulse. The output voltage
specified time, and is expressed as a percentage output variation due to load regulation is labeled ➀ and the thermal
voltage change per watt. The change in dissipated power regulation component is labeled ➁.
Figure 1. MC78T05AC Line and Thermal Regulation Figure 2. MC78T05AC Load and Thermal Regulation
V in , INPUT VOLTAGE DEVIATION (V)

2 2
∆ V O , OUTPUT
I O , OUTPUT ∆ V O , OUTPUT
2 1
(2.0 mV/DIV)
1 2
18
VOLTAGE (V)
(2.0 mV/DIV)
CURRENT (A) 2.0
8.0 0

Vin = 8.0 V → 18 V → 8.0 V Vin = 15
Iout = 2.0 A 2 = Regtherm = 0.0015%VO/W Iout = 0 A → 2.0 A → 0 A 2 = Regtherm = 0.0015%VO/W
1.0k 1.0k Input

Q1
Q2 Q21
Q20 210
Q22 6.7V
16k
Q24 100
Q9 Q25
1.0k 200 Q26
300 Q8 Q27
3.0k
Q3 3.6k 10pF
Q4 Q19 Q23
5.6k 300
Q5 6.4k Q16 13 0.12
Q10
50 200 Output
520
Q12 40
pF
2.6k 8.0–15 VO
6.0k Q17 Q18
5.0 VO
2.0k 3.9k
Q6 Q7
Q11 Q13 Q15
6.0k 2.8k Gnd

Q14

MC78T00 Series

1.02 100
NORMALIZED OUTPUT VOLTAGE
r O , OUTPUT IMPEDANCE ( Ω )
Vin – Vout = 10 V 10–1
Iout = 100 mA
Vout = 5.0 V
Vin = 7.5 V
1.0 10–2 Iout = 1.0 A
CO = 0
TJ = 25°C
10–3
.98 10–4
–90 –50 –10 30 70 110 150 190 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M

Figure 5. Ripple Rejection versus Frequency Output Current
100 100
Iout = 50 mA RR, RIPPLE REJECTION (dB)

80 80
Iout = 1.5 A
60 Vout = 5.0 V Vout = 5.0 V

Vin = 10 V 60 Vin = 10 V
CO = 0 CO = 0
TJ = 25°C f = 120 Hz
40 TJ = 25°C
40
20 30
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M 0.01 0.1 1.0 10

4.0 5.0
TJ = 0°C
TJ = 25°C
4.0 TJ = 0°C
3.0 TJ = 125°C
TJ = 25°C
3.0 TJ = 125°C
2.0
2.0
1.0 TJ = 0°C 1.0 Vin–Vout = 5.0 V

TJ = 25°C
TJ = 125°C
0 0
0 10 20 30 40 0.01 0.1 1.0 10

MC78T00 Series
Figure 9. Dropout Voltage Figure 10. Peak Output Current

2.5 8.0
I max, PEAK OUTPUT CURRENT (A)

Iout = 3.0 A
VOLTAGE DIFFERENTIAL (Vdc)
V in –Vout , INPUT TO OUTPUT
2.0 6.0
Iout = 1.0 A
1.5 4.0
Iout = 0.5 A
1.0 2.0 TJ = 0°C
∆VO = 50 mV TJ = 25°C
TJ = 125°C
0.5 0
–90 –50 –10 30 70 110 150 190 0 10 20 30 40
TJ, JUNCTION TEMPERATURE (°C) Vin–VO, INPUT–OUTPUT VOLTAGE (Vdc)
∆ V out , OUTPUT VOLTAGE
I out , OUTPUT ∆ V out , OUTPUT VOLTAGE

0.8 0.3
0.6 Vout = 5.0 V 0.2 Vin = 10 V
DEVIATION (V)
Iout = 150 mA
DEVIATION (V)
CO = 0
0.4 CO = 0 0.1 TJ = 25°C
0.2 TJ = 25°C 0
0 –0.1
–0.2 –0.2
–0.4 –0.3
–0.6 1.5
CURRENT (A)
1.0 1.0
CHANGE (V)
0.5 0.5
0 0
0 10 20 30 40 0 10 20 30 40
Figure 13. Maximum Average Power

P D(AV) , MAXIMUM AVERAGE POWER DISSIPATION (W)
Dissipation for MC78T00CT, ACT

40
Maximum Ambient
θSA of Heatsinks Temperature
30
2.4°C/W 1.3°C/W
Infinite
20 Heatsink
3.3°C/W
10 6.3°C/W
10.5°C
0
25 50 75 100 125

MC78T00 Series
The MC78T00 Series of fixed voltage regulators are lengths, or if the output load capacitance is large. An input
designed with Thermal Overload Protection that shuts down bypass capacitor should be selected to provide good high
the circuit when subjected to an excessive power overload frequency characteristics to insure stable operation under all
condition, Internal Short Circuit Protection that limits the load conditions. A 0.33 µF or larger tantalum, mylar, or other
maximum current the circuit will pass, and Output Transistor capacitor having low internal impedance at high frequencies
Safe–Area Compensation that reduces the output short should be chosen. The bypass capacitor should be mounted
circuit current as the voltage across the pass transistor is with the shortest possible leads directly across the regulator’s
increased. input terminals. Normally good construction techniques
In many low current applications, compensation should be used to minimize ground loops and lead resistance
capacitors are not required. However, it is recommended that drops since the regulator has no external sense lead.
the regulator input be bypassed with a capacitor if the
Input MC78T05
Output
R MC78T05
0.33µF Input
Constant
Current to
IO Grounded Load
7 2
The MC78T05 regulator can also be used as a current source when –
connected as above. In order to minimize dissipation the MC78T05 is 0.33µF 6 0.1µF
chosen in this application. Resistor R determines the current
as follows: 3
+ 10k
5.0 V 1.0k
IO = R + IB 4
MC1741
^
∆IB 0.7 mA over line, load and Temperature changes
^
IB 3.5 mA
VO, 8.0 V to 20 V
Vin – VO ≥ 2.5 V
For example, a 2.0 A current source would require R to be a 2.5 Ω,
10 W resistor and the output voltage compliance would be the input The addition of an operational amplifier allows adjustment to higher or
voltage less 7.0 V. intermediate values while retaining regulation characteristics. The
Figure 17. Current Boost With

2N4398
2N4398 or Equiv or Equiv.
Input Rsc
R
MC78TXX Output MJ2955
or Equiv.
R
MC78TXX
1.0µF
XX = 2 digits of type number indicating voltage.
The MC78T00 series can be current boosted with a PNP transistor. The XX = 2 digits of type number indicating voltage.
2N4398 provides current to 15 A. Resistor R in conjuction with the VBE of
The circuit of Figure 17 can be modified to provide supply protection
the PNP determines when the pass transistor begins conducting; this
against short circuits by adding a short circuit sense resistor, RSC, and
circuit is not short circuit proof. Input–output differential voltage
an additional PNP transistor. The current sensing PNP must be able to
minimum is increased by the VBE of the pass transistor.
handle the short circuit current of the three–terminal regulator.
Therefore, an eight–ampere power transistor is specified.

MC78BC00
Series
Product Preview
Micropower Voltage Regulator
The MC78BC00 voltage regulators are specifically designed to be used
with an external power transistor to deliver high current with high voltage VOLTAGE REGULATOR
accuracy and low quiescent current. WITH EXTERNAL POWER
The MC78BC00 series are devices suitable for constructing regulators
with ultra–low dropout voltage and output current in the range of several tens TRANSISTOR
of mA to hundreds of mA. These devices have a chip enable function, which
minimizes the standby mode current drain. Each of these devices contains a SEMICONDUCTOR
voltage reference unit, an error amplifier, a driver transistor and resistors. TECHNICAL DATA
These devices are available in the SOT–23, 5 pin surface mount packages.
These devices are ideally suited for battery powered equipment, and
power sources for hand–held audio instruments, communication equipment
and domestic appliances.
MC78BC00 Series Features:
• Ultra–Low Supply Current (50 µA) 5
• Standby Mode (0.2 µA)
• Ultra–Low Dropout Voltage (0.1 V with External Transistor and 1
IO = 100 mA)
• Excellent Line Regulation (Typically 0.1%/V)
N SUFFIX
• High Accuracy Output Voltage (±2.5%) PLASTIC PACKAGE
CASE 1212
(SOT–23)
Output Operating
MC78BC30NTR 3.0 PIN CONNECTIONS
MC78BC33NTR 3.3
TA = –30° to +80°C SOT–23
MC78BC40NTR 4.0
MC78BC50NTR 5.0 Ground 1 5 CE
Other voltages from 2.0 to 6.0 V, in 0.1 V increments, are available upon request. Consult your
local Motorola sales office for information. Input 2
Output 3 4 EXT
Representative Block Diagram (Top View)
EXT 4
2 3
Vin Vout
Input Output
Vref
MC78BCXX
1 Cin CO
Gnd
CE 5

MC78FC00
Series
Product Preview
The MC78FC00 series voltage regulators are specifically designed for
use as a power source for video instruments, handheld communication MICROPOWER ULTRA–LOW
equipment, and battery powered equipment. QUIESCENT CURRENT
The MC78FC00 series voltage regulator ICs feature a high accuracy
output voltage and ultra–low quiescent current. Each device contains a VOLTAGE REGULATORS
voltage reference unit, an error amplifier, a driver transistor, and resistors for
setting output voltage, and a current limit circuit. These devices are available SEMICONDUCTOR
in SOT–89 surface mount packages, and allow construction of an efficient, TECHNICAL DATA
constant voltage power supply circuit.
MC78FC00 Series Features:
• Ultra–Low Quiescent Current of 1.1 µA Typical
• Ultra–Low Dropout Voltage (0.5 V Typical)
• Large Output Current (120 mA Typical)
•
TAB
Excellent Line Regulation (0.1%)
• Wide Operating Voltage Range (2.0 V to 10 V) 1

• Wide Output Voltage Range (2.0 V to 6.0 V) H SUFFIX
• Surface Mount Package (SOT–89) PLASTIC PACKAGE
CASE 1213
(SOT–89)
Output Operating
MC78FC30HT1 3.0
MC78FC33HT1 3.3
TA = –30° to +80°C SOT–89 PIN CONNECTIONS
MC78FC40HT1 4.0
MC78FC50HT1 5.0
local Motorola sales office for information. Reset 1
Input 2 Tab
Representative Block Diagram Ground 3 (Tab is connected
to Pin 2)
2 3 (Top View)
Vin Vout
Input Output
Vref MC78FCXX
Cin CO
1
Gnd

MC78LC00
Product Preview Series
The MC78LC00 series voltage regulators are specifically designed for
use as a power source for video instruments, handheld communication MICROPOWER ULTRA–LOW
equipment, and battery powered equipment.
The MC78LC00 series features an ultra–low quiescent of 1.1 µA and a
QUIESCENT CURRENT
high accuracy output voltage. Each device contains a voltage reference, an VOLTAGE REGULATORS
error amplifier, a driver transistor and resistors for setting the output voltage.
These devices are available in either SOT–89, 3 pin, or SOT–23, 5 pin, SEMICONDUCTOR
surface mount packages.
TECHNICAL DATA
MC78LC00 Series Features:
• Low Quiescent Current of 1.1 µA Typical
• Low Dropout Voltage (30 mV Typical)
• Excellent Line Regulation (0.1%) TAB
• Wide Output Voltage Range (2.0 V to 6.0 V) 1
• Output Current for Low Power (80 mA Typical)

• Two Surface Mount Packages (SOT–89, 3 Pin, or SOT–23, 5 Pin)
H SUFFIX
PLASTIC PACKAGE
CASE 1213
ORDERING INFORMATION (SOT–89)
Output Operating
Device Voltage Temperature Range Package Ground 1
MC78LC30HT1 3.0
Input 2 Tab
MC78LC33HT1 3.3
SOT–89 (Tab is connected
MC78LC40HT1 4.0 Output 3
MC78LC50HT1 5.0 to Pin 2)
30° to +80°C
TA = –30° (Top View)
MC78LC30NTR 3.0
MC78LC33NTR 3.3
SOT–23
MC78LC40NTR 4.0 5
MC78LC50NTR 5.0
1
local Motorola sales office for information.
N SUFFIX
PLASTIC PACKAGE
CASE 1212
(SOT–23)
Representative Block Diagram
Ground 1 5 N/C
2 3
Vin Vout Input 2
Output 3 4 N/C
(Top View)
Vref Input Output

MC78LCXX
1
Gnd Cin CO

MC7900
Series
Three-Terminal Negative
Voltage Regulators
The MC7900 series of fixed output negative voltage regulators are THREE–TERMINAL
intended as complements to the popular MC7800 series devices. These
negative regulators are available in the same seven–voltage options as the NEGATIVE FIXED
MC7800 devices. In addition, one extra voltage option commonly employed VOLTAGE REGULATORS
in MECL systems is also available in the negative MC7900 series.
Available in fixed output voltage options from – 5.0 V to – 24 V, these
regulators employ current limiting, thermal shutdown, and safe–area
compensation – making them remarkably rugged under most operating
conditions. With adequate heatsinking they can deliver output currents in
T SUFFIX
excess of 1.0 A.
PLASTIC PACKAGE
• No External Components Required CASE 221A
Heatsink surface
connected to Pin 2.
• Output Transistor Safe–Area Compensation 1
• Available in 2% Voltage Tolerance (See Ordering Information) 2
3
Pin 1. Ground
2. Input
3. Output
Gnd
D2T SUFFIX
14.7 k
2.4 k
2.0 k
2.0 k 8.0 k PLASTIC PACKAGE

CASE 936
25
(D2PAK) 1 2
3.6 k 1.0 k 4.0 k R1
4.0 k
3
1.2 k Heatsink surface (shown as terminal 4 in
12 k
1.0 k
1.6 k
R2
10 k VO STANDARD APPLICATION
20 pF
Input MC79XX Output
10 pF 10 k
Cin*
CO**
20 k 20 k 240 0.33 µF
2.0 k
0.3 1.0 µF
1.1 k
750
VI
and the output voltages. The input voltage must
remain typically 2.0 V above more negative even
ORDERING INFORMATION during the high point of the input ripple voltage.
Output Voltage Operating
XX, These two digits of the type number
Device Tolerance Temperature Range Package
indicate nominal voltage.
MC79XXACD2T 2% ** Cin is required if regulator is located an
Surface Mount appreciable distance from power supply filter.
MC79XXCD2T 4% ** CO improve stability and transient response.
TJ = 0° to +125°C
MC79XXACT 2%
Insertion Mount
MC79XXCT 4%
MC79XXBD2T Surface Mount
4% TJ = – 40° to +125°C MC7905 5.0 V MC7912 12 V
MC79XXBT Insertion Mount MC7905.2 5.2 V MC7915 15 V
XX indicates nominal voltage. MC7906 6.0 V MC7918 28 V
MC7908 8.0 V MC7924 24 V

MC7900

Input Voltage (– 5.0 V ≥ VO ≥ –18 V) VI – 35 Vdc
Input Voltage (24 V) – 40
Power Dissipation
Case 221A
Case 936 (D2PAK)
Storage Junction Temperature Range Tstg – 65 to +150 °C
THERMAL CHARACTERISTICS
Characteristics Symbol Max Unit
MC7905C
ELECTRICAL CHARACTERISTICS (VI = –10 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.)
Output Voltage (TJ = +25°C) VO – 4.8 – 5.0 – 5.2 Vdc
(TJ = +25°C, IO = 100 mA)
–7.0 Vdc ≥ VI ≥ – 25 Vdc – 7.0 50
– 8.0 Vdc ≥ VI ≥ –12 Vdc – 2.0 25
(TJ = +25°C, IO = 500 mA)
–7.0 Vdc ≥ VI ≥ – 25 Vdc – 35 100
– 8.0 Vdc ≥ VI ≥ –12 Vdc – 8.0 50
Load Regulation, TJ = +25°C (Note 1) Regload mV
5.0 mA ≤ IO ≤ 1.5 A – 11 100
250 mA ≤ IO ≤ 750 mA – 4.0 50
–7.0 Vdc ≥ VI ≥ – 20 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, P ≤ 15 W – 4.75 – – 5.25
Input Bias Current (TJ = +25°C) IIB – 4.3 8.0 mA

–7.0 Vdc ≥ VI ≥ – 25 Vdc – – 1.3
5.0 mA ≤ IO ≤ 1.5 A – – 0.5
Output Noise Voltage (TA = +25°C, 10 Hz ≤ f ≤ 100 kHz) Vn – 40 – µV
Ripple Rejection (IO = 20 mA, f = 120 Hz) RR – 70 – dB
Dropout Voltage VI–VO Vdc
IO = 1.0 A, TJ = +25°C – 2.0 –
Average Temperature Coefficient of Output Voltage ∆VO/∆T mV/°C

IO = 5.0 mA, 0°C ≤ TJ ≤ +125°C – –1.0 –
NOTE: 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately.
NOTE: 1. Pulse testing with low duty cycle is used.

MC7900
MC7905AC
– 8.0 Vdc ≥ VI ≥ –12 Vdc; IO = 1.0 A, TJ = +25°C – 2.0 25
– 8.0 Vdc ≥ VI ≥ –12 Vdc; IO = 1.0 A – 7.0 50
–7.5 Vdc ≥ VI ≥ – 25 Vdc; IO = 500 mA – 7.0 50
–7.0 Vdc ≥ VI ≥ – 20 Vdc; IO = 1.0 A, TJ = +25°C – 6.0 50
5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C – 11 100
250 mA ≤ IO ≤ 750 mA – 4.0 50
5.0 mA ≤ IO ≤ 1.0 A – 9.0 100
Input Bias Current IIB – 4.4 8.0 mA

–7.5 Vdc ≥ VI ≥ – 25 Vdc – – 1.3
5.0 mA ≤ IO ≤ 1.0 A – – 0.5
5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C – – 0.5
Ripple Rejection (IO = mA, f = 120 Hz) RR – 70 – dB
IO = 1.0 A. TJ = +25°C – 2.0 –

IO = 5.0 A, 0°C ≤ TJ ≤ +125°C – –1.0 –
MC7905.2C
(TJ = +25°C, IO = 100 mA)
–7.2 Vdc ≥ VI ≥ – 25 Vdc – 8.0 52
– 8.0 Vdc ≥ VI ≥ –12 Vdc – 2.2 27
(TJ = +25°C, IO = 500 mA)
–7.2 Vdc ≥ VI ≥ – 25 Vdc – 37 105
– 8.0 Vdc ≥ VI ≥ –12 Vdc – 8.5 52
5.0 mA ≤ IO ≤ 1.5 A – 12 105
250 mA ≤ IO ≤ 750 mA – 4.5 52

–7.2 Vdc ≥ VI ≥ – 25 Vdc – – 1.3
5.0 mA ≤ IO ≤ 1.5 A – – 0.5
IO = 1.0 A, TJ = +25°C – 2.0 –

IO = 5.0 mA, 0°C ≤ TJ ≤ +125°C – –1.0 –

MC7900
MC7906C
(TJ = +25°C, IO = 100 mA)
– 8.0 Vdc ≥ VI ≥ – 25 Vdc – 9.0 60
–9.0 Vdc ≥ VI ≥ –13 Vdc – 3.0 30
(TJ = +25°C, IO = 500 mA)
– 8.0 Vdc ≥ VI ≥ – 25 Vdc – 43 120
– 9.0 Vdc ≥ VI ≥ –13 Vdc – 10 60
5.0 mA ≤ IO ≤ 1.5 A – 13 120
250 mA ≤ IO ≤ 750 mA – 5.0 60
– 8.0 Vdc ≥ VI ≥ – 21 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, P ≤ 15 W – 5.7 – – 6.3

– 8.0 Vdc ≥ VI ≥ – 25 Vdc – – 1.3
5.0 mA ≤ IO ≤ 1.5 A – – 0.5
IO = 1.0 A, TJ = +25°C – 2.0 –

IO = 5.0 A, 0°C ≤ TJ ≤ +125°C – –1.0 –
MC7908C
Output Voltage (TJ = +25°C) VO –7.7 – 8.0 – 8.3 Vdc
(TJ = +25°C, IO = 100 mA)
–10.5 Vdc ≥ VI ≥ –25 Vdc – 12 80
–11 Vdc ≥ VI ≥ –17 Vdc – 5.0 40
(TJ = +25°C, IO = 500 mA)
–10.5 Vdc ≥ VI ≥ –25 Vdc – 50 160
–11 Vdc ≥ VI ≥ –17 Vdc – 22 80
5.0 mA ≤ IO ≤ 1.5 A – 26 160
250 mA ≤ IO ≤ 750 mA – 9.0 80
–10.5 Vdc ≥ VI ≥ – 23 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, P ≤ 15 W –7.6 – – 8.4

–10.5 Vdc ≥ VI ≥ – 25 Vdc – – 1.0
5.0 mA ≤ IO ≤ 1.5 A – – 0.5
IO = 1.0 A, TJ = +25°C – 2.0 –

IO = 5.0 mA, 0°C ≤ TJ ≤ +125°C – –1.0 –

MC7900
MC7912C
Output Voltage (TJ = +25°C) VO –11.5 –12 –12.5 Vdc
(TJ = +25°C, IO = 100 mA)
–14.5 Vdc ≥ VI ≥ – 30 Vdc – 13 120
–16 Vdc ≥ VI ≥ – 22 Vdc – 6.0 60
(TJ = +25°C, IO = 500 mA)
–14.5 Vdc ≥ VI ≥ – 30 Vdc – 55 240
–16 Vdc ≥ VI ≥ – 22 Vdc – 24 120
5.0 mA ≤ IO ≤ 1.5 A – 46 240
250 mA ≤ IO ≤ 750 mA – 17 120
–14.5 Vdc ≥ VI ≥ – 27 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, P ≤ 15 W –11.4 – –12.6

–14.5 Vdc ≥ VI ≥ – 30 Vdc – – 1.0
5.0 mA ≤ IO ≤ 1.5 A – – 0.5
IO = 1.0 A, TJ = +25°C – 2.0 –

IO = 5.0 mA, 0°C ≤ TJ ≤ +125°C – –1.0 –
MC7912AC
–16 Vdc ≥ VI ≥ – 22 Vdc; IO = 1.0 A, TJ = +25°C – 6.0 60
–16 Vdc ≥ VI ≥ – 22 Vdc; IO = 1.0 A – 24 120
–14.8 Vdc ≥ VI ≥ – 30 Vdc; IO = 500 mA – 24 120
–14.5 Vdc ≥ VI ≥ – 27 Vdc; IO = 1.0 A, TJ = +25°C – 13 120
5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C – 46 150
250 mA ≤ IO ≤ 750 mA – 17 75
5.0 mA ≤ IO ≤ 1.0 A – 35 150

–15 Vdc ≥ VI ≥ – 30 Vdc – – 0.8
5.0 mA ≤ IO ≤ 1.0 A – – 0.5
5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C – – 0.5
IO = 1.0 A, TJ = +25°C – 2.0 –

IO = 5.0 A, 0°C ≤ TJ ≤ +125°C – –1.0 –

MC7900
MC7915C
ELECTRICAL CHARACTERISTICS (VI = – 23 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.)
(TJ = +25°C, IO = 100 mA)
–17.5 Vdc ≥ VI ≥ – 30 Vdc – 14 150
–20 Vdc ≥ VI ≥ – 26 Vdc – 6.0 75
(TJ = +25°C, IO = 500 mA)
–17.5 Vdc ≥ VI ≥ – 30 Vdc – 57 300
–20 Vdc ≥ VI ≥ – 26 Vdc – 27 150
5.0 mA ≤ IO ≤ 1.5 A – 68 300
250 mA ≤ IO ≤ 750 mA – 25 150

–17.5 Vdc ≥ VI ≥ – 30 Vdc – – 1.0
5.0 mA ≤ IO ≤ 1.5 A – – 0.5
IO = 1.0 A, TJ = +25°C – 2.0 –

IO = 5.0 A, 0°C ≤ TJ ≤ +125°C – –1.0 –
MC7915AC
– 20 Vdc ≥ VI ≥ – 26 Vdc, IO = 1.0 A, TJ = +25°C – 27 75
– 20 Vdc ≥ VI ≥ – 26 Vdc, IO = 1.0 A, – 57 150
–17.9 Vdc ≥ VI ≥ – 30 Vdc, IO = 500 mA – 57 150
–17.5 Vdc ≥ VI ≥ – 30 Vdc, IO = 1.0 A, TJ = +25°C – 57 150
5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C – 68 150
250 mA ≤ IO ≤ 750 mA – 25 75
5.0 mA ≤ IO ≤ 1.0 A – 40 150

–17.5 Vdc ≥ VI ≥ – 30 Vdc – – 0.8
5.0 mA ≤ IO ≤ 1.0 A – – 0.5
5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C – – 0.5
IO = 1.0 A, TJ = +25°C – 2.0 –

IO = 5.0 mA, 0°C ≤ TJ ≤ +125°C – –1.0 –

MC7900
MC7918C
(TJ = +25°C, IO = 100 mA)
–21 Vdc ≥ VI ≥ – 33 Vdc – 25 180
–24 Vdc ≥ VI ≥ – 30 Vdc – 10 90
(TJ = +25°C, IO = 500 mA)
–21 Vdc ≥ VI ≥ – 33 Vdc – 90 360
–24 Vdc ≥ VI ≥ – 30 Vdc – 50 180
5.0 mA ≤ IO ≤ 1.5 A – 110 360
250 mA ≤ IO ≤ 750 mA – 55 180
– 21 Vdc ≥ VI ≥ – 33 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, P ≤ 15 W –17.1 – –18.9

–21 Vdc ≥ VI ≥ – 33 Vdc – – 1.0
5.0 mA ≤ IO ≤ 1.5 A – – 0.5
IO = 1.0 A, TJ = +25°C – 2.0 –

IO = 5.0 mA, 0°C ≤ TJ ≤ +125°C – –1.0 –
MC7924C
Output Voltage (TJ = +25°C) VO – 23 – 24 – 25 Vdc
(TJ = +25°C, IO = 100 mA)
– 27 Vdc ≥ VI ≥ – 38 Vdc – 31 240
– 30 Vdc ≥ VI ≥ – 36 Vdc – 14 120
(TJ = +25°C, IO = 500 mA)
– 27 Vdc ≥ VI ≥ – 38 Vdc – 118 470
– 30 Vdc ≥ VI ≥ – 36 Vdc – 70 240
5.0 mA ≤ IO ≤ 1.5 A – 150 480
250 mA ≤ IO ≤ 750 mA – 85 240
– 27 Vdc ≥ VI ≥ – 38 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, P ≤ 15 W – 22.8 – – 25.2

– 27 Vdc ≥ VI ≥ – 38 Vdc – – 1.0
5.0 mA ≤ IO ≤ 1.5 A – – 0.5
IO = 1.0 A, TJ = +25°C – 2.0 –

IO = 5.0 mA, 0°C ≤ TJ ≤ +125°C – –1.0 –

MC7900
Figure 1. Worst Case Power Dissipation as a Figure 2. Peak Output Current as a Function
Function of Ambient Temperature of Input–Output Differential Voltage
20 2.5
Infinite Heatsink
10
θHS = 5°C/W

PD, POWER DISSIPATION (W)
2.0
5.0 TJ = +25°C
4.0 θHS = 15°C/W
3.0
1.5
2.0
No Heatsink
1.0 1.0
0.5
0.4
0.3 θJC = 5° C/W 0.5
0.2 θJA = 65° C/W
PD(max) = 15W
0.1 0
25 50 75 100 125 150 0 3.0 6.0 9.0 12 15 18 21 24 27 30
TA, AMBIENT TEMPERATURE (°C) |VI –VO| INPUT–OUTPUT VOLTAGE DIFFERENTIAL (V)
Figure 3. Ripple Rejection as a Figure 4. Ripple Rejection as a Function

Function of Frequency of Output Voltage
100 80
Vin = –11 V
VO = – 6.0 V
80 IO = 20 mA f = 120 Hz
70 IO = 20 mA
∆Vin = 1.0 V(RMS)
60
60
40
50
20
0 40
10 100 1.0 k 10 k 100 k 2.0 4.0 6.0 8.0 10 12 14 16 18 20 22
f, FREQUENCY (Hz) VO, OUTPUT VOLTAGE (V)
Figure 5. Output Voltage as a Function Figure 6. Quiescent Current as a

of Junction Temperature Function of Temperature
6.26 5.2
VO, OUTPUT VOLTAGE (–V)
6.22 5.0
6.18 4.8
6.14 4.6 Vin = –11 V

Vin = –11 V VO = – 6.0 V
VD = – 6.0 V IO = 20 mA
6.10 IO = 20 mA 4.4
6.06 4.2
–25 0 25 50 75 100 125 150 175 0 25 50 75 100 125

MC7900
The MC7900 Series of fixed voltage regulators are Figure 7. Current Regulator
designed with Thermal overload Protection that shuts down
the circuit when subjected to an excessive power overload –20 V IO = 200 mA
10
condition. Internal Short Circuit Protection that limits the Input MC7905
R –
maximum current the circuit will pass, and Output Transistor VO ≤ 10 V
Safe–Area Compensation that reduces the output short
circuit current as the voltage across the pass transistor is
increased. 1.0 µF 1.0 µF
+ +
In many low current applications, compensation Gnd Gnd
capacitors are not required. However, it is recommended that
the regulator input be bypassed with a capacitor if the
regulator is connected to the power supply filter with long wire
The MC7905, – 5.0 V regulator can be used as a constant current source when
lengths, or if the output load capacitance is large. An input connected as above. The output current is the sum of resistor R current and
bypass capacitor should be selected to provide good quiescent bias current as follows.
high–frequency characteristics to insure stable operation
under all load conditions. A 0.33 µF or larger tantalum, mylar, 5.0 V
IO = + IB
or other capacitor having low internal impedance at high R
frequencies should be chosen. The capacitor chosen should
The quiescent current for this regulator is typically 4.3 mA. The 5.0 V regulator was
have an equivalent series resistance of less than 0.7 Ω. The chosen to minimize dissipation and to allow the output voltage to operate to within
bypass capacitor should be mounted with the shortest 6.0 V below the input voltage.
possible leads directly across the regulators input terminals.
Normally good construction techniques should be used to
minimize ground loops and lead resistance drops since the
regulator has no external sense lead. Bypassing the output is
also recommended.
Figure 8. Current Boost Regulator

(– 5.0 V @ 4.0 A, with 5.0 A Current Limiting) Figure 9. Operational Amplifier Supply
(±15 @ 1.0 A)
–10 0.56 – 5.0 V
V
Input Output
2N3055* +20 V +15 V
0.56
or Equiv Input Output
MC7815
0.56
+ +
0.33 µF 1.0 µF 1.0 µF 1N4001
MJE200* or Equiv
or Equiv
Gnd Gnd
MC7905*
+ +
1.0 µF 1.0 µF
5.6
10 µF 1.0 µF 1.0 µF
+ + + MC7915
Gnd Gnd – 20 V –15 V
Input Output
*Mounted on heatsink.
The MC7815 and MC7915 positive and negative regulators may be connected as
When a boost transistor is used, short circuit currents are equal to the sum of the shown to obtain a dual power supply for operational amplifiers. A clamp diode
series pass and regulator limits, which are measured at 3.2 A and 1.8 A respectively should be used at the output of the MC7815 to prevent potential latch–up problems
in this case. Series pass limiting is approximately equal to 0.6 V/RSC. Operation whenever the output of the positive regulator (MC7815) is drawn below ground with
beyond this point to the peak current capability of the MC7905C is possible if the an output current greater than 200 mA.
regulator is mounted on a heatsink; otherwise thermal shutdown will occur when
the additional load current is picked up by the regulator.

MC7900

80 3.5


70 Free Air 3.0
Mounted
ÎÎÎ
60 2.5
ÎÎÎ
L
ÎÎÎ
50 Minimum 2.0
Size Pad L
40
RθJA ÎÎÎ 1.5
30 1.0
0 5.0 10 15 20 25 30
DEFINITIONS
Line Regulation – The change in output voltage for a Input Bias Current – That part of the input current that is
conditions of low dissipation or by using pulse techniques Output Noise Voltage – The rms AC voltage at the
such that the average chip temperature is not significantly output, with constant load and no input ripple, measured over
affected. a specified frequency range.
Load Regulation – The change in output voltage for a Long Term Stability – Output voltage stability under
change in load current at constant chip temperature. accelerated life test conditions with the maximum rated
Maximum Power Dissipation – The maximum total voltage listed in the devices’ electrical characteristics and
device dissipation for which the regulator will operate within maximum power dissipation.
specifications.

MC79L00, A
Series
Three-Terminal Low Current
Negative Voltage Regulators
The MC79L00, A Series negative voltage regulators are inexpensive, THREE–TERMINAL LOW
easy–to–use devices suitable for numerous applications requiring up to100 CURRENT NEGATIVE FIXED
mA. Like the higher powered MC7900 Series negative regulators, this series
features thermal shutdown and current limiting, making them remarkably VOLTAGE REGULATORS
rugged. In most applications, no external components are required for SEMICONDUCTOR
operation. TECHNICAL DATA
The MC79L00 devices are useful for on–card regulation or any other
application where a regulated negative voltage at a modest current level is
needed. These regulators offer substantial advantage over the common
resistor/zener diode approach. P SUFFIX
• No External Components Required PLASTIC PACKAGE
CASE 29
Pin 1. Ground
• Low Cost 2. Input
1
• Complementary Positive Regulators Offered (MC78L00 Series) 3. Output 2
3
• Available in Either ±5% (AC) or ±10% (C) Selections
D SUFFIX
PLASTIC PACKAGE
8 CASE 751
1 (SOP–8)*
Pin 1. Vout 5. GND
2. Vin 6. Vin
3. Vin 7. Vin
4. NC 8. NC
* SOP–8 is an internally modified SO–8 package.

Pins 2, 3, 6, and 7 are electrically common to the
die attach flag. This internal lead frame modifica-
Representative Schematic Diagram tion decreases package thermal resistance and
increases power dissipation capability when
appropriately mounted on a printed circuit board.
Gnd SOP–8 conforms to all external dimensions of the
R8 standard SO–8 package.
R6
R Q10
5 Q5 R9
R18 R17 Device No. Device No. Nominal
R1 Q4 ±10% 5% Voltage
MC79L05C MC79L05AC –5.0
R7
MC79L12C MC79L12AC –12
Q8 Q14
MC79L15C MC79L15AC –15
Q9 R16 MC79L18C MC79L18AC –18
Q1 R4 MC79L24C MC79L24AC –24
Output
R2 Q12 ORDERING INFORMATION
Q13 Operating
Z1 C Q2 Temperature Range
Device Package
R3 Q6 Q7 Q11
R10 R11 MC79LXXACD* SOP–8
R14 R15
MC79LXXACP TJ = 0° to +125°C Plastic Power
Input MC79LXXCP Plastic Power
MC79LXXABD* SOP–8
TJ = –40° to +125°C
* Automotive temperature range selections are available with special test conditions MC79LXXABP* Plastic Power
* and additional tests in 5, 12 and 15 V devices. Contact your local Motorola sales
* office for information. XX indicates nominal voltage

MC79L00, A Series
Input Voltage (–5 V) VI –30 Vdc
Input Voltage (–12, –15, –18 V) –35
Input Voltage (–24 V) –40
ELECTRICAL CHARACTERISTICS (VI = –10 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, –40°C < TJ +125°C (for MC79LXXAB),
0°C < TJ < +125°C (for MC79LXXAC)).
MC79L05C, AB MC79L05AC, AB
Output Voltage (TJ = +25°C) VO –4.6 –5.0 –5.4 –4.8 –5.0 –5.2 Vdc
Input Regulation Regline mV
(TJ = +25°C)
–7.0 Vdc ≥ VI ≥ –20 Vdc – – 200 – – 150
–8.0 Vdc ≥ VI ≥ –20 Vdc – – 150 – – 100
TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA – – 60 – – 60
1.0 mA ≤ IO ≤ 40 mA – – 30 – – 30
–7.0 Vdc ≥ VI ≥ –20 Vdc, 1.0 mA ≤ IO ≤ 40 mA –4.5 – –5.5 –4.75 – –5.25
VI = –10 Vdc, 1.0 mA ≤ IO ≤ 70 mA –4.5 – –5.5 –4.75 – –5.25
(TJ = +25°C) – – 6.0 – – 6.0
(TJ = +125°C) – – 5.5 – – 5.5
Input Bias Current Change IIB mA
–8.0 Vdc ≥ VI ≥ –20 Vdc – – 1.5 – – 1.5
1.0 mA ≤ IO ≤ 40 mA – – 0.2 – – 0.1
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
(–8.0 ≥ VI ≥ –18 Vdc, f = 120 Hz, TJ = +25°C)
Dropout Voltage (IO = 40 mA, TJ = +25°C) |VI–VO| – 1.7 – – 1.7 – Vdc
ELECTRICAL CHARACTERISTICS (VI = –19 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, –40°C < TJ +125°C (for MC79LXXAC),
0°C < TJ < +125°C (for MC79LXXAB)).
MC79L12C, AB MC79L12AC, AB
Output Voltage (TJ = +25°C) VO –11.1 –12 –12.9 –11.5 –12 –12.5 Vdc
(TJ = +25°C)
–14.5 Vdc ≥ VI ≥ –27 Vdc – – 250 – – 250
–16 Vdc ≥ VI ≥ –27 Vdc – – 200 – – 200
TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA – – 100 – – 100
1.0 mA ≤ IO ≤ 40 mA – – 50 – – 50
–14.5 Vdc ≥ VI ≥ –27 Vdc, 1.0 mA ≤ IO ≤ 40 mA –10.8 – –13.2 –11.4 – –12.6
VI = –19 Vdc, 1.0 mA ≤ IO ≤ 70 mA –10.8 – –13.2 –11.4 – –12.6
(TJ = +25°C) – – 6.5 – – 6.5
(TJ = +125°C) – – 6.0 – – 6.0
–16 Vdc ≥ VI ≥ –27 Vdc – – 1.5 – – 1.5
1.0 mA ≤ IO ≤ 40 mA – – 0.2 – – 0.2
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
(–15 ≤ VI ≤ –25 Vdc, f = 120 Hz, TJ = +25°C)
Dropout Voltage (IO = 40 mA, TJ = +25°C) |VI–VO| – 1.7 – – 1.7 – Vdc

MC79L00, A Series
ELECTRICAL CHARACTERISTICS (VI = –23 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, –40°C < TJ +125°C (for MC79LXXAB),
0°C < TJ < +125°C (for MC79LXXAC)).
MC79L15C MC79L15AC, AB
(TJ = +25°C)
–17.5 Vdc ≥ VI ≥ –30 Vdc – – 300 – – 300
–20 Vdc ≥ VI ≥ –30 Vdc – – 250 – – 250
TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA – – 150 – – 150
1.0 mA ≤ IO ≤ 40 mA – – 75 – – 75
–17.5 Vdc ≥ VI ≥ –Vdc, 1.0 mA ≤ IO ≤ 40 mA –13.5 – –16.5 –14.25 – –15.75
VI = –23 Vdc, 1.0 mA ≤ IO ≤ 70 mA –13.5 – –16.5 –14.25 – –15.75
(TJ = +25°C) – – 6.5 – – 6.5
(TJ = +125°C) – – 6.0 – – 6.0
–20 Vdc ≥ VI ≥ –30 Vdc – – 1.5 – – 1.5
1.0 mA ≤ IO ≤ 40 mA – – 0.2 – – 0.1
Output Noise Voltage VN – 90 – – 90 – µV
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
(–18.5 ≤ VI ≤ –28.5 Vdc, f = 120 Hz)
Dropout Voltage |VI–VO| – 1.7 – – 1.7 – Vdc
IO = 40 mA, TJ = +25°C
ELECTRICAL CHARACTERISTICS (VI = –27 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, 0°C < TJ > +125°C, unless otherwise noted).
MC79L18C MC79L18AC
(TJ = +25°C)
–20.7 Vdc ≥ VI ≥ –33 Vdc – – – – – 325
–21.4 Vdc ≥ VI ≥ –33 Vdc – – 325 – – –
–22 Vdc ≥ VI ≥ –33 Vdc – – 275 – – –
–21 Vdc ≥ VI ≥ –33 Vdc – – – – – 275
TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA – – 170 – – 170
1.0 mA ≤ IO ≤ 40 mA – – 85 – – 85
–20.7 Vdc ≥ VI ≥ –33 Vdc, 1.0 mA ≤ IO ≤ 40 mA – – – –17.1 – –18.9
–21.4 Vdc ≥ VI ≥ –33 Vdc, 1.0 mA ≤ IO ≤ 40 mA –16.2 – –19.8 – – –
–16.2
VI = –27 Vdc, 1.0 mA ≤ IO ≤ 70 mA – –19.8 –17.1 – –18.9
(TJ = +25°C) – – 6.5 – – 6.5
(TJ = +125°C) – – 6.0 – – 6.0
–21 Vdc ≥ VI ≥ –33 Vdc – – – – – 1.5
–27 Vdc ≥ VI ≥ –33 Vdc – – 1.5 – – –
1.0 mA ≤ IO ≤ 40 mA – – 0.2 – – 0.1
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
(–23 ≤ VI ≤ –33 Vdc, f = 120 Hz, TJ = +25°C)
IO = 40 mA, TJ = +25°C

MC79L00, A Series
ELECTRICAL CHARACTERISTICS (VI = –33 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, 0°C < TJ < +125°C, unless otherwise noted).
MC79L24C MC79L24AC
Output Voltage (TJ = +25°C) VO –22.1 –24 –25.9 –23 –24 –25 Vdc
(TJ = +25°C)
–27 Vdc ≥ VI ≥ –38 Vdc – – – – – 350
–27.5 Vdc ≥ VI ≥ –38 Vdc – – 350 – – –
–28 Vdc ≥ VI ≥ –38 Vdc – – 300 – – 300
TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA – – 200 – – 200
1.0 mA ≤ IO ≤ 40 mA – – 100 – – 100
–27 Vdc ≥ VI ≥ –38 V, 1.0 mA ≤ IO ≤ 40 mA – – – –22.8 – –25.2
–28 Vdc ≥ VI ≥ –38 Vdc, 1.0 mA ≤ IO ≤ 40 mA –21.4 – –26.4 – – –
VI = –33 Vdc, 1.0 mA ≤ IO ≤ 70 mA –21.4 – –26.4 –22.8 – –25.2
(TJ = +25°C) – – 6.5 – – 6.5
(TJ = +125°C) – – 6.0 – – 6.0
–28 Vdc ≥ VI ≥ –38 Vdc – – 1.5 – – 1.5
1.0 mA ≤ IO ≤ 40 mA – – 0.2 – – 0.1
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
(–29 ≤ VI ≤ –35 Vdc, f = 120 Hz, TJ = +25°C)

IO = 40 mA, TJ = +25°C
Design Considerations bypass capacitor should be selected to provide good
The MC79L00, A Series of fixed voltage regulators are high–frequency characteristics to insure stable operation
designed with Thermal Overload Protections that shuts down under all load conditions. A 0.33 µF or larger tantalum, mylar,
the circuit when subjected to an excessive power overload or other capacitor having low internal impedance at high
condition, Internal Short Circuit Protection that limits the frequencies should be chosen. The bypass capacitor should
maximum current the circuit will pass. be mounted with the shortest possible leads directly across
In many low current applications, compensation the regulator’s input terminals. Normally good construction
capacitors are not required. However, it is recommended that techniques should be used to minimize ground loops and
the regulator input be bypassed with a capacitor if the lead resistance drops since the regulator has no external
regulator is connected to the power supply filter with long wire sense lead. Bypassing the output is also recommended.
length, or if the output load capacitance is large. An input
Figure 1. Positive and Negative Regulator Figure 2. Standard Application
Input MC79LXX Output

+Vin MC78LXX +VO
CI* CO**
0.33µF 0.1µF
0.33µF 0.1µF
0.1µF
–Vin MC79LXX –VO A common ground is required between the input and the output
voltages. The input voltage must remain typically 2.0 V above
the output voltage even during the low point on the ripple voltage.
0.33µF
* CI is required if regulator is located an appreciable
* distance from the power supply filter
** CO improves stability and transient response.

MC79L00, A Series
TYPICAL CHARACTERISTICS
(TA = +25°C, unless otherwise noted.)

Figure 3. Dropout Characteristics Junction Temperature
8.0 –2.5
V I –V O , INPUT/OUTPUT DIFFERENTIAL
MC79L05C
VO = –5.0 V –2.0 IO = 70 mA
6.0 TJ = 25°C
IO = 40 mA
–1.5
VOLTAGE (V)
IO = 1.0 mA IO = 100 mA
4.0 IO = 1.0 mA
–1.0
Dropout of Regulation is
2.0 defined when
IO = 40 mA –0.5 ∆VO = 2% of VO
0 0
0 –2.0 –4.0 –6.0 –0.8 –10 0 25 50 75 100 125
Vin, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Input Bias Current versus Figure 6. Input Bias Current versus
Ambient Temperature Input Voltage
4.2 5.0
4.0
4.0
3.8
3.6 3.0
MC79L05C
VO = –5.0 V
3.4
2.0 IO = 40 mA
MC79L05C
3.2 Vin = –10 V
VO = –5.0 V 1.0
3.0 IO = 40 mA
0 0
0 25 50 75 100 125 0 –5.0 –10 –15 –20 –25 –30 –35 –40
TA, AMBIENT TEMPERATURE (°C) Vin, INPUT VOLTAGE (V)
Figure 7. Maximum Average Power Dissipation Figure 8. SOP–8 Thermal Resistance and Maximum
versus Ambient Temperature (TO–92) Power Dissipation versus P.C.B. Copper Length
10,000 170 3.2 PD, MAXIMUM POWER DISSIPATION (W)
150 2.8
RθJA , THERMAL RESISTANCE

P D , POWER DISSIPATION (mW)
130 2.4
1,000
ÎÎÎ ÎÎÎ
No Heatsink
110 Graph represents symmetrical layout 2.0
90
ÎÎÎ
ÎÎÎ ÎÎÎ 1.6
ÎÎÎ ÎÎÎ
2.0 oz.
L
100 Copper
70 1.2
L 3.0 mm
RΘJA = 200°C/W 50 0.8
PD(max) to 25°C = 625 mW RθJA
10 30 0.4
25 50 75 100 125 150 0 10 20 30 40 50
TA, AMBIENT TEMPERATURE (°C) L, LENGTH OF COPPER (mm)

MC79M00
Series
Three-Terminal Negative
Voltage Regulators
The MC79M00 series of fixed output negative voltage regulators are
intended as complements to the popular MC78M00 series devices. THREE–TERMINAL
Available in fixed output voltage options of –5.0, –8.0, –12 and –15 V, NEGATIVE FIXED
these regulators employ current limiting, thermal shutdown, and safe–area
compensation – making them remarkably rugged under most operating VOLTAGE REGULATORS
conditions. With adequate heatsinking they can deliver output currents in
excess of 0.5 A.
• Internal Short Circuit Current Limiting T SUFFIX
• Output Transistor Safe–Area Compensation PLASTIC PACKAGE
CASE 221A
• Also Available in Surface Mount DPAK (DT) Package
Heatsink surface
DEVICE TYPE/NOMINAL OUTPUT VOLTAGE connected to Pin 2.
MC79M05 –5.0 V MC79M12 –12 V

MC79M08 –8.0 V MC79M15 –15 V 1
2
3
Pin 1. Ground
ORDERING INFORMATION 2. Input
3. Output
Output
Voltage Operating
Device Tolerance Temperature Range Package
MC79MXXBDT, BDT–1 DPAK
TJ = – 40° to +125°C 1
MC79MXXBT Plastic Power 1
2
4 0%
4.0% 3 3
MC79MXXCDT, CDT–1 DPAK
TJ = 0° to +125°C DT SUFFIX DT–1 SUFFIX
MC79MXXCT Plastic Power PLASTIC PACKAGE PLASTIC PACKAGE
CASE 369A CASE 369
XX indicates nominal voltage.
(DPAK) (DPAK)


Gnd
STANDARD APPLICATION
2.0 k
2.4 k
2.0 k
14.7 k
11.5 k
25
Input MC79MXX Output

3.6 k
547
4.0 k R1
Cin* CO**
4.9 k
0.33 µF 1.0 µF
2.0 k
1.0 k
12 k
1.2 k
R2
10 k VO
and the output voltages. The input voltage must
remain typically 1.1 V more negative even during
20 pF the high point of the input ripple voltage.
10 pF 10 k
XX, These two digits of the type number indicate
20 k 20 k 240 nominal voltage.
2.0 k * Cin is required if regulator is located an
0.3
1.1 k 100
750 appreciable distance from power supply filter.
VI ** CO improve stability and transient response.

MC79M00

Input Voltage VI –35 Vdc
Power Dissipation
Case 221A
Case 369 and 369A (DPAK)
Storage Junction Temperature Tstg –65 to +150 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Value Unit
MC79M05B, C
ELECTRICAL CHARACTERISTICS (VI = –10 V, IO = 350 mA, Tlow to Thigh [Note 2], unless otherwise noted.)
Output Voltage (TJ = 25°C) VO –4.8 –5.0 –5.2 Vdc
–7.0 Vdc ≥ VI ≥ –25 Vdc – 7.0 50
–8.0 Vdc ≥ VI ≥ –18 Vdc – 2.0 30
5.0 mA ≤ IO ≤ 500 mA – 30 100

–7.0 Vdc ≥ VI ≥ –25 Vdc, 5.0 mA ≤ IO ≤ 350 mA –4.75 – –5.25

–8.0 Vdc ≥ VI ≥ –25 Vdc, IO = 350 mA – – 0.4
5.0 mA ≤ IO ≤ 350 mA, VI = –10 V – – 0.4
Output Noise Voltage, TA = 25°C, 10 Hz ≤ f ≤ 100 kHz Vn – 40 – µV
Ripple Rejection (f = 120 Hz) RR 54 66 – dB
IO = 500 mA, TJ = 25°C – 1.1 –

IO = 5.0 mA, 0°C ≤ TJ ≤ 125°C – 0.2 –
NOTES: 1. Load and line regulation are specified at constant temperature. Change in VO due to heating effects must be taken into account separately. Pulse
testing with low duty cycle is used.
2. B = Tlow to Thigh, –40°C < TJ < 125°C
C = Tlow to Thigh, 0°C < TJ < 125°C

MC79M00
MC79M08B, C
Output Voltage (TJ = 25°C) VO –7.7 –8.0 –8.3 Vdc
–7.0 Vdc ≥ VI ≥ –25 Vdc – 5.0 80
–8.0 Vdc ≥ VI ≥ –18 Vdc – 3.0 50
5.0 mA ≤ IO ≤ 500 mA – 30 100

–7.0 Vdc ≥ VI ≥ –25 Vdc, 5.0 mA ≤ IO ≤ 350 mA –7.6 –8.0 –8.4
Input Bias Current (TJ = 25°C) IIB – – 8.0 mA

–8.0 Vdc ≥ VI ≥ –25 Vdc, IO = 350 mA – – 0.4
5.0 mA ≤ IO ≤ 350 mA, VI = –10 V – – 0.4
IO = 500 mA, TJ = 25°C – 1.1 –

IO = 5.0 mA, 0°C ≤ TJ ≤ 125°C – 0.4 –
MC79M12B, C
Output Voltage (TJ = 25°C) VO –11.5 –12 –12.5 Vdc
–14.5 Vdc ≥ VI ≥ –30 Vdc – 5.0 80
–15 Vdc ≥ VI ≥ –25 Vdc – 3.0 50
5.0 mA ≤ IO ≤ 500 mA – 30 240

–14.5 Vdc ≥ VI ≥ –30 Vdc, 5.0 mA ≤ IO ≤ 350 mA –11.4 – –12.6

–14.5 Vdc ≥ VI ≥ –30 Vdc, IO = 350 mA – – 0.4
5.0 mA ≤ IO ≤ 350 mA, VI = –19 V – – 0.4
IO = 500 mA, TJ = 25°C – 1.1 –

IO = 5.0 mA, 0°C ≤ TJ ≤ 125°C – –0.8 –

MC79M00
MC79M15B, C
ELECTRICAL CHARACTERISTICS (VI = – 23 V, IO = 350 mA, Tlow to Thigh [Note 2], unless otherwise noted.)
Output Voltage (TJ = 25°C) VO –14.4 –15 –15.6 Vdc
–17.5 Vdc ≥ VI ≥ –30 Vdc – 5.0 80
–18 Vdc ≥ VI ≥ –28 Vdc – 3.0 50
5.0 mA ≤ IO ≤ 500 mA – 30 240

–17.5 Vdc ≥ VI ≥ –30 Vdc, 5.0 mA ≤ IO ≤ 350 mA –14.25 – –15.75

–17.5 Vdc ≥ VI ≥ –30 Vdc, IO = 350 mA – – 0.4
5.0 mA ≤ IO ≤ 350 mA, VI = –23 V – – 0.4
IO = 500 mA, TJ = 25°C – 1.1 –

IO = 5.0 mA, 0°C ≤ TJ ≤ 125°C – –1.0 –

100 2.4 PD, MAXIMUM POWER DISSIPATION (W)
Free Air
90 Mounted 2.0
Vertically
ÎÎÎÎ
2.0 oz. Copper
80 L 1.6
ÎÎÎÎ
Minimum
ÎÎÎÎ
70 Size Pad L 1.2
60 0.8
50 0.4
RθJA
40 0
0 5.0 10 15 20 25 30

MC33128
Power Management Controller
The MC33128 is a power management controller specifically designed for
use in battery powered cellular telephone and pager applications. This
device contains all of the active functions required to interface the user to the
system electronics via a microprocessor. This integrated circuit consists of a POWER MANAGEMENT
low dropout voltage regulator with power–up reset for MPU power, two low
dropout voltage regulators for independant powering of analog and digital CONTROLLER
circuitry, and a negative charge pump voltage regulator for full depletion of
gallium arsenide MESFETs. SEMICONDUCTOR
Also included are protective system shutdown features consisting of a
TECHNICAL DATA
battery latch that is activated upon battery insertion, low battery voltage
shutdown, and a thermal over temperature detector. This device is available
in a 16–pin narrow body surface mount plastic package.
• Three Positive Regulated Outputs Featuring Low Dropout Voltage
• Negative Regulated Output for Full Depletion of GaAs MESFETs
• MPU Power Up Reset
• Battery Latch
16
• Low Battery Shutdown

1
• Pinned–Out Reference for MPU A/D Converter

• Low Start–Up and Operating Current D SUFFIX
•
PLASTIC PACKAGE
Thermal Protection CASE 751B
(SO–16)

PIN CONNECTIONS
VCC VBB CPC
VBB Output
16 3 2 4
8 Output 2 1 16 VCC
+
Charge Output 4 VBB Charge Pump
Pump 2 15 Output 1
CPC Capacitor Input
ON/OFF 11 7 VBB Charge Pump 3
10 Control 14 Output 3
Toggle Capacitor Drive
9 Logic Negative 5 Output 4 VBB Output 4 13 Reset Output
Standby
Regulator –2.5 V/1.0 mA
Output 4 5 12 Reference Output
Low Battery
Shutdown Standby 15 Output 1 Gnd 6 11 Power Up Input
Regulator 1 3.0 V/30 mA
Output 4 Charge Pump 7 10 Power Down Input
Thermal 1 Output 2 Capacitor Input
Standby Output 4 Charge Pump 8
Protection Regulator 2 3.0 V/60 mA 9 Battery Saver Input
Capacitor Drive
Output 3
MPU 14 3.0 V/20 mA
Reference Regulator (Top View)
MPU Power 13
Up Reset R VDD
Gnd 6 12 Reference Output ORDERING INFORMATION

I MPU
O
O Operating
I V Device Temperature Range Package
SS
MC33128D TA = – 30° to +60°C SO–16

MC33128
MAXIMUM RATINGS
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Rating
Power Supply Input Voltage (Pin 16)
Symbol
VCC
Value
+7.0
Unit
V
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Input Voltage Range Power Up, Power Down,
ÁÁÁÁÁ
ÁÁÁ
and Battery Saver Inputs (Pins 11, 10, 9)
Vin – 1.0 to
VCC + 1.0
V
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Charge Pump Capacitor Drive Outputs, IO(max) 30 mA
Source or Sink Current (Pins 3, 8)
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Schottky Diode Forward Current
ÁÁÁÁÁ
ÁÁÁ
(Pins 16 to 2, 2 to 4, and 7 to 6)
IF(max) 30 mA
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Output Source Current (Note 1)
ÁÁÁÁÁ
ÁÁÁ
Regulator Output 1 (Pin 15)
Regulator Output 2 (Pin 1)
ISource
150
250
mA
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Regulator Output 3 (Pin 14) 50
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Regulator Output 4 (Pin 5) 10
Reference (Pin 12) 40
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Reset Sink Current (Pin 13) ISink 5.0 mA
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Power Dissipation and Thermal Characteristic
ÁÁÁÁÁ
ÁÁÁ
D Suffix, Plastic Package Case 751B
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Thermal Resistance, Junction–to–Air R∅JA 180 °C/W
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Operating Ambient Temperature (Note 1) TA – 30 to +60 °C
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ELECTRICAL CHARACTERISTICS (VCC = 4.5 V, Cin = 33 µF with ESR ≤ 1.6 Ω, CO = 4.7 µF with ESR ≤ 4.5 Ω, IO1 = 30 mA,
IO2 = 60 mA, IO3 = 20 mA, IO4 = 1.0 mA, IOref = 10 mA [Note 2], TA = 25°C.)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
POWER UP INPUT (Pin 11)
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Low State Input Threshold Voltage Vth(toggle) VCC – 1.5 VCC – 1.2 VCC – 0.8 V
µA
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Input Current (Vin = VO3) Iin(toggle) – – 120
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Internal Pull Up Resistance RPU(ON/OFF) 10 20 30 kΩ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
POWER DOWN INPUT (Pin 10)
High State Input Threshold Voltage (Places IC in Standby Mode) Vth(PDI) 1.3 1.5 1.8 V
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
Input Current (Vin = VO3)
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
Iin(PDI) – – 120 µA
BATTERY SAVER INPUT (Pin 9)
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
High State Input Threshold Voltage (VBB, VO1, VO2, VO4 Activated) Vth(BSI) 1.2 1.4 1.7 V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Input Current (Vin = VO3)
ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
Iin(BSI) – – 120 µA
VBB GENERATOR
ÁÁÁÁÁ
Oscillator Frequency
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
fOSC 85 95 105 kHz
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Oscillator Duty Cycle DC 35 50 65 %
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Charge Pump Capacitor Drive Output Voltage Swing (Pin 3) V
High State (ISource = 3.0 mA) VOH – VCC – 0.9 –
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
Low State (ISink = 3.0 mA)
ÁÁÁÁ
Schottky Diode (Pins 2, 4) ÁÁÁ
ÁÁÁÁ
ÁÁÁ
VOL – 0.15 –
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Forward Voltage Drop (IF = 3.0 mA) VF – 0.5 – V
Reverse Leakage Current (VBB = 7.0 V) IL – 0.01 – µA
VCC = 4.5 V
VCC = 2.9 V
ÁÁÁÁÁ
ÁÁÁÁ
Output Voltage (Pin 4)
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
VO(VBB)
–
–
7.9
4.4
–
–
V
NOTES: 1. Maximum package power dissipation limits must be observed.

2. All outputs are fully loaded as stated in the Electrical Characteristics Table above, except for the one under test.

MC33128
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
REGULATOR OUTPUT 1 (Pin 15)
Output Voltage (VCC = 3.15 V to 4.5 V, IO1 = 30 mA) Regline1 2.9 3.0 3.1 V
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Load Regulation (IO1 = 0 mA to 35 mA)
ÁÁÁÁ
ÁÁÁ
Dropout Voltage (VCC = 2.9 V, IO1 = 30 mA)
Regload1
Vin – VO1
–
–
5.0
–
30
0.1
mV
V
f = 120 Hz
f = 100 kHz
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
Power Supply Rejection Ratio
ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
PSRR 1
–
–
70
40
–
–
dB
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Turn ON Delay Time (Battery Saver Input to 90% VO1 Output)
ÁÁÁÁ
ÁÁÁ
tDLY1 – 0.2 2.0 ms
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Voltage (VCC = 3.15 V to 4.5 V, IO2 = 60 mA) Reg 2.9 3.0 3.1 V
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Load Regulation (IO2 = 0 mA to 60 mA)
ÁÁÁÁ
ÁÁÁ
Dropout Voltage (VCC = 2.9 V, IO2 = 60 mA)
Regload2
Vin – VO2
–
–
5.0
–
40
0.11
mV
V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Power Supply Rejection Ratio PSRR 2 dB
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
f = 120 Hz – 70 –
f = 100 kHz – 40 –
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Turn ON Delay Time (Battery Saver Input to 90% VO2 Output)
ÁÁÁÁ
ÁÁÁ
tDLY2 – 0.2 2.0 ms
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Voltage (VCC = 3.15 V to 4.5 V, IO3 = 20 mA) Regline3 2.9 3.0 3.1 V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Load Regulation (IO3 = 0 mA to 20 mA) Regload3 – 5.0 25 mV
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Dropout Voltage (VCC = 2.9 V, IO3 = 20 mA) Vin – VO3 – – 0.1 V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
f = 120 Hz – 70 –
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
f = 100 kHz – 40 –
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Turn ON Delay Time (ON/OFF Toggle Input to 90% VO3 Output) tDLY3 – 0.5 3.0 ms
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Voltage (VCC = 3.15 V to 4.5 V, IO4 = 1.0 mA) Regline4 – 2.35 – 2.5 – 2.65 V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Load Regulation (IO4 = 0 mA to 1.0 mA) Regload4 – 5.0 20 mV
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
f = 120 Hz – 70 –
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
f = 100 kHz – 40 –
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Schottky Diode Forward Voltage Drop (Pins 7, 6, IF = 1.0 mA) VF – 0.5 – V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Charge Pump Capacitor Drive Output Voltage Swing (Pin 8) V
High State (ISource = 1.0 mA) VOH – VBB – 0.25 –
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Low State (ISink = 1.0 mA) VOL – 0.15 –
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Turn ON Delay Time (Battery Saver Input to 90% VO4 Output) tDLY4 – 4.0 10 ms
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
REFERENCE OUTPUT (Pin 12)
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Voltage (IO = 0 mA to 10 mA) Regload 1.46 1.5 1.54 V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
MPU POWER UP RESET COMPARATOR (Pin 13)
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Threshold Voltage
Low State Output (VO3 Decreasing) Vth(low) 2.5 2.6 2.7 V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Hysteresis (VO3 Increasing) VH 40 60 100 mV
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Sink Saturation (ISink = 100 µA, VO3 = 2.5 V to 1.0 V) VCE(sat) – 130 300 mV
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Internal Pull–up Resistance RPU 10 26 40 kΩ
High State Output Voltage (VO3 = 2.8 V) VOH 0.95 VO3 VO3 – V
NOTE: 2. All outputs are fully loaded as stated in the Electrical Characteristics Table above, except for the one under test.

MC33128
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
LOW BATTERY SHUTDOWN COMPARATOR (Pin 16)
Shutdown Threshold Voltage (VCC Decreasing, Pin 10 = Gnd) Vth(LBSC) 2.25 2.4 2.55 V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
TOTAL DEVICE (Pin 16)
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Power Supply Current (No Load On All Outputs)
ÁÁÁÁ
ÁÁÁ
Operating
Battery Saver Input High (Pin 9 = 2.0 V)
ICC
– 2.6 4.0 mA
ÁÁÁÁÁ
ÁÁÁÁÁ
NOTE:
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Battery Saver Input Low (Pin 9 ≤ 0.8 V)
ÁÁÁÁ
ÁÁÁ
Standby (After Power Down Input Strobe)
2. All outputs are fully loaded as stated in the Electrical Characteristics Table above, except for the one under test.
–
–
270
8.0
330
12
µA
µA
Figure 1. Dropout Voltage Figure 2. Output 4 Voltage

versus Source Current versus Source Current
160 –3.0
V in – VO , DROPOUT VOLTAGE (mV)
VCC = 4.5 V
–2.5
120
VO , OUTPUT 4 VOLTAGE (V)

Output 3 –2.0 VCC = 3.15 V
Output 1
80 –1.5
Output 2
–1.0
40 VCC = 2.9 V
TA = 25°C –0.5 TA = 25°C
See Note
See Note
0 0
0 20 40 60 80 100 0 –1.0 –2.0 –3.0 –4.0 –5.0
IO, OUTPUT SOURCE CURRENT (mA) IO, OUTPUT 4 SOURCE CURRENT (mA)
Figure 3. Reference Output Figure 4. VBB Output

Voltage Change versus Source Current Voltage Change versus Source Current
8.0
∆Vref , OUTPUT VOLTAGE CHANGE (mV)
VCC = 4.5 V
0
VO ,VBB OUTPUT VOLTAGE (V)
6.0
–10
VCC = 3.15 V
–20 4.0
–30
2.0
TA = 25°C TA = 25°C
–40 See Note See Note
0
0 5.0 10 15 20 25 0 0.5 1.0 1.5 2.0
Iref, REFERENCE SOURCE CURRENT (mA) IO, VBB OUTPUT SOURCE CURRENT (mA)
NOTE: All outputs are fully loaded as stated in the Electrical Characteristics Table above, except for the one under test.

MC33128
OPERATING DESCRIPTION
The MC33128 is a complete power management accidentally left on for an extended time period. To prevent
controller that is designed to interface the user to the system this condition the following circuit blocks were incorporated.
electronics via a microprocessor. A means for low battery detection is accomplished by
using the Reference Output, Pin 12, in conjunction with the
Outputs
microprocessor’s analog to digital converter input. A
Three low dropout voltage regulators are provided at outputs microprocessor output (LBO) can be designated to flash a
1, 2 and 3. Outputs 1 and 2 were contemplated for independent display enunciator when a low battery condition exists. The
powering of the systems analog and digital circuitry. This Reference Output is 1.5 V ± 2.7% and is capable of sourcing
significantly reduces the possibility of digitally generated noise in excess of 10 mA.
and spurious signals from coupling into the RF and analog The Power Up Reset Output, Pin 13, is designed to hold
circuits. The low dropout characteristic of Outputs 1 and 2 is the microprocessor reset input low until the voltage at Output 3
achieved by applying a boosted battery voltage, VBB, to their rises above 2.66 V. This feature prevents the microprocessor
respective driver transistors. This allows the output pass from hanging or writing invalid information into its memory
transistors to be driven into saturation when the battery voltage during power up. Notice that the output of the MPU Power Up
approaches 3.0 V. The VBB Output appears at Pin 4 and can be Reset comparator also drives the base of transistor QPD. If
used to provide gate bias for enhancing external N channel Output 3 should fall below 2.6 V, due to an overload or a low
MOSFET switches. Excessive loading of the VBB output will battery condition, the comparator will drive QPD “ON”,
result in an increase in dropout voltage. causing its collector to pull high on the Power Down Input,
Output 4 is derived from a voltage inverting charge pump immediately forcing the system into standby mode.
circuit and is intended to provide the negative gate bias Externally pulling down on Pin 13, base of QPD, will also force
required for full depletion of RF gallium arsenide MESFETs. the system into standby mode.
In personal communication system applications such as A redundant Low Battery Shutdown circuit is included.
cellular telephone, negative gate bias is usually required by This circuit directly monitors the battery voltage and also
the antenna switch and power amplifier circuit blocks with a forces the system into standby mode when the battery
typical combined current of less than 1.0 mA. Output 4 can voltage falls below 2.4 V. To test the functionality of this
supply in excess of 2.0 mA, but there will be an increase in circuit, the high state signal generated by transistor QPD must
dropout voltage of Outputs 1, 2 and 3. be clamped low, to prevent resetting the ON/OFF Latch. An
Outputs 1, 2, 4, VBB Generator and Thermal Protection are external short or a pull–down, capable of sinking 2.0 mA at
all enabled and disabled in unison by the Battery Saver Input, less than 0.8 V, must be connected to Pin 10.
Pin 9. The microprocessor can be programmed to A Battery Latch circuit is designed into the IC to prevent
significantly extend the system battery operating time by the system from turning on when the batteries are inserted
periodically enabling the receiver circuitry. into the finished product. This feature is useful for the end
Output 3 provides power to the microprocessor, flash customer as well as the equipment manufacturer. Upon initial
EPROM and the system display. These blocks are enabled application of battery voltage, the lower comparator (0.7 V
by the Power Up Input, Pin 11, and disabled by the Power threshold) forces the Battery Latch into a reset state with its
Down Input, Pin 10. By having separate power up and power “Q” output low. This in turn triggers a reset of the ON/OFF
down inputs, the microprocessor can store any pending Latch via the OR gate and also locks out the set signal
information before turning the system and then itself OFF. present at the upper input of the AND gate. As the voltage at
This allows a controlled or graceful shutdown. Note that the Pin 11 rises above (VCC – 1.5 V), the set signal disappears,
power down request is initiated by pressing the toggle switch leaving the state of the ON/OFF Latch unchanged (reset).
while the system is “ON”. This action generates a When the voltage at Pin 11 rises above (VCC – 1.0 V), the
microprocessor non–maskable interrupt that initiates the upper comparator forces the Battery Latch into a set state
graceful shutdown. causing its “Q” output to go high. This allows the AND gate
Battery Voltage Detection and the ON/OFF Latch to receive a set signal from Pin 11.
Reverse biasing and eventual failure of the lowest The initial Battery Latch lockout time is controlled by the
capacity cell in the battery pack can occur if the system is internal 20 kΩ resistor and the external 0.1 µF capacitor.

MC33128
Figure 5. MC33128 Block Diagram

0.22 VCC
VBB Charge
Pump Capacitor 3 2 16 33 Vbat
VO3 5.0V to 3.0V
VBB Generator
Reference 4
1.27V
Oscillator 4.7
Logic VBB
Bias 8
Output 4
20k 0.1 Charge Pump Capacitor
7
–2.5V Output 4
VCC–1.0V Battery Regulator 5 –2.5V/1.0mA
Latch 4.7
S
1.27V
1.0µA Q
0.7V VBB
R 1.27V
Standby
10pF Regulator 1
15 Output 1
3.0V/30mA
VCC–1.5V 4.7
Power Up
VBB
Input 11 1.27V
ON/OFF Standby
Toggle ON/OFF Regulator 2
Latch 1 Output 2
Battery 9 3.0V/60mA
S 4.7
Saver
Input Thermal Q VCC
Power 10 1.27V MPU
Down R Regulator
Input Output 3
VO3 1.27V
Reference 14 3.0V/20mA
1.5V/10mA
V 4.7
1.27V O3 VO3 QPD
Low Battery
Shutdown VDD
Reset
MPU 26k Output Low Battery
Power Up R LBO Output
Reset 40k 13
1.27V
MPU
Reference 12 Gnd 6 Vbat
Output Ref
Out
Out
Out A/D
V In
In SS

MC33128
Figure 6. Voltage Tripler and Switch Driver
0.22 Vbat
3 2 16 33
0.1
VBB Generator
Vbat
4
Tripler
Oscillator 4.7 Output
VBB
8
4.7 R C2 Controlled
Turn ON/OFF
7 RFB
C1 Time
5 ON/OFF RL
Tripler Output Voltage Load Turn ON/OFF Time

Load Current
(mA) VCC = 3.15 V VCC = 4.5 V High RFB
0 7.96 12.01
0.5 7.48 11.54 Critical RFB
1.0 7.24 11.29
1.5 6.99 11.04 Low RFB
2.0 6.62 10.69
External Switch
A low threshold N–channel MOSFET can be used to In order to minimize adjacent channel splatter, the RF
switch the transmitting power amplifier (RL) ON and OFF. To power amplifier must be turned ON and OFF in a controlled
ensure that all of the available battery voltage appears (soft) manner. The applied voltage rise and fall time, as well
across the load, the MOSFET must be fully enhanced over as the rate of change in rise and fall time, must be tailored to
the system’s required operating voltage range. With the the amplifiers characteristics. The circuit consisting of
addition of two Schottky diodes and two capacitors, the VBB resistors R, RFB, and capacitors C1 and C2 is a simple
Generator can be made to function as a voltage tripler. The solution allowing the system designer a means to control the
table in Figure 6 shows the output voltage characteristics of ON and OFF time as well as the waveshape. Feedback
the tripler circuit. resistor RFB controls the waveshape. Capacitors C1 and C2
are usually of equal value.

MC33153
The MC33153 is specifcally designed as an IGBT driver for high power
applications that include ac induction motor control, brushless dc motor
control and uninterruptable power supplies. Although designed for driving
discrete and module IGBTs, this device offers a cost effective solution for SINGLE IGBT
driving power MOSFETs and Bipolar Transistors. Device protection features
include the choice of desaturation or overcurrent sensing and undervoltage GATE DRIVER
detection. These devices are available in dual–in–line and surface mount
packages and include the following features: SEMICONDUCTOR
TECHNICAL DATA
• Protection Circuits for Both Conventional and Sense IGBT’s
• Programmable Fault Blanking Time
• Protection against Overcurrent and Short Circuit
• Undervoltage Lockout Optimzed for IGBT’s
• Cost Effectively Drives Power MOSFETs and Bipolar Transistors 8
P SUFFIX
PLASTIC PACKAGE
CASE 626
Representative Block Diagram 8

1
VCC
6
D SUFFIX
VCC VCC Short Circuit PLASTIC PACKAGE
Short Circuit Comparator CASE 751
Latch (SO–8)
Fault S VCC
Output 7 Q
R Overcurrent
Current
Sense
S
Q PIN CONNECTIONS
R 65 mV
VEE
VCC Kelvin
VCC Gnd
2
270 µA Current Sense 1 8 Fault Blanking/
Fault Input Desaturation Input
8 Blanking/
Desaturation Kelvin Gnd 2 7 Fault Output
Fault Blanking/ 6.5 V Input
VEE
Desaturation
Comparator VEE 3 6 VCC
VCC
Input 4 5 Drive Output
VCC Output
Stage
Input Drive (Top View)

4 VCC 5 Output
Under 100 k
Voltage
VEE Lockout
VEE
Operating
12 V/ Device Temperature Range Package
11 V
MC33153D SO–8
3 VEE
TA = –40° to +105°C
MC33153P DIP–8

MC33153
MAXIMUM RATINGS
Power Supply Voltage V
VCC to VEE VCC – VEE 23
Kelvin Ground to VEE (Note 1) KGnd – VEE 23
Logic Input Vin VEE –0.3 to VCC V
Current Sense Input VS –0.3 to VCC V
Blanking/Desaturation Input VBD –0.3 to VCC V
Gate Drive Output IO A
Source Current 1.0
Sink Current 2.0
Diode Clamp Current 1.0
Fault Output IFO mA
Source Current 25
Sink Curent 10
D Suffix SO–8 Package, Case 751
Maximum Power Dissipation @ TA = 50°C PD 0.56 W
P Suffix DIP–8 Package, Case 626
Maximum Power Dissipation @ TA = 50°C PD 1.0 W
Operating Ambient Temperature TA –40 to +105 °C
ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = 0 V, Kelvin Gnd connected to VEE. For typical values
TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 2), unless otherwise noted.)
LOGIC INPUT
Input Threshold Voltage V
High State (Logic 1) VIH – 2.70 3.2
Low State (Logic 0) VIL 1.2 2.30 –
Input Current µA
High State (VIH = 3.0 V) IIH – 130 500
Low State (VIL = 1.2 V) IIL – 50 100
DRIVE OUTPUT
Output Voltage V
Low State (ISink = 1.0 A) VOL – 2.0 2.5
High State (ISource = 500 mA) VOH 12 13.9 –
Output Pull–Down Resistor RPD – 100 200 kΩ
FAULT OUTPUT
Output voltage V
Low State (ISink = 5.0 mA) VFL – 0.2 1.0
High State (ISource = 20 mA) VFH 12 13.3 –
SWITCHING CHARACTERISTICS
Propagation Delay (50% Input to 50% Output CL = 1.0 nF) ns
Logic Input to Drive Output Rise tPLH(in/out) – 80 300
Logic Input to Drive Output Fall tPHL (in/out) – 120 300
Drive Output Rise Time (10% to 90%) CL = 1.0 nF tr – 17 55 ns
Drive Output Fall Time (90% to 10%) CL = 1.0 nF tf – 17 55 ns
Propagation Delay µs
Current Sense Input to Drive Output tP(OC) – 0.3 1.0
Fault Blanking/Desaturation Input to Drive Output tP(FLT) – 0.3 1.0
NOTE: 1. Kelvin Ground must always be between VEE and VCC.
2. Low duty cycle pulse techniques are used during test to maintain the junction temperature as close to ambient as possible.
Tlow = –40°C for MC33153 Thigh = +105°C for MC33153

MC33153
ELECTRICAL CHARACTERISTICS (continued) (VCC = 15 V, VEE = 0 V, Kelvin Gnd connected to VEE. For typical values
TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 2), unless otherwise noted.)
UVLO
Startup Voltage VCC start 11.3 12 12.6 V
Disable Voltage VCC dis 10.4 11 11.7 V
COMPARATORS
Overcurrent Threshold Voltage (VPin8 > 7.0 V) VSOC 50 65 80 mV
Short Circuit Threshold Voltage (VPin8 > 7.0 V) VSSC 100 130 160 mV
Fault Blanking/Desaturation Threshold (VPin1 > 100 mV) Vth(FLT) 6.0 6.5 7.0 V
Current Sense Input Current (VSI = 0 V) ISI – –1.4 –10 µA
FAULT BLANKING/DESATURATION INPUT
Current Source (VPin8 = 0 V, VPin4 = 0 V) Ichg –200 –270 –300 µA
Discharge Current (VPin8 = 15 V, VPin4 = 5.0 V) Idschg 1.0 2.5 – mA
TOTAL DEVICE
Standby (VPin 4 = VCC, Output Open) – 7.2 14
Operating (CL = 1.0 nF, f = 20 kHz) – 7.9 20
NOTE: 1. Kelvin Ground must always be between VEE and VCC.
Tlow = –40°C for MC33153 Thigh = +105°C for MC33153
Figure 1. Input Current versus Input Voltage Figure 2. Output Voltage versus Input Voltage
1.5 16
14 VCC = 15 V
TA = 25°C
I in , INPUT CURRENT (mA)
12
1.0
10
8.0
6.0
0.5
4.0
VCC = 15 V
TA = 25°C 2.0
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 1.0 2.0 3.0 4.0 5.0

MC33153
Figure 3. Input Threshold Voltage Figure 4. Input Threshold Voltage

3.2 2.8
V IH – V IL , INPUT THRESHOLD VOLTAGE (V)

V IH – V IL , INPUT THRESHOLD VOLTAGE (V)
VCC = 15 V VIH TA = 25°C

3.0 2.7
2.8 VIH 2.6
2.6 2.5
2.4 2.4
VIL
2.2 VIL 2.3
2.0 2.2
–60 –40 –20 0 20 40 60 80 100 120 140 12 13 14 15 16 17 18 19 20
Figure 5. Drive Output Low State Voltage Figure 6. Drive Output Low State Voltage
versus Temperature versus Sink Current
2.5 2.0
V OL, OUTPUT LOW STATE VOLTAGE (V)
2.0
ISink = 1.0 A V OL, OUTPUT LOW STATE VOLTAGE (V) 1.6
= 500 mA
1.5 1.2
= 250 mA
1.0 0.8
0.5 0.4
TA = 25°C
VCC = 15 V
VCC = 15 V
0 0
–60 –40 –20 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0
TA, AMBIENT TEMPERATURE (°C) ISink, OUTPUT SINK CURRENT (A)
Figure 7. Drive Output High State Voltage Figure 8. Drive Output High State Voltage
versus Temperature versus Source Current
VOH , DRIVE OUTPUT HIGH STATE VOLTAGE (V)
VOH , DRIVE OUTPUT HIGH STATE VOLTAGE (V)
14.0 15.0
VCC = 15 V
13.9 14.6 TA = 25°C
13.8 14.2
13.7 13.8
13.6 VCC = 15 V 13.4

ISource = 500 mA
13.5 13.0
–60 –40 –20 0 20 40 60 80 100 120 140 0 0.1 0.2 0.3 0.4 0.5
TA, AMBIENT TEMPERATURE (°C) ISource, OUTPUT SOURCE CURRENT (A)

MC33153
Figure 9. Drive Output Voltage Figure 10. Fault Output Voltage

versus Current Sense Input Voltage versus Current Sense Input Voltage
16 14
V Pin 7, FAULT OUTPUT VOLTAGE (V)

14 VCC = 15 V 12 VCC = 15 V
VO , DRIVE OUTPUT VOLTAGE (V)
VPin 4 = 0 V VPin 4 = 0 V
12 VPin 8 > 7.0 V VPin 8 > 7.0 V
10
TA = 25°C TA = 25°C
10
8.0
8.0
6.0
6.0
4.0
4.0
2.0 2.0
0 0
50 55 60 65 70 75 80 100 110 120 130 140 150 160
VPin 1, CURRENT SENSE INPUT VOLTAGE (mV) VPin 1, CURRENT SENSE INPUT VOLTAGE (mV)
Figure 11. Overcurrent Protection Threshold Figure 12. Overcurrent Protection Threshold
V SOC , OVERCURRENT THRESHOLD VOLTAGE (mV)
V SOC , OVERCURRENT THRESHOLD VOLTAGE (mV)

Voltage versus Temperature Voltage versus Supply Voltage
70 70
VCC = 15 V TA = 25°C
68 68
66 66
64 64
62 62
60 60
–60 –40 –20 0 20 40 60 80 100 120 140 12 14 16 18 20
Figure 13. Short Circuit Comparator Threshold Figure 14. Short Circuit Comparator Threshold
VSSC, SHORT CIRCUIT THRESHOLD VOLTAGE (mV)
VSSC, SHORT CIRCUIT THRESHOLD VOLTAGE (mV)
Voltage versus Temperature Voltage versus Supply Voltage

135 135
VCC = 15 V TA = 25°C
130 130
125 125
–60 –40 –20 0 20 40 60 80 100 120 140 12 14 16 18 20

MC33153
Figure 15. Current Sense Input Current Figure 16. Drive Output Voltage versus Fault
ISI , CURRENT SENSE INPUT CURRENT (µ A) versus Voltage Blanking/Desaturation Input Voltage
0 16
14

VCC = 15 V VCC = 15 V
TA = 25°C VPin 4 = 0 V
12
VPin 1 > 100 mV
–0.5 TA = 25°C
10
8.0
6.0
–1.0
4.0
2.0
–1.5 0
0 2.0 4.0 6.0 8.0 10 12 14 16 6.0 6.2 6.4 6.6 6.8 7.0
VPin 1, CURRENT SENSE INPUT VOLTAGE (V) VPin 8, FAULT BLANKING/DESATURATION INPUT VOLTAGE (V)
Figure 17. Fault Blanking/Desaturation Comparator Figure 18. Fault Blanking/Desaturation Comparator
Threshold Voltage versus Temperature Threshold Voltage versus Supply Voltage
6.6 6.6
V BDT , FAULT BLANKING/DESATURATION
VCC = 15 V V BDT , FAULT BLANKING/DESATURATION VPin 4 = 0 V

THRESHOLD VOLTAGE (V)
VPin 4 = 0 V THRESHOLD VOLTAGE (V) VPin 1 > 100 mV

VPin 1 > 100 mV TA = 25°C
6.5 6.5
6.4 6.4
–60 –40 –20 0 20 40 60 80 100 120 140 12 14 16 18 20
Figure 19. Fault Blanking/Desaturation Current Figure 20. Fault Blanking/Desaturation Current
Source versus Temperature Source versus Supply Voltage
–200 –200
VCC = 15 V
Ichg, CURRENT SOURCE ( µ A)
Ichg, CURRENT SOURCE ( µ A)
–220 –220 VPin 4 = 0 V

VPin 8 = 0 V VPin 8 = 0 V
TA = 25°C
–240 –240
–260 –260
–280 –280
–300 –300
–60 –40 –20 0 20 40 60 80 100 120 140 5.0 10 15 20

MC33153
Figure 21. Fault Blanking/Desaturation Figure 22. Fault Blanking/Desaturation Discharge

Current Source versus Input Voltage Current versus Input Voltage
–200 2.5
I dscg, DISCHARGE CURRENT (mA)

2.0
I chg, CURRENT SOURCE ( µ A)
–220 VCC = 15 V
VPin 4 = 0 V
TA = 25°C 1.5
–240
1.0
–260
0.5
–280 VCC = 15 V
0 VPin 4 = 5.0 V
TA = 25°C
–300 –0.5
0 2.0 4.0 6.0 8.0 10 12 14 16 0 4.0 8.0 12 16
VPin 8, FAULT BLANKING/DESATURATION INPUT VOLTAGE (V) VPin 8, FAULT BLANKING/DESATURATION INPUT VOLTAGE (V)
Figure 23. Fault Output Low State Voltage Figure 24. Fault Output High State Voltage
versus Sink Current versus Source Current
1.0 14.0
VPin 7 , FAULT OUTPUT VOLTAGE (V)
0.8 VCC = 15 V VPin 7 , FAULT OUTPUT VOLTAGE (V) 13.8

VCC = 15 V
VPin 4 = 0 V
VPin 4 = 5.0 V
VPin 1 = 1.0 V
TA = 25°C
Pin 8 = Open
0.6 13.6 TA = 25°C
0.4 13.4
0.2 13.2
0 13.0
0 2.0 4.0 6.0 8.0 10 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
ISink, OUTPUT SINK CURRENT (mA) ISource, OUTPUT SOURCE CURRENT (mA)
Figure 25. Drive Output Voltage Figure 26. UVLO Thresholds

versus Supply Voltage versus Temperature
16 12.5
14 Startup Threshold
VCC Increasing
Vth(UVLO), UNDERVOLTAGE
LOCKOUT THRESHOLD (V)
12 12.0
10
Turn–Off
8.0 Threshold 11.5
6.0 Turn–Off Threshold

VCC Decreasing
4.0 Startup 11.0
Threshold VPin 4 = 0 V
2.0 TA = 25°C
0 10.5
10 11 12 13 14 15 –60 –40 –20 0 20 40 60 80 100 120 140
VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

MC33153
Figure 27. Supply Current versus

Supply Voltage Figure 28. Supply Current versus Temperature
10 10
Output High
8.0
ICC, SUPPLY CURRENT (mA)

8.0
Output Low
6.0 6.0
4.0 4.0
2.0 TA = 25°C 2.0 VCC = 15 V

VPin 4 = VCC
Drive Output Open
0 0
5.0 10 15 20 –60 –40 –20 0 20 40 60 80 100 120 140
VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 29. Supply Current versus Input Frequency

80
CL = 10 nF
VCC = 15 V
TA = 25°C
60 = 5.0 nF
40
= 2.0 nF
20
= 1.0 nF
0
1.0 10 100 1000
f, INPUT FREQUENCY (kHz)
GATE DRIVE
Controlling Switching Times
The most important design aspect of an IGBT gate drive is circuits. The turn–off resistor, Roff, controls the turn–off speed
optimization of the switching characteristics. The switching and ensures that the IGBT remains off under commutation
characteristics are especially important in motor control stresses. Turn–off is critical to obtain low switching losses.
applications in which PWM transistors are used in a bridge While IGBTs exhibit a fixed minimum loss due to minority
configuration. In these applications, the gate drive circuit carrier recombination, a slow gate drive will dominate the
components should be selected to optimize turn–on, turn–off turn–off losses. This is particularly true for fast IGBTs. It is
and off–state impedance. A single resistor may be used to also possible to turn–off an IGBT too fast. Excessive turn–off
control both turn–on and turn–off as shown in Figure 30. speed will result in large overshoot voltages. Normally, the
However, the resistor value selected must be a compromise turn–off resistor is a small fraction of the turn–on resistor.
in turn–on abruptness and turn–off losses. Using a single The MC33153 contains a bipolar totem pole output stage
resistor is normally suitable only for very low frequency that is capable of sourcing 1.0 amp and sinking 2.0 amps
PWM. An optimized gate drive output stage is shown in peak. This output also contains a pull down resistor to ensure
Figure 31. This circuit allows turn–on and turn–off to be that the IGBT is off whenever there is insufficient VCC to the
optimized separately. The turn–on resistor, Ron, provides MC33153.
control over the IGBT turn–on speed. In motor control In a PWM inverter, IGBTs are used in a half–bridge
circuits, the resistor sets the turn–on di/dt that controls how configuration. Thus, at least one device is always off. While
fast the free–wheel diode is cleared. The interaction of the the IGBT is in the off–state, it will be subjected to changes in
IGBT and free–wheeling diode determines the turn–on dv/dt. voltage caused by the other devices. This is particularly a
Excessive turn–on dv/dt is a common problem in half–bridge problem when the opposite transistor turns on.

MC33153
When the lower device is turned on, clearing the upper and if desired, isolation from ac line voltages. An optoisolator
diode, the turn–on dv/dt of the lower device appears across with a very high dv/dt capability should be used, such as the
the collector emitter of the upper device. To eliminate Hewlett Packard HCPL4053. The IGBT gate turn–on resistor
shoot–through currents, it is necessary to provide a low sink should be set large enough to ensure that the opto’s dv/dt
impedance to the device that is in the off–state. In most capability is not exceeded. Like most optoisolators, the
applications the turn–off resistor can be made small enough HCPL4053 has an active low open–collector output. Thus,
to hold off the device that is under commutation without when the LED is on, the output will be low. The MC33153 has
causing excessively fast turn–off speeds. an inverting input pin to interface directly with an optoisolator
using a pull up resistor. The input may also be interfaced
Figure 30. Using a Single Gate Resistor directly to 5.0 V CMOS logic or a microcontroller.
VCC Optoisolator Output Fault

IGBT
The MC33153 has an active high fault output. The fault
Output
Rg output may be easily interfaced to an optoisolator. While it is
important that all faults are properly reported, it is equally
5
important that no false signals are propagated. Again, a high
dv/dt optoisolator should be used.
VEE
The LED drive provides a resistor programmable current
VEE
of 10 to 20 mA when on, and provides a low impedance path
3
when off. An active high output, resistor, and small signal
VEE
diode provide an excellent LED driver. This circuit is shown in
Figure 32.
Figure 31. Using Separate Resistors
Figure 32. Output Fault Optoisolator
for Turn–On and Turn–Off
VCC Short Circuit

IGBT Latch Output VCC
Ron
Output
Doff Roff Q
5
7
VEE VEE
VEE VEE
3
VEE
UNDERVOLTAGE LOCKOUT
A negative bias voltage can be used to drive the IGBT into
It is desirable to protect an IGBT from insufficient gate
the off–state. This is a practice carried over from bipolar
voltage. IGBTs require 15 V on the gate to achieve the rated
Darlington drives and is generally not required for IGBTs.
on–voltage. At gate voltages below 13 V, the on–voltage
However, a negative bias will reduce the possibility of
increases dramatically, especially at higher currents. At very
shoot–through. The MC33153 has separate pins for VEE and
low gate voltages, below 10 V, the IGBT may operate in the
Kelvin Ground. This permits operation using a +15/–5.0 V
linear region and quickly overheat. Many PWM motor drives
supply.
use a bootstrap supply for the upper gate drive. The UVLO
provides protection for the IGBT in case the bootstrap
INTERFACING WITH OPTOISOLATORS capacitor discharges.
Isolated Input The MC33153 will typically start up at about 12 V. The
UVLO circuit has about 1.0 V of hysteresis and will disable
The MC33153 may be used with an optically isolated
the output if the supply voltage falls below about 11V.
input. The optoisolator can be used to provide level shifting,

MC33153
PROTECTION CIRCUITRY The MC33153 also features a programmable fault

blanking time. During turn–on, the IGBT must clear the
Desaturation Protection
opposing free–wheeling diode. The collector voltage will
Bipolar Power circuits have commonly used what is known remain high until the diode is cleared. Once the diode has
as “Desaturation Detection”. This involves monitoring the been cleared, the voltage will come down quickly to the
collector voltage and turning off the device if this voltage rises VCE(sat) of the device. Following turn–on, there is normally
above a certain limit. A bipolar transistor will only conduct a considerable ringing on the collector due to the COSS
certain amount of current for a given base drive. When the capacitance of the IGBTs and the parasitic wiring inductance.
base is overdriven, the device is in saturation. When the The fault signal from the Desaturation Comparator must be
collector current rises above the knee, the device pulls out of blanked sufficiently to allow the diode to be cleared and the
saturation. The maximum current the device will conduct in ringing to settle out.
the linear region is a function of the base current and the dc The blanking function uses an NPN transistor to clamp the
current gain (hFE) of the transistor. comparator input when the gate input is low. When the input
The output characteristics of an IGBT are similar to a is switched high, the clamp transistor will turn “off”, allowing
Bipolar device. However, the output current is a function of the internal current source to charge the blanking capacitor.
gate voltage instead of current. The maximum current The time required for the blanking capacitor to charge up
depends on the gate voltage and the device type. IGBTs tend from the on–voltage of the internal NPN transistor to the trip
to have a very high transconductance and a much higher voltage of the comparator is the blanking time.
current density under a short circuit than a bipolar device. If a short circuit occurs after the IGBT is turned on and
Motor control IGBTs are designed for a lower current density saturated, the delay time will be the time required for the
under shorted conditions and a longer short circuit survival current source to charge up the blanking capacitor from the
time. VCE(sat) level of the IGBT to the trip voltage of the
The best method for detecting desaturation is the use of a comparator. Fault blanking can be disabled by leaving Pin 8
high voltage clamp diode and a comparator. The MC33153 unconnected.
has a Fault Blanking/Desaturation Comparator which senses
the collector voltage and provides an output indicating when Sense IGBT Protection
the device is not fully saturated. Diode D1 is an external high Another approach to protecting the IGBTs is to sense the
voltage diode with a rated voltage comparable to the power emitter current using a current shunt or Sense IGBTs. This
device. When the IGBT is “on” and saturated, D1 will pull method has the advantage of being able to use high gain
down the voltage on the Fault Blanking/Desaturation Input. IGBTs which do not have any inherent short circuit capability.
When the IGBT pulls out of saturation or is “off”, the current Current sense IGBTs work as well as current sense
source will pull up the input and trip the comparator. The MOSFETs in most circumstances. However, the basic
comparator threshold is 6.5 V, allowing a maximum problem of working with very low sense voltages still exists.
on–voltage of about 5.8 V. Sense IGBTs sense current through the channel and are
A fault exists when the gate input is high and VCE is therefore linear with respect to the collector current. Because
greater than the maximum allowable VCE(sat). The output of IGBTs have a very low incremental on–resistance, sense
the Desaturation Comparator is ANDed with the gate input IGBTs behave much like low–on resistance current sense
signal and fed into the Short Circuit and Overcurrent Latches. MOSFETs. The output voltage of a properly terminated
The Overcurrent Latch will turn–off the IGBT for the sense IGBT is very low, normally less than 100 mV.
remainder of the cycle when a fault is detected. When input The sense IGBT approach requires fault blanking to
goes high, both latches are reset. The reference voltage is prevent false tripping during turn–on. The sense IGBT also
tied to the Kelvin Ground instead of the VEE to make the requires that the sense signal is ignored while the gate is low.
threshold independent of negative gate bias. Note that for This is because the mirror output normally produces large
proper operation of the Desaturation Comparator and the transient voltages during both turn–on and turn–off due to the
Fault Output, the Current Sense Input must be biased above collector to mirror capacitance. With non–sensing types of
the Overcurrent and Short Circuit Comparator thresholds. IGBTs, a low resistance current shunt (5.0 to 50 mΩ) can be
This can be accomplished by connecting Pin 1 to VCC. used to sense the emitter current. When the output is an
actual short circuit, the inductance will be very low. Since the
Figure 33. Desaturation Detection blanking circuit provides a fixed minimum on–time, the peak
current under a short circuit can be very high. A short circuit
discern function is implemented by the second comparator
Desaturation VCC
VCC which has a higher trip voltage. The short circuit signal is
Comparator
270 µA
latched and appears at the Fault Output. When a short circuit
D1
is detected, the IGBT should be turned–off for several
8 milliseconds allowing it to cool down before it is turned back
Vref on. The sense circuit is very similar to the desaturation
Kelvin 6.5 V VEE circuit. It is possible to build a combination circuit that
Gnd
provides protection for both Short Circuit capable IGBTs and
Sense IGBTs.

MC33153
Figure 34 shows a basic IGBT driver application. When If desaturation protection is desired, a high voltage diode
driven from an optoisolator, an input pull up resistor is is connected to the Fault Blanking/Desaturation pin. The
required. This resistor value should be set to bias the output blanking capacitor should be connected from the
transistor at the desired current. A decoupling capacitor Desaturation pin to the VEE pin. If a dual supply is used, the
should be placed close to the IC to minimize switching noise. blanking capacitor should be connected to the Kelvin
A bootstrap diode may be used for a floating supply. If the Ground. The Current Sense Input should be tied high
protection features are not required, then both the Fault because the two comparator outputs are ANDed together.
Blanking/Desaturation and Current Sense Inputs should both Although the reverse voltage on collector of the IGBT is
be connected to the Kelvin Ground (Pin 2). When used with a clamped to the emitter by the free–wheeling diode, there is
single supply, the Kelvin Ground and VEE pins should be normally considerable inductance within the package itself. A
connected together. Separate gate resistors are small resistor in series with the diode can be used to protect
recommended to optimize the turn–on and turn–off drive. the IC from reverse voltage transients.
Figure 34. Basic Application Figure 36. Desaturation Application
+18 V +18 V
B+
Bootstrap
6 6
VCC Desat/ 8 7 VCC Desat/ 8
Fault Blank
7 Blank
Fault 5 CBlank
Output MC33153
5
MC33153 Output
1
4 Sense 1
Input 4 Sense
2 Input 2
VEE Gnd VEE Gnd
3 3
Figure 35. Dual Supply Application When using sense IGBTs or a sense resistor, the sense
+15 V voltage is applied to the Current Sense Input. The sense trip
voltages are referenced to the Kelvin Ground pin. The sense
voltage is very small, typically about 65 mV, and sensitive to
6 noise. Therefore, the sense and ground return conductors
VCC Desat/ 8 should be routed as a differential pair. An RC filter is useful in
7 Blank filtering any high frequency noise. A blanking capacitor is
Fault 5
Output connected from the blanking pin to VEE. The stray
MC33153 capacitance on the blanking pin provides a very small level of
1 blanking if left open. The blanking pin should not be grounded
4 Sense
Input when using current sensing, that would disable the sense.
2
VEE Gnd The blanking pin should never be tied high, that would short
3 out the clamp transistor.
Figure 37. Sense IGBT Application
+18 V
–5.0 V
6
When used in a dual supply application as in Figure 35, the 7 VCC Desat/ 8
Kelvin Ground should be connected to the emitter of the Fault Blank
5
IGBT. If the protection features are not used, then both the Output
Fault Blanking/Desaturation and the Current Sense Inputs
MC33153
should be connected to Ground. The input optoisolator Sense
1
should always be referenced to VEE. 4
Input 2
VEE Gnd
3

MC33154
Product Preview
The MC33154 is specifically designed as an IGBT driver for high power
applications including ac induction motor control, brushless dc motor control SINGLE IGBT
and uninterruptible power supplies. GATE DRIVER
The MC33154 is similar to the MC33153, except that the output drive is
in–phase with the logic input, the output source current drive is four times
higher and the supply voltage rating is higher. SEMICONDUCTOR
Although designed for driving discrete and module IGBTs, this device TECHNICAL DATA
offers a cost effective solution for driving power MOSFETs and Bipolar
Transistors.
These devices are available in dual–in–line and surface mount packages
and include the following features:
• Protection Circuits for Both Conventional and Sense IGBTs
• Programmable Fault Blanking Time 8
• Protection against Overcurrent and Short Circuit

1
• Undervoltage Lockout Optimzed for IGBTs P SUFFIX

PLASTIC PACKAGE
• Negative Gate Drive Capability CASE 626
• Cost Effectively Drives Power MOSFETs and Bipolar Transistors
Representative Block Diagram 8

1
D SUFFIX
VCC Short Circuit PLASTIC PACKAGE
Short Circuit Comparator CASE 751
Latch (SO–8)
Fault S VCC
Output 7 Q
R Overcurrent
Current
Sense
S
Q
R 65 mV
VEE
PIN CONNECTIONS
VCC VCC Kelvin
VCC Gnd
2
VCC 1.0 mA Current Sense 1 8 Fault Blanking/
6 Fault Input Desaturation Input
VEE 8 Blanking/
Desaturation
3 6.5 V Input Kelvin Gnd 2 7 Fault Output
Desat/Blank VEE
VEE Comparator
VEE 3 6 VCC
VCC
Output Input 4 5 Drive Output
VCC
Stage
Gate
Input Drive (Top View)
4 VCC 5 Output
Under
Voltage
VEE Lockout
VEE ORDERING INFORMATION
12 V/ Operating
11 V Device Temperature Range Package
MC33154D SO–8
This device contains 133 active transistors. TA = –40° to +85°C
MC33154P DIP–8

MC33169
Advance Information
GaAs Power Amplifier
Support IC GaAs POWER AMPLIFIER
SUPPORT IC
The MC33169 is a support IC for GaAs Power Amplifier Enhanced FETs
used in hand portable telephones such as GSM, PCN and DECT. This
device provides negative voltages for full depletion of Enhanced MESFETs SEMICONDUCTOR
as well as a priority management system of drain switching, ensuring that the TECHNICAL DATA
negative voltage is always present before turning “on” the Power Amplifier.
Additional features include an idle mode input and a direct drive of the
N–Channel drain switch transistor.
This product is available in two versions, – 2.5 and – 4.0 V. The – 4.0 V
version is intended for supplying RF modules for GSM and DCS1800
applications, whereas the – 2.5 V version is dedicated for DECT and PHS
systems.
• Negative Regulated Output for Full Depletion of GaAs MESFETs 14
• Drain Switch Priority Management Circuit

• CMOS Compatible Inputs 1
• Idle Mode Input (Standby Mode) for Very Low Current Consumption
• Output Signal Directly Drives N–Channel FET DTB SUFFIX
• Low Startup and Operating Current PLASTIC PACKAGE
CASE 948G
(TSSOP–14)
PIN CONNECTIONS

C3 C2 Input 1 14 VCC
+
VBB Double +
12 VBattery
+ – – + VCC C1/C2 2 13 Idle Mode Input
(2.7 to 7.0 V)
C1 2 C2 1 14
C1 Input 3 12 VBB Double
8 MMSF4N01HD
VBB 11 3 VBB
Gate Drive Output VO Output 4 11 VBB Triple
Triple + Generator MC33169
C4 (Voltage Tripler) VO Charge Pump
– Capacitor+ 5 10 Sense Input
Tx Power Gnd 6 9 Tx Power

Priority Control Input
Control 9 Management
Input RF RF VO Charge Pump
7 8 Gate Drive Output
In Out Capacitor–
13 Power Amplifier
Idle Sense (Top View)
10
Mode Input
6 Sense Input
Gnd
Negative
Generator
Charge
Pump
7 5 4 – + ORDERING INFORMATION
– +
C
Cp VO Ci + f Operating
Output Device Temperature Range Package
(– 2.5 V or – 4.0 V) Rf
MC33169DTB–4.0
This device contains 148 active transistors. TA = –40° to +85°C TSSOP–14
MC33169DTB–2.5

MC33169
MAXIMUM RATINGS
Rating Pin Symbol Value Unit
Power Supply Voltage 14 VCC 9.5 V
Tx Power Control Input 9 VTx VCC V
Idle Mode Input 13 Vi VCC V
Sense Input 10 VSense –5.0 to 0 V
Negative Generator Output Source Current 4 ISS 20 mA
Charge Pump Capacitor Current – Imax 60 mA
Diode Forward Current – IFmax 60 mA
Gate Drive Output Current 8 IGO 5.0 mA
Power Dissipation and Thermal Characteristics –
Operating Ambient Temperature – TA –40 to +85 °C
Storage Temperature Range – Tstg –60 to +150 °C
MC33169–4.0
ELECTRICAL CHARACTERISTICS (VCC = 4.8 V. For typical values TA = 25°C, for min/max values TA is the operating
ambient temperature range that applies, unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit
VBB GENERATOR (VOLTAGE TRIPLER)
Oscillator Frequency – fosc 90 100 110 kHz
Oscillator Duty Cycle – DC 35 50 65 %
Output Voltage (VCC = 3.0 V, IO = 3.0 mA) V
Double Voltage 12 VBBD 4.6 5.0 –
Triple Voltage 11 VBBT 6.1 7.0 –
Triple Voltage (VCC = 7.2 V, IO = 3.0 mA) 11 VBBT – 11.2 –
NEGATIVE GENERATOR OUTPUT
Output Voltage (IO = 3.0 mA) 4 VO –3.75 –4.0 –4.25 V
Output Voltage Ripple with Filter (Rf = 33 Ω, Cf = 4.7 µF) 4 Vr mVpp
(IO = 0 to 5.0 mA) – 2.0 –
PRIORITY MANAGEMENT SECTION
Idle Mode Input 13
Input Voltage High State (Logic 1) VIH 2.0 – 2.7 V
Input Voltage Low State (Logic 0) VIL 0 – 0.5 V
Input Current High State (Logic 1) IIH 10 – 80 µA
Input Current Low State (Logic 0), i.e. Standby Mode IIL – – 1.0 µA
Tx Power Control Input 9
Input Voltage Range VTx 0 – 3.1 V
Input Voltage “Off” State (Zero RF Output Level) VTx(off) – 0.7 – V
Input Voltage “On” State (Maximum RF Output Level) VTx(on) – 2.7 – V
Input Resistance Rin – 90 – kΩ
Bandwidth (– 3.0 dB) B – 1.0 – MHz
Gate Drive Output 8
Voltage (VTx = 0 V) VGO – – 0.5 V
Voltage (VTx = 3.0 V) VCC+2.7 – –
Peak Current (Source and Sink) (VTx = 3.0 V) IGO – 3.0 – mA
Undervoltage Lockout Voltage on Sense Input (Magnitude) 10 Vsense –3.0 –3.2 – V

MC33169
MC33169–4.0
ELECTRICAL CHARACTERISTICS (continued) (VCC = 4.8 V. For typical values TA = 25°C, for min/max values TA is the operating
TOTAL DEVICE POWER CONSUMPTION

ICC Operating (VTx = 3.0 V, IO = 3.0 mA) – ICC – 10 15 mA
ICC Operating – ICC mA
(VTx = 0 V, IO = 3.0 mA) – 12 15
(VTx = 0 V, IO = 0 mA) – 4.0 5.0
Standby Mode (Idle Mode Input = 0 V) – ICC – – 1.0 µA
MC33169–4.0
Output Voltage (IO = 1.0 mA) 4 VO – 3.75 – 4.0 – 4.25 V
(IO = 0 to 5.0 mA) – 2.0 –
Idle Mode Input 13
Gate Drive Output 8
Peak Current (Source and Sink) (VTx = 3.0 V) IGO – 3.0 – mA
ICC Operating (VTx = 3.0 V) 14 ICC mA
(IO = 3.0 mA) – – 15
(IO = 1.0 mA) – – 9.0
ICC Operating (VTx = 0 V) 14 ICC mA
(IO = 3.0 mA) – – 13
(IO = 1.0 mA) – – 9.0
(IO = 0 mA) – 4.5 6.0
Standby Mode (Idle Mode Input = 0 V) 14 ICC – – 1.0 µA

MC33169
MC33169–2.5
Output Voltage 4 VO V
(IO = 3.0 mA) – 2.35 – 2.5 – 2.65
(IO = 5.0 mA, VCC = 6.0 V) – – 2.5 –
(IO = 0 to 5.0 mA) – 2.0 8.0
Idle Mode Input 13
Gate Drive Output 8
Peak Current (VTx = 3.0 V) IGO – 3.0 – mA
ICC Operating (VTx = 3.0 V, IO = 3.0 mA) 14 ICC – 14 17 mA
ICC Operating 14 ICC mA
(VTx = 0 V, IO = 3.0 mA) – 13.5 16
(VTx = 0 V, IO = 0 mA) – 4.5 6.0
Standby Mode (Idle Mode Input = 0 V) 14 ICC – – 1.0 µA
PRIORITY MANAGEMENT TRUTH TABLE

Control Inputs Outputs
Idle Mode Tx Power Control VO Gate Drive
0 0 Off 0.5 V max
1 0 –2.5 or – 4.0 V 0.5 V max
0 1 Off 0.5 V max
1 1 –2.5 or – 4.0 V VCC + 2.7 V min

MC33169

Pin Name Description
1 C2 Input This is the positive pin for the charge pump capacitor in the voltage doubler.
2 C1/C2 This is the negative pin for the charge pump capacitors.
3 C1 Input This is the positive pin for the charge pump capacitor in the voltage tripler.
4 VO Output It delivers a regulated negative voltage of –4.0 V or –2.5 V depending on the product version. It can
source an output current in excess of 5.0 mA.
5 VO Charge Pump This is the positive pin for the capacitor in the inverting charge pump.
Capacitor +
6 Gnd This pin is Ground for both signal and power circuitry.
7 VO Charge Pump This is the negative pin for the capacitor in the inverting charge pump.
Capacitor –
8 Gate Drive Output This is the output of the gate amplifier which directly drives the gate of an N–Channel MOSFET. It can
sink and source peak currents up to 3.0 mA.
9 Tx Power Control The input signal applied on this pin controls the N–Channel switching MOSFET in follower mode and
Input therefore, linearly controls the RF output voltage.
10 Sense Input Pin It senses the negative voltage directly on the Power Amplifier. It is also the input pin of an internal
Undervoltage Lockout circuit which blocks the switching of the N–Channel MOSFET if the sensed
voltage is more positive than –3.0 V (–4.0 V version) or –2.0 V (–2.5 V version).
11 VBB Triple This is the positive pin of the output filter capacitor in the voltage tripler. The triple voltage at that pin is
used internally to supply the inverting charge pump and the gate amplifier.
12 VBB Double This is the positive pin of the output filter capacitor in the voltage doubler.
13 Idle Mode Input This pin is used to set the circuit in Low Power Consumption Standby mode. It is CMOS compatible, i.e.
a voltage lower than 0.5 V applied on this pin makes the device go into Standby mode in which the
current consumption is lower than 1.0 µA. The MC33169 is then awakened by a voltage higher than
2.0 V applied on that pin.
14 VCC This is the supply input pin for the MC33169, VCC voltage ranges from 2.7 V to 7.2 V.
Figure 1. MC33169 Representative Block Diagram
C2 C1
VCC
1 2 3 14
Priority
VBB Double Management
Positive VBB Triple
12
Cd Charge Pump 11 + VBattery
Ct
Standby Idle Mode

Positive Circuit 13 Input
Regulator
Oscillator Voltage
Reference
Negative Regulator VGout

(–4.0 or –2.5 V) UVLO
8 VDD
RF In RF Out
Negative Gate 9
Charge Pump Amplifier Tx(on) GaAs
PA
6 Gnd 7 5 VO 4 10 Vsense
Cp Cn

MC33169
Figure 2. Operating Current versus Temperature Figure 3. Operating Current versus Temperature
5.0 15
VCC = 4.8 V
4.5 14 VCC = 4.8 V
I CC , OPERATING (mA)
4.0 VCC = 2.7 V 13
3.5 12 VCC = 2.7 V
VTx = 0 V
3.0 IO = 0 mA 11 VTx = 0 V
IO = 0 mA
2.5 10
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100
Figure 4. Operating Current versus Temperature Figure 5. Operating Current versus Temperature
16 8.0
VCC = 4.8 V VTx = 3.0 V
7.6
15
VCC = 2.7 V 7.2

14 VTx = 0 V
6.8
VTx = 3.0 V VCC = 2.7 V

13
IO = 3.0 mA 6.4 IO = 1.0 mA
12 6.0
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100
Figure 6. Output Voltage versus Temperature Figure 7. Output Voltage versus Temperature
–4.04 –4.04
–4.035 ISS = 3.0 mA
VSS, OUTPUT VOLTAGE (V)
–4.02
–4.03 ISS = 1.0 mA
OUTPUT VOLTAGE (V)
–4.025 –4.0
–4.02 ISS = 3.0 mA
–4.015 –3.98
VCC = 2.7 V VCC = 4.8 V
–4.01
–3.96
–4.005
–4.0 –3.94
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100

MC33169
Figure 9. VTx Control Voltage versus Gate

Figure 8. Output Voltage versus Load Current Drive Output Voltage
–4.04 8.0
VGO, GATE DRIVE OUTPUT VOLTAGE (V)

7.0
–4.035
6.0
OUTPUT VOLTAGE (V)
25°C
–4.03 –25°C
0°C 5.0
–4.025 85°C 4.0
3.0
–4.02
2.0
–4.015
1.0
–4.01 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0
LOAD CURRENT (mA) VTx, POWER CONTROL INPUT VOLTAGE (V)
The MC33169 is a power amplifier support IC that is glitches on the VCC line which could cause disturbances to
designed to properly switch “on” or “off” a MESFET Power other circuitry.
Amplifier either manually or by microprocessor. Controlling
Inputs
the power drain of the RF Amplifier extends operating battery
life in many portable systems. A Sense Input, Pin 10, protects the Power Amplifier load
by monitoring the level of the negative output voltage. If the
Outputs negative voltage magnitude falls below a preset level, 3.2 V
The IC is designed to provide a –4.0 V or –2.5 V bias to typical for the –4.0 V version or 2.3 V for the –2.5 V version,
the gate of the RF Ampllifier MESFET devices prior to an undervoltage lockout circuit disables the external
application of a positive battery voltage to the drain. The MOSFET gate drive.
negative output voltage can provide up to 5.0 mA of current. The Tx Power Control Input controls the N–Channel
The positive voltage control requires an external external switching MOSFET in source follower mode, which
N–Channel logic level MOSFET, connected as a source allows linear control of the RF Output voltage level.
follower. The Gate Drive Output, Pin 8, can source or sink The Idle mode input is CMOS compatible, allowing the RF
3.0 mA to the external MOSFET. The low drive current slows Amplifier to be placed in a standby mode, drawing less than
the MOSFET switching speed, thereby minimizing voltage 1.0 µA from the power source.

MC33169
Figure 10. Class 4 GSM with a Two–Stage Integrated Power Amplifier (I.P.A.)
VBatt
= 4.8 V Tx Power
(4 cells Control
3.0 V NlCd/NIMH) Input 3.0 V
Idle MMSF4N01HD
0V 0V
100
5 G 4
C2 0.1 6 S 3
1 14
7 Drain S 2
2 13 68 8 1
C1 0.1 C3 1.0
3 12
Ci 0.22 100 C4 1.0
4 MC33169 11
MMBD701
LT1 5 10
Cp 1.0 6 9
9 MRF IC 093 8
7 8
10 7
.047 47 pF 47 pF .047
11 6
3.3 k 2 mm 4 mm 47 pF
VG2 tune 12 Out 5
1.0 k 30 Ω 30 Ω 50 Ω Out
VG1 tune
13 Out 4 5.6 pF 5.6 pF
14 3
8.2 nH
50 Ω In 15 In 2
Cf
16 1 0.22
6.8 pF RF
330
Grounded Backside
– 4.0 V
Figure 11. Transfer Characteristic for

Gate Drive Output
1.4
1.2
VBatt = 4.8 V
1.0 Pin = 10 dBm
IPA RF OUT (Vrms)
VIdle = 3.0 V
0.8
Vramp: 40 Hz sinusoidal voltage
0.6
set for 95% AM depth on RF
TA = 25°C
0.4 VBatt = 4.8 V
VIdle = 3.0 V Peak output
0.2 power: 34.6 dBm
0
0 0.5 1.0 1.5 2.0 2.5
VTx (V)

MC33169
CURVES RELATED TO APPLICATION GSM CLASS 4
Figure 12. RF Output Voltage (40 Hz/95% AM) and Figure 13. Idle, PA Drain, RF Output and VO
VTx Driving Voltage Voltages During a Burst Period
Output RF Idle Voltage
Voltage
VTx
VTx AND RF OUTPUT (V)
0V
VTx 0V
VT 0V
Negative Output RF Voltage
VO
Voltage
–0 V
–50 ms –25 ms 0s –350 µs 150 µs 850 µs
TIMEBASE = 5.0 ms/DIV TIMEBASE = 5.0 µs/DIV
VERTICAL SCALE = 0.5 V/DIV VERTICAL SCALE = 0.5 V/DIV
Figure 14. RF Output Voltage, PA Drain Voltage Figure 15. RF Output Voltage, PA Drain Voltage and
and VTx Driving Voltage, During Fall Time VTx Driving Voltage, During Rise Time
VTx
VTx
PA Drain
Voltage
PA Drain
Voltage
Output
RF Voltage
Output
RF Voltage
–13.4 µs 11.6 µs 36.6 µs –13.4 µs 11.6 µs 36.6 µs

TIMEBASE = 5.0 µs/DIV VERTICAL SCALE = 0.5 V/DIV
VERTICAL SCALE = 0.5 V/DIV

MC33169
Figure 16. AMPS version with MRFIC0913, Integrated Power Amplifier (I.P.A.)
VBatt
= 3.6 V Tx Power
(3 cells Control
3.0 V NlCd/NIMH) Input 3.0 V
Idle MMSF4N01HD
0V 0V
100
5 G 4
C2 0.1 6
1 14
S 3
7 Drain S 2
2 13 68 8 1
C1 0.1 C3 1.0
3 12
Ci 0.22 100 C4 1.0
4 MC33169 11
MMBD701
LT1 5 10
Cp 1.0 6 9
9 MRFIC0913 8
7 8
10 7
.047 68 pF 68 pF .047
11 6
3.3 k 2.5 mm 7 mm 68 pF
VG2 tune 12 Out 5
1.0 k 30 Ω 30 Ω 50 Ω Out
VG1 tune
13 Out 4 5.6 pF 5.6 pF
14 3
10 nH
50 Ω In 15 In 2
Cf
16 1 0.22
6.8 pF Rf
330
Grounded Backside
– 4.0 V
Figure 17. MC33169 with GaAs RF Power Amplifier
Tx Power
Control
3.0 V VBatt Input 3.0 V
Idle MMSF4N01HD
0V 0V
100
5 G 4
C2 0.1 6 S 3
1 14
7 Drain S 2
2 13 68 8 1
C1 0.1 C3 1.0
3 12
Ci 0.22 100 C4 1.0
4 MC33169 11
MMBD701
LT1 5 10
Cp 1.0 6 9 VDD
RF In RF Out
7 8 50 Ω In 50 Ω Out
GaAs Power Amplifier

VO
Cf
0.22 Rf
330
– 4.0 V

MC33264
Advance Information
Micropower Voltage
Regulators with On/Off Control
LOW DROPOUT
The MC33264 series are micropower low dropout voltage regulators
available in SO–8 and Micro–8 surface mount packages and a wide range of
MICROPOWER VOLTAGE
output voltages. These devices feature a very low quiescent current (100 µA REGULATORS WITH
in the ON mode; 0.1 µA in the OFF mode), and are capable of supplying
output currents up to 100 mA. Internal current and thermal limiting protection
ON/OFF CONTROL
is provided.
Additionally, the MC33264 has either active HIGH or active LOW control SEMICONDUCTOR
(Pins 2 and 3) that allows a logic level signal to turn–off or turn–on the TECHNICAL DATA
regulator output.
Due to the low input–to–output voltage differential and bias current
specifications, these devices are ideally suited for battery powered
computer, consumer, and industrial equipment where an extension of useful
battery life is desirable. D SUFFIX
PLASTIC PACKAGE
MC33264 Features:
CASE 751
• Low Quiescent Current (0.3 µA in OFF Mode; 95 µA in ON Mode)
8
(SO–8)
• Low Input–to–Output Voltage Differential of 47 mV at 10 mA, and
1
131 mV at 50 mA
• Multiple Output Voltages Available
• Extremely Tight Line and Load Regulation DM SUFFIX
PLASTIC PACKAGE
• Stable with Output Capacitance of Only 8 CASE 846A
0.33 µF for 5.0 V, 6.0 V and 4.75 V Output Voltages 1
(Micro–8)
• Internal Current and Thermal Limiting
• Logic Level ON/OFF Control
• Functionally Equivalent to TK115XXMC and LP2980 PIN CONNECTIONS
Input 1 8 Output
Representative Block Diagram On/Off 2 7 Base
On/Off 3 6 Gnd
1 8 N/C 4 5 Adjust
Vin Vout (Top View)

Thermal and
Anti–Sat 7
Protection
2 Base ORDERING INFORMATION
On/Off Operating
Rint Device Temperature Range Package
MC33264D–2.8
MC33264D–3.0
MC33264D–3.3
5 MC33264D–3.8 SO–8
MC33264D–4.0
Adj MC33264D–4.75
MC33264D–5.0
1.23 V
TA = – 40° to +85°C
Vref 52.5 k MC33264DM–2.8
MC33264DM–3.0
3 MC33264 6 MC33264DM–3.3
On/Off MC33264DM–3.8 Micro–8
Gnd MC33264DM–4.0
MC33264DM–4.75
This device contains 37 active transistors. MC33264DM–5.0

MC33264
MAXIMUM RATINGS (TC = 25°C, unless otherwise noted.)
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ
ÁÁÁÁ
Input Voltage ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
Rating Symbol
VCC
Value
13
Unit
Vdc
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
Maximum Power Dissipation
Case 751 (SO–8) D Suffix
PD Internally Limited W

ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
Case 846A (Micro–8) DM Suffix
ÁÁÁÁ
Output Current
ÁÁÁÁ ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
Maximum Adjustable Output Voltage
IO
VO
100
1.15 x Vnom
mA
Vdc
ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Operating Junction Temperature
ÁÁÁÁÁÁ
ÁÁÁ
Operating Ambient Temperature
TJ
TA
125
–40 to +85
°C
°C
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
Storage Temperature Range
Tstg –65 to +150 °C
ELECTRICAL CHARACTERISTICS (Vin = 6.0 V, IO = 10 mA, CO = 1.0 µF, TJ = 25°C (Note 1), unless otherwise noted.)
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Voltage (IO = 0 mA) VO V
2.8 Suffix (VCC = 3.8 V) 2.74 2.8 2.86
3.0 Suffix (VCC = 4.0 V) 2.96 3.0 3.04
3.3 Suffix (VCC = 4.3 V) 3.23 3.3 3.37
3.8 Suffix (VCC = 4.8 V) 3.72 3.8 3.88
4.0 Suffix (VCC = 5.0 V) 3.92 4.0 4.08
4.75 Suffix (VCC = 5.75 V) 4.66 4.75 4.85
5.0 Suffix (VCC = 6.0 V) 4.9 5.0 5.1
Vin = (VO + 1.0) V to 12 V, IO < 60 mA,TA= –40° to +85°C
2.8 Suffix 2.7 – 2.9
3.0 Suffix 2.9 – 3.1
3.3 Suffix 3.18 – 3.42
3.8 Suffix 3.67 – 3.93
4.0 Suffix 3.86 – 4.14
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
4.75 Suffix 4.58 – 4.92
5.0 Suffix 4.83 – 5.17
ÁÁÁÁÁ
All Suffixes ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Line Regulation (Vin = [VO + 1.0] V to 12 V, IO = 60 mA)
ÁÁÁÁ
ÁÁÁ
Regline – 2.0 10 mV
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Load Regulation (Vin = [VO + 1.0], IO = 0 mA to 60 mA) Regload – 16 25 mV
All Suffixes
Dropout Voltage
IO = 10 mA ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ VI – VO
– 47 90
mV
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
IO = 50 mA – 131 200
IO = 60 mA
ÁÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
147
ÁÁÁÁ
230
Quiescent Current
ÁÁÁ
ON Mode (Vin = [VO + 1.0] V, IO = 0 mA)
IQ
– 95 150
µA
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
OFF Mode – 0.3 2.0
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ON Mode (Vin = [VO – 0.5] V, IO = 0 mA) [Note2] – 540 900
Ripple Rejection (Vin peak–to–peak = [VO + 1.5] to [VO + 5.5] – 55 65 – dB
ÁÁÁÁÁ
V at f = 1.0 kHz)
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Voltage Temperature Coefficient TC – ±120 – ppm/°C
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Current Limit (Vin = [VO + 1.0], VO Shorted) ILimit 100 150 – mA
CL = 1.0 µF
CL = 100 µF
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Noise Voltage (10 Hz to 100 kHz) (Note 3) Vn
–
–
110
46
–
–
µVrms
2. Quiescent current is measured where the PNP pass transistor is in saturation. VCE = –0.5 V guarantees this condition.
3. Noise tests on the MC33264 are made with a 0.01 µF capacitor connected across Pins 8 and 5.

MC33264
ELECTRICAL CHARACTERISTICS (continued) (Vin = 6.0 V, IO = 10 mA, CO = 1.0 µF, TJ = 25°C (Note 1), unless otherwise noted.)
ON/OFF INPUTS
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Logic “1” (Regulator ON)
Logic “0” (Regulator OFF)
ÁÁÁÁ
ÁÁÁ
On/Off Input (Pin 3 Tied to Ground) VOn/Off
2.4
0
–
–
Vin
0.5
V
On/Off Input (Pin 2 Tied to Vin)

Logic “0” (Regulator ON) 0 – Vin – 2.4
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Logic “1” (Regulator OFF) Vin – 0.2 – Vin
On/Off Pin Input Current (Pin 3 Tied to Ground) IOn/Off µA
VOn/Off= 2.4 V – 1.9 –
On/Off Pin Input Current (Pin 2 Tied to Vin)
VOn/Off = Vin – 2.4 V – 12 –
2. Quiescent current is measured where the PNP pass transistor is in saturation. VCE = –0.5 V guarantees this condition.
3. Noise tests on the MC33264 are made with a 0.01 µF capacitor connected across Pins 8 and 5.
DEFINITIONS
Dropout Voltage – The input/output voltage differential at Load Regulation – The change in output voltage for a
which the regulator output no longer maintains regulation change in load current at constant chip temperature.
against further reductions in input voltage. Measured when Maximum Power Dissipation – The maximum total
the output drops 100 mV below its nominal value (which is device dissipation for which the regulator will operate within
measured at 1.0 V differential), dropout voltage is affected by specifications.
junction temperature, load current and minimum input supply Quiescent Current – Current which is used to operate the
requirements. regulator chip and is not delivered to the load.
Line Regulation – The change in output voltage for a Output Noise Voltage – The rms ac voltage at the output,
change in input voltage. The measurement is made under with constant load and no input ripple, measured over a
conditions of low dissipation or by using pulse techniques such specified frequency range.
that average chip temperature is not significantly affected.
Figure 1. Quiescent Current

versus Load Current Figure 2. Dropout Voltage versus Input Voltage
5.0 6.0
IQ, MC33264 QUIESCENT CURRENT (mA)
5.0
TA = 25°C
MC33264D–5.0
1.0 4.0
RL = 5.0 k
3.0
RL = 100 Ω
2.0
0.10
1.0
0.03 0
0.1 1.0 10 100 0 1.0 2.0 3.0 4.0 5.0 6.0
Iload, LOAD CURRENT (mA) Vin, INPUT VOLTAGE (V)

MC33264
Figure 3. Input Current versus Input Voltage Figure 4. Output Voltage versus Temperature
1000 5.04
5.03
800

Iin , INPUT CURRENT (mA)
5.02
IO = 10 mA
600 5.01 TA = 25°C
MC33264D–5.0
No Load 5.00
TA = 25°C
400
MC33264D–5.0 4.99
4.98
200
4.97
0 4.96
0 2.0 4.0 6.0 8.0 10 12 –55 –25 0 25 50 75 100 125
Vin, INPUT VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
V I – VO, DROPOUT VOLTAGE (mV) RL= 100 to 500 Ω

Figure 5. Dropout Voltage versus Output Current Figure 6. Dropout Voltage versus Temperature
V I – VO, DROPOUT VOLTAGE (mV) RL= 5.0 k

240 300 55
VCC = 6.0 V RL = 5.0 k
V I – VO, DROPOUT VOLTAGE (mV)
VO = 5.0 V Vin= 6.0 V

200 RL = 40 to 50 k 250 TA = 25°C RL = 100 50
CL = 1.0 µF
160 TA = 25°C
200 45
120 RL = 5.0 k
150 40
80
100 RL = 500 35
40
0 50 30
0.3 1.0 10 100 400 –50 0 50 100 150
IO, OUTPUT CURRENT (mA) TA, TEMPERATURE (°C)
Introduction On/Off Control
The MC33264 regulators are designed with internal On/Off control of the regulator may be accomplished in
current limiting and thermal shutdown making them either of two ways. Pin 3 may be tied to circuit ground and a
user–friendly. These regulators require only 0.33 µF (or positive logic control applied to Pin 2. The regulator will be
greater) capacitance between the output terminal and ground turned on by a positive (>2.4 V) level, typically 5.0 V with
for stability for 2.8 V, 3.0 V, and 3.3 V output voltage options. respect to ground, sourcing a typical current of 6.0 µA. The
Output voltage options of 5.0 V, 6.0 V and 4.75 V require only regulator will turn off if the control input is a logic “0”
0.22 µF for stability. The output capacitor must be mounted (<0.5 V). Alternatively, Pin 2 may be tied to the regulator
as close to the MC33264 as possible. If the output capacitor input voltage and a negative logic control applied to Pin 3.
must be mounted further than two centimeters away from the The regulator will be turned on when the control voltage is
MC33264, then a larger value of output capacitor may be less than Vin – 2.4 V, sinking a typical current of 18 µA when
required for stability. A value of 0.68 µF or larger is Vin = 6.0 V. The regulator is off when the control input is
recommended. Most types of aluminum, tantalum or open or greater than Vin – 0.2 V.
multilayer ceramic will perform adequately. Solid tantalums
Programming The Output Voltage
or appropriate multilayer ceramic capacitors are
recommended for operation below 25°C. The MC33264 output voltage is automatically set using its
A bypass capacitor is recommended across the MC33264 internal voltage divider. Alternatively, it may be programmed
input to ground if more than 4.0 inches of wire connects the within a typical ±15% range of its preset output voltage. An
input to either a battery or power supply filter capacitor. external pair of resistors is required, as shown in Figure 7.

MC33264
Figure 7. Regulator Output Voltage Trim

Vin
3.3 µF
1
Vin
2 8 Vout
Control Input On/Off Vout
3.0, 3.3 or 5.0 V
7 3.3 µF
Base N/C
3 4 R1
On/Off N/C
0.01
Gnd Adj
6 5
R2
ǒ Ǔ
The complete equation for the output voltage is: increasing the size of the output capacitor is the only method
V out + Vref 1 ) R1
R2
) IFB R1 for reducing noise.
Noise can be reduced fourfold by a bypass capacitor
across R1, since it reduces the high frequency gain from 4 to
where Vref is the nominal 1.235 V reference voltage and IFB is unity for the MC33264D–5.0. Pick
the feedback pin bias current, nominally –20 nA. The
minimum recommended load current of 1.0 µA forces an C
BYPASS
+ 2π R1 x1 200 Hz
upper limit of 1.2 MΩ on the value of R2, if the regulator must
work with no load. IFB will produce a 2% typical error in Vout or about 0.01 µF. When doing this, the output capacitor must
which may be eliminated at room temperature by adjusting be increased to 3.3 µF to maintain stability. These changes
R1. For better accuracy, choosing R2 = 100 K reduces this reduce the output noise from 430 µV to 100 Vrms for a
error to 0.17% while increasing the resistor program current 100 kHz bandwidth for the 5.0 V output device. With the
to 12 µA. bypass capacitor added, noise no longer scales with output
voltage so that improvements are more dramatic at higher
Output Noise output voltages.
In many applications it is desirable to reduce the noise
present at the output. Reducing the regulator bandwidth by
TYPICAL APPLICATIONS
Figure 8. Lithium Ion Battery Cell Charger
Unregulated Input
6.0 to 10 Vdc
1
2 Vin 8 1N4001 4.2 V ± 0.15 V
Control On/Off Vout
200 k
7 1%
Base N/C
0.1
MC33264D–5.0 Lithium Ion
3 4 Rechargeable Cell
On/Off N/C
100 k
1%
0.22
Gnd Adj
6 5 50 k
Ground

MC33264
Figure 9. Low Drift Current Source
+V = 4.0 to 12 V
IL
Load IL = 1.23/R
1 0.1
Vin
2 8
Control On/Off Vout
7
Base N/C
3
On/Off 4
N/C
Gnd Adj
6 5
R 1.0 µF
Figure 10. 2.0 Ampere Low Dropout Regulator

+Vin
Current Limit
Section
1000 µF
680 470 0.05
2N3906
2N3906
120 k
TIP32B
0.33
1
Vin
2 8
On/Off Vout
7
Base N/C
MC33264 Vout @ 2.0 A
220 3 4 4.7 µF 100 µF
On/Off Tant
N/C
0.01 R1
75 k Gnd Adj
0.033
6 5
R2

MC33264
Figure 11. Low Battery Disconnect
6.0 V
22.1 k 31.6 k Lead–Acid Battery
100 k
2
1
Vin
MC34164P–5 1 5 8
On/Off Vout Main V+
0.1
3 2 Memory V+
Base
MC33264
3 4
On/Off 20
N/C
Gnd Adj NiCad

R2 1.0 µF
4 5 3.0 k Backup Battery
R1
1.0 k
Figure 12. RF Amplifier Supply

1.0
VBattery 7.0 V
0.1 0.1 100 µF
200
VBB Double 12 2 1 VCC 14 TIP32B

3 1 0.33
VBB 8
Vin
11 Generator Gate Drive 2 8
(Voltage Tripler) MC33169 Output On/Off Vout
VBB
1.0
Triple 7
Base N/C
9 MC33264
Priority
3 4
Tx On Input Management On/Off N/C
13
On/Off
Idle Mode Input Sense Gnd Adj 3.0 k
10
0.01
6 5
Sense 5.0 V @ 0.5 A
6 Input
Gnd Charge Negative 4.7 µF 100 µF
1.0 k
Pump Generator Tant
VSS
(–2.5 V or –4.0 V) Output
7 5 4
RF
RF In
Out
1.0 1N5819 Power Amplifier
0.22
0.1
100

MC33267
Low Dropout Regulator
The MC33267 is a positive fixed 5.0 V regulator that is specifically
designed to maintain proper voltage regulation with an extremely low
input–to–output voltage differential. This device is capable of supplying
LOW DROPOUT
output currents in excess of 500 mA and contains internal current limiting and REGULATOR with
thermal shutdown protection. Also featured is an on–chip power–up reset
circuit that is ideally suited for use in microprocessor based systems.
POWER–UP RESET
Whenever the regulator output voltage is below nominal, the reset output is SEMICONDUCTOR
held low. A programmable time delay is initiated after the regulator has TECHNICAL DATA
reached its nominal level and upon timeout, the reset output is released.
Due to the low dropout voltage specifications, the MC33267 is ideally
suited for use in battery powered industrial and consumer equipment where
an extension of useful battery life is desirable. This device is contained in an Pin 1. VCC Input
economical five lead TO–220 type package. 2. Reset
• Low Input–to–Output Voltage Differential 3. Ground
4. Delay
• Output Current in Excess of 500 mA 5. Output
• On–Chip Power–Up Reset Circuit with Programmable Delay
• Internal Current Limiting with Thermal Shutdown
• Economical Five Lead TO–220 Type Packages
1
5
Tested Operating T SUFFIX
PLASTIC PACKAGE
CASE 314D
MC33267T Plastic Power
TJ = –40 ° to +125°C
MC33267TV Plastic Power
MC33267D2T TJ = –40 ° to +105°C Surface Mount
1
TV SUFFIX
PLASTIC PACKAGE
CASE 314B
Representative Block Diagram
Heatsink surface connected to Pin 3.
Input Output
1 5
3.01
R 20 µA
Reference Reset
1.25 V Reset
0.03 2 1
R +
5
3.8 V
R Delay
Thermal D2T SUFFIX
Delay
200 4 PLASTIC PACKAGE
Overcurrent
Detector + CASE 936A
(D2PAK)
1.25 V
Ground 3 Heatsink surface (shown as

terminal 6 in case outline
drawing) is connected to Pin 3.

MC33267
MAXIMUM RATINGS
Input Voltage Range Vin – 20 to + 40 Vdc
Delay Voltage Range VDLYR – 0.3 to VO V
Delay Sink Current IDLY(sink) 25 mA
Reset Voltage Range VRR – 0.3 to +15 V
Reset Sink Current IR(sink) 50 mA
Power Dissipation
Case 314B and 314D (TO–220 Type)
Thermal Resistance, Junction–to–Ambient RθJA 62.5 °C/W
Case 936A (D2PAK) [Note 1]
NOTE: 1. D2PAK Junction–to–Ambient Thermal Resistance is for vertical mounting. Refer to Figure 7
for board mounted thermal resistance.
ELECTRICAL CHARACTERISTICS (Vin = 14.4 V, IO = 5.0 mA, CO = 100 µF, CO(ESR) ≤ 0.3 Ω, TJ = 25°C (Note 2), unless otherwise noted.)
Output Voltage (IO = 5.0 mA to 500 mA, Vin = 6.0 V to 28 V) VO V
TJ = 25°C 4.95 5.05 5.15
TJ = – 40° to +125°C 4.9 – 5.2
Line Regulation (Vin = 6.0 V to 26 V) Regline – 3.0 50 mV
Load Regulation (IO = 5.0 mA to 500 mA) Regload – 1.0 50 mV
Bias Current IB mA
IO = 0 mA – 12 20
IO = 150 mA – 22 40
IO = 500 mA – 100 200
IO = 500 mA, Vin = 6.2 V – 120 300
Ripple Rejection (f = 120 Hz, Vin = 7.0 V to 17 V, RR dB
IO = 350 mA, CO = 100 µF) 60 80 –
Dropout Voltage (IO = 500 mA) Vin – VO – 0.58 0.8 V

Delay Comparator Threshold (VO Decreasing) Vth(DLY) 4.8 VO – 0.15 VO – 0.08 V
Delay Pin Source Current IDLY(source) 12 20 28 µA
Reset Comparator Threshold Vth(R) 3.6 3.8 4.0 V
Reset Sink Saturation (Isink = 10 mA) VCE(sat) – 0.2 0.8 V
Reset Off–State Leakage (VCE = 5.0 V) IR(leak) – 0.3 10 µA
NOTE: 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

MC33267
Figure 1. Typical Application Circuit
Input Output
Vin VO
+ 1 5 +
Cin 0.1 3.01 CO 100
R 20 µA
Reference
1.25 V Reset Reset
Output
0.03 2
R +
3.8 V
R
Thermal Delay
Delay
200 4 +
CDLY
Overcurrent
+
Detector
1.25 V
Ground 3
Sink Only
=
Positive True Logic
APPLICATION CIRCUIT INFORMATION

The MC33267 is a low dropout, positive fixed 5.0 V, decrease and the ESR will increase drastically, causing the
500 mA regulator. Protection features include output current circuit to oscillate. Quality electrolytic capacitors with
limiting and thermal shutdown. System protection consists of extended temperature ranges of – 40°C to + 85°C and
an on–chip power–up microprocessor reset circuit. – 55°C to +105°C are readily available. It is suggested that
A typical applications circuit is shown in Figure 1. The input oven testing of the entire circuit be performed with maximum
bypass capacitor (Cin) is recommended if the regulator is load, minimum input voltage, and minimum ambient
located an appreciable distance (≥ 4″) from the supply input temperature.
filter. This will reduce the circuit’s sensitivity to the input line Figure 2 shows the reset circuit timing relationship. Note
impedance at high frequencies. that whenever the regulator’s output is less than 4.9 V, the
These regulators are not internally compensated and thus delay capacitor (CDLY) is immediately discharged, and the
require an external output capacitor (CO) for stability. The reset output is held in a low state. As the regulator’s output
recommended capacitance is 100 µF with an equivalent voltage increases beyond 4.97 V, the delay comparator will
series resistance (ESR) of less than 0.3 Ω. A minimum allow the 20 µA current source to charge CDLY. The reset
capacitance of 33 µF with a maximum ESR of 3.0 Ω can be output will go to a high state when CDLY crosses the 3.8 V
used in applications where space is a premium, however, threshold of the reset comparator. The reset delay time is
these limits must be observed over the entire operating controlled by the value selected for CDLY. The required
temperature range of the regulator circuit. system reset time is governed by the microprocessor and
With economical electrolytic capacitors, cold temperature usually a reset signal which lasts several machine cycles is
operation can pose a serious stability problem. As the sufficient.
electrolyte freezes, around – 30°C, the capacitance will

MC33267
Figure 2. Timing Waveforms
5.05 V
Regulator Output 4.97 V 150 mV
(Pin 5) 4.90 V
4.70 V
3.80 V
Delay Capacitor
(Pin 4)
0.48 V
5.05 V
Reset Output
(Pin 2)
0V
tDLY tDLY
Figure 3. Reset Output versus Input Voltage Figure 4. Output Voltage versus Input Voltage
6.0 6.0
RL = 10 k to VO TJ = 25°C
VO , RESET OUTPUT VOLTAGE (V)
5.0 TJ = 25°C 5.0

RL = ∞
4.0 4.0
RL = 10 Ω
3.0 3.0
RL = 10 Ω
2.0 2.0
RL = ∞
1.0 1.0
0 0
0 2.0 4.0 6.0 8.0 0 2.0 4.0 6.0 8.0

MC33267
Figure 5. Reset Output versus Input Voltage Figure 6. Output Voltage versus Input Voltage
6.0 6.0
RL = 10 k to VO TJ = 25°C
VO , RESET OUTPUT VOLTAGE (V)
5.0 TJ = 25°C 5.0

RL = ∞
4.0 4.0
RL = 10 Ω
3.0 3.0
RL = 10 Ω
2.0 2.0
RL = ∞
1.0 1.0
0 0
0 2.0 4.0 6.0 8.0 0 2.0 4.0 6.0 8.0

80 3.5

70 Free Air 3.0

Mounted
60 2.5
ÎÎÎ
L
ÎÎÎ
50 Minimum 2.0
ÎÎÎ
Size Pad L
40 1.5
RθJA
30 1.0
0 5.0 10 15 20 25 30

MC33269
Advance Information
Low Dropout Positive
Fixed and Adjustable 800 mA
Voltage Regulators
LOW DROPOUT
THREE–TERMINAL
The MC33269 series are low dropout, medium current, fixed and VOLTAGE REGULATORS
adjustable, positive voltage regulators specifically designed for use in low
input voltage applications. These devices offer the circuit designer an
economical solution for precision voltage regulation, while keeping power
losses to a minimum. D SUFFIX
The regulator consists of a 1.0 V dropout composite PNP–NPN pass 8 PLASTIC PACKAGE
CASE 751
transistor, current limiting, and thermal shutdown. 1 (SOP–8)
• 3.3 V, 5.0 V, 12 V and Adjustable Versions
• Space Saving DPAK and SOP–8 Power Package
Gnd/Adj 1 8 NC
• 1.0 V Dropout
2 7
• Output Current in Excess of 800 mA Vout Vout
6
•
3
Thermal Protection
Vin 4 5 NC
• Output Trimmed to 1.0% Tolerance (Top View)

• No Minimum Load Requirement for Fixed Voltage Output Devices
DT SUFFIX
PLASTIC PACKAGE
1 CASE 369A
3 (DPAK)
Operating
1. Gnd/Adj
MC33269D SOP–8
2. Vout
MC33269DT DPAK 3. Vin
1 2 3
MC33269T Insertion Mount
MC33269D–3.3 SOP–8 (Top View)
MC33269DT–3.3 DPAK
MC33269T–3.3 Insertion Mount case outline drawing) is connected to Pin 2.
TJ = – 40° to +125°C
MC33269D–5.0 SOP–8
MC33269DT–5.0 DPAK
MC33269T–5.0 Insertion Mount
T SUFFIX
MC33269D–12 SOP–8
PLASTIC PACKAGE
MC33269DT–12 DPAK CASE 221A
MC33269T–12 Insertion Mount
1
Pin: 1. Gnd/Adj
DEVICE TYPE/NOMINAL OUTPUT VOLTAGE 2
3 2. Vout
MC33269D Adj MC33269D–5.0 5.0 V 3. Vin
MC33269DT Adj MC33269DT–5.0 5.0 V
MC33269T Adj MC33269T–5.0 5.0 V 1 2 3
MC33269D–3.3 3.3 V MC33269D–12 12 V (Top View)
MC33269DT–3.3 3.3 V MC33269DT–12 12 V
MC33269T–3.3 3.3 V MC33269T–12 12 V Heatsink surface (shown as terminal 4 in

MC33269
MAXIMUM RATINGS
Power Supply Input Voltage Vin 20 V
Power Dissipation
Case 369A (DPAK)
Case 751 (SOP–8)
Thermal Resistance, Junction–to–Case θJC 25 °C/W
Case 221A
ELECTRICAL CHARACTERISTICS (CO = 10 µF, TA = 25°C, for min/max values TJ = –40°C to +125°C, unless otherwise noted.)
Output Voltage (Iout = 10 mA, TJ = 25°C) VO V
3.3 Suffix (VCC = 5.3 V) 3.27 3.3 3.33
5.0 Suffix (VCC = 7.0 V) 4.95 5.0 5.05
12 Suffix (VCC = 14 V) 11.88 12 12.12
Output Voltage (Line, Load and Temperature) (Note 1) VO V
(1.25 V ≤ Vin – Vout ≤ 15 V, Iout = 500 mA)
3.3 Suffix 3.23 3.3 3.37
5.0 Suffix 4.9 5.0 5.1
12 Suffix 11.76 12 12.24
Reference Voltage (Iout = 10 mA, Vin – Vout = 2.0 V, TJ = 25°C) Vref 1.235 1.25 1.265 V
Adjustable
Reference Voltage (Line, Load and Temperature) (Note 1) Vref 1.225 1.25 1.275 V
Adjustable
Line Regulation Regline – – 0.3 %
(Iout = 10 mA, Vin = [Vout + 1.5 V] to Vin = 20 V, TJ = 25°C)
Load Regulation (Vin = Vout + 3.0 V, Iout = 10 mA to 800 mA, TJ = 25°C) Regload – – 0.5 %
Dropout Voltage Vin – Vout V
(Iout = 500 mA) – 1.0 1.25
(Iout = 800 mA) – 1.1 1.35
Ripple Rejection RR 55 – – dB
(10 Vpp, 120 Hz Sinewave; Iout = 500 mA)
Current Limit (Vin – Vout = 10 V) ILimit 800 – – mA

Quiescent Current (Fixed Output) IQ – 5.5 8.0 mA
Minimum Required Load Current ILoad mA
Fixed Output – – 0
Adjustable 8.0 – –
Adjustment Pin Current IAdj – – 120 µA
NOTE 1: The MC33269–12, Vin – Vout is limited to 8.0 V maximum, because of the 20 V maximum rating applied to Vin.

MC33269
Internal Schematic
Vin
Vout
Trim Links
VAdj Gnd

R θ JA, THERMAL RESISTANCE, JUNCTION–TO–AIR (° C/W)
R θ JA, THERMAL RESISTANCE, JUNCTION–TO–AIR (°C/W)
Figure 1. SOP–8 Thermal Resistance and Maximum Figure 2. DPAK Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length Power Dissipation versus P.C.B. Copper Length
170 3.2 2.4

100

Free Air
150 2.8 2.0
PD(max) for TA = 50°C 90 Mounted
ÏÏÏ
Vertically
130 2.4 2.0 oz. Copper
80 1.6
ÏÏÏ ÏÏÏ ÏÏÏ

L
110 Graph represents symmetrical layout 2.0 Minimum
ÏÏÏ
70 Size Pad 1.2
1.6 L
90

2.0 oz.
L
Copper 60 0.8
70 1.2
L 3.0 mm
0.8 50 0.4
50
RθJA
RθJA
30 0.4 40 0
0 10 20 30 40 50 0 5.0 10 15 20 25 30
L, LENGTH OF COPPER (mm) L, LENGTH OF COPPER (mm)

MC33269

Output Load Current Figure 4. Transient Load Regulation
1.5
VOLTAGE DEVIATION
Vin–Vout , DROPOUT VOLTAGE (V)
∆ VO , OUTPUT
1.3
TA = 25°C TA = –40°C 100

1.1
mV/Div
Cin = 10 µF
0.9 TA = 125°C CO = 10 µF Tantalum
Vin = VO + 3.0 V
I O , OUTPUT
Preload = 0.1 A
CURRENT
0.7 0.5 A
0.5 0A
0 200 400 600 800 1000 20 ms/DIV
IO, OUTPUT LOAD CURRENT (mA)
Figure 5. Dropout Voltage Figure 6. MC33269–XX Output DC Current versus

V FB(OV), OVERVOLTAGE INPUT THRESHOLD (%VFB )
versus Temperature Input–Output Differential Voltage

1100 1.6
IO = 800 mA 1.4
1060 OUTPUT CURRENT (A) 1.2
1.0 TA = 25°C
1020
MC33269D–XX
0.8 L = 25 mm Copper
980 0.6
0.4
940
0.2
900 0
–55 –25 0 25 50 75 100 125 0 2.0 4.0 6.0 8.0 10 12 14 16
TA, AMBIENT TEMPERATURE (°C) INPUT–OUTPUT VOLTAGE DIFFERENTIAL (V)
Figure 7. MC33269 Ripple Rejection Figure 8. MC33269–ADJ Ripple Rejection

70 70
VO = 3.3 V or 5.0 V
60 60
VO = 12 V
50 50
Vin = 8.0 V
Vout = 5.0 V
40 Vin = VO + 3.0 V 40 IL = 800 mA
IL = 800 mA CAdj = 22 µF
TA = 25°C TA = 25°C
30 30
20 20
0.1 1.0 10 100 0.1 1.0 10 100
f, FREQUENCY (kHz) f, FREQUENCY (kHz)

MC33269
Figures 9 through 13 are typical application circuits. The filter with long wire lengths. This will reduce the circuit’s
output current capability of the regulator is in excess of sensitivity to the input line impedance at high frequencies. A
800 mA, with a typical dropout voltage of less than 1.0 V. 0.33 µF or larger tantalum, mylar, ceramic, or other capacitor
Internal protective features include current and thermal having low internal impedance at high frequencies should be
limiting. chosen. The bypass capacitor should be mounted with
The MC33269 is not internally compensated and thus shortest possible lead or track length directly across the
requires an external output capacitor for stability. The regulator’s input terminals. Applications should be tested
capacitor should be at least 10 µF with an equivalent series over all operating conditions to insure stability.
resistance (ESR) of less than 10 Ω over the anticipated Internal thermal limiting circuitry is provided to protect the
operating temperature range. With economical electrolytic integrated circuit in the event that the maximum junction
capacitors, cold temperature operation can pose a problem. temperature is exceeded. When activated, typically at 170°C,
As temperature decreases, the capacitance also decreases the output is disabled. There is no hysteresis built into the
and the ESR increases, which could cause the circuit to thermal limiting circuit. As a result, if the device is
oscillate. Solid tantalum capacitors may be a better choice if overheating, the output will appear to be oscillating. This
small size is a requirement. Also capacitance and ESR of a feature is provided to prevent catastrophic failures from
solid tantalum capacitor is more stable over temperature. An accidental device overheating. It is not intended to be used
input bypass capacitor is recommended to improve transient as a substitute for proper heatsinking.
response or if the regulator is connected to the supply input
Figure 9. Typical Fixed Output Application Figure 10. Typical Adjustable Output Application
Vin Vout Vin Vout

MC33269–XX MC33269
CO Cin
Cin R1
10 µF CO
Adj
Gnd 10 µF
R2
CAdj*
ǒ Ǔ
An input capacitor is not necessary for stability, however
it will improve the overall performance.
V out + 1.25 1 ) R2
R1
) IAdj R2
Figure 11. Current Regulator
*CAdj is optional, however it will improve the ripple rejection.
Vin RS Iout The MC34269 develops a 1.25 V reference voltage between the
MC33269 output and the adjust terminal. Resistor R1, operates with
Cin CO constant current to flow through it and resistor R2. This current
10 µF should be set such that the Adjust Pin current causes negligible
Adj
drop across resistor R2. The total current with minimum load
should be greater than 8.0 mA.
I out + 1.25
R
S
Figure 12. Battery Backed–Up Power Supply Figure 13. Digitally Controlled Voltage Regulator
Vin Vout Vin Vout

MC33269–XX MC33269
Cin Cin
R1
Gnd Adj
CO
10 µF
R2
MC33269–XX
Cin CO
10 µF
Gnd
The Schottky diode in series with the ground leg of the upper R2 sets the maximum output voltage. Each transistor
regulator shifts its output voltage higher by the forward reduces the output voltage when turned on.
voltage drop of the diode. This will cause the lower device
to remain off until the input voltage is removed.

MC33340
Product Preview
Battery Fast Charge
Controller
The MC33340 is a monolithic control IC that is specifically designed as a
fast charge controller for Nickel Cadmium (NiCd) and Nickel Metal Hydride BATTERY FAST CHARGE
(NiMH) batteries. This device features negative slope voltage detection as CONTROLLER
the primary means for fast charge termination. Accurate detection is ensured
by an output that momentarily interrupts the charge current for precise
voltage sampling. An additional secondary backup termination method can SEMICONDUCTOR
be selected that consists of either a programmable time or temperature limit. TECHNICAL DATA
Protective features include battery over and undervoltage detection, latched
over temperature detection, and power supply input undervoltage lockout
with hysteresis. Provisions for entering a rapid test mode are available to
enhance end product testing. This device is available in an economical
8–lead surface mount package.
• Negative Slope Voltage Detection
• Accurate Zero Current Battery Voltage Sensing
• Programmable 1 to 4 Hour Fast Charge Time Limit
P SUFFIX
PLASTIC PACKAGE
• Programmable Over/Under Temperature Detection
8
CASE 626
• Battery Over and Undervoltage Fast Charge Protection 1
• Rapid System Test Mode
• Power Supply Input Undervoltage Lockout with Hysteresis
• Operating Voltage Range of 3.0 V to 18 V
D SUFFIX
8
PLASTIC PACKAGE
1 CASE 751
Simplified Block Diagram (SO–8)
DC
Regulator
Input VCC 8
Undervoltage
Internal Bias Lockout
VCC
PIN CONNECTIONS
Vsen Voltage to
Frequency
1 Converter Over
Temp Vsen Input 1 8 VCC
Ck F/V R Latch
R Battery
High Over Q Vsen Gate Output 2 7 t1/Tref High
S Pack
Battery Temp
Detect Detect Fast/Trickle Output 3 6 t2/Tsen
Low Under
t1/Tref High Gnd 4 5 t3/Tref Low
t1
–∆V Detect 7
Counter
Vsen t2/Tsen (Top View)
Timer t2
Gate
Vsen 6
2
Gate t3/Tref Low
t3
3 5
Fast/ F/T t/T VCC ORDERING INFORMATION
Trickle Time/
Temp Operating
Select Temperature Range
Device Package
Gnd 4
MC33340D SO–8
TA = –25° to +85°C
This device contains 2,512 active transistors. MC33340P Plastic DIP

MC33340
MAXIMUM RATINGS
Power Supply Voltage (Pin 8) VCC 18 V
Input Voltage Range V
Time/Temperature Select (Pins 5, 6, 7) VIR(t/T) –1.0 to VCC
Battery Sense, Note 1 (Pin 1) VIR(sen) –1.0 to VCC + 0.6
or
–1.0 to 10
Vsen Gate Output (Pin 2)
Voltage VO(gate) 20 V
Current IO(gate) 50 mA
Fast/Trickle Output (Pin 3)
Voltage VO(F/T) 20 V
Current IO(F/T) 50 mA
Thermal Resistance, Junction–to–Air RθJA °C/W
P Suffix, DIP Plastic Package, Case 626 100
D Suffix, SO–8 Plastic Package, Case 751 178
Operating Ambient Temperature (Note 2) TA –25 to +85 °C
ELECTRICAL CHARACTERISTICS (VCC = 6.0 V, TA = 25°C, for min/max values TA is the operating ambient temperature
range that applies (Note 2), unless otherwise noted.)
BATTERY SENSE INPUT (Pin 1)
Overvoltage Threshold Vth(OV) V
TA = 25°C – 2.0 –
TA = Tlow to Thigh – 1.94 to 2.06 –
Undervoltage Threshold Vth(UV) V
TA = 25°C – 1.0 –
TA = Tlow to Thigh – 1.97 to 1.03 –
Input Bias Current IIB – 10 – nA
Input Resistance Rin – 10 – MΩ
TIME/TEMPERATURE INPUTS (Pins 5, 6, 7)
Programming Inputs (Vin = 1.5 V)
Input Current Iin – –30 – µA
Input Current Matching ∆Iin – 0.5 – %
Input Offset Voltage, Over and Under Temperature Comparators VIO – 5.0 – mV
Under Temperature Comparator Hysteresis (Pin 5) VH(T) – 44 – mV
Temperature Select Threshold Vth(t/T) – VCC – 0.7 – mV
INTERNAL TIMING
Internal Clock Oscillator Frequency fOSC kHz
TA = 25°C
VCC = 6.0 V – 840 –
VCC = 3.0 V to 18 V – 693 to 987 –
TA = Tlow to Thigh
VCC = 6.0 V – 680 to 1000 –
VCC = 3.0 V to 18 V – 670 to 1010 –
Vsen Gate Output (Pin 2) tgate
Gate Time – 30 – ms
Gate Repetition Rate – 1.25 – s
Trickle Mode Holdoff Time from –∆V Detection thold – 160 – s
NOTES: 1. Whichever voltage is lower.
2. Tested ambient temperature range for the MC33340: Tlow = – 25°C Thigh = + 85°C
Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

MC33340
ELECTRICAL CHARACTERISTICS (continued) (VCC = 6.0 V, TA = 25°C, for min/max values TA is the operating ambient temperature
range that applies (Note 2), unless otherwise noted.)
Vsen GATE OUTPUT (Pin 2)
Off–State Leakage Current (VO = 20 V) Ioff – 0.1 – µA
Low State Saturation Voltage (Isink = 10 mA) VOL – 1.2 – V
FAST/TRICKLE OUTPUT (Pin 3)
Off–State Leakage Current (VO = 20 V) Ioff – 0.1 – µA
Low State Saturation Voltage (Isink = 10 mA) VOL – 1.0 – V
UNDERVOLTAGE LOCKOUT (Pin 8)
Startup Threshold (VCC Increasing) Vth(on) – 3.0 – V
Hysteresis (VCC Decreasing) VH – 100 – mV
Power Supply Current (Pins 5, 6, 7 Open) ICC mA
Startup (VCC = 2.9 V) – 0.65 –
Operating (VCC = 6.0 V) – 0.61 –
NOTES: 1. Whichever voltage is lower.
2. Tested ambient temperature range for the MC33340: Tlow = – 25°C Thigh = + 85°C
Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Figure 1. Battery Sense Input Thresholds Figure 2. Oscillator Frequency

∆ f OSC, OSCILLATOR FREQUENCY CHANGE (%)
V th, OVER/UNDERVOLTAGE THRESHOLDS (V)
2.10 20
VCC = 6.0 V
VCC = 6.0 V
2.00
12
1.90
4.0
1.02
–4.0
1.00
0.98 –12
– 50 – 25 0 25 50 75 100 125 – 50 – 25 0 25 50 75 100 125

MC33340
V th(t/T), TEMPERATURE SELECT THRESHOLD VOLTAGE (V

Figure 3. Temperature Select Threshold Voltage Figure 4. Saturation Voltage versus Sink Current
versus Temperature Vsen Gate and Fast/Trickle Outputs
0 3.2
VOL , SINK SATURATION VOLTAGE (V)

VCC = 6.0 V VCC = 6.0 V
VCC TA = 25°C
–0.2
Threshold voltage is measured with respect to VCC. 2.4
Vsen Gate
–0.4
Pin 2
Time mode is selected if any of
1.6
the three inputs are above the
–0.6 threshold. Fast/Trickle
Pin 3
Temperature mode is selected 0.8

–0.8
when all three inputs are below
the threshold.
–1.0 0
–50 –25 0 25 50 75 100 125 0 8.0 16 24 32 40
TA, AMBIENT TEMPERATURE (°C) Isink, SINK SATURATION (mA)
Figure 5. Undervoltage Lockout Thresholds Figure 6. Supply Current

3.1 1.0
TA = 25°C
Startup Threshold

(VCC Increasing)
VCC , SUPPLY VOLTAGE (V)
0.8
3.0
0.6
2.9
0.4
2.8
Minimum Operating Threshold 0.2
(VCC Decreasing)
2.7 0
– 50 – 25 0 25 50 75 100 125 0 4.0 8.0 12 16
INTRODUCTION
Nickel Cadmium and Nickel Metal Hydride batteries counter for detection of a negative slope in battery voltage. A
require precise charge termination control to maximize cell timer with three programming inputs is available to provide
capacity and operating time while preventing overcharging. backup charge termination. Alternatively, these inputs can be
Overcharging can result in a reduction of battery life as well used to monitor the battery pack temperature and to set the
as physical harm to the end user. Since most portable over and under temperature limits also for backup charge
applications require the batteries to be charged rapidly, a termination.
primary and usually a secondary or redundant charge Two active low open collector outputs are provided to
sensing technique is employed into the charging system. It is interface this controller with the external charging circuit. The
also desirable to disable rapid charging if the battery voltage first output furnishes a gating pulse that momentarily
or temperature is either too high or too low. In order to interrupts the charge current. This allows an accurate
address these issues, an economical and flexible fast charge method of sampling the battery voltage by eliminating voltage
controller was developed. drops that are associated with high charge currents and
The MC33340 contains many of the building blocks and wiring resistances. Also, any noise voltages generated by the
protection features that are employed in modern high charging circuitry are eliminated. The second output is
performance battery charger controllers that are specifically designed to switch the charging source between fast and
designed for Nickel Cadmium and Nickel Metal Hydride trickle modes based upon the results of voltage, time, or
batteries. The device is designed to interface with either temperature. These outputs normally connect directly to a
primary or secondary side regulators for easy implementation linear or switching regulator control circuit in non–isolated
of a complete charging system. A representative block primary or secondary side applications. Both outputs can be
diagram in a typical charging application is shown in Figure 7. used to drive optoisolators in primary side applications that
The battery voltage is monitored by the Vsen input that require galvanic isolation. Figure 8 shows the typical charge
internally connects to a voltage to frequency converter and characteristics for NiCd and NiMh batteries.

MC33340
Figure 7. Typical Battery Charging Application
Regulator
DC
Input
MC33340 VCC 8
Reg Control
Undervoltage
Lockout
Internal Bias VCC
R2 Voltage to
Vsen 2.9 V T RNTC
Frequency
1 Converter
Over
R1 Temp
Charge Latch
Ck F/V R R
Status Battery
High Over Q Pack
2.0 V S
Battery Temp
Detect Detect
1.0 V
Low Under
30 µA t1/Tref High
t1
–∆V Detect 7
Counter SW1 R3
Vsen Timer 30 µA t2/Tsen
Gate t2
Vsen 6
2 SW2
Gate
30 µA t3/Tref Low
t3
3 5
SW3 R4
Fast/ F/T t/T VCC
Trickle Time/
Temp
0.7 V
Select
Gnd 4
R2 + R1 ǒ Ǔ
VBatt
Vsen
–1
Figure 8. Typical Charge Characteristics for NiCd and NiMh Batteries

1.6 Vmax 70
–∆V
dV
1.5 dt 60
Tmax
CELL TEMPERATURE (° C)
CELL VOLTAGE (V)
1.4 50
1.3 40
Voltage
1.2 30
Temperature
1.1 20
Relative Pressure
1.0 10
0 40 80 120 160
CHARGE INPUT PERCENT OF CAPACITY

MC33340
The MC33340 starts up in the fast charge mode when The Sample Timer circuit provides a 105 kHz system clock
power is applied to VCC. A change to the trickle mode can signal (SCK) to the VFC. This signal synchronizes the FV
occur as a result of three possible conditions. The first is if the output to the other Sample Timer outputs used within the
Vsen input voltage is above 2.0 V or below 1.0 V. Above 2.0 V detector. At 1.25 second intervals the Vsen Gate output goes
indicates that the battery pack is open or disconnected, while low for a 30 ms period. This output is used to momentarily
below 1.0 V indicates the possibility of a shorted or defective interrupt the external charging power source so that a precise
cell. The second condition is if a negative slope in battery voltage measurement can be taken. As the Vsen Gate goes
voltage is detected after a minimum of 160 seconds of fast low, the internal Preset control line is driven high for 10 ms.
charging. This indicates that the battery pack is fully charged. During this time, the battery voltage at the Vsen input is
The third condition is either due to the battery pack being out allowed to stabilize and the previous FV count is preloaded.
of a programmed temperature range, or that the preset timer At the Preset high–to–low transition, the Convert line goes
period has been exceeded. high for 20 ms. This gates the FV pulses into the ratchet
There are three conditions that will cause the controller to counter for a comparison to the preloaded count. Since the
return from trickle to fast charge mode. The first is if the Vsen Convert time is derived from the same clock that controls the
input voltage moved to within the 1.0 to 2.0 V range from VFC, the number of FV pulses is independent of the clock
initially being either too high or too low. The second is if the frequency. If the new sample has more counts than were
battery pack temperature moved to within the programmed preloaded, it becomes the new peak count and the cycle is
temperature range, but only from initially being too cold. Third repeated 1.25 seconds later. If the new sample has two fewer
is by cycling VCC off and then back on causing the internal counts, a less than peak voltage event has occurred, and a
logic to reset. A concise description of the major circuit blocks register is initialized. If two successive less than peak voltage
is given below. events occur, the –∆V ‘AND’ gate output goes high and the
Negative Slope Voltage Detection Fast/Trickle output is latched in a low state, signifying that the
A representative block diagram of the negative slope battery pack has reached full charge status. Negative slope
voltage detector is shown in Figure 9. It includes a voltage detection can only occur after 160 seconds have
Synchronous Voltage to Frequency Converter, a Sample elapsed in the fast charge mode. The trickle mode holdoff
Timer, and a Ratchet Counter. The Vsen pin is the input for the time is implemented to ignore any initial drop in voltage that
Voltage to Frequency Converter (VFC), and it connects to the may occur when charging batteries that have been stored for
rechargeable battery pack terminals through a resistive an extended time period. The negative slope voltage detector
voltage divider. The input has an impedance of has a maximum resolution of 2.0 V divided by 1023, or 1.955
approximately 3.0 MΩ and a maximum voltage range of mV per count with an uncertainty of ±1.0 count. In order to
–1.0 V to VCC + 0.6 V or 0 V to 10 V, whichever is lower. The obtain maximum sensing accuracy, the R2/R1 voltage divider
10 V upper limit is set by an internal zener clamp that must be adjusted so that the Vsen input voltage is slightly less
provides protection in the event of an electrostatic discharge. than 2.0 V when the battery pack is fully charged. Voltage
The VFC is a charge–balanced synchronous type which variations due to temperature and cell manufacturing must
generates output pulses at a rate of FV = Vsen (26 kHz). be considered.
Figure 9. Negative Slope Voltage Detector

Battery Detect
FV = Vsen (26 kHz) Low High UVLO
Synchronous F/T
Vsen Voltage to
Input Ck Rachet
Frequency –∆V
Converter Counter Logic
Trickle Mode Over Under Charge

Convert
Temperature Timer
Preset
Holdoff 160s
Vsen Gate
SCK Sample
105 kHz Timer
Vsen Gate
1.25 s
Preset
10 ms
Convert
20 ms
Rachet Counter Convert
0 to 1023 FV Pulses

MC33340
Fast Charge Timer The resistance change approximates a thermal hysteresis
A programmable backup charge timer is available for fast of 2°C with a 10 kΩ thermistor operating at 0°C. The under
charge termination. The timer is activated by the Time/Temp temperature fast charge inhibit feature can be disabled by
Select comparator, and is programmed from the t1/Tref High, biasing the t3/Tref Low input to a voltage that is greater than
t2/Tsen, and t3/Tref Low inputs. If one or more of these inputs that present at t2/Tsen, and less than VCC – 0.7 V. Under
is allowed to go above VCC – 0.7 V or is left open, the extremely cold conditions, it is possible that the thermistor
comparator output will switch high, indicating that the timer resistance can become too high, allowing the t2/Tsen input to
feature is desired. The three inputs allow one of seven go above VCC – 0.7 V, and activate the timer. This condition
possible fast charge time limits to be selected. The can be prevented by placing a resistor in parallel with the
programmable time limits, rounded to the nearest whole thermistor. Note that the time/temperature threshold of VCC
minute, are shown in Figure 10. – 0.7 V is a typical value at room temperature. Refer to the
Electrical Characteristics table and to Figure 3 for additional
Over/Under Temperature Detection information.
A backup over/under temperature detector is available The upper comparator senses the presence of an over
and can be used in place of the timer for fast charge temperature condition. When the upper temperature limit is
termination. The timer is disabled by the Time/Temp Select exceeded, the comparator output sets the Over Temperature
comparator when each of the three programming inputs are Latch and the charger is switched to trickle mode. Once the
held below VCC – 0.7 V. latch is set, the charger cannot be returned to fast charge,
Temperature sensing is accomplished by placing a even after the temperature falls below the limit. This feature
negative temperature coefficient (NTC) thermistor in thermal prevents the battery pack from being continuously
contact with the battery pack. The thermistor connects to the temperature cycled and overcharged. The latch can be reset
t2/Tsen input which has a 30 µA current source pull–up for by removing and reconnecting the battery pack or by cycling
developing a temperature dependent voltage. The the power supply voltage.
temperature limits are set by a resistor that connects from the If the charger does not require either the time or
t1/Tref High and the t3/Tref Low inputs to ground. Since all temperature backup features, they can both be easily
three inputs contain matched 30 µA current source pull–ups, disabled. This is accomplished by biasing the t3/Tref Low
the required programming resistor values are identical to that input to a voltage greater than t2/Tsen, and by grounding the
of the thermistor at the desired over and under trip t1/Tref High input. Under these conditions, the Time/Temp
temperature. The temperature window detector is composed Select comparator output is low, indicating that the
of two comparators with a common input that connects to the temperature mode is selected, and that the t2/Tsen input is
t2/Tsen input. biased within the limits of an artificial temperature window.
The lower comparator senses the presence of an under
Operating Logic
temperature condition. When the lower temperature limit is
The order of events in the charging process is controlled
exceeded, the charger is switched to the trickle mode. The
by the logic circuitry. Each event is dependent upon the input
comparator has 44 mV of hysteresis to prevent erratic
conditions and the chosen method of charge termination. A
switching between the fast and trickle modes as the lower
table summary containing all of the possible operating modes
temperature limit is crossed. The amount of temperature rise
is shown in Figure 11.
to overcome the hysteresis is determined by the thermistor’s
rate of resistance change or sensitivity at the under
temperature trip point. The required resistance change is:
³
DR(TLow T High) + VH(T)
I
+ 44 mV
30 mA
+ 1.46 k
in
Figure 10. Fast Charge Backup Termination Time/Temperature Limit

Programming Inputs
Backup Time Limit
Termination t3/Tref Low t2/Tsen t1/Tref High Fast Charge
Mode (Pin 5) (Pin 6) (Pin 7) (Minutes)
Time Open Open Open 256
Time Open Open Gnd 224
Time Open Gnd Open 192
Time Open Gnd Gnd 160
Time Gnd Open Open 128
Time Gnd Open Gnd 96
Time Gnd Gnd Open 64
Temperature 0 V to VCC – 0.7 V 0 V to VCC – 0.7 V 0 V to VCC – 0.7 V Timer Disabled

MC33340
Figure 11. Controller Operating Mode Table

Input Condition Controller Operation
Vsen Input Voltage:
>1.0 V and <2.0 V The divided down battery pack voltage is within the fast charge voltage range. The charger switches from
trickle to fast charge mode as Vsen enters this voltage range, and the reset signal that was applied to the
timer and the over temperature latch is now released.
>1.0 V and <2.0 V with The battery pack has reached full charge and the charger switches from fast to a latched trickle mode.
two consecutive –∆V A reset signal must be applied and then released for the charger to switch back to the fast mode. The
events detected after 160 s reset signal is applied when either Vsen <1.0 V or >2.0 V, or VCC <2.8 V. A signal is released when both
Vsen >1.0 V and <2.0 V, and VCC >3.0 V.
<1.0 V or >2.0 V The divided down battery pack voltage is outside of the fast charge voltage range. The charger switches
from fast to trickle mode, and a reset signal is applied to the timer and over temperature latch.
Timer Backup:
Within time limit The timer has not exceeded the programmed limit. The charger will be in fast charge mode if Vsen and
VCC are within their respective operating limits.
Beyond time limit The timer has exceeded the programmed limit. The charger switches from fast to a latched trickle mode.
Temperature Backup:
Within limits The battery pack temperature is within the programmed limits. The charger will be in fast charge mode if
Vsen and VCC are within their respective operating limits.
Below lower limit The battery pack temperature is below the programmed lower limit. The charger will stay in trickle mode
until the lower temperature limit is exceeded. When exceeded, the charger will switch from trickle to fast
charge mode.
Above upper limit The battery pack temperature has exceeded the programmed upper limit. The charger switches from fast
to a latched trickle mode. A reset signal must be applied and then released for the charger to switch back
to the fast charge mode. A reset signal is applied when either Vsen <1.0 V or >2.0 V, or VCC <2.8 V, and
is released when both Vsen >1.0 V and <2.0 V, and VCC >3.0 V.
Power Supply Voltage:
VCC >3.0 V and <18 V This is the nominal power supply operating voltage range. The charger will be in fast charge mode if
Vsen, and temperature backup or timer backup are within their respective operating limits.
VCC >0.6 V and <2.8 V The undervoltage lockout comparator will be activated and the charger will be in trickle mode. A reset
signal is applied to the timer and over temperature latch.
Testing
Under normal operating conditions, it would take 256 Switch 2 bypasses 11 divider stages to provide a 2048
minutes to verify the operation of the 34 stage ripple counter times speedup of the clock. This switch is necessary for
used in the timer. In order to significantly reduce the test time, testing the 19 stages that were bypassed when switch 1 was
three digital switches were added to the circuitry and are enabled. Switch 2 is enabled when the Vsen input falls below
used to bypass selected divider stages. Entering each of the 1.0 V and the t1/Tref Low input is biased at –100 mV.
test modes without requiring additional package pins or Verification of the 19 stages is accomplished by measuring a
affecting normal device operation proved to be challenging. nominal propagation delay of 308 ms from when the Vsen
Refer to the timer functional block diagram in Figure 12. input falls below 1.0 V, to when the F/T output changes from
Switch 1 bypasses 19 divider stages to provide a 524,288 a high–to–low state.
times speedup of the clock. This switch is enabled when the Switch 3 is a dual switch consisting of sections “A” and “B”.
Vsen input falls below 1.0 V. Verification of the programmed Section “A” bypasses 5 divider stages to provide a 32 times
fast charge time limit is accomplished by measuring the speedup of the Vsen gate signal that is used in sampling the
propagation delay from when the Vsen input falls below 1.0 V, battery voltage. This speedup allows faster test verification of
to when the F/T output changes from a high–to–low state. two successive –∆V events. Section “B” bypasses 11 divider
The 64, 96, 128, 160, 192, 224 and 256 minute timeouts will stages to provide a 2048 speedup of the trickle mode holdoff
now correspond to 7.3, 11, 14.6, 18.3, 22, 25.6 and 29.3 ms timer. Switches 3A and 3B are both activated when the t1/Tref
delays. It is possible to enter this test mode during operation Low input is biased at –100 mV with respect to Pin 4.
if the equivalent battery pack voltage was to fall below 1.0 V. Activation results in a reduction of the Vsen gate sample rate
This will not present a problem since the device would from 1.25 s to 39 ms, and a trickle mode holdoff time of 160 s
normally switch from fast to trickle mode under these to 68 ms.
conditions, and the relatively short variable time delay would
be transparent to the user.

MC33340
Figure 12. Timer Functional Block Diagram

Switch 1
219
Switch 2 Switch 3A
211 25
Oscillator
840 kHz ÷23 ÷28 ÷24 ÷21 ÷24 ÷27 ÷23 ÷2 ÷2 ÷2 ÷2
1.25 s 21.3 42.6 85.2 170.4 340.9

105 kHz Decoder Vsen Gate
Time Period Minutes
SCK
to 10 ms 20 ms Switch 3B
Voltage to Preset Convert 211 t1/Tref High
Frequency
Converter 78 ms 160 s Time and Test t2/Tsen
Decoder
t3/Tref Low
Trickle
Handoff
Each test mode bypass switch is shown
in the proper position for normal charger operation. Timer Output
Figure 13. Line Isolated Linear Regulator Charger
C2
R5 IC1 MC33340 VCC 8 0.1
1.0 k D3
Undervoltage
Lockout
AC Internal Bias
1N4002 VCC
Line R2 Voltage to RNTC
D2 Vsen 2.9 V
Input Frequency 10 k
LM317 1 Converter Over
R1 Temp
IC2
R7 C1 Ck F/V R R Latch
DC IAdj 20 0.01 Over Battery
High Q
Input 2.0 V S Pack
Battery Temp
R8 Detect Detect
220 1.0 V Low Under
R6 30 µA t1/Tref High
1.8 k D4 t1
–∆V Detect 7
SW1 R3
D1 Vsen Counter 30 µA t2/Tsen
Charge Gate Timer t2
Status Vsen 6
ǒ Ǔ
2 SW2
Gate 30 µA t3/Tref Low
R2 + R1 VBatt
Vsen
–1 3
t3
5
SW3 R4
+ Vref )R7(IAdj R8)

Fast/ F/T t/T VCC
Trickle
Ichg(fast) Time/Temp
0.6 V
Select
Ichg(trickle) + Vin – Vf(D3) – VBatt

R5
Gnd 4
This application combines the MC33340 with an adjustable three terminal regulator to form an isolated secondary side battery charger. Regulator IC2 operates as
a constant current source with R7 setting the fast charge level. The trickle charge level is set by R5. The R2/R1 divider should be adjusted so that the Vsen input is
less than 2.0 V when the batteries are fully charged. The printed circuit board shown below will accept the several TO–220 style heatsinks for IC2 and are all
manufactured by AAVID Engineering Inc.
AAVID # θSA °C/W

592502B03400 24.0
593002B03400 14.0
590302B03600 9.2

MC33340
Figure 14. Printed Circuit Board and Component Layout

(Circuit of Figure 13)
2.25″
Input Charge Mode Battery
Return MC33340
ÎÎÎÎÎÎ
Input RNTC Negative
Input 3 2 1 RNTC
R4
ÎÎÎÎÎÎ
Positive D1
C1 RNTC
R3
ÎÎÎÎÎÎ
Battery
R1
IC1
ÎÎÎÎÎÎ
D4
Output Positive 1.70″
R5
R6
C2
D2
ÎÎÎÎÎÎ
R2
D3 R8
ÎÎÎÎÎÎ
IC2
R7
(Top View) (Bottom View)
Figure 15. Line Isolated Switch Mode Charger
UC3842 Series
VCC
Voltage 1.0 mA
Feedback 2R
R2 Input
2 Error R 1.0 V
R1
Amplifier
1 Current Sense
Comparator
Output/
Compensation Gnd 5
Primary Circuitry
Isolation Boundary
Secondary Circuitry
OC2 VBattery
Vsen MC33340
Gate
Vsen
R3 2 Gate
OC1
3
Fast/
F/T
Trickle
Gnd 4
The MC33340 can be combined with any of the devices in the UC3842 family of current mode controllers to form a switch mode battery charger. In this example,
optocouplers OC1 and OC2 are used to provide isolated control signals to the UC3842. During battery voltage sensing, OC2 momentarily grounds the
Output/Compensation pin, effectively turning off the charger. When fast charge termination is reached, OC1 turns on, and grounds the lower side of R3. This reduces
the peak switch current threshold of the Current Sense Comparator to a programmed trickle current level. For additional converter design information, refer to the
UC3842 and UC3844 device family data sheets.

MC33340
Figure 16. Switch Mode Fast Charger
MC34166 or MC34167
VCC AC
ILimit Line
4 +
Input
Osc
S
Switch R4
Q Output
R
PWM 2
UVLO
Thermal
R2
Ref Voltage
Feedback
EA
Input
Battery
1 Pack
Gnd 3 Compensation 5
C1 R3
R1
Vsen MC33340
Gate
Vsen
2 Gate
3
Fast/
F/T
Trickle
Gnd 4
The MC33340 can be used to control the MC34166 or MC34167 power switching regulators to produce an economical and efficient fast charger. These devices are
capable of operating continuously in current limit with an input voltage range of 7.5 to 40 V. The typical charging current for the MC34166 and MC34167 is 4.3 A and
6.5 A respectively. Resistors R2 and R1 are used to set the battery pack fast charge float voltage. If precise float voltage control is not required, components R1, R2,
R3 and C1 can be deleted, and Pin 1 must be grounded. The trickle current level is set by resistor R4. It is recommended that a redundant charge termination method
be employed for end user protection. This is especially true for fast charger systems. For additional converter design information, refer to the MC34166 and MC34167
data sheets.

MC33341
Product Preview
Power Supply
Battery Charger POWER SUPPLY
Regulation Control Circuit BATTERY CHARGER
The MC33341 is a monolithic regulation control circuit that is specifically REGULATION
designed to close the voltage and current feedback loops in power supply CONTROL CIRCUIT
and battery charger applications. This device features the unique ability to
perform source high–side, load high–side, source low–side and load SEMICONDUCTOR
low–side current sensing, each with either an internally fixed or externally TECHNICAL DATA
adjustable threshold. The various current sensing modes are accomplished
by a means of selectively using the internal differential amplifier, inverting
amplifier, or a direct input path. Positive voltage sensing is performed by an
internal voltage amplifier. The voltage amplifier threshold is internally fixed
and can be externally adjusted in all low–side current sensing applications.
An active high drive output is provided to directly interface with economical
optoisolators for isolated output power systems. This device is available in
8–lead dual–in–line and surface mount packages. 8
• Differential Amplifier for High–Side Source and Load Current Sensing 1
• Inverting Amplifier for Source Return Low–Side Current Sensing

• Non–Inverting Input Path for Load Low–Side Current Sensing
P SUFFIX
PLASTIC PACKAGE
• Fixed or Adjustable Current Threshold in All Current Sensing Modes CASE 626
• Positive Voltage Sensing in All Current Sensing Modes
• Fixed Voltage Threshold in All Current Sensing Modes
• Adjustable Voltage Threshold in All Low–Side Current Sensing Modes 8
• Output Driver Directly Interfaces with Economical Optoisolators 1
• Operating Voltage Range of 2.3 V to 18 V

D SUFFIX
PLASTIC PACKAGE
Representative Block Diagram CASE 751
(SO–8)
Drive Current Sense Input B/ Voltage Sense

Output VCC Voltage Threshold Adjust Input
8 7 6 5
PIN CONNECTIONS
Current Sense
Differential 8 Drive Output
Input A 1
Amp Voltage and Current
1.0 Transconductance Current Threshold
Amp/Driver Adjust 2 7 VCC
V Current Sense Input B/

1.2 V Compensation 3 6 Voltage Threshold Adjust
#1.0 I Gnd 4 5 Voltage Sense Input

0.2 V
Inverting/
Reference (Top View)
Noninverting Amp
1 2 3 4 Operating
Current Sense Current Compensation Gnd Device Temperature Range Package
Input A Threshold Adjust
MC33341D SO–8
TA = –40° to +85°C
This device contains 114 active transistors. MC33341P Plastic DIP

MC33341
MAXIMUM RATINGS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
Rating
Power Supply Voltage (Pin 7)
Symbol
VCC
Value
18
Unit
V
ÁÁÁÁ
Voltage Range
ÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
Current Sense Input A (Pin 1)
VIR –1.0 to VCC V
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Current Threshold Adjust (Pin 2)
Compensation (Pin 3)
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Voltage Sense Input (Pin 5)
Current Sense Input B/Voltage Threshold Adjust (Pin 6)
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Drive Output (Pin 8)
ÁÁÁ
Drive Output Source Current (Pin 8) ISource 50 mA
ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Thermal Resistance, Junction–to–Air
ÁÁÁÁ
ÁÁÁ
P Suffix, DIP Plastic Package, Case 626
D Suffix, SO–8 Plastic Package, Case 751
RθJA
100
178
°C/W
ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Operating Junction Temperature (Note 1)
ÁÁÁÁ
ÁÁÁ
Storage Temperature
TJ
Tstg
–25 to +150
–55 to +150
°C
°C
ELECTRICAL CHARACTERISTICS (VCC = 6.0 V, TA = 25°C, for min/max values TA is the operating junction
temperature range that applies (Note 1), unless otherwise noted.)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
CURRENT SENSING (Pins 1, 2, 6)
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Source High–Side and Load High–Side Sensing Pin 1 to Pin 6 (Pin 1 >1.6 V)
ÁÁÁÁ
ÁÁÁ
Internally Fixed Threshold Voltage (Pin 2 = VCC)
Vth(I HS) mV
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
TA = 25°C – 200 –
TA = Tlow to Thigh – 196 to 204 –
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Externally Adjusted Threshold Voltage (Pin 2 = 0 V) – 10 –
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Externally Adjusted Threshold Voltage (Pin 2 = 200 mV) – 180 –
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Load Low–Side Sensing Pin 1 to Pin 4 (Pin 1 = 0 V to 0.8 V) Vth(I LS+) mV
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
TA = 25°C – 200 –
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
TA = Tlow to Thigh – 196 to 204 –
Externally Adjusted Threshold Voltage (Pin 2 = 0 V) – 10 –
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Externally Adjusted Threshold Voltage (Pin 2 = 200 mV) – 180 –
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Source Return Low–Side Sensing Pin 1 to Pin 4 (Pin 1 = 0 V to –0.2 V) Vth(I LS–) mV
TA = 25°C
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
TA = Tlow to Thigh
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
Externally Adjusted Threshold Voltage (Pin 2 = 0 V)
–
–
–
–200
–196 to –204
–10
–
–
–
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Externally Adjusted Threshold Voltage (Pin 2 = 200 mV)
ÁÁÁÁ
Current Sense Input A (Pin 1)
ÁÁÁ
– –180 –
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Input Bias Current, High–Side Source and Load Sensing
(Pin 2 = 0 V to VPin 6 V) IIB(A HS) – 40 – µA
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Input Bias Current, Low–Side Load Sensing
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
(Pin 2 = 0 V to 0.8 V) IIB(A LS+) – 10 – nA
Input Resistance, Low–Side Source Return Sensing
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
(Pin 2 = –0.6 V to 0 V) Rin(A LS–) – 10 – kΩ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Current Sense Input B/Voltage Threshold Adjust (Pin 6) IIB(B)
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Input Bias Current
High–Side Source and Load Current Sensing (Pin 6 > 2.0 V) – 20 – µA
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Voltage Threshold Adjust (Pin 6 < 1.2 V) – 100 – nA
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Current Sense Threshold Adjust (Pin 2) IIB(I th) – 10 – nA
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Input Bias Current
Transconductance, Current Sensing Inputs to Drive Output (IO – 0.7 mA) gm(I) – 6.0 – mhos
NOTE: 1. Tested ambient temperature range for the MC33341: Tlow = –25°C, Thigh = +85°C.

MC33341
ELECTRICAL CHARACTERISTICS (continued) (VCC = 6.0 V, TA = 25°C, for min/max values TA is the operating junction
temperature range that applies (Note 1), unless otherwise noted.)
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
Characteristic
DIFFERENTIAL AMPLIFIER DISABLE LOGIC (Pins 1, 6)

Symbol Min Typ Max Unit
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Logic Threshold Voltage Pin 1 (Pin 6 = 0 V) V
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Enabled, High–Side Source and Load Current Sensing Vth(I HS) – 1.2 –
Disabled, Low–Side Load and Source Return Current Sensing Vth(I LS) – 1.2 –
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
VOLTAGE SENSING (Pins 5, 6)
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Positive Sensing Pin 5 to Pin 4
ÁÁÁÁ
ÁÁÁ
Internally Fixed Threshold Voltage Vth(V)
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
TA = 25°C – 1.200 – V
TA = Tlow to Thigh – 1.176 to 1.224 – mV
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Externally Adjusted Threshold Voltage (Pin 6 = 0 V) – 40 – V
Externally Adjusted Threshold Voltage (Pin 6 = 1.2 V) – 1.175 –
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Voltage Sense, Input Bias Current (Pin 5)
IIB(V) – 10 – nA
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Transconductance, Voltage Sensing Inputs to Drive Output (IO = 0.7 mA)
ÁÁÁÁ
ÁÁÁ
gm(V) – 7.0 – mhos
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
DRIVE OUTPUT (Pin 8)
High State Source Voltage (ISource = 8.0 mA) VOH – VCC – 0.8 – V
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
Operating Voltage Range
ÁÁÁ
ÁÁÁÁ
ÁÁÁ VCC – 2.3 to 18 – V
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Power Supply Current (VCC = 6.0 V)
NOTE: 1. Tested ambient temperature range for the MC33341: Tlow = –25°C, Thigh = +85°C.
ICC – 300 – µA
ÁÁÁ
ÁÁÁÁÁÁÁÁ
Pin
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Name Description
ÁÁÁ
ÁÁÁÁÁÁÁÁ
1
ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Current Sense Input A
ÁÁÁÁÁÁÁÁ
This multi–mode current sensing input can be used for either source high–side, load high–side,
source–return low–side, or load low–side sensing. It is common to a Differential Amplifier, Inverting
Amplifier, and a Noninverting input path. Each of these sensing paths indirectly connect to the current
ÁÁÁ
ÁÁÁÁÁÁÁÁ
sense input of the Transconductance Amplifier. This input is connected to the high potential side of a
ÁÁÁ
ÁÁÁÁÁÁÁÁ
current sense resistor when used in source high–side, load high–side, or load low–side current
sensing modes. In source return low–side current sensing mode, this pin connects to the low potential
ÁÁÁ
ÁÁÁÁÁÁÁÁ
side of a current sense resistor.
ÁÁÁ
ÁÁÁÁÁÁÁÁ
2 Current Threshold Adjust The current sense threshold can be externally adjusted over a range of 0 V to 200 mV with respect to
ÁÁÁ
ÁÁÁÁÁÁÁÁ
Pin 4, or internally fixed at 200 mV by connecting Pin 2 to VCC.
ÁÁÁ
ÁÁÁÁÁÁÁÁ
3 Compensation This pin is connected to a high impedance node within the transconductance amplifier and is made
available for loop compensation. It can also be used as an input to directly control the Drive Output.
ÁÁÁ
ÁÁÁÁÁÁÁÁ
An active low at this pin will force the Drive Output into a high state.
ÁÁÁ
ÁÁÁÁÁÁÁÁ
4 Ground This pin is the regulation control IC ground. The control threshold voltages are with respect to this pin.
ÁÁÁ
ÁÁÁÁÁÁÁÁ
5 Voltage Sense Input This is the voltage sensing input of the Transconductance Amplifier. It is normally connected to the
ÁÁÁ
ÁÁÁÁÁÁÁÁ
power supply/battery charger output through a resistor divider. The input threshold is controlled by
Pin 6.
ÁÁÁ
ÁÁÁÁÁÁÁÁ
6
Current Sense Input B/
ÁÁÁÁÁÁÁÁ
Voltage Threshold Adjust
This is a dual function input that is used for either high–side current sensing, or as a voltage threshold
adjustment for Pin 5. This input is connected to the low potential side of a current sense resistor when
ÁÁÁ
ÁÁÁÁÁÁÁÁ
used in source high–side or load high–side current sensing modes. In all low–side current sensing
modes, Pin 6 is available as a voltage threshold adjustment for Pin 5. The threshold can be externally
ÁÁÁ
ÁÁÁÁÁÁÁÁ
adjusted over a range of 0 V to 1.2 V with respect to Pin 4, or internally fixed at 1.2 V by connecting
Pin 6 to VCC.
ÁÁÁ
ÁÁÁÁÁÁÁÁ
7
VCC
ÁÁÁÁÁÁÁÁ
This is the positive supply voltage for the regulation control IC. The typical operating voltage range is
2.3 V to 18 V with respect to Pin 4.
ÁÁÁ
ÁÁÁÁÁÁÁÁ
8
Drive Output
ÁÁÁÁÁÁÁÁ
This is a source–only output that normally connects to a linear or switching regulator control circuit.
This output is capable of 15 mA, allowing it to directly drive an optoisolator in primary side control
applications where galvanic isolation is required.

MC33341
∆ Vth(v) , VOLTAGE SENSING THRESHOLD CHANGE (mV)

Figure 1. Voltage Sensing Figure 2. Current Sensing
Threshold Change versus Temperature Threshold Change versus Temperature
4.0 1.0
VCC = 6.0 V VCC = 6.0 V
∆ V th(I HS), CURRENT SENSING

THRESHOLD CHANGE (mV)
0 0
–4.0 –1.0
3
2
–8.0 –2.0
1 – Source High–Side and Load High–Side 1
2 – Source Return Low–Side
3 – Load Low–Side
–12 –3.0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
Figure 3. Closed–Loop Voltage Sensing Input Figure 4. Closed–Loop Current Sense Input B
V Pin 1 –V Pin 6 , INPUT DIFFERENCE VOLTAGE (mV)

versus Voltage Threshold Adjust V Pin 6 –V Pin 5 , INPUT DIFFERENCE VOLTAGE (mV) versus Current Threshold Adjust
1.6 16 0 0
V Pin 6 , CURRENT SENSE INPUT B (mV)
V Pin 5 , VOLTAGE SENSING INPUT (V)
VCC = 6.0 V VCC

1.4 VO = 1.0 V 14 –40 2.0
IO = 1.0 mA VPin 1–VPin 6
1.2 12
TA = 25°C –80 VCC = 6.0 V 4.0
1.0 10 VPin 6 VO = 1.0 V
–120 IO = 1.0 mA 6.0
0.8 VPin 5 8.0 Pin 1 = VCC
–160 TA = 25°C 8.0
0.6 6.0
–200 Differential Amplifier is active for 10
0.4 4.0 source high–side and load high–side
–240 current sensing. Both vertical axis are 12
0.2 VPin 6–VPin 5 2.0 expressed in millivolts down to VCC.
0 0 –280 14
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 40 80 120 160 200 240 280
VPin 6, VOLTAGE THRESHOLD ADJUST (V) VPin 2, CURRENT THRESHOLD ADJUST (V)
Figure 5. Closed–Loop Current Sensing Input A Figure 6. Closed–Loop Current Sensing Input A
V Pin 2 –|V Pin 1 |, INPUT DIFFERENCE VOLTAGE (mV)

V Pin 2 –V Pin 1, INPUT DIFFERENCE VOLTAGE (mV)
versus Current Threshold Adjust versus Current Threshold Adjust

280 14 0 14
V Pin 1, CURRENT SENSE INPUT A (mV)
V Pin 1, CURRENT SENSE INPUT A (mV)
Noninverting input path is active Gnd VCC = 6.0 V

240 for load low–side current sensing. 12 –40 VO = 1.0 V 12
VCC = 6.0 V VPin 5 IO = 1.0 mA
200 VO = 1.0 V 10 –80 TA = 25°C 10
IO = 1.0 mA
160 TA = 25°C 8.0 –120 8.0
120 6.0 –160 6.0

VPin 5
80 4.0 –200 4.0
VPin 2–VPin 1 VPin 2–|VPin 1|
Inverting Amplifier is
40 2.0 –240 active for source return 2.0
Gnd
low–side current sensing.
0 0 –260 0
0 40 80 120 160 200 240 280 0 40 80 120 160 200 240 280
VPin 2, CURRENT THRESHOLD ADJUST (mV) VPin 2, CURRENT THRESHOLD ADJUST (mV)

MC33341
Figure 7. Bode Plot Figure 8. Bode Plot

Voltage Sensing Inputs to Drive Output Current Sensing Inputs to Drive Output
A VOL(V) , VOLTAGE SENSING OPEN–LOOP
A VOL(I), CURRENT SENSING OPEN–LOOP

60 60
80 80
50 50 Phase
Phase Phase
Low–Side Sensing
φ, EXCESS PHASE (°)
φ, EXCESS PHASE (°)

100 100
VOLTAGE GAIN (dB)

High–Side Sensing
VOLTAGE GAIN (dB)
40 40
120 120
30 Gain 30 Gain
140 140
20 VCC = 6.0 V 20 VCC = 6.0 V
VO = 1.0 V 160 VO = 1.0 V 160
RL = 1.0 k RL = 1.0 k
10 Pin 3 = 1.0 nF 10 Pin 3 = 1.8 nF
TA = 25°C 180 TA = 25°C 180
0 0
1.0 k 10 k 100 k 1.0 M 1.0 k 10 k 100 k 1.0 M
g m(v) , VOLTAGE SENSING TRANSCONDUCTANCE (mhos)
g m(I), CURRENT SENSING TRANSCONDUCTANCE (mhos)

Figure 9. Transconductance Figure 10. Transconductance
Voltage Sensing Inputs to Drive Output Current Sensing Inputs to Drive Output
8.0 8.0
VCC = 6.0 V VCC = 6.0 V
VO = 1.0 V VO = 1.0 V
TA = 25°C TA = 25°C
6.0 6.0
4.0 4.0
2.0 2.0
0 0
0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10
IO, DRIVE OUTPUT LOAD CURRENT (mA) IO, DRIVE OUTPUT LOAD CURRENT (mA)
I CC, SUPPLY CURRENT, DRIVE OUTPUT LOW STATE (mA)
Figure 11. Drive Output High State Figure 12. Supply Current
V OH , OUTPUT SOURCE SATURATION VOLTAGE (V)
Source Saturation versus Load Current versus Supply Voltage

0 1.0
VCC = 6.0 V
VCC Drive Output High State
TA = 25°C
–0.4 0.8
–0.8 0.6 IO = 0 mA
TA = 25°C
–1.2 0.4
Drive Output Low State
–1.6 0.2
–2.0 0
0 4.0 8.0 12 16 20 0 4.0 8.0 12 16
IL, OUTPUT LOAD CURRENT (mA) VCC, SUPPLY VOLTAGE (V)

MC33341
INTRODUCTION noninverting Isen input of the transconductance amplifier. In

Power supplies and battery chargers require precise order to allow for maximum circuit flexibility, there are three
control of output voltage and current in order to prevent methods of current sensing, each with different internal
catastrophic damage to the system load. Many present day paths.
power sources contain a wide assortment of building blocks In source high–side (Figures 13 and 14) and load high–side
and glue devices to perform the required sensing for proper (Figures 17 and 18) current sensing, the Differential Amplifier
regulation. Typical feedback loop circuits may consist of a is active with a gain of 1.0. Pin 1 connects to the high potential
voltage and current amplifier, level shifting circuitry, summing side of current sense resistor RS while Pin 6 connects to the
circuitry and a reference. The MC33341 contains all of these low side. Logic circuitry is provided to disable the Differential
basic functions in a manner that is easily adaptable to many Amplifier output whenever low–side current sensing is
of the various power source–load configurations. required. This circuit clamps the Differential Amplifier output
high which disconnects it from the Isen input of the
OPERATING DESCRIPTION Transconductance Amplifier. This happens if Pin 1 is less than
The MC33341 is an analog regulation control circuit that is 1.2 V or if Pin 1 is less than Pin 6.
specifically designed to simultaneously close the voltage and With source return low–side current sensing (Figures 15
current feedback loops in power supply and battery charger and 16), the Inverting Amplifier is active with a gain of –1.0.
applications. This device can control the feedback loop in Pin 1 connects to the low potential side of current sense
either constant–voltage or constant–current mode with resistor RS while Pin 4 connects to the high side. Note that a
automatic crossover. A concise description of the integrated negative voltage appears across RS with respect to Pin 4.
circuit blocks is given below. Refer to the block diagram in In load low–side current sensing (Figures 19 and 20) a
Figure 13. Noninverting input path is active with a gain of 1.0. Pin 1
Transconductance Amplifier connects to the high potential side of current sense resistor
A quad input transconductance amplifier is used to control RS while Pin 4 connects to the low side. The Noninverting
the feedback loop. This amplifier has separate voltage and input path lies from Pin 1, through the Inverting Amplifier
current channels, each with a sense and a threshold input. input and feedback resistors R, to the cathode of the output
Within a given channel, if the sense input level exceeds that diode. With load low–side current sensing, Pin 1 will be more
of the threshold input, the amplifier output is driven high. The positive than Pin 4, forcing the Inverting Amplifier output low.
channel with the largest difference between the sense and This causes the diode to be reverse biased, thus preventing
threshold inputs will set the output source current of the the output stage of the amplifier from loading the input signal
amplifier and thus dominate control of the feedback loop. The that is flowing through the feedback resistors.
amplifier output appears at Pin 8 and is a source–only type The regulation threshold in all of the current sensing
that is capable of 15 mA. modes is internally fixed at 200 mV with Pin 2 connected to
A high impedance node within the transconductance VCC. Pin 2 can be used to externally adjust the threshold over
amplifier is made available at Pin 3 for loop compensation. a range of 0 to 200 mV with respect to the IC ground at Pin 4.
This pin can sink and source up to 10 µA of current. System Reference
stability is achieved by connecting a capacitor from Pin 3 to An internal band gap reference is used to set the 1.2 V
ground. The Compensation Pin signal is out of phase with voltage threshold and 200 mV current threshold. The
respect to the Drive Output. By actively clamping Pin 3 low, reference is initially trimmed to a ±1.0% tolerance at TA =
the Drive Output is forced into a high state. This, in effect, will 25°C and is guaranteed to be within ±2.0% over an ambient
shutdown the power supply or battery charger, by forcing the operating temperature range of –25° to 85°C.
output voltage and current regulation threshold down Applications
towards zero.
Each of the application circuits illustrate the flexibility of
Voltage Sensing this device. The circuits shown in Figures 13 through 20
The voltage that appears across the load is monitored by contain an optoisolator connected from the Drive Output at
the noninverting Vsen input of the transconductance amplifier. Pin 8 to ground. This configuration is shown for ease of
This voltage is resistively scaled down and connected to understanding and would normally be used to provide an
Pin 5. The threshold at which voltage regulation occurs is set isolated control signal to a primary side switching regulator
by the level present at the inverting Vth input of the controller. In non–isolated, primary or secondary side
transconductance amplifier. This level is controlled by Pin 6. applications, a load resistor can be placed from Pin 8 to
In source high–side and load high–side current sensing ground. This resistor will convert the Drive Output current to
modes, Pin 6 must be connected to the low potential side of a voltage for direct control of a regulator.
current sense resistor RS. Under these conditions, the In applications where excessively high peak currents are
voltage regulation threshold is internally fixed at 1.2 V. In possible from the source or load, the load induced voltage
source return low–side and load low–side current sensing drop across RS could exceed 1.6 V. Depending upon the
modes, Pin 6 is available, and can be used to lower the current sensing configuration used, this will result in forward
regulation threshold of Pin 5. This threshold can be externally biasing of either the internal VCC clamp diode, Pin 6, or the
adjusted over a range of 0 V to 1.2 V with respect to the IC device substrate, Pin 1. Under these conditions, input series
ground at Pin 4. resistor R3 is required. The peak input current should be
Current Sensing limited to 20 mA. Excessively large values for R3 will
Current sensing is accomplished by monitoring the degrade the current sensing accuracy. Figure 21 shows a
voltage that appears across sense resistor RS, level shifting method of bounding the voltage drop across RS without
it with respect to Pin 4 if required, and applying it to the sacrificing current sensing accuracy.

MC33341
Figure 13. Source High–Side Current Sensing with

Internally Fixed Voltage and Current Thresholds
RS
Source Load
R2
R3
8 7 6 5
VCC VCC
VCC
VCC
1.2 V R1
Differential Amp
Disable Logic 0.4 V 1.2 V
Vsen Transconductance
Opto VCC Vth Amp
Isolator V
Differential Amp
R Isen
R I
Ith VCC
R R
Reference
R VCC Battery or
VCC Resistive
R 0.2 V 0.4 V 1.2 V Load
VCC
Inverting Amp 0.2 V
1 2 3 4
Comp
Source
Load
Return
The above figure shows the MC33341 configured for source high–side current sensing allowing a common ground path
between Load – and Source Return –. The Differential Amplifier inputs, Pins 1 and 6, are used to sense the load induced
voltage drop that appears across resistor RS. The internal voltage and current regulation thresholds are selected by the
respective external connections of Pins 2 and 6. Resistor R3 is required in applications where a high peak level of reverse
current is possible if the source inputs are shorted. The resistor value should be chosen to limit the input current of the internal
VCC clamp diode to less than 20 mA. Excessively large values for R3 will degrade the current sensing accuracy.
V reg ǒ Ǔ
+ Vth(V) R2
R1
)1 I reg +
V
th(I HS)
R +
ǒ Ǔ
I R
pk S
– 0.6
ǒ )Ǔ
S R3
0.02
+ 1.2 R2
R1
1 + R0.2
S

MC33341
Figure 14. Source High–Side Current Sensing with

Externally Adjustable Current and Internally Fixed Voltage Thresholds
RS
Source Load
R2
R3
8 7 6 5
VCC VCC
VCC
VCC
1.2 V R1
Differential Amp
Opto VCC Vth Amp
Isolator V
Differential Amp
R Isen
R I
Ith VCC
R R
Reference
R VCC Battery or
VCC Resistive
R 0.2 V 0.4 V 1.2 V Load
VCC
Inverting Amp 0.2 V
1 2 3 4
Current
Control Comp
Source
Load
Return
The above figure shows the MC33341 configured for source high–side current sensing with an externally adjustable current
threshold. Operation of this circuit is similar to that of Figure 13. The current regulation threshold can be adjusted over a range
of 0 V to 200 mV with respect to Pin 4.
V reg ǒ Ǔ
+ Vth(V) R2
R1
)1 I reg +
V
th(Pin 2)
R +
ǒ Ǔ I R
pk S
– 0.6
ǒ )Ǔ
S R3
0.02
+ 1.2 R2
R1
1

MC33341
Figure 15. Source Return Low–Side Current Sensing with

Internally Fixed Current and Voltage Thresholds
Source Load
R2
8 7 6 5
VCC VCC
VCC
VCC
1.2 V R1
Differential Amp
Opto VCC Vth Amp
Isolator V
Differential Amp
R Isen
R I
Ith VCC
R R
Reference
R VCC Battery or
VCC Resistive
R 0.2 V 0.4 V 1.2 V Load
VCC
Inverting Amp 0.2 V
1 2 3 4
R3 Comp
Source RS
Load
Return
The above figure shows the MC33341 configured for source return low–side current sensing allowing a common power path
between Source + and Load +. This configuration is especially suited for negative output applications where a common ground
path, Source + to Load +, is desired. The Inverting Amplifier inputs, Pins 1 and 4, are used to sense the load induced voltage
drop that appears across resistor RS. The internal voltage and current regulation thresholds are selected by the respective
external connections of Pins 2 and 6. Resistor R3 is required in applications where high peak levels of inrush current are
possible. The resistor value should be chosen to limit the negative substrate current to less than 20 mA. Excessively large
values for R3 will degrade the current sensing accuracy.
V reg ǒ Ǔ
+ Vth(V) R2
R1
)1 I reg +
V
th(I LS–)
R
S R3 +
ǒ Ǔ
I R
pk S
– 0.6
ǒ )Ǔ
0.02
+ 1.2 R2
R1
1 + –0.2
R
S

MC33341
Figure 16. Source Return Low–Side Current Sensing with

Externally Adjustable Current and Voltage Thresholds
Source Load
Voltage R2
Control
8 7 6 5
VCC VCC
VCC
VCC
1.2 V R1
Differential Amp
Opto VCC Vth Amp
Isolator V
Differential Amp
R Isen
R I
Ith VCC
R R
Reference
R VCC Battery or
VCC Resistive
R 0.2 V 0.4 V 1.2 V Load
VCC
Inverting Amp 0.2 V
1 2 3 4
Current
Control
Comp
R3
Source RS
Load
Return
The above figure shows the MC33341 configured for source return low–side current sensing with externally adjustable voltage
and current thresholds. Operation of this circuit is similar to that of Figure 15. The respective voltage and current regulation
threshold can be adjusted over a range of 0 to 1.6 V and 0 V to 200 mV with respect to Pin 4.
V reg ǒ Ǔ
+ Vth(Pin 6) R2
R1
)1 I reg +–
V
th(Pin 2)
R
S R3 +
ǒ Ǔ
I R
pk S
– 0.6
0.02

MC33341
Figure 17. Load High–Side Current Sensing with

Source Load
R2 RS
R3
8 7 6 5
VCC VCC
VCC
VCC
1.2 V R1
Differential Amp
Opto VCC Vth Amp
Isolator V
Differential Amp
R Isen
R I
Ith VCC
R R
Reference
R VCC Battery or
VCC Resistive
R 0.2 V 0.4 V 1.2 V Load
VCC
Inverting Amp 0.2 V
1 2 3 4
Comp
Source
Load
Return
The above figure shows the MC33341 configured for load high–side current sensing allowing common paths for both power
and ground, between the source and load. The Differential Amplifier inputs, Pins 1 and 6, are used to sense the load induced
voltage drop that appears across resistor RS. The internal voltage and current regulation thresholds are selected by the
respective external connections of Pins 2 and 6. Resistor R3 is required in applications where high peak levels of load current
are possible from the battery or load bypass capacitor. The resistor value should be chosen to limit the input current of the
internal VCC clamp diode to less than 20 mA. Excessively large values for R3 ill degrade the current sensing accuracy.
V reg ǒ Ǔ
+ Vth(V) R2
R1
)1 I reg +
V
th(I HS)
R +
ǒ Ǔ
I R
pk S
– 0.6
ǒ )Ǔ
S R3
0.02
+ 1.2 R2
R1
1 + R0.2
S

MC33341
Figure 18. Load High–Side Current Sensing with

Externally Adjustable Current and Internally Fixed Voltage Thresholds
Source Load
R2 RS
R3
8 7 6 5
VCC VCC
VCC
VCC
1.2 V R1
Differential Amp
Opto VCC Vth Amp
Isolator V
Differential Amp
R Isen
R I
Ith VCC
R R
Reference
R VCC Battery or
VCC Resistive
R 0.2 V 0.4 V 1.2 V Load
VCC
Inverting Amp 0.2 V
1 2 3 4
Current
Control Comp
Source
Load
Return
The above figure shows the MC33341 configured for load high–side current sensing with an externally adjustable current
threshold. Operation of this circuit is similar to that of Figure 17. The current regulation threshold can be adjusted over a range
of 0 V to 200 mV with respect to Pin 4.
V reg ǒ Ǔ
+ Vth(V) R2
R1
)1 I reg +
V
th(Pin 2)
R R3 +
ǒ Ǔ
I R
pk S
– 0.6
ǒ )Ǔ
S 0.02
+ 1.2 R2
R1
1

MC33341
Figure 19. Load Low–Side Current Sensing with

Source Load
R2
8 7 6 5
VCC VCC
VCC
VCC
1.2 V R1
Differential Amp
Opto VCC Vth Amp
Isolator V
Differential Amp
R Isen
R I
Ith VCC
R R
Reference
R VCC Battery or
VCC Resistive
R 0.2 V 0.4 V 1.2 V Load
VCC
Inverting Amp 0.2 V
1 2 3 4
R3
Comp RS
Source
Load
Return
The above figure shows the MC33341 configured for load low–side current sensing allowing common paths for both power and
ground, between the source and load. The Noninverting input paths, Pins 1 and 4, are used to sense the load induced voltage
drop that appears across resistor RS. The internal voltage and current regulation thresholds are selected by the respective
external connections of Pins 2 and 6. Resistor R3 is required in applications where high peak levels of load current are possible
from the battery or load bypass capacitor. The resistor value should be chosen to limit the negative substratecurrent to less than
20 mA. Excessively large values for R3 will degrade the current sensing accuracy.
V reg ǒ Ǔ
+ Vth(V) R2
R1
)1 I reg +
V
th(I LS
R
))
+
ǒ Ǔ
I R
pk S
– 0.6
ǒ )Ǔ
S R3
0.02
+ 1.2 R2
R1
1 + R0.2
S

MC33341
Figure 20. Load Low–Side Current Sensing with

Externally Adjustable Current and Voltage Thresholds
Source Load
R2
Voltage
Current
8 7 6 5
VCC VCC
VCC
VCC
1.2 V R1
Differential Amp
Opto VCC Vth Amp
Isolator V
Differential Amp
R Isen
R I
Ith VCC
R R
Reference
R VCC Battery or
VCC Resistive
R 0.2 V 0.4 V 1.2 V Load
VCC
Inverting Amp 0.2 V
1 2 3 4
R3
Current
Comp RS
Control
Source
Load
Return
The above figure shows the MC33341 configured for load low–side current sensing with an externally adjustable voltage and
current threshold. Operation of this circuit is similar to that of Figure 19. The respective voltage and current regulation threshold
can be adjusted over a range of 0 to 1.2 V and 0 V to 200 mV, with respect to Pin 4.
V reg ǒ Ǔ
+ Vth(Pin 6) R2
R1
)1 I reg +
V
th(Pin 2)
R
S R3 +
ǒ Ǔ
I R
pk S
– 0.6
0.02

MC33341
Figure 21. Current Sense Resistor Bounding
Source Load
RS
8 7 6 5
Input MC33341 Output

Short Short
1 2 3 4
Source Load
Return
NOTE: An excessive load induced voltage across RS can occur if either the source input or load output is shorted. This voltage can
easily be bounded with the addition of the diodes shown without degrading the current sensing accuracy. This bounding technique
can be used in any of the MC33341 applications where high peak currents are anticipated.
Figure 22. Multiple Output Current and Voltage Regulation
Source Load Output 2
8 7 6 5
MC33341
1 2 3 4
Source Load Output 1
Opto 8 7 6 5
Isolator
MC33341
1 2 3 4
Source Load
Return Output Common
NOTE: Multiple outputs can be controlled by summing the error signal into a common optoisolator. The converter output with the largest
voltage or current error will dominate control of the feedback loop.

MC33345
Product Preview
Lithium Battery Protection
Circuit for One to Four Cell
Battery Packs LITHIUM BATTERY
PROTECTION CIRCUIT
The MC33345 is a monolithic lithium battery protection circuit that is FOR
designed to enhance the useful operating life of one to four cell rechargeable
battery packs. Cell protection features consist of independently ONE TO FOUR CELL
programmable charge and discharge limits for both voltage and current with SMART BATTERY PACKS
a delayed current shutdown, cell voltage balancing with on–chip balancing
resistors, and a virtually zero current sleepmode state when the cells are
discharged. Additional features include an on–chip charge pump for reduced SEMICONDUCTOR
MOSFET losses while charging or discharging a low cell voltage battery TECHNICAL DATA
pack, and the programmability for a one to four cell battery pack. This
protection circuit requires a minimum number of external components and is
targeted for inclusion within the battery pack. The MC33345 is available in
standard and low profile 20 lead surface mount packages.
DW SUFFIX
• Independently Programmable Charge and Discharge Limits for Both 20
PLASTIC PACKAGE
Voltage and Current 1
CASE 751D
• Charge and Discharge Current Limit Detection with Delayed Shutdown (SO–20L)
• Cell Voltage Balancing

• On–Chip Balancing Resistors
• Virtually Zero Current Sleepmode State when Cells are Discharged DTB SUFFIX
•
20
Charge Pump for Reduced Losses with a Low Cell Voltage Battery Pack PLASTIC PACKAGE
CASE 948E
• Programmable for One, Two, Three or Four Cell Applications 1
(TSSOP–20)
• Minimum External Components for Inclusion within the Battery Pack
PIN CONNECTIONS
Cell Voltage Return 1 20 Cell 3
Cell 4/VCC/ 2 19 Cell 2
Cell 4/VCC/ Discharge Current Limit
Discharge Current Sense Charge
Common 6 7 Current Limit
Current Limit Cell Voltage 3 18 Cell 1/VC
2 Discharge Voltage
Threshold 4 17 Fault Output
Cell 3 Cell Voltage
Charge Voltage 5 16 Ground
3
20 Threshold
Discharge Voltage
Threshold Current Sense 6 15 Test Input
Cell 2
Common
4
19 Charge Voltage Charge Current Limit 7 14 Charge Pump Output
Threshold
Cell 1/VC MC33345 Charge 8
5 13 Discharge
18 Cell Voltage
Gate Drive Common Gate Drive Output
Return Charge 9 12 No Connection
Ground
1
Gate Drive Output
16 Test Input Program 2 10 11 Program 1
Program 1
15
11 (Top View)
Fault Output
Program 2
17
10
Output Gate Drive Gate Drive Gate Drive ORDERING INFORMATION
Operating
MC33345DW SO–20L
TA = –25° to +85°C
This device contains 1808 active transistors. MC33345DTB TSSOP–20

MC33345
MAXIMUM RATINGS
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ Ratings Symbol Value Unit
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Input Voltage (Measured with Respect to Ground, Pin 16)
Cell Voltage Divider (Pins 1, 3, 4 and 5)
Cell 1/VC (Pin 18)
VIR
18
7.5
V
Cell 2 (Pin 19) 10

Cell 3 (Pin 20) 18
Cell 4/VCC/Discharge Current Limit (Pin 2) 20
Current Sense Common (Pin 6) 30
Charge Current Limit (Pin 7) 30
Charge Gate Drive Common (Pin 8) ±20
Charge Gate Drive Output (Pin 9) 18 to –20
Program 1 (Pin 11) 7.5
Program 2 (Pin 10) 7.5
Discharge Gate Drive Output (Pin 13) 18
Charge Pump Output (Pin 14) 12
ÁÁÁÁ
Test (Pin 15)
ÁÁÁÁ
ÁÁÁ 7.5
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Fault Output (Pin 17) 20
Cell Voltage Divider Current Idiv mA
Source Current (Pin 4 to 6) 0.5
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Sink Current (Pin 5 to 16) 0.5
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Fault Output Sink Current (Pin 17) Iflt 10 mA
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Thermal Resistance, Junction to Air RθJA °C/W
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
DTB Suffix, TSSOP–20 Plastic Package, Case 948E 135
DW Suffix, SO–20 Plastic Package, Case 751D 105
ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Operating Junction Temperature (Notes 1, 2 and 3)
ÁÁÁÁ
ÁÁÁ
Storage Temperature
TJ
Tstg
–40 to +150
–55 to +150
°C
°C
ELECTRICAL CHARACTERISTICS (VCC (Pin 2) = 8.0 V, VC (Pin 18) = 4.0 V, TA = 25°C, for min/max values TA is the
operating junction temperature range that applies (Notes 2 and 3), unless otherwise noted.)
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
VOLTAGE SENSING
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Charge or Discharge Voltage Inputs (Pin 4 or 5 to Pin 1)
Threshold Voltage Vth – 1.23 – V
ÁÁÁÁ
Input Bias Current
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
Input Hysteresis Source Current (Pin 5)
IIB
IH
–
–
20
2.0
–
–
nA
µA
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Cell Charge or Discharge Programmable Input Voltage Range (Pin 4 or 5) VIR(pgm) – Vth to 7.5 – V
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Cell Selector Series Resistance
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Cell Positive to Top of Divider (Pin 2, 20, 19, or 18 to Pin 3)
Cell Negative to Bottom of Divider (Pin 20, 19, 18 or 16 to Pin 1)
RS+
RS–
–
–
100
100
–
–
Ω
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
Cell Voltage Sampling Rate
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Test Input Threshold Voltage (Pin 15)
t(smpl)
Vth
–
–
1.0
VCell 1/2.0
–
– V
s
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
CELL VOLTAGE BALANCING
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Internal Balancing Resistance (Pins 2, 20, 19 and 18)
ÁÁÁÁ
ÁÁÁ
CURRENT SENSING
Rbal – 140 – Ω
ÁÁÁÁ
Input Bias Current
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Charge Current Limit (Pin 7 to Pin 6)
Threshold Voltage Vth(chg)
IIB(chg)
–
–
18
200
–
–
mV
nA
Delay Idly(chg) – 1.0 – s
3. Tested ambient temperature range for the MC33345:
Tlow = –25°C Thigh = +85°C

MC33345
ELECTRICAL CHARACTERISTICS (continued) (VCC (Pin 2) = 8.0 V, VC (Pin 18) = 4.0 V, TA = 25°C, for min/max values TA is the
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
CURRENT SENSING
Discharge Current Limit (Pin 2 to Pin 6)
Threshold Voltage Vth(dschg) – 50 – mV
Input Bias Current IIB(dschg) – 200 – nA
Delay Idly(dschg) – 3.0 – ms
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
CHARGE PUMP
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Voltage (Pin 14, RL ≥ 1010 Ω) VO – 10.2 – V
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
TOTAL DEVICE
Average Cell Current ICC
Operating (VCC = 8.0 V) – 15 – µA
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Sleepmode (VCC = 5.0 V) – 5.0 – nA
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Minimum Operating Cell Voltage for Logic and Gate Drivers VCC V
Programmed for One Cell Operation
Cell 1 Voltage – 2.2 –
Programmed for Two, Three, or Four Cell Operation
Cell 2, Cell 3, or Cell 4 Voltage, Sum Voltage of Cells – 0.7 –

MC33345
ÁÁÁ
ÁÁÁÁÁÁÁ
Pin
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Symbol Description
ÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Cell Voltage Return
ÁÁÁÁÁÁÁ
The bottom side of a three resistor divider string connects to this pin. The Cell Selector internally
switches this point to the negative terminal of the cell that is to be monitored.
ÁÁÁ
2
ÁÁÁÁÁÁÁ
Cell 4/VCC/
ÁÁÁÁÁÁÁ
This is a multifunction pin that connects to a high impedance node of the Cell Selector where it is used to
Discharge Current Limit monitor the positive terminal of Cell 4 and to provide positive supply voltage for the protection IC. This pin
is also used to monitor the voltage drop across the discharge current limit resistor and it provides a
ÁÁÁ
3ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
discharge path for the internal balancing of Cell 4.
Cell Voltage The top side of a three resistor divider string connects to this pin. The Cell Selector internally switches
ÁÁÁ
ÁÁÁÁÁÁÁ
this point to the positive terminal of the cell that is to be monitored.
ÁÁÁ
ÁÁÁÁÁÁÁ
4 Discharge Voltage The upper tap of a three resistor divider string connects to this pin. The Cell Voltage Detector compares
Threshold the divided down cell voltage to an internal reference. If the comparator detects that the cell voltage has
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
fallen below the programmed level, discharge switch Q2 is disabled, and the protection circuit enters into
a low current sleepmode state. This prevents further discharging of the battery pack.
ÁÁÁ
ÁÁÁÁÁÁÁ
5 Charge Voltage The lower tap of a three resistor divider string connects to this pin. The Cell Voltage Detector compares
Threshold the divided down cell voltage to an internal reference. If the comparator detects that the cell voltage has
ÁÁÁ
ÁÁÁÁÁÁÁ
risen above the programmed level, charge switch Q1 is disabled, preventing further charging of the
battery pack. A 2.0 µA current source pull–up is internally applied to this pin creating input hysteresis.
ÁÁÁ
6
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Current Sense Common This pin is a common point that is used to monitor the voltage drop across the charge and discharge
current limit resistors.
ÁÁÁ
7
ÁÁÁÁÁÁÁ
Charge Current Limit This pin is used to monitor the voltage drop across the charge current limit resistor.
ÁÁÁ
8
ÁÁÁÁÁÁÁ
Charge Gate Drive
ÁÁÁÁÁÁÁ
This pin provides a gate turn–off path for charge switch Q1. The charge switch source and the battery
Common pack negative terminal connect to this point.
ÁÁÁ
ÁÁÁÁÁÁÁ
9 Charge Gate Drive This output connects to the gate of charge switch Q1 allowing it to enable or disable battery pack
ÁÁÁ
ÁÁÁÁÁÁÁ
Output charging.
ÁÁÁ
ÁÁÁÁÁÁÁ
10 Program 2 This pin is used in conjunction with Pin 11 to program the number of cells.
ÁÁÁ
ÁÁÁÁÁÁÁ
11 Program 1 This pin is used in conjunction with Pin 10 to program the number of cells.
ÁÁÁ
ÁÁÁÁÁÁÁ
12 No Connection This pin is not internally connected.
ÁÁÁ
ÁÁÁÁÁÁÁ
13 Discharge Gate Drive This output connects to the gate of discharge switch Q2 allowing it to enable or disable battery pack
Output discharging.
ÁÁÁ
ÁÁÁÁÁÁÁ
14
Charge Pump Output This is the charge pump output. A reservoir capacitor is connected from this pin to ground.
ÁÁÁ
ÁÁÁÁÁÁÁ
15
Test Input
ÁÁÁÁÁÁÁ
This input is used to facilitate circuit testing and is normally not connected. It has an internal 2.0 k pull–up
resistor.
ÁÁÁ
ÁÁÁÁÁÁÁ
16
Ground This is the protection IC ground and all voltage ratings are with respect to this pin.
ÁÁÁ
ÁÁÁÁÁÁÁ
17
Fault Output
ÁÁÁÁÁÁÁ
This is on open drain output that is active low when a charging fault limit has been exceeded. The limits
sensed are both charge voltage and current.
ÁÁÁ
ÁÁÁÁÁÁÁ
18 Cell 1/VC This is a multifunction pin that connects to a high impedance node of the Cell Selector where it is used to
monitor the positive terminal of Cell 1 and the negative terminal of Cell 2. This pin also provides logic
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
19
biasing and a discharge path for the internal balancing of Cell 1.
Cell 2 This pin connects to a high impedance node of the Cell Selector where it is used to monitor the positive
ÁÁÁ
ÁÁÁÁÁÁÁ
terminal of Cell 2 and the negative terminal of Cell 3. This pin also provides a discharge path for the
internal balancing of Cell 2.
ÁÁÁ
ÁÁÁÁÁÁÁ
20
Cell 3
ÁÁÁÁÁÁÁ
This pin connects to a high impedance node of the Cell Selector where it is used to monitor the positive
terminal of Cell 3 and the negative terminal of Cell 4. This pin also provides a discharge path for the
ÁÁÁ
ÁÁÁÁÁÁÁ
internal balancing of Cell 3.

MC33345
INTRODUCTION This configuration allows the protection circuit to interrupt
The insatiable demand for smaller lightweight portable the appropriate charge or discharge path FET in the event
electronic equipment has dramatically increased the that a programmed voltage or current limit for any cell has
requirements of battery performance. Batteries are expected been exceeded.
to have higher energy densities, superior cycle life, be safe in A functional description of the protection circuit blocks
operation and environmentally friendly. To address these high follows. Refer to the detailed block diagram shown in
expectations, battery manufacturers have invested heavily in Figure 6.
developing rechargeable lithium–based cells. Today’s most Voltage Sensing
attractive chemistries include lithium–polymer, lithium–ion, Individual cell voltage sensing is accomplished by the use
and lithium–metal. Each of these chemistries require of the Cell Selector in conjunction with the Floating
electronic protection in order to constrain cell operation to Over/Under Voltage Detector and Reference block. The Cell
within the manufacturers limits. Selector applies the voltage of each cell across an external
Rechargeable lithium–based cells require precise charge resistor divider string that connects from Pins 3 to 1. The
and discharge termination limits for both voltage and current voltage at each of the tap points is sequentially polled and
in order to maximize cell capacity, cycle life, and to protect compared to an internal reference. If a limit has been
the end user from a catastrophic event. The termination limits exceeded, the result is stored in the Over/Under Data Latch
are not as well defined as with older non–lithium chemistries. and Control Logic block. The Cell Selector is gated on for an
These limits are dependent upon a manufacturer’s particular 8.0 ms period at a one second repetition rate. This low duty
lithium chemistry, construction technique, and intended cycle sampling technique reduces the average load current
application. Battery pack assemblers may also choose to that the divider presents across each cell, thus extending the
enhance cell capacity at the expense of cycle life. In order to useful battery pack capacity. The cells are sensed in the
address these requirements the MC33345 was developed. following sequence:
This device features programmable voltage and current
limits, cell voltage balancing, low operating current, a virtually Figure 2. Cell Sensing Sequence
zero current sleepmode state, and requires few external Polling Time Cell Tested
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
components to implement a complete one to four cell smart Sequence (ms) Sensed Limit
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
battery pack.
1 1.0 Cell 4 Overvoltage
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
OPERATING DESCRIPTION 2 1.0 Cell 3 Overvoltage
The MC33345 is specifically designed to be placed in the
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
battery pack where it is continuously powered from either one, 3 1.0 Cell 2 Overvoltage
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
two, three, or four lithium cells. In order to maintain cell 4 1.0 Cell 1 Overvoltage
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
operation within specified limits, the protection circuit senses
5 1.0 Cell 4 Undervoltage
both cell voltage and current, and correspondingly controls the
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
state of two N–channel MOSFET switches. These switches, 6 1.0 Cell 3 Undervoltage
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Q1 and Q2, are placed in series with the negative terminal of 7 1.0 Cell 2 Undervoltage
Cell 1 and the negative terminal of the battery pack.
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Figure 1. Simplified Four Cell Smart Battery Pack
By incorporating this polling technique with a single
RLim(dschg) RLim(chg)
floating comparator and voltage divider, a significant
reduction of circuitry and trim elements is achieved. This
6 7 results in a smaller die size, lower cost, and reduced
operating current.
2
Cell 4
Figure 3. Cell Voltage Limit Programming
3
R1
Cell 3 20
From Cell Voltage
4 Cell
R2 Selector 3
Cell 2 19 Discharge Voltage R1
MC33345 Floating Threshold +
5 Over/Under
R3 Cell Voltage 4 Cell
18 Charge Voltage R2 Voltage
Cell 1 Detector
Threshold
1 &
Reference 5 –
Cell Voltage R3
16 To
15 Return
Cell
11 1
Selector
17
10 14 13 9 8 The cell charge and discharge voltage limits are controlled
by the values selected for the resistor divider string and the
1.23 V input threshold of Pins 4 and 5. As the battery pack
Discharge Charge reaches full charge, the Cell Voltage Detector will sense an
MOSFET Q2 MOSFET Q1 overvoltage fault condition on the first cell that exceeds the
programmed overvoltage limit. The fault information is stored

MC33345
in a data latch and charge MOSFET Q1 is turned off, capacity. Figure 4 illustrates the operation of an unbalanced
disconnecting the battery pack from the charging source. An two cell pack. As the cells become unbalanced, the full
internal 2.0 µA current source pull–up is then applied to Pin 5 battery pack capacity is not realized. This is due to the
creating an input hysteresis voltage. As a result of an requirement that charging must terminate when Cell 2
overvoltage fault, the battery pack is available for reaches the overvoltage limit, and discharging must
discharging only. terminate when Cell 1 reaches the undervoltage limit. By
The overvoltage fault is reset by applying a load to the employing a method of keeping the cell voltages equal, both
battery pack. As the voltage across each cell falls below the cells can be charged and discharged to their specified limits,
input hysteresis level, charge MOSFET Q1 will turn on. The thus attaining the maximum possible capacity .
battery pack will now be available for charging or
Figure 4. Unbalanced Battery Pack Operation
discharging. The over voltage limit and hysteresis voltage are
ǒ Ǔ
given by:
V
OV
+ Vth (Pin 5) R1 ) R3
R2 ) R3
V +I (R1 ) R2)
Cell 2 Cell 2
4.2 V
H H (Pin 5) Overvoltage Charge 2.7 V
As the load eventually depletes the battery pack charge, Limit
the Cell Voltage Detector will sense an undervoltage fault
condition on the first cell that falls below the programmed Cell 1 Cell 1
2.5 V
undervoltage limit. After an undervoltage cell is detected, 4.0 V Disharge Undervoltage
discharge MOSFET Q2 is turned off, disconnecting the Limit
battery pack from the load. The protection circuit will now
enter a low current sleepmode state drawing just 5.0 nA
typically, thus preventing any further cell discharging. As a
result of the undervoltage fault, the battery pack is available Charged Discharged
ǒ Ǔ
for charging only. The undervoltage limit is given by:
The MC33345 contains a Cell Voltage Balancing Logic
+ Vth (Pin 4) ) R2 ) R3 circuit that controls four N–channel MOSFETs. The circuit
R2 ) R3
V R1
UV samples the voltage of each cell during the polling period. If
The undervoltage fault is reset by applying charge current all of the cells are below the programmed overvoltage fault
to the battery pack. When the voltage on Pin 16 exceeds limit, no cell balancing takes place. If one or more cells
Pin 8 by 0.6 V, discharge MOSFET Q2 will turned on. The reach the overvoltage fault limit, a specific latch is set for
battery pack will now be available for charging or discharging. each cell. At the end of the polling period, charge
Since the thresholds of Pins 4 and 5 are equal, the above MOSFET Q1 is turned off and the latches are interrogated. If
equations can be rewritten to directly solve for specific all of the latches were set, no cell balancing takes place. If
resistor values as shown in the example below. one, two, or three latches were set, the required cell
balancing MOSFETs are then activated. The overvoltage
Let the desired limits be:
cells are discharged to the programmed level of VOV – VH.
VOV = 4.2 V, VH = 0.4 V, and VUV = 2.5 V
As each cell attains this level, the discharge MOSFETs
ǒǓ ǒ Ǔ
With nominal values for: successively turn off. Upon completion of cell balancing,
Vth = 1.23 V, and IH = 2.0 µA charge MOSFET Q1 is turned on. Cell voltage balancing is
active during charge and discharge, but disabled during the
ǒ Ǔǒ Ǔ
V
H 0.4 low current sleepmode state.
I
R3 + H
+ 2.0 x 10 –6
4.2 – 1
+ 82,828 W Cell Programming and Test
V The protection circuit can be programmed for operation
OV – 1 1.23
ǒ Ǔ ǒ
V with either one, two, three, or four cell battery packs.
th Programming inputs 1 and 2 are used to set up the internal
+ R3 V
+ 82,828 Ǔ+ W
logic for the number of cells to be monitored. If less than
ǒǓ ǒ Ǔ
OV – 1 4.2 – 1 four cells are required, the input for each empty cell position
R2 56,323
V 2.5 must be connected to VCC. This process starts with Cell 4
UV
decending down to Cell 2 if required. Refer to the Cell
R1 + V
I
H –R2 + 0.4 –56,323 + 143,677 W Programming table shown below and the specific
application figure.
H 2.0 x 10 –6
Figure 5. Cell Sensing Sequence
Note that the Cell Selector has a typical total series
resistance of 200 Ω. This will have a minimal effect on the Number of Program 1 Program 2 Application
programmed limits if the total divider resistance is in excess
of 100 kΩ. ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
Cells
ÁÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
(Pin 11)
Ground
(Pin 10)
Cell 1/VC
Figure
16
Cell Voltage Balancing
With series connected cells, successive charge and ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
2
ÁÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁÁ
3
ÁÁÁÁÁ
Cell 1/VC
Cell 1/VC
Ground
Cell 1/VC
15
14
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
discharge cycles can result in a significant difference in cell
voltage with a corresponding degradation of battery pack 4 Ground Ground 13

MC33345
A test option is provided to speed up device and battery The discharge current fault is reset by either disconnecting
pack testing. By connecting Pin 15 to ground, the internal the load from the battery pack, or by connecting the battery
logic is held in a reset state and both MOSFET switches are pack to the charger. When the voltage on Pin 8 no longer
turned on. Upon release, the Control Logic becomes active exceeds Pin 16 by approximately 2.0 V, the Sense Enable
and the cells are polled within 8.0 ms. circuit will turn on discharge MOSFET Q2. Discharge current
sensing can be disabled by connecting Pin 2 to Pin 6.
Current Sensing
The charge and discharge current protection circuits
Charge and discharge current limit protection can be contain a built in response delay of 1.0 s and 3.0 ms
selectively added to the battery pack with the addition of a respectively. This helps to prevent fault activation when the
sense resistor. The resistors are placed in series with the battery pack is subjected to pulsed currents during charging
positive terminal of the battery pack and the cells. Refer to or discharging.
Figure 1.
As the battery pack charges, Pins 6 and 7 sense the Charge Pump and MOSFET Switches
voltage drop across RLim(chg). A charge current limit fault is The MC33345 contains an on chip Charge Pump to
detected if the voltage at Pin 7 exceeds Pin 6 by 18 mV for ensure that the MOSFET switches are fully enhanced for
the entire delay period of 1.0 second. The fault information is reduced power losses. An external reservoir capacitor
stored in a data latch and charge MOSFET Q1 is turned off, normally connects from the Charge Pump output to ground,
disconnecting the battery pack from the charging source. As Pins 14 and 16. The capacitor value is not critical and is
a result of the charge current fault, the battery pack is usually within the range of 10 nF to 100 nF. The Charge
available for discharging only. The charge current limit is Pump output is regulated at 10.2 V allowing the use of
given by: economical logic level MOSFETs in one and two cell
V applications. The main requirement in selecting a particular
I
Lim(chg)
+ R
th(chg)
+
R
18 mV type of MOSFET switch is to consider the desired
Lim(chg) Lim(chg) on–resistance at the lowest anticipated operating voltage of
the battery pack. A table of small outline surface mount
The charge current fault is reset by either disconnecting
devices is given in Figure 6. When using extremely low
the battery pack from the charger, or by connecting a load to
threshold MOSFETs, it may be desirable to disable the
the battery pack. When the voltage on Pin 16 no longer
Charge Pump so that the maximum gate to source voltage is
exceeds Pin 8 by approximately 2.0 V, the Sense Enable
not exceeded. This is accomplished by connecting Pin 14 to
circuit will turn on charge MOSFET Q1. Charge current
Pin 19 with two, three, or four cell battery packs.
sensing can be disabled by connecting Pin 7 to Pin 6.
The discharge current limiting operates in a similar Battery Pack Application
manner. As the battery pack discharges, Pins 2 and 6 sense Upon assembly of the battery pack, it is imperative that
the voltage drop across RLim(dschg). A discharge current limit Cell 1 be connected first so that VC is properly biased. The
fault is detected if the voltage at Pin 2 is less than Pin 6 by remaining cells can then be connected in any order. This
50 mV for more than 3.0 ms. The fault information is stored in assembly method prevents forward biasing the protection IC
a data latch and discharge MOSFET Q2 is turned off, substrate which can result in overheating and
disconnecting the battery pack from the load. As a result of non–functionality.
the discharge current fault, the battery pack is available for Each of the application figures show a capacitor labeled
charging only. The discharge current limit is given by: CESD. This capacitor provides a path around the MOSFET
V switches in the event of an electrostatic discharge.
I
Lim(dschg)
+ R th(dschg) + R 50 mV
Lim(dschg) Lim(dschg)
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Figure 6. Small Outline Surface Mount MOSFET Switches
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On–Resistance (Ω) versus Gate to Source Voltage (V)
Device
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Type 2.5 V 3.0 V 4.0 V 5.0 V 6.0 V 7.5 V 9.0 V
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MMFT3055VL – – – 0.120 Ω 0.115 Ω 0.108 Ω 0.100 Ω
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MMDF3N03HD – 0.525 Ω 0.080 Ω 0.065 Ω 0.063 Ω 0.062 Ω 0.060 Ω
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MMDF4N01HD 0.047 Ω 0.042 Ω 0.037 Ω 0.035 Ω 0.034 Ω 0.033 Ω See Note
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MMSF5N02HD – 0.065 Ω 0.023 Ω 0.021 Ω 0.020 Ω 0.018 Ω 0.018 Ω
MMDF6N02HD 0.043 Ω 0.035 Ω 0.029 Ω 0.028 Ω 0.026 Ω 0.025 Ω 0.023 Ω
NOTE: Exceeds maximum VGS voltage rating.

MC33345
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PROTECTION CIRCUIT OPERATING MODE TABLE
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ÁÁÁÁÁÁÁ MOSFET Switches
Outputs
Function
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Input Conditions
ÁÁÁÁ Circuit Operation Charge Discharge Charge
Cell
Balancing
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ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
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Cell Status Battery Pack Status Q1 Q2 Pump (See Note)
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CELL CHARGING/DISCHARGING
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Storage or Nominal Operation: Both Charge MOSFET Q1 and Discharge MOSFET On On Active Active
No current or voltage faults Q2 are on. The battery pack is available for charging
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or discharging.
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CELL CHARGING FAULT/RESET
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Charge Current Limit Fault: Charge MOSFET Q1 is latched off and the cells are On to Off On Active Active
VPin 7 ≥ (VPin 6 + 18 mV)
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disconnected from the charging source. Q1 will remain
for 1.0 s in the off state as long as VPin 16 exceeds VPin 11 by
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≈ 2.0 V. The battery pack is available for discharging.
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Charge Current Limit Reset: The Sense Enable circuit will reset and turn on charge Off to On On Active Active
VPin 16 – VPin 8 < 2.0 V MOSFET Q1 when VPin 16 no longer exceeds VPin 11
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ÁÁÁÁÁÁÁÁÁ ÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
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by ≈ 2.0 V. This can be accomplished by either dis-
connecting the charger from the battery pack, or by
connecting a load to the battery pack.
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
Charge Voltage Limit Fault:
ÁÁÁÁ ÁÁÁÁ
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VPin 5 ≥ 1.23 V for 1.0 s
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Charge MOSFET Q1 is latched off and the cells are
disconnected from the charging source. An internal
current source pull–up of 2.0 µA is applied to Pin 8
On to Off On Active Active
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ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
creating an input hysteresis voltage of VH with divider
resistors R1 and R2. The battery pack is available for
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ÁÁÁ
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discharging.
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Charge Voltage Limit Reset: Charge MOSFET Q1 will turn on when the voltage Off to On On Active Active
VPin 5 < 1.23 V for 1.0 s across each cell falls sufficiently to overcome the in-
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put hysteresis voltage. This can be accomplished by
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applying a load to the battery pack.
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CELL DISCHARGING FAULT/RESET
Discharge Current Limit Fault: Discharge MOSFET Q2 is latched off and the cells On On to Off Active Active
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for 3.0 ms
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VPin 6 ≤ (VPin 2 – 50 mV)
ÁÁÁÁ ÁÁÁÁ
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are disconnected from the load. Q2 will remain in the
off state as long as VPin 11 exceeds VPin 16 by ≈ 2.0 V.
The battery pack is available for charging.
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VPin 8 – VPin 16 < 2.0 V ÁÁÁÁ
Discharge Current Limit Reset:
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The Sense Enable circuit will reset and turn on dis-
charge MOSFET Q2 when VPin 11 no longer exceeds
On Off to On Active Active
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VPin 16 by ≈ 2.0 V. This can be accomplished by either
disconnecting the load from the battery pack, or by
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connecting the battery pack to the charger.
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Discharge Voltage Limit Fault: Discharge MOSFET Q2 is latched off, the cells are On On to Off Disabled Disabled
VPin 4 ≤ 1.23 V for 1.0 s
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disconnected from the load, and the protection circuit
enters a low current sleepmode state. The battery
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ÁÁÁÁ
pack is available for charging.
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Discharge Voltage Limit Reset: The Sense Enable circuit will reset and turn on dis- On Off to On Active Active
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VPin 16 > (VPin 8 + 0.6 V)
charge MOSFET Q2 when VPin 16 exceeds VPin 8 by
ÁÁÁ ÁÁÁÁ
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0.6 V. This can be accomplished by connecting the
battery pack to the charger.
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FAULTY CELL
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Simultaneous Charge and This condition can happen if there is a defective cell in Cycles Cycles Cycles Cycles
Discharge Voltage Limit Faults: the battery pack. The protection circuit will remain in Cell 1 Cell 1 Cell 1 Cell 1
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VPin 5 ≥ 1.23 V for 1.0 s and the sleepmode state until the battery pack is con- Good Good Good Good
VPin 4 ≤ 1.23 V for 1.0 s
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nected to a charger. If Cell 2, 3, or 4 is faulty and a
charger is connected, the protection circuit will cycle Disabled Disabled Disabled Disabled
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in and out of sleepmode. If Cell 1 is faulty (<1.5 V), Cell 1 Cell 1 Cell 1 Cell 1
Faulty
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ÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
the protection circuit logic will not function and the Faulty Faulty Faulty
battery pack cannot be charged.
NOTE: Cell balancing is not active when programmed for one cell operation.

MC33345
Figure 7. Four Cell Smart Battery Pack
Current Sense Charge Current

MC33345 Common 6 7 Limit
Cell 4/VCC/
Discharge Charge/Discharge
Current Limit Overcurrent Detector
2
140
Cell Voltage
Cell 4
Cell 3 3
Discharge Voltage R1
20 Floating Threshold
140 Over/Under
Cell 3 Cell Voltage 4
Cell 2 Detector Charge Voltage R2
Cell
& Threshold
Selector
19 140 Reference 5
Cell 2 Cell Voltage R3
Cell 1/VC Return
1
18 140 VC
Cell 1
2.0 k Test Input
Ground
16 Over/Under 15
Program 1 Data Latch Fault Output
&
11 Cell Voltage Control Logic 17
Program 2 Balancing
Logic
10
Sense
Ck Ck En Enable
Charge/Discharge
Oscillator Charge Pump Gate Drivers

CO Charge
Discharge Switch
Switch Q2 Q1
CESD

MC33345
Figure 8. Three Cell Smart Battery Pack

Cell 4/VCC/
2
140
Cell Voltage
Cell 3 3
140 Over/Under
Cell 3 Cell Voltage 4
Cell
& Threshold
Selector
19 140 Reference 5
Cell 1/VC Return
1
18 140 VC
Cell 1
2.0 k Test Input
Ground
16 Over/Under 15
&
Program 2 Balancing
Logic
10
Sense
Ck Ck En Enable
Charge/Discharge

CO Charge
Discharge Switch
Switch Q2 Q1
CESD

MC33345
Figure 9. Two Cell Smart Battery Pack

Cell 4/VCC/
2
140
Cell Voltage
Cell 3 3
140 Over/Under
Cell Voltage 4
Cell
& Threshold
Selector
19 140 Reference 5
Cell 1/VC Return
1
18 140 VC
Cell 1
2.0 k Test Input
Ground
16 Over/Under 15
&
Program 2 Balancing
Logic
10
Sense
Ck Ck En Enable
Charge/Discharge

CO Charge
Discharge Switch
Switch Q2 Q1
CESD

MC33345
Figure 10. One Cell Smart Battery Pack

Cell 4/VCC/
2
140
Cell Voltage
Cell 3 3
140 Over/Under
Cell Voltage 4
Cell
& Threshold
Selector
19 140 Reference 5
Cell Voltage R3
Cell 1/VC Return
1
18 140 VC
Cell 1
2.0 k Test Input
Ground
16 Over/Under 15
&
Program 2 Balancing
Logic
10
Sense
Ck Ck En Enable
Charge/Discharge

CO Charge
Discharge Switch
Switch Q2 Q1
CESD

MC33346
Product Preview
Circuit for Three or Four Cell LITHIUM BATTERY
Battery Packs
PROTECTION CIRCUIT
FOR
The MC33346 is a monolithic lithium battery protection circuit that is THREE OR FOUR CELL
designed to enhance the useful operating life of three or four cell SMART BATTERY PACKS
rechargeable battery packs. Cell protection features consist of
independently programmable charge and discharge limits for both voltage
and current with a delayed current shutdown, cell voltage balancing with
on–chip balancing resistors, and virtually zero current sleepmode state
when the cells are discharged. Additional features consists of a six wire DW SUFFIX
microcontroller interface bus that can selectively provide a pulse output that PLASTIC PACKAGE
24
CASE 751E
represents the internal reference voltage, cell voltage, cell current and (SO–24L)
temperature, as well as control the states of four internal balancing and two 1
external MOSFET switches. A microcontroller time reference output is

available for gas gauge implementation. This protection circuit requires a DTB SUFFIX
minimum number of external components and is targeted for inclusion within 24 PLASTIC PACKAGE
the battery pack. The MC33346 is available in standard and low profile 24 CASE 948H
lead surface mount packages. 1 (TSSOP–24)
• Independently Programmable Charge and

Discharge Limits for Both Voltage and
Current Typical Four Cell Smart Battery Pack
• Delayed Current Shutdown
• Cell Voltage Balancing with On–Chip
Resistors
• Six Wire Microcontroller Interface Bus
• Data Output for Reference, Voltage, Current,
and Temperature Current Charge Discharge Charge Charge
Sense Current Gate Drive Gate Drive Gate Drive
•
Cell 4/VCC/
Microcontroller Time Reference Output for Discharge Common Limit Output Output Common
Current Limit 7 6 14 20 21 Cell Voltage
Gas Gauging
• Virtually Zero Current Sleepmode State when
3 2
Discharge Voltage
Cells are Discharged Cell 3 Threshold
• Programmable for Three or Four Cell 24 4

Charge Voltage
Applications Cell 2 Threshold
• Minimum External Components for Inclusion 23 5
within the Battery Pack MC33346

Cell Voltage
Cell 1 Return
• Available in Low Profile Surface Mount 22 1
Packages Data Output
Ground Ref/V/I/T
Cell 15 16
Program Reference Clock Output
11 19
ORDERING INFORMATION Temp Interrupt Output
8 12
Operating 17 18 13 10 9
Device Temperature Range Package A–to–D VC Address Data Charge Gate
Converter Logic Input Input Turn Off/
Period Supply Test Input
MC33346DW SO–24L
TA = –40° to +85°C
MC33346DTB TSSOP–24

MC33347
Product Preview
Circuit for One or Two LITHIUM BATTERY
Cell Battery Packs PROTECTION CIRCUIT
The MC33347 is a monolithic lithium battery protection circuit that is
FOR
designed to enhance the useful operating life of one or two cell ONE OR TWO CELL
rechargeable battery packs. Cell protection features consist of SMART BATTERY PACKS
independently programmable charge and discharge limits for both voltage
and current with a delayed current shutdown, continuous cell voltage
SEMICONDUCTOR
balancing with the choice of on–chip or external balancing resistors, and a
virtually zero current sleepmode state when the cells are discharged. TECHNICAL DATA
Additional features include an on–chip charge pump for reduced MOSFET
losses while charging or discharging a low cell voltage battery pack, and the
programmability for one or two cell battery pack. This protection circuit
requires a minimum number of external components and is targeted for
inclusion within the battery pack. This MC33347 is avaialble in standard and
D SUFFIX
low profile 16 lead surface mount packages. PLASTIC PACKAGE
16
• Independently Programmable Charge and Discharge Limits for Both CASE 751B
1 (SO–16)
Voltage and Current
• Charge and Discharge Current Limit Detection with Delayed Shutdown
• Continuous Cell Voltage Balancing
• On–Chip or External Balancing Resistors DTB SUFFIX
• Virtually Zero Current Sleepmode State when Cells are Discharged 16 PLASTIC PACKAGE
• Charge Pump for Reduced Losses with a Low Cell Voltage Battery Pack 1
CASE 948F
(TSSOP–16)
• Programmable for One or Two Cell Applications
• Minimum External Components for Inclusion within the Battery Pack
PIN CONNECTIONS
Typical Two Cell Smart Battery Pack

Balance 1 1 16 Ground
Balance 2 2 15 Charge Pump Output

Cell Program/ Current Sense Charge
Common 9 10 Current Limit Discharge
Test 13 Cell 1/VC 3 14
Gate Drive Output
Cell 2/VCC/
Cell Voltage
Cell 2/VCC/ Cell Program/
Discharge
Current Limit Discharge Current Limit 4 13
Test
6
4 Discharge Voltage Cell Voltage Return 5 12 Charge
Gate Drive Output
Balance 2 Threshold
7
Cell Voltage 6 11 Charge
2 MC33347 Gate Drive Common
Cell 1/VC Charge Voltage Discharge Voltage
Threshold 7 10 Charge Current Limit
Threshold
3
8 Charge Voltage 8 Current Sense
Balance 1 9 Common
Cell Voltage Threshold
1 Return
Ground 5 (Top View)
16
Output Output Common ORDERING INFORMATION
Operating
MC33347D SO–16
TA = –25° to +85°C
This device contains 1543 active transistors. MC33347DTB TSSOP–16

MC33347
MAXIMUM RATINGS
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ÁÁÁ
Input Voltage (Measured with Respect to Ground, Pin 16) VIR V
Balance 1, 2 (Pin 1, 2) 15
Cell 1/VC (Pin 3) 7.5
Cell 2/VCC/Discharge Current Limit (Pin 4) 18
Cell Voltage Divider (Pins 5, 6, 7 and 8) 18
Current Sense Common (Pin 9) 30
Charge Current Limit (Pin 10) 30
Charge Gate Drive Common (Pin 11) ±20
Cell Program/Test (Pin 13) 7.5
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ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
External Cell Balancing Current (Pin 1, 2, Note 1) Ibal 1.0 A
ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Cell Voltage Divider Current
ÁÁÁÁ
ÁÁÁ
Source Current (Pin 4 to 6)
Idiv
0.5
mA
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Sink Current (Pin 5 to 16) 0.5
Thermal Resistance, Junction–to–Air RθJA °C/W
DTB Suffix, TSSOP–16 Plastic Package, Case 948F 176
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ÁÁÁÁ
ÁÁÁ
D Suffix, SO–16 Plastic Package, Case 751B 145
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Operating Junction Temperature (Notes 1, 2 and 3) TJ –40 to +150 °C
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ELECTRICAL CHARACTERISTICS (VCC (Pin 4) = 8.0 V, VC (Pin 3) = 4.0 V, TA = 25°C, for min/max values TA is the
VOLTAGE SENSING
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ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Charge or Discharge Voltage Inputs (Pin 7 or 8 to Pin 5)
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Threshold Voltage Vth – 1.230 – V
Input Bias Current IIB – 20 – nA
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Input Hysteresis Source Current (Pin 8)
ÁÁÁÁ
ÁÁÁ
Cell Charge or Discharge Programmable Input Voltage Range (Pin 7 or 8)
IH
VIR(pgm)
–
–
2.0
Vth to 7.5
–
–
µA
V
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Cell Selector Series Resistance
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
ÁÁÁ
Cell Positive to Top of Divider (Pin 3 or 4 to Pin 6) RS+ – 100 –
Ω
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Cell Negative to Bottom of Divider (Pin 3 or 16 to Pin 5) RS– – 100 –
Cell Voltage Sampling Rate t(smpl) – 1.0 – s
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
Cell Program/ Test Input Threshold Voltage (Pin 13)
ÁÁÁÁ
ÁÁÁ
Vth – VCell 1/2.0 – V
ÁÁÁÁ
ÁÁÁ
CELL VOLTAGE BALANCING
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Cell Voltage Balancing Accuracy (Note 4) ∆V – 1.0 – %
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Internal Balancing Resistance (Pin 3, 4) Rbal – 80 – Ω
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Balancing MOSFET On Resistance (Pin 1, 2)
RDS(on) – 1.0 – Ω
ȧȧ ȧȧ
Ť Ť
ȧȧǒ Ǔȧȧȧ
V – V
Cell 1 Cell 2
+
ȧ
DV
4. Cell voltage balancing accuracy is defined as:
V avg
x 100 V
Cell 1
) VCell 2 x 100
2

MC33347
ELECTRICAL CHARACTERISTICS (continued) (VCC (Pin 4) = 8.0 V, VC (Pin 3) = 4.0 V, TA = 25°C, for min/max values TA is the
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
CURRENT SENSING
ÁÁÁÁ
Threshold Voltage
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Charge Current Limit (Pin 10 to Pin 9)
Vth(chg) – 18 – mV
Input Bias Current IIB(chg) – 200 – nA
Delay
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ Idly(chg) – 3.0 – ms
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Threshold Voltage Vth(dschg) – 50 – mV
Input Bias Current IIB(dschg) – 200 – nA
Delay
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Idly(dschg) – 3.0 – ms
CHARGE PUMP
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Output Voltage (Pin 15, RL ≥ 1010 Ω) VO – 10.2 – V
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
TOTAL DEVICE
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Average Cell Current ICC
µA
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Operating (VCC = 8.0 V) – 12.5 –
Sleepmode (VCC = 5.0 V) – 15 – nA
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Minimum Operating Cell Voltage for Logic and Gate Drivers
Programmed for Two Cell Operation
Cell 1 Voltage
VCC
– 1.5 –
V
Cell 2 Voltage – 0 –
Programmed for One Cell Operation
ȧȧ ȧȧ
Ť Ť
ȧȧǒ Ǔȧȧȧ
V – V
Cell 1 Cell 2
+
ȧ
DV
4. Cell voltage balancing accuracy is defined as:
V avg
x 100 V
Cell 1
) VCell 2 x 100
2

MC33347
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Pin
Symbol Description
ÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Balance 1
ÁÁÁÁÁÁÁ
This is the drain connection to an internal MOSFET. An external resistor is placed from this pin to the
positive terminal of Cell 1 for increased cell balancing capability. This allows most of the additional
ÁÁÁÁ
ÁÁÁÁÁÁÁ
power to be dissipated off–chip.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
2 Balance 2 This is the drain connection to an internal MOSFET. An external resistor is placed from this pin to the
positive terminal of Cell 2 for increased cell balancing capability. This allows most of the additional
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
3
Cell 1/VC
power to be dissipated off–chip.
This is a multifunction pin that connects to a high impedance node of the Cell Selector where it is
ÁÁÁÁ
ÁÁÁÁÁÁÁ
used to monitor the positive terminal of Cell 1 and the negative terminal of Cell 2. This pin also
provides logic biasing and a discharge path for the internal balancing of Cell 1.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
4
Cell 2/VCC/
ÁÁÁÁÁÁÁ
Discharge Current Limit
This is a multifunction pin that connects to a high impedance node of the Cell Selector where it is
used to monitor the positive terminal of Cell 2 and to provide positive supply voltage for the protection
ÁÁÁÁ
ÁÁÁÁÁÁÁ
IC. This pin is also used to monitor the voltage drop across the discharge current limit resistor and it
provides a discharge path for the internal balancing of Cell 2.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
5
Cell Voltage Return
ÁÁÁÁÁÁÁ
The bottom side of a three resistor divider string connects to this pin. The Cell Selector internally
switches this point to the negative terminal of the cell that is to be monitored.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
6 Cell Voltage The top side of a three resistor divider string connects to this pin. The Cell Selector internally switches
ÁÁÁÁ
ÁÁÁÁÁÁÁ
this point to the positive terminal of the cell that is to be monitored.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
7 Discharge Voltage The upper tap of a three resistor divider string connects to this pin. The Cell Voltage Detector
Threshold compares the divided down cell voltage to an internal reference. If the comparator detects that the cell
ÁÁÁÁ
ÁÁÁÁÁÁÁ
voltage has fallen below the programmed level for three consecutive samples, discharge switch Q2 is
ÁÁÁÁ
ÁÁÁÁÁÁÁ
disabled, and the protection circuit enters into a low current sleepmode state. This prevents further
discharging of the battery pack.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
8
Charge Voltage
ÁÁÁÁÁÁÁ
Threshold
The lower tap of a three resistor divider string connects to this pin. The Cell Voltage Detector
compares the divided down cell voltage to an internal reference. If the comparator detects that the cell
ÁÁÁÁ
ÁÁÁÁÁÁÁ
voltage has risen above the programmed level, charge switch Q1 is disabled, preventing further
charging of the battery pack. A 2.0 µA current source pull–up is internally applied to this pin creating
ÁÁÁÁ
ÁÁÁÁÁÁÁ
input hysteresis.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
9 Current Sense Common This pin is a common point that is used to monitor the voltage drop across the charge and discharge
current limit resistors.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
10 Charge Current Limit This pin is used to monitor the voltage drop across the charge current limit resistor.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
11 Charge Gate Drive This pin provides a gate turn–off path for charge switch Q1. The charge switch source and the battery
Common pack negative terminal connect to this point.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
12
Charge Gate Drive
ÁÁÁÁÁÁÁ
Output
This output connects to the gate of charge switch Q1 allowing it to enable or disable battery pack
charging.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
13 Cell Program/Test This is a multifunction input that is used to program the number of cells and to facilitate circuit testing.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
This input is connected to Pin 3 for two cell operation, and to Pin 16 for one cell operation.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Output discharging.
ÁÁÁÁ
ÁÁÁÁÁÁÁ
15
Charge Pump Output
ÁÁÁÁÁÁÁ
16
Ground
This is the charge pump output. A reservoir capacitor is connected from this pin to ground.
This is the protection IC ground and all voltage ratings are with respect to this pin.

MC33347
INTRODUCTION A functional description of the protection circuit blocks
The insatiable demand for smaller lightweight portable follows. Refer to the detailed block diagram shown in
electronic equipment has dramatically increased the Figures 7 and 8.
requirements of battery performance. Batteries are expected
Voltage Sensing
to have higher energy densities, superior cycle life, be safe in
Individual cell voltage sensing is accomplished by the use
operation and environmentally friendly. To address these
of the Cell Selector in conjunction with the Floating
high expectations, battery manufacturers have invested
Over/Under Voltage Detector and Reference block. The Cell
heavily in developing rechargeable lithium–based cells.
Selector applies the voltage of each cell across an external
Today’s most attractive chemistries include lithium–polymer,
resistor divider string that connects from Pins 6 to 5. The
lithium–ion, and lithium–metal. Each of these chemistries
voltage at each of the tap points is sequentially polled and
require electronic protection in order to constrain cell
compared to an internal reference. If a limit has been
operation to within the manufacturers limits.
exceeded, the result is stored in the Over/Under Data Latch
Rechargeable lithium–based cells require precise charge
and Control Logic block. The Cell Selector is gated on for a
and discharge termination limits for both voltage and current
1.0 ms period at a one second repetition rate. This low duty
in order to maximize cell capacity, cycle life, and to protect
cycle sampling technique reduces the average load current
the end user from a catastrophic event. The termination limits
that the divider presents across each cell, thus extending the
are not as well defined as with older non–lithium chemistries.
useful battery pack capacity. The cells are sensed in the
These limits are dependent upon a manufacturer’s particular
following sequence:
lithium chemistry, construction technique, and intended
application. Battery pack assemblers may also choose to Figure 2. Cell Sensing Sequence
enhance cell capacity at the expense of cycle life. In order to
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Polling Time Cell Tested
address these requirements the MC33347 was developed.
Sequence (ms) Sensed Limit
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
This device features programmable voltage and current
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
limits, cell voltage balancing, low operating current, a virtually 1 0.25 Cell 2 Overvoltage
zero current sleepmode state, and requires few external
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
2 0.25 Cell 1 Overvoltage
components to implement a complete one or two cell smart
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
battery pack.
The MC33347 is specifically designed to be placed in the By incorporating this polling technique with a single
battery pack where it is continuously powered from either one floating comparator and voltage divider, a significant
or two lithium cells. In order to maintain cell operation within reduction of circuitry and trim elements is achieved. This
specified limits, the protection circuit senses both cell voltage results in a smaller die size, lower cost, and reduced
and current, and correspondingly controls the state of two operating current.
N–channel MOSFET switches. These switches, Q1 and Q2,
are placed in series with the negative terminal of Cell 1 and Figure 3. Cell Voltage Limit Programming
the negative terminal of the battery pack. This configuration
allows the protection circuit to interrupt the appropriate From Cell Voltage
charge or discharge path FET in the event that a programmed Cell
Selector 6
voltage or current limit for either cell has been exceeded. Discharge Voltage R1
Floating Threshold +
Figure 1. Simplified Two Cell Smart Battery Pack Over/Under
Cell Voltage 7 Cell
Charge Voltage R2 Voltage
Detector
RLim(dschg) RLim(chg) Threshold
&
Reference 8 –
9 10 Cell Voltage R3
To Return
13 Cell
6 Selector 5
4 R1
Cell 2 The cell charge and discharge voltage limits are controlled
2 7 by the values selected for the resistor divider string and the
MC33347 R2
1.23 V input threshold of Pins 7 and 8. As the battery pack
3 reaches full charge, the Cell Voltage Detector will sense an
Cell 1 8 overvoltage fault condition on the first cell that exceeds the
R3
1 programmed overvoltage limit. The fault information is stored
16 in a data latch and charge MOSFET Q1 is turned off,
5
disconnecting the battery pack from the charging source. An
15 14 12 11
internal 2.0 µA current source pull–up is then applied to Pin 8
creating an input hysteresis voltage. As a result of an
overvoltage fault, the battery pack is available for
Discharge Charge discharging only.
MOSFET Q2 MOSFET Q1

MC33347
The overvoltage fault is reset by applying a load to the pack. As the cells become unbalanced, the full battery pack
battery pack. As the voltage across each cell falls below the capacity is not realized. This is due to the requirement that
input hysteresis level, charge MOSFET Q1 will turn on. The charging must terminate when Cell 2 reaches the
battery pack will now be available for charging or overvoltage limit, and discharging must terminate when
discharging. The over voltage limit and hysteresis voltage are Cell 1 reaches the undervoltage limit. By employing a
ǒ Ǔ
given by: method of keeping the cell voltages equal, both cells can be
+ Vth (Pin 8) R1 ) R3
R2 ) R3
charged and discharged to their specified limits, thus
V attaining the maximum possible capacity.
OV
V +I (R1 ) R2)
Figure 4. Unbalanced Battery Pack Operation
H H (Pin 8)
As the load eventually depletes the battery pack charge,
condition on the first cell that falls below the programmed
Cell 2 Cell 2
undervoltage limit. After three consecutive faults are 4.2 V
detected, discharge MOSFET Q2 is turned off, disconnecting Overvoltage Charge 2.7 V
Limit
the battery pack from the load. The protection circuit will now
enter a low current sleepmode state drawing just 15 nA, thus
Cell 1 Cell 1
preventing any further cell discharging. As a result of the 2.5 V
undervoltage fault, the battery pack is available for charging 4.0 V Disharge Undervoltage
ǒ Ǔ
only. The undervoltage limit is given by: Limit
) R2 ) R3
+ Vth (Pin 7) R1 R2
V
UV ) R3
The undervoltage logic is designed to automatically reset Charged Discharged
if less than three consecutive faults appear. This helps to The MC33347 contains a Cell Voltage Balancing Amplifier
prevent a premature disconnection of the load during high that controls four N–channel MOSFETs. The amplifier
current pulses when the battery pack charge is close to being samples the cell voltages during the polling period. If the
depleted. detected cell voltage difference exceeds 1.0 %, the MOSFET
The undervoltage fault is reset by applying charge current that connects across the higher voltage cell is turned on. The
to the battery pack. When the voltage on Pin 16 exceeds excess charge will eventually be bled off through the internal
Pin 11 by 0.6 V, discharge MOSFET Q2 will turned on. The 80 Ω resistor with a typical balancing current that ranges
battery pack will now be available for charging or from 40 mA to 80 mA. If higher balancing currents are
discharging. desired, Pins 1 and 2 provide a means for paralleling a lower
Since the thresholds of Pin 7 and 8 are equal, the above value external resistor for in excess of 500 mA. The use of an
equations can be rewritten to directly solve for specific external resistor allows a reduction of on–chip power
resistor values as shown in the example below. dissipation. Cell voltage balancing is active during charge
Let the desired limits be: and discharge, but disabled during the low current
VOV = 4.2 V, VH = 0.4 V, and VUV = 2.5 V sleepmode state.
ǒǓ ǒ Ǔ
With nominal values for: Cell Programming and Test
Vth = 1.23 V, and IH = 2.0 µA The protection circuit can be programmed for operation
with either one or two cell battery packs. The Cell
ǒ Ǔ ǒ Ǔ
V
H 0.4 Programming/Test input, Pin 13, is used to control the Cell
I
R3 + H
+ 2.0 x 10 –6
4.2 – 1
+ 82,828 W Selector and to enable or disable the Cell Voltage Balancing
Amplifier. For one cell operation, Pin 13 is connected to
V
ǒ Ǔ ǒ Ǔ
OV – 1 1.23 Pin 16, and Pin 4 is connected to Pin 3 and the positive
V terminal of Cell 1, refer to Figure 8. For two cell operation,
th
Pin 13, is connected to Pin 3 and the positive terminal of
+ R3 V
+ 82,828 + 56,323 W
ǒǓ ǒ Ǔ
OV –1 4.2 –1 Cell 1, and Pin 4 is connected to the positive terminal of
R2
V 2.5 Cell 2, refer to Figure 7.
UV
A test option is provided to speed up device and battery
+ + +
V pack testing. By biasing Pin 13 above Pin 3 by 2.0 V, the
R1 H – R2 0.4 – 56,323 143,677 W internal logic is held in a reset state and both MOSFET
I 2.0x10 –6
H switches are turned on. Upon release, the logic becomes
Note that the Cell Selector has a maximum total series active and the cells are polled within 2.0 ms.
resistance of 200 Ω. This will have a minimal effect on the
Current Sensing
programmed limits if the total divider resistance is in excess
of 100 kΩ. Charge and discharge current limit protection can be
selectively added to the battery pack with the addition of a
Cell Voltage Balancing sense resistor. The resistors are placed in series with the
With series connected cells, successive charge and positive terminal of the battery pack and the cells. Refer to
discharge cycles can result in a significant difference in cell Figure 1.
voltage with a corresponding degradation of battery pack As the battery pack charges, Pins 9 and 10 sense the
capacity. Figure 4 illustrates the operation of an unbalanced voltage drop across RLim(chg). A charge current limit fault is

MC33347
detected if the voltage at Pin 10 exceeds Pin 9 by 18 mV. The exceeds Pin 16 by approximately 2.0 V, the Sense Enable
fault information is stored in a data latch and charge circuit will turn on discharge MOSFET Q2. Discharge current
MOSFET Q1 is turned off, disconnecting the battery pack sensing can be disabled by connecting Pin 4 to Pin 9.
from the charging source. As a result of the charge current The charge and discharge current protection circuits
fault, the battery pack is available for discharging only. The contain a built in response delay of 3.0 ms. This helps to
charge current limit is given by: prevent fault activation when the battery pack is subjected to
V pulsed currents during charging or discharging. An additional
I
Lim(chg)
+ R th(chg) + R 18 mV current sense delay can selectively be added as shown in
Figure 5.
Lim(chg) Lim(chg)
The charge current fault is reset by either disconnecting Charge Pump and MOSFET Switches
the battery pack from the charger, or by connecting a load to The MC33347 contains an on chip Charge Pump to
the battery pack. When the voltage on Pin 16 no longer ensure that the MOSFET switches are fully enhanced for
exceeds Pin 11 by approximately 2.0 V, the Sense Enable reduced power losses. An external reservoir capacitor
circuit will turn on charge MOSFET Q1. Charge current normally connects from the Charge Pump output to ground,
sensing can be disabled by connecting Pin 10 to Pin 9. Pins 15 and 16. The capacitor value is not critical and is
The discharge current limiting operates in a similar usually within the range of 10 nF to 100 nF. The Charge
manner. As the battery pack discharges, Pins 4 and 9 sense Pump output is regulated at 10.2 V allowing the use of
the voltage drop across RLim(dschg). A discharge current limit economical logic level MOSFETs in one and two cell
fault is detected if the voltage at Pin 4 is less than Pin 9 by applications. The main requirement in selecting a particular
50 mV. The fault information is stored in a data latch and type of MOSFET switch is to consider the desired
discharge MOSFET Q2 is turned off, disconnecting the on–resistance at the lowest anticipated operating voltage of
battery pack from the load. As a result of the discharge the battery pack. A table of small outline surface mount
current fault, the battery pack is available for charging only. devices is given in Figure 6. When using extremely low
The discharge current limit is given by: threshold MOSFETs, it may be desirable to disable the
V Charge Pump so that the maximum gate to source voltage is
I
Lim(dschg)
+ R th(dschg) + R 50 mV not exceeded. This is accomplished by connecting Pin 15 to
Pin 4. Application Figures 7 and 8 show a capacitor labeled
Lim(dschg) Lim(dschg)
CESD. This capacitor provides a path around the MOSFET
The discharge current fault is reset by either disconnecting
switches in the event of an electrostatic discharge.
the load from the battery pack, or by connecting the battery
pack to the charger. When the voltage on Pin 11 no longer
Figure 5. Additional Current Limit Delay
RLim(dschg) RLim(chg) RLim(dschg) RLim(chg)
Rdly Rdly
Cdly Cdly
9 10 9 10
4 4
Cell 2 Cell 2
MC33347 MC33347
3 3
Cell 1 Cell 1
16 16
Charge Delay Discharge Delay
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ÁÁÁÁÁ
ÁÁÁÁÁ
On–Resistance (Ω) versus Gate to Source Voltage (V)
Device
ÁÁÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁÁÁ
Type 2.5 V 3.0 V 4.0 V 5.0 V 6.0 V 7.5 V 9.0 V
ÁÁÁÁÁÁ
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MMFT3055VL – – – 0.120 Ω 0.115 Ω 0.108 Ω 0.100 Ω
ÁÁÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
MMDF3N03HD – 0.525 Ω 0.080 Ω 0.065 Ω 0.063 Ω 0.062 Ω 0.060 Ω
ÁÁÁÁÁÁ
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MMDF4N01HD 0.047 Ω 0.042 Ω 0.037 Ω 0.035 Ω 0.034 Ω 0.033 Ω See Note
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ÁÁÁÁÁ
MMSF5N02HD – 0.065 Ω 0.023 Ω 0.021 Ω 0.020 Ω 0.018 Ω 0.018 Ω
MMDF6N02HD 0.043 Ω 0.035 Ω 0.029 Ω 0.028 Ω 0.026 Ω 0.025 Ω 0.023 Ω

MC33347
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ MOSFET Switches
Outputs
Function
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ
Input Conditions
ÁÁÁÁ Circuit Operation Charge Discharge Charge
Cell
Balancing
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Cell Status Battery Pack Status Q1 Q2 Pump (See Note)
ÁÁÁ
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ÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Storage or Nominal Operation: Both Charge MOSFET Q1 and Discharge MOSFET On On Active Active
No current or voltage faults Q2 are on. The battery pack is available for
ÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
charging or discharging.
ÁÁÁ
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ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Charge Current Limit Fault: Charge MOSFET Q1 is latched off and the cells are On to Off On Active Active
VPin 10 ≥ (VPin 9 + 18 mV) disconnected from the charging source. Q1 will
for 3.0 ms
ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
remain in the off state as long as VPin 16 exceeds
VPin 11 by ≈ 2.0 V. The battery pack is available for
discharging.
ÁÁÁ ÁÁÁÁ
Charge Current Limit Reset:
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
VPin 16 – VPin 11 < 2.0 V
ÁÁÁÁ
The Sense Enable circuit will reset and turn on
charge MOSFET Q1 when VPin 16 no longer
exceeds VPin 11 by ≈ 2.0 V. This can be
Off to On On Active Active
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
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accomplished by either disconnecting the charger
from the battery pack, or by connecting a load to the
ÁÁÁ
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ÁÁÁÁ
battery pack.
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
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Charge Voltage Limit Fault: Charge MOSFET Q1 is latched off and the cells are On to Off On Active Active
VPin 8 ≥ 1.23 V for 1.0 s disconnected from the charging source. An internal
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
current source pull–up of 2.0 µA is applied to Pin 8
creating an input hysteresis voltage of VH with
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
divider resistors R1 and R2. The battery pack is
available for discharging.
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
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Charge Voltage Limit Reset: Charge MOSFET Q1 will turn on when the voltage Off to On On Active Active
VPin 8 < 1.23 V for 1.0 s across each cell falls sufficiently to overcome the
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input hysteresis voltage. This can be accomplished
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by applying a load to the battery pack.
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Discharge Current Limit Fault: Discharge MOSFET Q2 is latched off and the cells On On to Off Active Active
VPin 4 ≤ (VPin 9 – 50 mV) are disconnected from the load. Q2 will remain in
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ÁÁÁÁ
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for 3.0 ms the off state as long as VPin 11 exceeds VPin 16 by ≈
2.0 V. The battery pack is available for charging.
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
Discharge Current Limit Reset:
ÁÁÁÁ
VPin 11 – VPin 16 < 2.0 V
ÁÁÁÁ
discharge MOSFET Q2 when VPin 11 no longer
ÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
exceeds VPin 16 by ≈ 2.0 V. This can be
accomplished by either disconnecting the load from
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ÁÁÁÁ
the battery pack, or by connecting the battery pack
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to the charger.
ÁÁÁ
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Discharge Voltage Limit Fault: Discharge MOSFET Q2 is latched off, the cells are On On to Off Disabled Disabled
VPin 7 ≤ 1.23 V for three disconnected from the load, and the protection
ÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
consecutive 1.0 s samples circuit enters a low current sleepmode state. The
battery pack is available for charging.
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
Discharge Voltage Limit Reset:
ÁÁÁÁ
VPin 16 > (VPin 11 + 0.6 V)
ÁÁÁÁ
discharge MOSFET Q2 when VPin 16 exceeds
ÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
VPin 11 by 0.6 V. This can be accomplished by
connecting the battery pack to the charger.
ÁÁÁ
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ÁÁÁÁ
FAULTY CELL
Simultaneous Charge and
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
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Discharge Voltage Limit Faults:
VPin 8 ≥ 1.23 V for 1.0 s and
This condition can happen if there is a defective cell
in the battery pack. The protection circuit will
Cycles
Cell 1
Cycles
Cell 1
Cycles
Cell 1
Cycles
Cell 1
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remain in the sleepmode state until the battery pack Good Good Good Good
VPin 7 ≤ 1.23 V for three is connected to a charger. If Cell 2 is faulty and a
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consecutive 1.0 s samples charger is connected, the protection circuit will Disabled Disabled Disabled Disabled
cycle in and out of sleepmode. If Cell 1 is faulty Cell 1 Cell 1 Cell 1 Cell 1
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ÁÁÁÁ
ÁÁÁÁ (<1.5 V), the protection circuit logic will not function
and the battery pack cannot be charged.
NOTE: Cell balancing is not active when programmed for one cell operation.
Faulty Faulty Faulty Faulty

MC33347
Figure 7. Two Cell Smart Battery Pack
Current Sense Charge

Cell Program/ MC33347 Common 9 10 Current Limit
Test 13
Cell 2/VCC/ Charge/Discharge

Discharge Overcurrent Detector
Current Limit
Cell Voltage
4
RB2 80 6
Balance 2 Discharge Voltage R1
Cell 2
Floating Threshold
2
Cell 1/VC Over/Under
Cell Cell Voltage 7
Selector Detector Charge Voltage R2
3 Threshold
RB1 80 &
Balance 1 Reference 8
Cell 1
Cell Voltage R3
1 Return
Ground
5
16
Over/Under
Cell Voltage
Data Latch
Balancing
&
Amplifier
Control Logic
Sense
Enable
Ck Ck En
Charge/Discharge
Oscillator Charge Pump
Gate Drivers

Gate Drive Gate Drive Gate Drive
CO Charge
Discharge Switch
Switch Q2 Q1
CESD

MC33347
Current Sense Charge

Cell Program/ MC33347 Common 9 10 Current Limit
Test 13
Cell 2/VCC/ Charge/Discharge

Discharge Overcurrent Detector
Current Limit
Cell Voltage
4
80 6
Balance 2 Discharge Voltage R1
Floating Threshold
2
Cell 1/VC Over/Under
Cell Cell Voltage 7
Selector Detector Charge Voltage R2
3 Threshold
80 &
Balance 1 Reference 8
Cell 1
Cell Voltage R3
1 Return
Ground
5
16
Over/Under
Cell Voltage
Data Latch
Balancing
&
Amplifier
Control Logic
Sense
Enable
Ck Ck En
Charge/Discharge
Oscillator Charge Pump
Gate Drivers

Gate Drive Gate Drive Gate Drive
CO Charge
Discharge Switch
Switch Q2 Q1
CESD

MC33348
Product Preview
Circuit for One Cell
Battery Packs LITHIUM BATTERY
PROTECTION CIRCUIT
The MC33348 is a monolithic lithium battery protection circuit that is
designed to enhance the useful operating life of one cell rechargeable FOR
battery pack. Cell protection features consist of internally trimmed charge ONE CELL
and discharge voltage limits, discharge current limit detection with a
delayed shutdown, and a virtually zero current sleepmode state when the SMART BATTERY PACKS
cell is discharged. An additional feature includes an on–chip charge pump
for reduced MOSFET losses while charging or discharging a low cell SEMICONDUCTOR
voltage battery pack. This protection circuit requires a minimum number of TECHNICAL DATA
external components and is targeted for inclusion within the battery pack.
This MC33348 is available in standard and micro 8 lead surface mount
packages.
• Internally Trimmed Charge and Discharge Voltage Limits
• Discharge Current Limit Detection with Delayed Shutdown
• Virtually Zero Current Sleepmode State when Cells are Discharged
• Charge Pump for Reduced Losses with a Low Cell Voltage Battery Pack 8
• Dedicated for One Cell Applications 1
• Minimum Components for Inclusion within the Battery Pack

D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
Ordering Information shown on following page.
Typical One Cell Smart Battery Pack 8
DM SUFFIX
PLASTIC PACKAGE
VCC CASE 846A
7
(Micro–8)
Cell
Voltage
MC33348 PIN CONNECTIONS
Ground
3 Cell Voltage 1 8 Charge Pump

Output
Test
2 Test 2 7 VCC
Output Gate Drive Gate Drive Gate Drive Charge Gate
Output Output Common/ Ground 3 6
Drive Output
Discharge
Current Limit Discharge Gate 4 Charge Gate Drive
5 Common/Discharge
Drive Output
Current Limit
(Top View)

MC33348
Charge Charge Discharge Discharge
Overvoltage Overvoltage Undervoltage Current Limit Operating
Device Threshold (V) Hysteresis (mV) Threshold (V) Threshold (mV) Temperature Range Package
MC33348D–1 4.20 300 2.25 400 TA = –25° to +85°C SO–8
MC33348D–2 200
MC33348D–3 4.25 2.28 400
MC33348D–4 200
MC33348D–5 4.35 2.30 400
MC33348D–6 200
MC33348DM–1 4.20 2.25 400 Micro–8
MC33348DM–2 200
MC33348DM–3 4.25 2.28 400
MC33348DM–4 200
MC33348DM–5 4.35 2.30 400
MC33348DM–6 200
NOTE: Additional threshold limit options can be made available. Consult your local Motorola sales office for information.
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MAXIMUM RATINGS
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ÁÁÁÁÁ
ÁÁ
Input Voltage (Measured with Respect to Ground, Pin 3) VIR V
Cell Voltage (Pin 1) 7.5
Test (Pin 2) 7.5
Charge Gate Drive Common/Discharge Current Limit (Pin 5) ±20
ÁÁÁÁ
ÁÁÁÁÁÁÁ
VCC (Pin 7) 7.5
ÁÁÁÁ
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Thermal Resistance, Junction–to–Air
ÁÁÁÁ
ÁÁÁÁÁÁÁ
DM Suffix, Micro–8 Plastic Package, Case 846A
RθJA
240
°C/W
ÁÁÁÁ
ÁÁÁÁÁÁÁ
D Suffix, SO–8 Plastic Package, Case 751 178
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Operating Junction Temperature (Note 1) TJ –40 to +150 °C
ÁÁÁÁ
ÁÁÁÁÁÁÁ
NOTE: 1. Tested ambient temperature range for the MC33348:

MC33348
ELECTRICAL CHARACTERISTICS (VCC = 4.0 V, TA = 25°C, for min/max values TA is the operating junction temperature range
that applies (Note 1), unless otherwise noted.)
VOLTAGE SENSING
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Cell Charging Cutoff (Pin 1 to Pin 3)
Overvoltage Threshold, VCell Increasing Vth(OV) V
–1 Suffix – 4.20 –
–2 Suffix – 4.20 –
–3 Suffix – 4.25 –
–4 Suffix – 4.25 –
–5 Suffix – 4.35 –
–6 Suffix – 4.35 –
Overvoltage Hysteresis VCell Decreasing VH mV
–1 Suffix – 300 –
–2 Suffix – 300 –
–3 Suffix – 300 –
–4 Suffix – 300 –
ÁÁÁÁ
ÁÁÁÁ
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ÁÁÁÁ
ÁÁÁ
–5 Suffix – 300 –
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
–6 Suffix – 300 –
Cell Discharging Cutoff (Pin 1 to Pin 3, TA = 25°C)
Undervoltage Threshold, VCell Decreasing Vth(UV) V
–1 Suffix – 2.25 –
–2 Suffix – 2.25 –
–3 Suffix – 2.28 –
–4 Suffix – 2.28 –
ÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
–5 Suffix – 2.30 –
–6 Suffix – 2.30 –
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ÁÁÁÁÁ
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Input Bias Current During Cell Voltage Sample (Pin 1)
IIIB – 28 – µA
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
Cell Voltage Sampling Rate
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁ
ÁÁÁÁ
ÁÁÁ
CURRENT SENSING
t(smpl) – 1.0 – s
ÁÁÁÁ
Threshold Voltage
–1 Suffix
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Vth(dschg)
– 400 –
mV
–2 Suffix – 200 –
–3 Suffix – 400 –
–4 Suffix – 200 –
–5 Suffix – 400 –
–6 Suffix – 200 –
ÁÁÁÁ
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ÁÁÁÁÁ
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Delay Idly(dschg) – 3.0 – ms
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CHARGE PUMP
Output Voltage (Pin 8, RL ≥ 1010 Ω)
ÁÁÁÁ
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VO – 10.2 – V
TOTAL DEVICE
ÁÁÁÁ
ÁÁÁÁ
Average Cell Current
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ ICC
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
Operating (VCC = 4.0 V)
ÁÁÁÁ
ÁÁÁ – 20 – µA
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
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Sleepmode (VCC = 2.0 V) – 1.4 – nA
ÁÁÁÁ
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ÁÁÁ
Minimum Operating Cell Voltage for Logic and Gate Drivers VCC – 1.5 – V
NOTE: 1. Tested ambient temperature range for the MC33348:

MC33348
Figure 1. Charge and Discharge Figure 2. Discharge Current Limit

∆ V th(OV & UV) , THRESHOLD VOLTAGE CHANGE (%)
Threshold Voltage Change versus Temperature Threshold Voltage Change versus Temperature
1.2
∆ V th(dschg), CURRENT LIMIT THRESHOLD

16 VCC = 4.0 V
0.8
VOLTAGE CHANGE (%)

Maximum Threshold
Charge Limits 8.0
0.4
0 Typical Threshold Change Typical Threshold Change 0
–0.4
–8.0
–0.8
–16
–1.2
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
Figure 3. Gate Drive Output Voltage Figure 4. Gate Drive Output Voltage
versus Load Current versus Supply Voltage
12 12
VO , GATE DRIVE OUTPUT VOLTAGE (V)
VO , GATE DRIVE OUTPUT VOLTAGE (V)

TA = 25°C Pin 2 = Gnd
RL ≥ 1010 Ω
10 10 TA = 25°C
8.0 8.0
VCC = 4.15 V
6.0 VCC = 3.25 V 6.0
VCC = 2.35 V
4.0 4.0
0 0.2 0.4 0.6 0.8 1.0 0 1.0 2.0 3.0 4.0 5.0
IL, OUTPUT LOAD CURRENT (µA) VCC, SUPPLY VOLTAGE (V)
Figure 5. Charge Pump Output Voltage Figure 6. Supply Current

12 102
VO , CHARGE PUMP OUTPUT VOLTAGE (V)
Battery Pack
RL ≥ 1010 Ω Sleepmode Range
101
ICC , SUPPLY CURRENT (µ A)
11 Battery Pack
Operating Range
VCC = 4.15 V 100
In Regulation 3 2 1
10 10–1
1 – Battery pack unloaded without
10–2 discharge current limit fault.
VCC = 2.35 V 2 – Battery pack loaded without
9.0
Out of Regulation discharge current limit fault.
10–3
3 – Battery pack loaded or unloaded
with discharge current limit fault.
8.0 10–4
–40 –20 0 20 40 60 80 100 0 1.0 2.0 3.0 4.0 5.0

MC33348
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ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
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Outputs
MOSFET Switches Function
ÁÁÁÁÁÁÁÁÁ
Input Conditions
ÁÁÁÁÁÁÁÁÁ Cell Status ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Circuit Operation
Battery Pack Status
Charge
Q1
Discharge
Q2
Charge
Pump
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Storage or Nominal Operation: Both Charge MOSFET Q1 and Discharge MOSFET Q2 are on. On On Active
ÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
No current or voltage faults The battery pack is available for charging or discharging.
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Charge Voltage Limit Fault: Charge MOSFET Q1 is latched off and the cell is disconnected On to Off On Active
VPin 1 ≥ Vth(OV) for 1.0 s from the charging source. An internal current source pull–up is
ÁÁÁÁÁÁÁÁÁ
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applied to divider resistors R1 and R2 creating a hysteresis
ÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
voltage of VH. The battery pack is available for discharging.
Discharge current limit protection is disabled.
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
Charge Voltage Limit Reset:
ÁÁÁÁ
VPin 1 < (Vth(OV) – VH)
for 1.0 s
ÁÁÁÁ
ÁÁÁÁ
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Charge MOSFET Q1 will turn on when the voltage across the cell
falls sufficiently to overcome hysteresis voltage VH. This can be
accomplished by applying a load to the battery pack. Discharge
Off to On On Active
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
current limit protection is enabled.
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Discharge Current Limit Fault: Discharge MOSFET Q2 is latched off and the cell is On On to Off Active
ÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
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VPin 5 ≥ (VPin 1 + 400 mV) disconnected from the load. Q2 will remain in the off state as long
for 3.0 ms and as VPin 5 exceeds VPin 3 by ≈ 2.0 V. The battery pack is available
ÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
VPin 1 < (Vth(OV) – VH) for charging.
ÁÁÁÁÁÁÁÁÁ
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for 1.0 ms
ÁÁÁÁÁÁÁÁÁ
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Discharge Current Limit Reset: The Sense Enable circuit will reset and turn on discharge On Off to On Active
VPin 5 – VPin 3 < 2.0 V MOSFET Q2 when VPin 3 no longer exceeds VPin 5 by ≈ 2.0 V.
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
This can be accomplished by either disconnecting the load from
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
the battery pack, or by connecting the battery pack to the
charger.
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
Discharge Voltage Limit Fault:
ÁÁÁÁ
VPin 1 ≤ Vth(UV) for three
consecutive 1.0 s samples
ÁÁÁÁ
Discharge MOSFET Q2 is latched off, the cells are disconnected
from the load, and the protection circuit enters a low current
sleepmode state. The battery pack is available for charging.
On On to Off Disabled
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
VPin 3 > (VPin 5 + 0.6 V) ÁÁÁÁ
Discharge Voltage Limit Reset:
ÁÁÁÁ
ÁÁÁÁ
The Sense Enable circuit will reset and turn on discharge
MOSFET Q2 when VPin 3 exceeds VPin 5 by 0.6 V. This can be
On Off to On Active
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accomplished by connecting the battery pack to the charger.
ÁÁÁÁÁÁÁÁÁ
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FAULTY CELL
ÁÁÁÁÁÁÁÁÁ
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Discharge Voltage Limit Fault: This condition can happen if the cell is a defective (<1.5 V). The Disabled Disabled Disabled
VPin 1 ≤ 1.5 V protection circuit logic will not function and the battery pack
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
cannot be charged.

MC33348
C R
MC33348 7 VCC
Cell
Voltage
1
R1
Cell Voltage Over/Under
Sample Cell Voltage
Cell Switch Detector R2
&
Reference
R3
Ground
3
Test 2.0 k Discharge
Over/Under Overcurrent
2 Data Latch Detector
Ck &
Oscillator Control Logic
Ck Sense
En
Enable
Charge Pump Charge/Discharge

Gate Drivers

Output Output Common/
CO Charge
Switch Discharge
Discharge
Q1 Current Limit
Switch Q2
CESD
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Pin Symbol Description
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1 Cell Voltage This input is connected to the positive terminal of the cell for voltage monitoring. Internally, the Cell
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Voltage Sample Switch applies this voltage to a resistor divider where it is compared by the Cell Voltage
Detector to an internal reference.
ÁÁÁ
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2
ÁÁÁÁÁÁÁ
Test
This pin is normally not connected and is used in testing the protection IC. An active low at this input
resets the internal logic and turns on both MOSFET switches. Upon release, the logic becomes active and
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the cell voltage is sampled within 1.0 ms.
ÁÁÁ
ÁÁÁÁÁÁÁ
3 Ground This is the protection IC ground and all voltage ratings are with respect to this pin.
ÁÁÁ
ÁÁÁÁÁÁÁ
Output discharging.
ÁÁÁ
ÁÁÁÁÁÁÁ
5
ÁÁÁÁÁÁÁ
Charge Gate Drive
Common/Discharge
This is a multifunction pin that is used to monitor cell discharge current and to provide a gate turn–off
path for charge switch Q1. A discharge current limit fault is set when the battery pack load causes the
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Current Limit combined voltage drop of charge switch Q1 and discharge switch Q2 to exceed the discharge current limit
threshold voltage, Vth(dschg), with respect to Pin 3.
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6
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Charge Gate Drive
Output
This output connects to the gate of charge switch Q1 allowing it to enable or disable battery pack
charging.
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7 VCC This pin is the positive supply voltage for the protection IC.
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8 Charge Pump Output This is the charge pump output. A reservoir capacitor is connected from this pin to ground.

MC33348
INTRODUCTION
A functional description of the protection circuit blocks
The insatiable demand for smaller lightweight portable
follows. Refer to the detailed block diagram shown in
electronic equipment has dramatically increased the
Figure 7.
requirements of battery performance. Batteries are expected
to have higher energy densities, superior cycle life, be safe in Voltage Sensing
operation and environmentally friendly. To address these Voltage sensing is accomplished by the use of the Cell
high expectations, battery manufacturers have invested Voltage Sample Switch in conjunction with the Over/Under
heavily in developing rechargeable lithium–based cells. Voltage Detector and Reference block. The Sample Switch
Today’s most attractive chemistries include lithium–polymer, applies the cell voltage to the top resistor of an internal
lithium–ion, and lithium–metal. Each of these chemistries divider string. The voltage at each of the tap points is
require electronic protection in order to constrain cell sequentially polled and compared to an internal reference. If
operation to within the manufacturers limits. a limit has been exceeded, the result is stored in the
Rechargeable lithium–based cells require precise charge Over/Under Data Latch and Control Logic block. The Cell
and discharge termination limits for both voltage and current Voltage Sample Switch is gated on for a 1.0 ms period at a
in order to maximize cell capacity, cycle life, and to protect one second repetition rate. This low duty cycle sampling
the end user from a catastrophic event. The termination limits technique reduces the average load current that the divider
are not as well defined as with older non–lithium chemistries. presents across the cell, thus extending the useful battery
These limits are dependent upon a manufacturer’s particular pack capacity. The cell voltage limits are tested in the
lithium chemistry, construction technique, and intended following sequence:
application. Battery pack assemblers may also choose to
Figure 9. Cell Sensing Sequence
enhance cell capacity at the expense of cycle life. In order to
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address these requirements, six versions of the MC33348 Polling Time Tested
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protection circuit were developed. These devices feature Sequence (ms) Limit
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charge overvoltage protection, discharge current limit 1 0.5 Overvoltage
protection with delayed shutdown, low operating current, a
2 0.5 Undervoltage
virtually zero current sleepmode state, and requires few
external components to implement a complete one cell smart
battery pack. By incorporating this polling technique with a single
comparator and voltage divider, a significant reduction of
Operating Description circuitry and trim elements is achieved. This results in a
The MC33348 is specifically designed to be placed in the smaller die size, lower cost, and reduced operating current.
battery pack where it is continuously powered from a single
lithium cell. In order to maintain cell operation within specified Figure 10. Cell Voltage Limit Sampling
limits, the protection circuit senses both cell voltage and
discharge current, and correspondingly controls the state of From Cell Voltage
two N–channel MOSFET switches. These switches, Q1 and Cell Voltage
Q2, are placed in series with the negative terminal of the Cell Sample Switch
and the negative terminal of the battery pack. This Threshold +
Over/Under
configuration allows the protection circuit to interrupt the Cell Voltage Cell
appropriate charge or discharge path FET in the event that Detector Charge Voltage R2 Voltage
either a voltage threshold or the discharge current limit for the & Threshold
Reference –
cell has been exceeded.
Cell Voltage R3
Figure 8. Simplified One Cell Smart Battery Pack To
Return
Cell Negative
Terminal
The cell charge and discharge voltage limits are controlled

7 by the values selected for the internal resistor divider string
and the comparator input threshold. As the battery pack
reaches full charge, the Cell Voltage Detector will sense an
1 overvoltage fault condition when the cell exceeds the
designed overvoltage limit. The fault information is stored in
Cell a data latch and charge MOSFET Q1 is turned off,
MC33348
disconnecting the battery pack from the charging source. An
internal current source pull–up is then applied to lower tap of
the divider, creating a hysteresis voltage. As a result of an
3 overvoltage fault, the battery pack is available for
discharging only.
8 4 6 5 The overvoltage fault is reset by applying a load to the
battery pack. As the voltage across the cell falls below the
hysteresis level, charge MOSFET Q1 will turn on. The battery
Discharge Charge pack will now be available for charging or discharging.
MOSFET Q2 MOSFET Q1 As the load eventually depletes the battery pack charge,

MC33348
condition when the cell falls below the designed undervoltage The undervoltage fault is reset by applying charge current
limit. After three consecutive faults are detected, discharge to the battery pack. When the voltage on Pin 3 exceeds Pin 5
MOSFET Q2 is turned off, disconnecting the battery pack by 0.6 V, discharge MOSFET Q2 will turned on. The battery
from the load. The protection circuit will now enter a low pack will now be available for charging or discharging.
current sleepmode state drawing less than 10 nA, thus
Current Sensing
preventing any further cell discharging. As a result of the
undervoltage fault, the battery pack is available for charging Discharge current limit protection is internally provided by
only. The typical cutoff thresholds and hysteresis voltage are the MC33348. As the battery pack discharges, Pins 8 and 5
shown in Figure 11. sense the voltage drop across MOSFETs Q1 and Q2. A
discharge current limit fault is detected if the voltage at Pin 5
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Figure 11. Cutoff and Hysteresis Limits is greater than Pin 3 by 400 mV for –1, –3 and –5 suffix
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devices, or 200 mV for –2, –4 and –6 suffix devices. The fault
Charging Disharging information is stored in a data latch and discharge MOSFET
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Device Cutoff Hysteresis Cutoff
Q2 is turned off, disconnecting the battery pack from the load.
Suffix (V) (mV) (V)
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As a result of the discharge current fault, the battery pack is
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–1, –2 4.20 300 2.25 available for charging only. The discharge current limit is
–3, –4 4.25 300 2.28 given by:
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–5, –6
ÁÁÁÁÁ 4.35 300
The undervoltage logic is designed to automatically reset

2.30
I
Lim(dschg)
V
+ R th(dschg) + R
Lim(dschg) DS(on)Q1
V
th(dschg)
R )
DS(on)Q2
if less than three consecutive faults appear. This helps to The discharge current fault is reset by either disconnecting
prevent a premature disconnection of the load during high the load from the battery pack, or by connecting the battery
current pulses when the battery pack charge is close to pack to the charger. When the voltage on Pin 5 no longer
being depleted. exceeds Pin 3 by approximately 2.0 V, the Sense Enable
circuit will turn on discharge MOSFET Q2.
Figure 12. Additional Current Limit Delay Figure 13. VCC Decoupling
MC33348 C R
3 7
8 4 6 5 1
Cell
Cdly Rdly
MC33348
Discharge Delay 3
Power Supply Decoupling

MC33348
As previously stated in the voltage sensing operating reduced power losses. An external reservoir capacitor
description, charge MOSFET Q1 is held off during an normally connects from the Charge Pump output to ground,
overvoltage fault condition. When this condition is present, Pins 8 and 3. The capacitor value is not critical and is usually
the discharge current limit protection function is internally within the range of 10 nF to 100 nF. The Charge Pump output
disabled. This is required, since the voltage across Q1, in the is regulated at 10.2 V allowing the use of economical logic
off state, would exceed the current sense threshold. This level MOSFETs. The main requirement in selecting a
would cause Q2 to turn off as well, preventing both charging particular type of MOSFET switch is to consider the desired
and discharging of the cell. Discharge current limit protection on–resistance at the lowest anticipated operating voltage of
is enabled whenever an overvoltage fault is not present. the battery pack. A table of small outline surface mount
The discharge current protection circuit contain a built in devices is given in Figure 14. When using extremely low
response delay of 3.0 ms. This helps to prevent fault threshold MOSFETs, it may be desirable to disable the
activation when the battery pack is subjected to pulsed Charge Pump so that the maximum gate to source voltage is
currents during discharging. An additional current sense not exceeded. This is accomplished by connecting Pin 8 to
delay can be added as shown in Figure 12. If the battery pack Pin 7. Application Figure 7 show a capacitor labeled CESD.
is subjected to extremely high discharge current pulses or is This capacitor provides a path around the MOSFET switches
shorted, the VCC pin must be decoupled from the cell. This is in the event of an electrostatic discharge.
required so that the protection circuit will have sufficient
Testing
operating voltage during the load transient, to ensure turn off
of discharge MOSFET Q2. Figure 13 shows the placement of A test pin is provided in order to speed up device and
decoupling components. battery pack testing. By grounding Pin 2, the internal logic is
held in a reset state and both MOSFET switches are turned
Charge Pump and MOSFET Switches on. Upon release, the logic becomes active and the cell
The MC33348 contains an on chip Charge Pump to voltage is polled within 1.0 ms.
ensure that the MOSFET switches are fully enhanced for
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Device On–Resistance (Ω) versus Gate to Source Voltage (V)
Type
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2.5 V 3.0 V 4.0 V 5.0 V 6.0 V 7.5 V 9.0 V
0.120 Ω 0.115 Ω 0.108 Ω 0.100 Ω
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MMFT3055VL – – –
0.525 Ω 0.080 Ω 0.065 Ω 0.063 Ω 0.062 Ω 0.060 Ω
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MMDF3N03HD –
0.047 Ω 0.042 Ω 0.037 Ω 0.035 Ω 0.034 Ω 0.033 Ω
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MMDF4N01HD See Note
0.065 Ω 0.023 Ω 0.021 Ω 0.020 Ω 0.018 Ω 0.018 Ω
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MMSF5N02HD –
0.043 Ω 0.035 Ω 0.029 Ω 0.028 Ω 0.026 Ω 0.025 Ω 0.023 Ω
MMDF6N02HD

MC33362
Advance Information
High Voltage Switching
Regulator HIGH VOLTAGE
OFF–LINE
The MC33362 is a monolithic high voltage switching regulator that is
specifically designed to operate from a rectified 120 VAC line source. This SWITCHING REGULATOR
integrated circuit features an on–chip 500 V/2.0 A SenseFET power switch,
250 V active off–line startup FET, duty cycle controlled oscillator, current SEMICONDUCTOR
limiting comparator with a programmable threshold and leading edge TECHNICAL DATA
blanking, latching pulse width modulator for double pulse suppression, high
gain error amplifier, and a trimmed internal bandgap reference. Protective
features include cycle–by–cycle current limiting, input undervoltage lockout
with hysteresis, output overvoltage protection, and thermal shutdown. This
device is available in a 16–lead dual–in–line and wide body surface mount 16
packages.
• On–Chip 500 V, 2.0 A SenseFET Power Switch 1
• Rectified 120 VAC Line Source Operation DW SUFFIX

PLASTIC PACKAGE
• On–Chip 250 V Active Off–Line Startup FET CASE 751N
• Latching PWM for Double Pulse Suppression (SOP–16L)
• Cycle–By–Cycle Current Limiting

• Input Undervoltage Lockout with Hysteresis
• Output Overvoltage Protection Comparator
• Trimmed Internal Bandgap Reference
16
1
P SUFFIX
Simplified Application PLASTIC PACKAGE
CASE 648E
(DIP–16)
AC Input
Startup Input 1
PIN CONNECTIONS
Regulator Startup Power Switch
Output Mirror VCC Startup Input 1 16
Reg Drain
8 3 DC Output
UVLO Overvoltage
Protection VCC 3
6 Input
RT OVP 11
4 13
Gnd Gnd
PWM Latch 16 5 12
Osc
CT 7 Power Switch Overvoltage
S Driver RT 6 11
Drain Protection Input
Q
CT 7 10 Voltage Feedback
R Input
PWM
Regulator Output 8 9 Compensation
LEB
Ipk
Thermal Compensation (Top View)

9
EA 10 ORDERING INFORMATION
Voltage Operating
Feedback
Gnd 4, 5, 12, 13 Input
MC33362DW SOP–16L
This device contains 221 active transistors. TJ = –25° to +125°C
MC33362P DIP–16

MC33362
MAXIMUM RATINGS
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ÁÁÁ Rating Symbol Value Unit
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Drain Voltage ÁÁÁ
Power Switch (Pin 16)
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VDS 500 V
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Drain Current IDS 2.0 A
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Startup Input Voltage (Pin 1, Note 1) Vin V
Pin 3 = Gnd 250
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Pin 3 ≤ 1000 µF to ground 400
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Power Supply Voltage (Pin 3) VCC 40 V
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Input Voltage Range VIR –1.0 to Vreg V
Voltage Feedback Input (Pin 10)
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ÁÁÁÁ ÁÁÁ
Compensation (Pin 9)
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Overvoltage Protection Input (Pin 11)
RT (Pin 6)
CT (Pin 7)
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Thermal Characteristics °C/W
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P Suffix, Dual–In–Line Case 648E
Thermal Resistance, Junction–to–Air RθJA 80
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Thermal Resistance, Junction–to–Case RθJC 15
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(Pins 4, 5, 12, 13)
DW Suffix, Surface Mount Case 751N
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Thermal Resistance, Junction–to–Air RθJA 95
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Thermal Resistance, Junction–to–Case RθJC 15
(Pins 4, 5, 12, 13)
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Refer to Figures 15 and 16 for additional thermal
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information.
Operating Junction Temperature TJ – 25 to +150 °C
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Storage Temperature
Tstg – 55 to +150 °C
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies (Note 2), unless otherwise noted.)
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REGULATOR (Pin 8)
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Output Voltage (IO = 0 mA, TJ = 25°C) Vreg 5.5 6.5 7.5 V
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Line Regulation (VCC = 20 V to 40 V) Regline – 30 500 mV
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Load Regulation (IO = 0 mA to 10 mA) Regload – 44 200 mV
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Total Output Variation over Line, Load, and Temperature Vreg 5.3 – 8.0 V
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OSCILLATOR (Pin 7)
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Frequency fOSC kHz
CT = 390 pF
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TJ = 25°C (VCC = 20 V) 260 285 310
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TJ = Tlow to Thigh (VCC = 20 V to 40 V) 255 – 315
CT = 2.0 nF
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TJ = 25°C (VCC = 20 V) 60 67.5 75
TJ = Tlow to Thigh (VCC = 20 V to 40 V) 59 – 76
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Frequency Change with Voltage (VCC = 20 V to 40 V) ∆fOSC/∆V – 0.1 2.0 kHz
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ERROR AMPLIFIER (Pins 9, 10)
Voltage Feedback Input Threshold VFB 2.52 2.6 2.68 V
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ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Line Regulation (VCC = 20 V to 40 V, TJ = 25°C)
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Input Bias Current (VFB = 2.6 V)
Regline
IIB
–
–
0.6
20
5.0
500
mV
nA
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Open Loop Voltage Gain (TJ= 25°C) AVOL – 82 – dB
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Gain Bandwidth Product (f = 100 kHz, TJ= 25°C)
NOTES: 1. Maximum power dissipation limits must be observed.
2. Tested junction temperature range for the MC33362:
GBW – 1.0 – MHz

MC33362
ELECTRICAL CHARACTERISTICS (continued) (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies (Note 2), unless otherwise noted.)
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ERROR AMPLIFIER (Pins 9, 10)
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Output Voltage Swing V
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High State (ISource = 100 µA, VFB < 2.0 V) VOH 4.0 5.3 –
Low State (ISink = 100 µA, VFB > 3.0 V) VOL – 0.2 0.35
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OVERVOLTAGE DETECTION (Pin 11)
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Input Threshold Voltage Vth 2.47 2.6 2.73 V
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ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Input Bias Current (Vin = 2.6 V)
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IIB – 100 500 nA
PWM COMPARATOR (Pins 7, 9)
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Duty Cycle %
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Maximum (VFB = 0 V) DC(max) 48 50 52
Minimum (VFB = 2.7 V) DC(min) – 0 0
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POWER SWITCH (Pin 16)
Drain–Source On–State Resistance (ID = 200 mA) RDS(on) Ω
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
TJ = 25°C
ÁÁÁÁ
ÁÁÁ
TJ = Tlow to Thigh
–
–
4.4
–
6.0
12
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Drain–Source Off–State Leakage Current (VDS = 500 V) ID(off) – 0.2 50 µA
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Rise Time tr – 50 – ns
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Fall Time tf – 50 – ns
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OVERCURRENT COMPARATOR (Pin 16)
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ÁÁÁ
Current Limit Threshold (RT = 10 k) Ilim 0.7 0.9 1.1 A
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ÁÁÁ
STARTUP CONTROL (Pin 1)
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Peak Startup Current (Vin = 200 V) Istart mA
VCC = 0 V – 55 –
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
VCC = (Vth(on) – 0.2 V) – 26 –
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Off–State Leakage Current (Vin = 50 V, VCC = 20 V) ID(off) – 40 200 µA
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
UNDERVOLTAGE LOCKOUT (Pin 3)
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Startup Threshold (VCC Increasing) Vth(on) 11 14.5 18 V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Minimum Operating Voltage After Turn–On VCC(min) 7.5 9.5 11.5 V
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Startup (VCC = 10 V, Pin 1 Open) – 0.3 0.5
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Operating – 3.6 5.0
Figure 1. Oscillator Frequency Figure 2. Power Switch Peak Drain Current

versus Timing Resistor versus Timing Resistor
I PK, POWER SWITCH PEAK DRAIN CURRENT (A)
1.0 M 2.0
CT = 100 pF VCC = 20 V VCC = 20 V
f OSC , OSCILLATOR FREQUENCY (Hz)
TA = 25°C 1.5 CT = 1.0 µF

500 k CT = 200 pF
TA = 25°C
CT = 500 pF 1.0
200 k
CT = 1.0 nF 0.8
100 k 0.6
CT = 2.0 nF
50 k
0.4
CT = 5.0 nF
20 k Inductor supply voltage and inductance value are

CT = 10 nF
adjusted so that Ipk turn–off is achieved at 5.0 µs.
10 k 0.2
5.0 10 15 20 30 50 5.0 7.0 10 15 20 30 40 50
RT, TIMING RESISTOR (kΩ) RT, TIMING RESISTOR (kΩ)

MC33362
Figure 3. Oscillator Charge/Discharge Figure 4. Maximum Output Duty Cycle
Current versus Timing Resistor versus Timing Resistor Ratio
Dmax, MAXIMUM OUTPUT DUTY CYCLE (%)

1.0 70
RD/RT Ratio VCC = 20 V
VCC = 20 V
CHARGE/DISCHARGE CURRENT (mA)
Discharge Resistor CT = 2.0 nF

0.7 TA = 25°C
Pin 6 to Gnd TA = 25°C
I chg /I dscg , OSCILLATOR
60
0.5
0.3 50
0.2
40
0.15 RC/RT Ratio
Charge Resistor
Pin 6 to Vreg
0.1 30
5.0 10 15 20 30 50 1.0 2.0 3.0 5.0 7.0 10
RT, TIMING RESISTOR (kΩ) TIMING RESISTOR RATIO
Figure 5. Error Amp Open Loop Gain and Figure 6. Error Amp Output Saturation
Phase versus Frequency Voltage versus Load Current
100 0 0

VCC = 20 V
VO = 1.0 to 4.0 V θ, EXCESS PHASE (DEGREES) Source Saturation) Vref
80 RL = 5.0 MΩ 30 –1.0 (Load to Ground)
Gain CL = 2.0 pF
60 TA = 25°C 60 – 2.0
Phase
40 90
20 120 2.0 Sink Saturation VCC = 20 V

(Load to Vref) TA = 25°C
0 150 1.0
Gnd
– 20 180 0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 0.2 0.4 0.6 0.8 1.0
f, FREQUENCY (Hz) IO, OUTPUT LOAD CURRENT (mA)
Figure 7. Error Amplifier Small Signal Figure 8. Error Amplifier Large Signal
VCC = 20 V VCC = 20 V
AV = –1.0 AV = –1.0
1.80 V CL = 10 pF 3.00 V CL = 10 pF
TA = 25°C TA = 25°C
20 mV/DIV
0.5 V/DIV
1.75 V 1.75 V
1.70 V 0.50 V
1.0 µs/DIV 1.0 µs/DIV

MC33362
Figure 9. Regulator Output Voltage Figure 10. Peak Startup Current
Change versus Source Current versus Power Supply Voltage
∆ V reg, REGULATOR VOLTAGE CHANGE (mV) 0 60
VCC = 20 V VPin 1 = 200 V
I pk , PEAK STARTUP CURRENT (mA)

RT = 10 k TA = 25°C
– 20 CPIN 8 = 1.0 µF
TA = 25°C
40
– 40
20
– 60 Pulse tested with an on–time of 20 µs to 300 µs
at < 1.0% duty cycle. The on–time is adjusted at
Pin 1 for a maximum peak current out of Pin 3.
– 80 0
0 4.0 8.0 12 16 20 0 2.0 4.0 6.0 8.0 10 12 14
Ireg, REGULATOR SOURCE CURRENT (mA) VCC, POWER SUPPLY VOLTAGE (V)
Figure 11. Power Switch Drain–Source Figure 12. Power Switch

On–Resistance versus Temperature Drain–Source Capacitance versus Voltage
R DS(on), DRAIN–SOURCE ON–RESISTANCE (Ω )
COSS, DRAIN–SOURCE CAPACITANCE (pF)

10 200
ID = 200 mA VCC = 20 V
TA = 25°C
8.0
150
6.0
100
4.0
50
2.0
Pulse tested at 5.0 ms with < 1.0% duty cycle
so that TJ is as close to TA as possible. COSS measured at 1.0 MHz with 50 mVpp.
0 0
–50 –25 0 25 50 75 100 125 150 0.5 5.0 50 500
TA, AMBIENT TEMPERATURE (°C) VDS, DRAIN–SOURCE VOLTAGE (V)
Figure 14. DW and P Suffix Transient

Figure 13. Supply Current versus Supply Voltage Thermal Resistance
4.0 100
CT = 390 pF L = 12.7 mm of 2.0 oz.
Rθ JA , THERMAL RESISTANCE
copper. Refer to Figures

I CC, SUPPLY CURRENT (mA)
3.2
15 and 16.
CT = 2.0 nF
2.4
10
1.6
RT = 10 k
Pin 1 = Open
0.8 Pin 4, 5, 10, 11,
12, 13 = Gnd
TA = 25°C
0 1.0
0 10 20 30 40 0.01 0.1 1.0 10 100
VCC, SUPPLY VOLTAGE (V) t, TIME (s)

MC33362
Figure 15. DW Suffix (SOP–16L) Thermal Resistance and Figure 16. P Suffix (DIP–16) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length Maximum Power Dissipation versus P.C.B. Copper Length
ÎÎÎ
ÎÎÎ
100 2.8 100 5.0
P D , MAXIMUM POWER DISSIPATION (W)

Printed circuit board heatsink example
ÎÎÎ
ÎÎÎ
90 2.4

Rθ JA , THERMAL RESISTANCE
80 2.0 oz 4.0
ÎÎÎÎÎÎ
Copper
80 2.0
Printed circuit board heatsink example
RθJA
ÎÎÎÎÎÎ
L 3.0 mm
1.6 60 3.0
70 2.0 oz Graphs represent symmetrical layout
ÎÎÎÎÎÎ
L
Copper
60 1.2 40 2.0
L 3.0 mm
Graphs represent symmetrical layout
50 0.8
RθJA 20 PD(max) for TA = 70°C 1.0
40 0.4
30 0 0 0
0 10 20 30 40 50 0 10 20 30 40 50
L, LENGTH OF COPPER (mm) L, LENGTH OF COPPER (mm)
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
Pin
ÁÁÁÁÁÁ
Function
Description
1 Startup Input This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the drain
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and charges
an external capacitor that connects from the VCC pin to ground.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
2 – This pin has been omitted for increased spacing between the rectified AC line voltage on Pin 1 and
the VCC potential on Pin 3.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3 VCC This is the positive supply voltage input. During startup, power is supplied to this input from Pin 1.
When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is supplied
ÁÁÁÁÁ
ÁÁÁÁÁÁ
from an auxiliary transformer winding.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
4, 5, 12, 13 Ground These pins are the control circuit grounds. They are part of the IC lead frame and provide a thermal
path from the die to the printed circuit board.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
6 RT Resistor RT connects from this pin to ground. The value selected will program the Current Limit
Comparator threshold and affect the Oscillator frequency.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
7 CT Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor RT,
programs the Oscillator frequency.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
8 Regulator Output This 6.5 V output is available for biasing external circuitry. It requires an external bypass capacitor
of at least 1.0 µF for stability.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9 Compensation This pin is the Error Amplifier output and is made available for loop compensation. It can be used as
an input to directly control the PWM Comparator.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10 Voltage Feedback
Input
This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter
ÁÁÁÁÁ
ÁÁÁÁÁÁ
output.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
11 Overvoltage This input provides runaway output voltage protection due to an external component or connection
Protection Input failure in the control loop feedback signal path. It has a 2.6 V threshold and normally connects
ÁÁÁÁÁ
ÁÁÁÁÁÁ
through a resistor divider to the converter output, or to a voltage that represents the converter
output.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
14, 15
– These pins have been omitted for increased spacing between the high voltages present on the
Power Switch Drain, and the ground potential on Pins 12 and 13.
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
16 Power Switch
Drain
This pin is designed to directly drive the converter transformer and is capable of switching a
maximum of 500 V and 2.0 A.

MC33362
AC Input
Startup Input 1
Startup
Current
Mirror Control VCC
Regulator Output Band Gap
6.5 V 8 Regulator 3
UVLO DC Output
I 2.25 I Overvoltage
14.5 V/ Protection
6 9.5 V Input
RT
4I 11
OVP 2.6 V
Oscillator 16
CT 7 PWM Latch
Power Switch
S Driver Drain
Q
R
PWM
Comparator
Leading Edge
Blanking
9.0
Thermal
Compensation
Shutdown Current Limit
Comparator 450
9
2.6 V
270 µA Error 10
Amplifier
Voltage
Gnd 4, 5, 12, 13 Feedback Input
Figure 18. Timing Diagram
2.6 V
Capacitor CT
Compensation 0.6 V
Oscillator Output
PWM
Comparator
Output
PWM Latch
Q Output Current Limit
Propagation
Power Switch Delay
Gate Drive
Current
Leading Edge Limit
Blanking Input
Threshold
(Power Switch
Drain Current)
Normal PWM Operating Range Output Overload

MC33362
Introduction The formula for the charge/discharge current along with
The MC33362 represents a new higher level of integration the oscillator frequency are given below. The frequency
by providing all the active high voltage power, control, and formula is a first order approximation and is accurate for CT
protection circuitry required for implementation of a flyback or values greater than 500 pF. For smaller values of CT, refer to
forward converter on a single monolithic chip. This device is Figure 1. Note that resistor RT also programs the Current
designed for direct operation from a rectified 120 VAC line Limit Comparator threshold.
source and requires a minimum number of external
components to implement a complete converter. A
+ 5.4 [
I
ń
chg dscg
chgńdscg
description of each of the functional blocks is given below, I R f
T 4C
T
and the representative block and timing diagrams are shown
in Figures 17 and 18.
PWM Comparator and Latch
Oscillator and Current Mirror The pulse width modulator consists of a comparator with
The oscillator frequency is controlled by the values the oscillator ramp voltage applied to the non–inverting input,
selected for the timing components RT and CT. Resistor RT while the error amplifier output is applied into the inverting
programs the oscillator charge/discharge current via the input. The Oscillator applies a set pulse to the PWM Latch
Current Mirror 4 I output, Figure 3. Capacitor CT is charged while CT is discharging, and upon reaching the valley
and discharged by an equal magnitude internal current voltage, Power Switch conduction is initiated. When CT
source and sink. This generates a symmetrical 50 percent charges to a voltage that exceeds the error amplifier output,
duty cycle waveform at Pin 7, with a peak and valley the PWM Latch is reset, thus terminating Power Switch
threshold of 2.6 V and 0.6 V respectively. During the conduction for the duration of the oscillator ramp–up period.
discharge of CT, the oscillator generates an internal blanking This PWM Comparator/Latch combination prevents multiple
pulse that holds the inverting input of the AND gate Driver output pulses during a given oscillator clock cycle. The timing
high. This causes the Power Switch gate drive to be held in a diagram shown in Figure 18 illustrates the Power Switch duty
low state, thus producing a well controlled amount of output cycle behavior versus the Compensation voltage.
deadtime. The amount of deadtime is relatively constant with
respect to the oscillator frequency when operating below Current Limit Comparator and Power Switch
1.0 MHz. The maximum Power Switch duty cycle at Pin 16 The MC33362 uses cycle–by–cycle current limiting as a
can be modified from the internal 50% limit by providing an means of protecting the output switch transistor from
additional charge or discharge current path to CT, Figure 19. overstress. Each on–cycle is treated as a separate situation.
In order to increase the maximum duty cycle, a discharge Current limiting is implemented by monitoring the output
current resistor RD is connected from Pin 7 to ground. To switch current buildup during conduction, and upon sensing
decrease the maximum duty cycle, a charge current resistor an overcurrent condition, immediately turning off the switch
RC is connected from Pin 7 to the Regulator Output. Figure 4 for the duration of the oscillator ramp–up period.
shows an obtainable range of maximum output duty cycle The Power Switch is constructed as a SenseFET allowing
versus the ratio of either RC or RD with respect to RT. a virtually lossless method of monitoring the drain current. It
consists of a total of 3770 cells, of which 50 are connected to
a 9.0 Ω ground–referenced sense resistor. The Current
Figure 19. Maximum Duty Cycle Modification Sense Comparator detects if the voltage across the sense
resistor exceeds the reference level that is present at the
inverting input. If exceeded, the comparator quickly resets
Current the PWM Latch, thus protecting the Power Switch. The
Mirror current limit reference level is generated by the 2.25 I output
Regulator Output
of the Current Mirror. This current causes a reference voltage
1.0 8 to appear across the 450 Ω resistor. This voltage level, as
2.25 I
well as the Oscillator charge/discharge current are both set
I
RC
by resistor RT. Therefore when selecting the values for RT
6 Current
Limit and CT, RT must be chosen first to set the Power Switch peak
RT Reference drain current, while CT is chosen second to set the desired
4I Oscillator frequency. A graph of the Power Switch peak drain
current versus RT is shown in Figure 2 with the related
Oscillator
ǒǓ
CT 7 Blanking formula below.
RD Pulse
+ 12.3
R
T – 1.115
I 1000
PWM pk
Comparator

MC33362
The Power Switch is designed to directly drive the converter Startup Control
transformer and is capable of switching a maximum of 500 V An internal Startup Control circuit with a high voltage
and 2.0 A. Proper device voltage snubbing and heatsinking enhancement mode MOSFET is included within the
are required for reliable operation. MC33362. This circuitry allows for increased converter
A Leading Edge Blanking circuit was placed in the current efficiency by eliminating the external startup resistor, and its
sensing signal path. This circuit prevents a premature reset associated power dissipation, commonly used in most
of the PWM Latch. The premature reset is generated each off–line converters that utilize a UC3842 type of controller.
time the Power Switch is driven into conduction. It appears as Rectified ac line voltage is applied to the Startup Input, Pin 1.
a narrow voltage spike across the current sense resistor, and This causes the MOSFET to enhance and supply internal
is due to the MOSFET gate to source capacitance, bias as well as charge current to the VCC bypass capacitor
transformer interwinding capacitance, and output rectifier that connects from Pin 3 to ground. When VCC reaches the
recovery time. The Leading Edge Blanking circuit has a UVLO upper threshold of 14.5 V, the IC commences
dynamic behavior in that it masks the current signal until the operation and the startup MOSFET is turned off. Operating
Power Switch turn–on transition is completed. The current bias is now derived from the auxiliary transformer winding,
limit propagation delay time is typically 233 ns. This time is and all of the device power is efficiently converted down from
measured from when an overcurrent appears at the Power the rectified ac line.
Switch drain, to the beginning of turn–off. The startup MOSFET will provide an initial peak current of
55 mA, Figure 10, which decreases rapidly as VCC and the
Error Amplifier
die temperature rise. The steady state current will self limit in
An fully compensated Error Amplifier with access to the
the range of 12 mA with VCC shorted to ground. The startup
inverting input and output is provided for primary side voltage
MOSFET is rated at a maximum of 250 V with VCC shorted to
sensing, Figure 17. It features a typical dc voltage gain of 82
ground, and 400 V when charging a VCC capacitor of
dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of
1000 µF or less.
phase margin, Figure 5. The noninverting input is internally
biased at 2.6 V ±3.1% and is not pinned out. The Error Regulator
Amplifier output is pinned out for external loop compensation A low current 6.5 V regulated output is available for
and as a means for directly driving the PWM Comparator. biasing the Error Amplifier and any additional control system
The output was designed with a limited sink current capability circuitry. It is capable of up to 10 mA and has short–circuit
of 270 µA, allowing it to be easily overridden with a pull–up protection. This output requires an external bypass capacitor
resistor. This is desirable in applications that require of at least 1.0 µF for stability.
secondary side voltage sensing, Figure 20. In this
application, the Voltage Feedback Input is connected to the Thermal Shutdown and Package
Regulator Output. This disables the Error Amplifier by placing Internal thermal circuitry is provided to protect the Power
its output into the sink state, allowing the optocoupler Switch in the event that the maximum junction temperature is
transistor to directly control the PWM Comparator. exceeded. When activated, typically at 155°C, the Latch is
forced into a ‘reset’ state, disabling the Power Switch. The
Overvoltage Protection Latch is allowed to ‘set’ when the Power Switch temperature
An Overvoltage Protection Comparator is included to falls below 145°C. This feature is provided to prevent
eliminate the possibility of runaway output voltage. This catastrophic failures from accidental device overheating. It is
condition can occur if the control loop feedback signal path is not intended to be used as a substitute for proper
broken due to an external component or connection failure. heatsinking.
The comparator is normally used to monitor the primary side The MC33362 is contained in a heatsinkable plastic
VCC voltage. When the 2.6 V threshold is exceeded, it will dual–in–line package in which the die is mounted on a
immediately turn off the Power Switch, and protect the load special heat tab copper alloy lead frame. This tab consists of
from a severe overvoltage condition. This input can also be the four center ground pins that are specifically designed to
driven from external circuitry to inhibit converter operation. improve thermal conduction from the die to the circuit board.
Figures 15 and 16 show a simple and effective method of
Undervoltage Lockout
utilizing the printed circuit board medium as a heat dissipater
An Undervoltage Lockout comparator has been
by soldering these pins to an adequate area of copper foil.
incorporated to guarantee that the integrated circuit has
This permits the use of standard layout and mounting
sufficient voltage to be fully functional before the output stage
practices while having the ability to halve the junction to air
is enabled. The UVLO comparator monitors the VCC voltage
thermal resistance. The examples are for a symmetrical
at Pin 3 and when it exceeds 14.5 V, the reset signal is
layout on a single–sided board with two ounce per square
removed from the PWM Latch allowing operation of the
foot of copper. Figure 22 shows a practical example of a
Power Switch. To prevent erratic switching as the threshold is
printed circuit board layout that utilizes the copper foil as a
crossed, 5.0 V of hysteresis is provided.
heat dissipater. Note that a jumper was added to the layout
from Pins 8 to 10 in order to enhance the copper area near
the device for improved thermal conductivity. The application
circuit requires two ounce copper foil in order to obtain
20 watts of continuous output power at room temperature.

MC33362
Figure 20. 20 W Off–Line Converter
F1
1.0 A D4 D3 C1 C5 R6 C6
47 4.0 nF 100 k 47 pF
1N4004 1.0 W
92 to 138 D2 D1 R7
Vac Input D5 2.2 k
1 MUR 1.0 W
160
D6 D7 L1 5.05 V/4.0 A
Startup R5 MUR T1 MBR C9 C10 5.0 µH DC Output
Mirror 3 39 120 2515L 330 330
Reg
C4 8 C2 R8
1.0 UVLO 10 220
14.5 V/ R4 R9
6 9.5 V C8
11 16 k 330 1 2.80 k
R1 C11
8.2 k OVP R3 C7 220
2.6 V 2.7 k 2
PWM Latch 100 nF
Osc 16 IC2
C3 7 MOC 3
1 C12
1.5 nF 8103 IC3
S Driver 1.0
TL431B 2
Q
PWM R R10
2.74 k
5
LEB
ILimit
Thermal 4
9
R2
2.6 V 2.7 k
270 µA EA 10
4, 5, 12, 13 IC1 MC33362
Figure 21. Converter Test Data
Test Conditions Results

Line Regulation Vin = 92 Vac to 138 Vac, IO 4.0 A ∆ = 1.0 mV
Load Regulation Vin = 115 Vac, IO = 1.0 A to 4.0 A ∆ = 9.0 mV
Output Ripple Vin = 115 Vac, IO = 4.0 A Triangular = 10 mVpp
Spike = 60 mVpp
Efficiency Vin = 115 Vac, IO = 4.0 A 78.4%
This data was taken with the components listed below mounted on the printed circuit board shown in Figure 22.
For high efficiency and small circuit board size, the Sanyo Os–Con capacitors are recommended for C8, C9, C10 and C11.
C8, C9, C10 = Sanyo Os–Con #6SA330M, 330 µF 6.3 V.
C11 = Sanyo Os–Con #10SA220M, 220 µF 10 V.
D7 = MBR2515L mounted on Aavid #592502B03400 heatsink.
L1 = Coilcraft S5088–A, 5.0 µH, 0.11 Ω.
T1 = Coilcraft S5069–A
Primary: 58 turns of # 26 AWG, Pin 1 = start, Pin 8 = finish.
Two layers 0.002″ Mylar tape.
Secondary: 4 turns of # 18 AWG, 2 strands bifiliar wound, Pin 5 = start, Pin 4 = finish.
Auxiliary: 10 turns of # 26 AWG wound in center of bobbin, Pin 2 = start, Pin 7 = finish.
Gap: 0.014″ total for a primary inductance (LP) of 330 µH.
Core and Bobbin: Coilcraft PT1950, E187, 3F3 material.

MC33362
Figure 22. Printed Circuit Board and Component Layout
(Circuit of Figure 20)
Caution! DC Output
High
Voltages C4
IC3
C3
J1 C12
R10
R1
R9
D1 R2 R3
R3 IC2
D2 C7 C11
F1 IC1
R8 L1
AC R4
Line
C2 R5
Input
D6 C10
D3
D4
D5 C9
R7
T1
R6
C1
D7

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Volumes

Alphanumeric Index and

I Amplifiers and Comparators 2

I Power Supply Circuits 3

I Power/Motor Control Circuits 4

II Consumer Electronic Circuits 9

II Automotive Electronic Circuits 10

II Other Analog Circuits 11

II I Tape and Reel Options 12

II Quality and Reliability Assurance 14

II Applications and Product Literature 15

CHAPTER 3 CHAPTER 7 MC13283

LM307 MC3372A MC33344

New Product Literature (Referenced)

AN454A AN1044 AN1544

Not Recommended For New Designs

AM26LS31 MC3450 MC3485

How to reach us:

JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

Mfax: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

Mfax is a trademark of Motorola, Inc.

Mfax – Touch–Tone Fax

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Motorola SPS World Marketing Internet Server

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C–QUAM, Designer’s, Easy Switcher, GreenLine, MDTL, MECL, MECL 10,000,

MOTOROLA ANALOG IC DEVICE DATA 1–1

1–2 MOTOROLA ANALOG IC DEVICE DATA

* = See Communications Device Data (DL136).

MOTOROLA ANALOG IC DEVICE DATA 1–3

1–4 MOTOROLA ANALOG IC DEVICE DATA

MOTOROLA ANALOG IC DEVICE DATA 1–5

1–6 MOTOROLA ANALOG IC DEVICE DATA

MOTOROLA ANALOG IC DEVICE DATA 1–7

1–8 MOTOROLA ANALOG IC DEVICE DATA

MOTOROLA ANALOG IC DEVICE DATA 1–9

1–10 MOTOROLA ANALOG IC DEVICE DATA

MOTOROLA ANALOG IC DEVICE DATA 1–11

1–12 MOTOROLA ANALOG IC DEVICE DATA

MOTOROLA ANALOG IC DEVICE DATA 1–13

1–14 MOTOROLA ANALOG IC DEVICE DATA

MOTOROLA ANALOG IC DEVICE DATA 1–15

MOTOROLA ANALOG IC DEVICE DATA 2–1

Table 1. Single Operational Amplifiers

2–2 MOTOROLA ANALOG IC DEVICE DATA

MOTOROLA ANALOG IC DEVICE DATA 2–3

Table 3. Quad Operational Amplifiers

2–4 MOTOROLA ANALOG IC DEVICE DATA

High Frequency Amplifiers

Table 4. High Frequency Amplifier Specifications

MOTOROLA ANALOG IC DEVICE DATA 2–5

2–6 MOTOROLA ANALOG IC DEVICE DATA

Table 8. Dual Comparators

Table 9. Quad Comparators

MOTOROLA ANALOG IC DEVICE DATA 2–7

CASE 626 CASE 646 CASE 648, 648C

CASE 751 CASE 751A CASE 751B

CASE 751G CASE 904

2–8 MOTOROLA ANALOG IC DEVICE DATA

MOTOROLA ANALOG IC DEVICE DATA 2–9

RELATED APPLICATION NOTES

AN587 Analysis and Design of the Op Amp Current Source . . . . . . . . . . . . . . . MC1741C