energies

Article
A Novel High Controllable Voltage Gain Push-Pull
Topology for Wireless Power Transfer System
Qichang Duan *, Yanling Li, Xin Dai and Tao Zou
School of Automation, Chongqing University, 174 Shazheng Street, Shapingba District, Chongqing 400030,
China; liyanling1978@gmail.com (Y.L.); daixin@cqu.edu.cn (X.D.); 20161301007@cqu.edu.cn (T.Z.)
* Correspondence: duanqichang1953@gmail.com; Tel.: +86-23-6510-6188

Academic Editor: Chunhua Liu

Received: 2 February 2017; Accepted: 29 March 2017; Published: 1 April 2017

Abstract: Wireless Power Transfer (WPT) is commonly used to transmit power from a transmitting
coil to various movable power devices. In the WPT system, due to a resonant tank inherent
characteristic, the system cannot achieve a high output voltage gain. This paper proposes a novel
current-fed push–pull circuit to realize high output voltage gain by adding a bi-directional switch
between the resonant network and inverter. To obtain a high voltage gain, this paper proposes energy
storage and energy injection mode to realize an energy boost function. A duty cycle control method
for mode switching is also proposed. The proposed method allows the converter to operate with a
variable voltage gain over a wide range with high efficiency. Experimental validation shows that the
system gain of a proposed circuit can achieve a variable gain from 2 to 7 of which the converter can
be two times higher than the classical system with the same condition.

Keywords: wireless power transfer; push–pull circuit; voltage gain

1. Introduction
The Wireless Power Transfer (WPT) system as a novel technology can realize power wireless
transmission from power supply to electrical equipment with the aid of magnetic coupling. With
its rapid development, more and more applications have appeared in electrical vehicles, biomedical
implants and cell phone areas [1–6].
More and more applications in WPT technology require low DC voltage input and high voltage
output. These applications include the Photovoltaic (PV) system, battery power supply system and
Universal Serial Bus (USB) powered devices. However, it is not easy for the WPT system to obtain
high voltage gain according to the following reasons—first, due to the WPT system being a weakly
coupling system with very low coupling coefficient k (normally below 0.2) [7,8] and the coupling
coefficient of transformer can almost reach 1. The second reason is the inherent characteristic of
the resonant network. There are four fundamental resonant topologies SS, SP, PS, and PP (S and P
denotes series and parallel topology, respectively). Series resonant network exhibits voltage source
characteristics that cannot obtain a high voltage gain. The parallel resonant network exhibits current
source characteristics that obtain high voltage gain on the light load condition. However, for heavy
load conditions, it still cannot obtain high voltage gain. Furthermore, its reflecting impedance will
bring relatively large frequency drift, which may cause a large reduction in output power [9,10]. For
the same reason, composite resonant networks such as Inductor Capacitor Inductor (LCL), Inductor
Capacitor Capacitor (LCC), and Capacitor Inductor Capacitor (CLC), which are combinations of the
series and resonant topology, cannot reach high voltage gain. Reference [11] analyzes wireless charging
circuit characteristics under hybrid compensation topology. The analysis results show that the output
voltage gain is below three in hybrid compensation topology.

Energies 2017, 10, 474; doi:10.3390/en10040474 www.mdpi.com/journal/energies

Energies 2017, 10, 474 2 of 13

Energies 2017, 10, 474 2 of 13

To achieve high output voltage gain, the classical method is implemented by placing an additional
To achieve high output voltage gain, the classical method is implemented by placing an
Boost converter
additional at the
Boost primary
converter at or
thesecondary
primary orside. However,
secondary side.the added Boost
However, converter
the added Boostwill increase
converter
thewill
volume
increaseandthe weight
volume ofand
the weight
whole of system [12,13],
the whole and[12,13],
system make the andsystem
make the complicated to control.
system complicated
There are few papers related with voltage gain improvement. Aiming at voltage
to control. There are few papers related with voltage gain improvement. Aiming at voltage gain gain optimization and
control, Reference [14] proposes a uniform voltage gain control method. This
optimization and control, Reference [14] proposes a uniform voltage gain control method. This method is implemented
by method
control system operating
is implemented byfrequency.
control systemHowever, the method
operating frequency.only aims at the
However, improving
method theonlyrobustness
aims at
against misalignment.
improving Reference
the robustness [15]
against proposes a detached
misalignment. Referencemagnetic core to
[15] proposes improve the
a detached voltage
magnetic gain
core
method. The obtained
to improve the voltage voltage gain is 0.83.
gain method. Reference
The obtained [16] proposes
voltage an Reference
gain is 0.83. S/SP topology converter
[16] proposes an to
S/SPconstant
obtain topologyvoltage
converter
gain.toHowever,
obtain constant voltage
the voltage gaingain.
cannotHowever, the and
be adjusted voltage
willgain cannot
be very be
sensitive
adjusted and
to frequency will
drift onbethevery
highsensitive to frequency drift on the high gain condition.
gain condition.
In In order
order to to obtain
obtain a high
a high andcontrollable
and controllableoutput
outputvoltage
voltagegain
gainWPT
WPT system,
system, this
this paper
paper proposes
proposes a
a novel current-fed push–pull converter at the primary side. A pair
novel current-fed push–pull converter at the primary side. A pair of Insulated Gate Bipolar of Insulated Gate Transistor
Bipolar
Transistor
(IGBT) switches,(IGBT)
which switches,
act as awhich act asswitch,
directional a directional
is added switch, is of
in front added in front network
the resonant of the resonant
to isolate
network to isolate the inverter and resonant network. An energy storage
the inverter and resonant network. An energy storage and injection switching mode is proposed to and injection switching
modethe
control is proposed to control
energy flowing intothe
theenergy flowing
resonant into the
network. resonant network.
A switching duty cycleA switching
regulation duty cycle is
method
regulation method is also proposed to reach high voltage gain.
also proposed to reach high voltage gain.
2. High
2. High Output
Output GainPush–Pull
Gain Push–PullCircuit
Circuit
The proposed high output gain push–pull circuit is shown in Figure 1. Compared with
The proposed high output gain push–pull circuit is shown in Figure 1. Compared with traditional
traditional push–pull circuits, the proposed circuit adds two additional switches S3 and S4 to form a
push–pull circuits, the proposed circuit adds two additional switches S3 and S4 to form a bi-directional
bi-directional switch. At the primary side, a DC power supply is a series with an inductor to form a
switch. At the primary side, a DC power supply is a series with an inductor to form a quasi-current
quasi-current source. A push–pull transformer including L1 and L2 is utilized to divide the DC
source. A push–pull transformer including L1 and L2 is utilized to divide the DC current in half,
current in half, so that the current flowing into the resonant tank is approximately a square
so waveform
that the current flowing into the resonant tank is approximately a square waveform with half the
with half the magnitude of the input DC current. The primary side uses two main
magnitude of the input
switches (S1 and S2) with DCa current.
common The groundprimary
and twoside uses two
auxiliary main switches
switches (S3 and S4(S 1 and
) in S2with
series ) witha a
common ground resonant
parallel-tuned and two tank,
auxiliary
whichswitches
consists(Sof
3 and S4 ) in series
a resonant withCaP, parallel-tuned
capacitor resonant
a resonant inductor tank,
LP and
which consists of a resonant capacitor C , a resonant inductor L and equivalent
equivalent series resistance RP. The secondary side comprises a parallel resonant tank, which
P P series resistance
RP .consists
The secondary side comprises
of a resonant inductor LS,aequivalent
parallel resonant tank, which
series resistance consists
RS, and of a resonant
a resonant CS. WithLS ,
capacitorinductor
equivalent series
the rectifier bridge (D1–D4) R
resistance S , and
and a resonant
Inductor capacitor
Capacitor CS . network,
(LC) filter With theAC rectifier
energybridge (D1 –D4 ) to
is transformed and
Inductor Capacitor
DC output filter network, AC energy is transformed to DC output to the load R.
(LC) R.
to the load

Id Lf
LDC
D1
A D2
L1 L2

B CP LP LS CS R
Vin Cf
S3 S4

RP RS
D3 D4
S1 S2

Figure 1. High controllable voltage gain push–pull topology.

Figure 1. High controllable voltage gain push–pull topology.

Aiming at voltage gain promotion, this paper proposes a resonant energy promotion method at
theAiming
primaryat voltage gainenergy
side. An promotion,
storage thismode
paperisproposes
realizeda resonant
by shorting energy
the promotion
DC inductor method
and at
thephase-shifting
primary side. transformer.
An energy storage
An energymode is realized
injection mode byisshorting
realizedtheby DC inductor
combining and
the phase-shifting
storage energy
transformer.
and DC inputAn energy
energy injection mode
together and is realized
outputting to by
thecombining the storage
resonant tank. energy between
The switching and DC input
the
energy
energytogether
storageand
andoutputting to the
injection mode resonant tank.
is implemented byThe switching
auxiliary switchbetween the energy
pair S3 and S4. storage and
injection mode2isshows
Figure implemented by auxiliary
fundamental operation switch pair S3ofand
principles theSproposed
4. method. The pulses and
current
Figurewaveforms of the proposed
2 shows fundamental circuit
operation switchesofare
principles theshown.
proposed VGE1 to VGE4 The
method. denotes
pulses the
anddriving
current
signals ofofswitches
waveforms S1 to Scircuit
the proposed 4, respectively.
switches are The shown.
current Vwaveform
GE1 to VGE4 of denotes
iL2 is similar to the signals
the driving current of
Energies 2017, 10, 474 3 of 13

Energies 2017, 10, 474 3 of 13

switches S to S4 , 474
Energies12017, 10,
respectively. The current waveform of iL2 is similar to the current waveform 3 of 13
of iL1 ,
except for half-cycle delay. The function of anti-series switches
waveform of iL1, except for half-cycle delay. The function of anti-series (S 3 and S ) is to control the connection
4switches (S3 and S4) is to
between resonant
waveform
control the of iL1tank
connection and
, except push–pull
for half-cycle
between circuit.
delay.
resonant During
The
tank and one full
function
push–pull switching
ofcircuit.
anti-series
During cycle,
one fullthe
switches (S 3 circuit operation
and S4) cycle,
switching is to
control
can be divided
the the operation
circuit connection between
into the following
can resonant
fourinto
be divided tank
modes and can
and push–pull
the following be circuit.
shown
four modes During
inand
Figure
can be one full switching
3.shown in Figurecycle,
3.
the circuit operation can be divided into the following four modes and can be shown in Figure 3.
I II III IV
VGE 4 I II III IV
VGE 4

VGE1
VGE1

VGE 3
VGE 3

VGE 2
VGE 2
iL1
iL1

i AB
i AB t t t t3 t4 t
0 1 2
t0 t1 t2 t3 t4 t

Figure 2. Operation principle of the push–pull topology.

Figure 2. 2.Operation
Figure Operation principle ofthe
principle of thepush–pull
push–pull topology.
topology.

Id LDC Id LDC
Id LDC Id LDC
L1 L2 A L1 L2 A
L1 L2 A L1 L2 A

Vin CP LP Vin CP LP
Vin B CP LP Vin B CP LP
S3 B S3
S3
S4
S3
S4 B
S4 S4

S1 S2 S1 S2
S1 S2 S1 S2
(a) (b)
(a) (b)
LDC Id LDC
Id
LDC Id LDC
Id A
L1 L2 A L1 L2
A
A
L1 L2 L1 L2

Vin CP LP Vin CP LP
Vin S3 B CP LP Vin S3
B CP LP
S4 B S4 B
S3 S3 S4
S4

S1 S2 S1 S2
S1 S2 S1 S2
(c) (d)
(c) (d)
Figure 3. Operating modes of the proposed circuit in one cycle. (a) Mode I; (b) Mode II; (c) Mode III;
Figure
and (d)3.Mode
Operating
IV. modes of the proposed circuit in one cycle. (a) Mode I; (b) Mode II; (c) Mode III;
Figure 3. Operating modes of the proposed circuit in one cycle. (a) Mode I; (b) Mode II; (c) Mode III;
and (d) Mode IV.
and (d) Mode IV.
Energies 2017, 10, 474 4 of 13

Mode I: t0–t1: In this mode, switches S2 and S4 are turned on; switches S1 and S3 are turned off.
Energies 2017, 10, 474 4 of 13
The operation of this mode is shown in Figure 2a. The energy stored in L1 is transfer into the resonant
circuit by switch S4 and the reverse diode of S3; switch S2 is remaining conduction, so that the current
flowing Mode t0 –t1 : slowly
L2 isI:rising In this mode,
and L2 switches S2 andin
is still working S4the
arestate
turned on; switches S1 and S3 are turned off.
of storage.
The operation
Mode II: tof 1–tthis
2: In mode is shown
this mode, in Figure
switches S1 and3a. SThe
2 areenergy
turnedstored
on and L1 is transfer
in switches S3 andintoS4the
areresonant
turned
off. Thebyoperation
circuit switch S4of andthisthemode
reverse shownofinS3Figure
is diode ; switch3b. S2 Switches
is remainingS3 and S4 are turned
conduction, so thatofftheand the
current
flowing Lcircuit
resonant 2 is enters
rising the
slowly state
and Lof
2 free
is energy
still working oscillation
in the between
state of L
storage.
P and C P . Switches S 1 and S 2 are
Mode II: t
turned on and L1 1 and –t 2 : In this mode, switches S
L2 are both working in1the state and S 2 of storage.
are turned on and switches S 3 and S 4 are turned
off. Mode III: t2–t3: In
The operation of this mode,
mode is switches
shownSin 1 and S3 are
Figure 3b.turned
Switches S3 and S4S2are
on; switches andturned
S4 are off
turned
and off.
the
The operation
resonant circuitofenters
this mode the stateis shown
of free in Figure
energy 2c. The energy
oscillation LP and
betweenstored inCLP2. is S1 and
transferred
Switches intoS2 the
are
resonant
turned oncircuit
and L1by and switch
L2 areSboth
3 and the reverse
working in thediode
state ofof storage.
S4 and the current flowing through L2 is
decreasing;
Mode III:switcht2 –tS3 :1 is
Inremaining
this mode,conduction,
switches S1so thatS3the
and arecurrent
turnedflowing L1 is rising
on; switches S2 and slowly
S4 areand L1 is
turned
still
off. working in the state
The operation of this of mode
storage. is shown in Figure 3c. The energy stored in L2 is transferred into
Mode IV:circuit
the resonant t3–t4: by This modeS3isand
switch similarly with diode
the reverse ModeofII,S4switches
and the Scurrent
1 and Sflowing
2 are turned
through on Land2 is
switches
decreasing;S3 and
switch S4 areS1 isturned
remainingoff. The operationsoofthat
conduction, thisthe
mode is shown
current flowing in Figure 3d. Switches
L1 is rising slowly and S3 Land
1 is
S4 are turned off and the resonant circuit enters the state of free energy oscillation between LP and CP.
still working in the state of storage.
SwitchesMode S1 and
IV: tS3 –t
2 are turned
4 : This modeon and L1 and L2with
is similarly are both
Mode working in the S
II, switches state
1 andof S storage.
2 are turned on and
switches S3 and S4 are turned off. The operation of this mode is shown in Figure 3d. Switches S3 and
3.
S4Voltage
are turnedGain offAnalysis
and the resonant circuit enters the state of free energy oscillation between LP and CP .
Switches S 1 and
Assuming that S 2 aretheturned
resonant and Lof
oncycle 1 and L2 are both
the circuit is T, working in the state
and the switching dutyof storage.
cycle of S1 and S2 is
D; correspondingly, the duty cycle of S3 and S4 is (1 − D). According to the volt–second balance of
3. Voltage Gain Analysis
inductors L1 and L2, the average voltage across L1 and L2 is equal to zero during one switching cycle
period.Assuming thatsteady
During the the resonant cycle
state, the of the
current circuit
flows is T, and
through the Lswitching
L1 and 2 is equal duty cycle
so that the of S1 and
energy S2 is
stored
D; correspondingly, the duty cycle of
in inductors L1 and L2 is equal as well. Next, S 3 and S is (1 − D). According to the volt–second
the 4paper will calculate the output gain based on the fact balance of
inductors L
that the energy
1 and L
stored
2 , the average voltage across L
and released in inductor L11is equaland L is equal to zero during
2 during one switching cycle. one switching cycle
period. During
In the the state,
steady steadythe state, the current
supply currentflows and theLcurrent
is Id,through 1 and L2 flowing
is equal through
so that the
L1energy
or L2 isstored
Id/2.
in inductors L and
Assuming the1resonant L is equal as well. Next, the paper will calculate the output
2 network terminal voltage is UAB, thus the volt-second balance equation can gain based on the fact
that
be as stored and released in inductor L1 is equal during one switching cycle.
the energy
obtained
In the steady state, the supply current is Id , and the current flowing through L1 or L2 is Id /2.
Id I
Assuming the resonant network DT = (voltage
Vin terminal
2
U AB − Vinis)UdAB
2
(1, −thus
D ) Tthe volt-second balance equation can (1) be
obtained as .
I I
Thus: Vin d DT = (U AB − Vin ) d (1 − D ) T. (1)
2 2
Thus: V
U AB = in Vin ( 0.5 ≤ D < 1) (2)
U AB1= −D (0.5 ≤ D. < 1). (2)
1−D
Note that
Note that duty
duty cycle
cycle ofof switches and SS22isisno
switches S11 and noless
lessthan
than0.5.
0.5.ItItisisbecause
becausewhen
whenthetheduty
dutycycle
cycle isis
less than
less than 0.5, switches SS11and
0.5, switches andSS22will
willenter
enterthe
thestate
stateofofturning
turningoff
offatatthethesame
sametime;
time;correspondingly,
correspondingly,
switches SS33and
switches andSS44will
willenter
enterthe
thestate
stateof
ofturning
turning on.on. ItIt will
will result
result that
that the
the current of L11 and
and L22 drops
drops
sharply to
sharply to zero
zero and
and the
the current
current will become discontinuities.
discontinuities. On On the
the assumption,
assumption, system
system equivalent
equivalent
circuit
circuit can
can bebe shown
shown asas Figure
Figure 4.
4.

IP IS

RP LS
U AB LP CS Req
VS
CP
RS
ZP k ZS
Figure 4. Equivalent circuit of the push–pull circuit.
Figure 4. Equivalent circuit of the push–pull circuit.
Energies 2017, 10, 474 5 of 13

At the secondary side, according to the energy balance equation, the equivalent resistance Req of
DC part including rectifier, filter and load at the secondary side is

Req = π2 R/8. (3)

The reflection impendence from the secondary to primary side can be expressed by

Rre f = ω 2 k2 L P LS /ZS , (4)

where ZS = (jωLS + RS ) + Req /(jωCS Req + 1) is the input impendence of secondary resonant network.
Its resonant angular frequency is ω = 2πf.
The input impendence of the push–pull network can be expressed as

jωL P + R P + Rre f
ZP =   . (5)
jωCP jωL P + R P + Rre f + 1

The resonant current of the primary side IP can be expressed as

r
 2
IP = U AB / (ωL P )2 + R P + Rre f . (6)

It is well known that the inductive voltage source of secondary side can be expressed as
p
VS = ωkIP L P LS . (7)

On the resonant condition ω 2 LS CS = 1, the output voltage VO the load can be obtained as
√
Req jωkU AB L P LS
VO = . (8)
jωCS Req + 1 ( jωL P + R P ) ZS + ω 2 k2 ( L P LS )

Therefore, the voltage gain of the proposed circuit can be expressed as Equation (9)
  √
 VO  ωk L P LS Req
V  = q . (9)
  q
2
2
in
(ωL P )2 + ( R P ZS + ω 2 k2 L P LS ) (1 − D ) ωCS Req +1

Equation (9) shows that the output voltage can be controlled by duty cycle D, coupling coefficient
k, switching frequency f and the equivalent resistance Req . However, frequency f and the load R usually
are constant in the proposed circuit, thus the output voltage can be regulated by the duty cycle D of
the push–pull switches S1 and S2 .
Compared with traditional full-bridge circuit, its equivalent AC input UAB can be calculated by
√
2 2Vin
U AB = . (10)
π
In addition, the voltage gain of the full-bridge converter will be
  √ √
 VO  ωk L P LS 2 2Req
V  = q . (11)
  q
in 2 2
2
( P) + R Z
( P S + 2 k 2 L L π R + π
ωL ω P S) ωCS eq

As can be seen from Equations (9) and (11), we can draw a conclusion that the voltage gain of
proposed topology can be at least two times than traditional full-bridge topology.
Compared with a traditional push–pull circuit, its equivalent AC input UAB can be calculated by
Energies 2017, 10, 474 6 of 13

Energies 2017, 10, 474 6 of 13

πVin
U AB = (12)
2 .
πV
U AB = √ in . (12)
2
Furthermore, the voltage gain of the full-bridge converter will be
Furthermore, the voltage
VO gain ofωthek Lfull-bridge
L π Rwill
converter eq
be
= P S
√ (13)
( ) ( )
 V
 = q(ωLP ) + Rωk
2 2 2
Z +LωP2 L 2 ωCS Reqq +πR

 VO  in k2SLP LS 1 eq
P S (13)
2√ .

V 
2
in
(ωL P )2 + ( R P ZS + ω 2 k2 L P LS ) 2 ωCS Req + 1
As can be seen from Equations (9) and (13), we can draw a conclusion that the voltage gain of
As can be seen from Equations (9)
2 and (13), we can draw a conclusion that the voltage gain of
proposed topology can achieve √2
proposed topology can achieve π(π1−( 1D−) D
( 0.5 ≤ D < 1) times the traditional push–pull topology.
) ≤ D < 1) times the traditional push–pull topology.
(0.5

4. System Performance
4. System Performance Analysis
Analysis
In order to
In order to analyze
analyzethe
theperformance
performanceofofthe
the proposed
proposed method,
method, several
several performance
performance analyses
analyses are
are carried out including load variation, coupling coefficient and comparison with a traditional
carried out including load variation, coupling coefficient and comparison with a traditional WPT
WPT system.
system.
4.1. Influence of Load (R) Variation on Voltage Gain and Efficiency
4.1. Influence of Load (R) Variation on Voltage Gain and Efficiency
According to Equation (9), Figure 5 shows the voltage gain against switching duty cycle D with
According to Equation (9), Figure 5 shows the voltage gain against switching duty cycle D with
different load R, and the efficiency against load R when k = 0.2. The analysis results show
different load R, and the efficiency against load R when k = 0.2. The analysis results show
(1)
1) With the
With the increase
increaseofofswitch
switchduty
dutycycle D,D,
cycle thethe
output gaingain
output enhancement increases
enhancement obviously
increases and
obviously
the increasing rate of voltage gain increases gradually.
and the increasing rate of voltage gain increases gradually.
(2) The voltage gain ratio is higher when the load R becomes larger at the same switching duty
2) The voltage gain ratio is higher when the load R becomes larger at the same switching duty cycle
cycle D.
D.
(3) From Figure 5b, the system can keep efficiency above 85% in the whole duty cycle range.
3) From Figure 5b, the system can keep efficiency above 85% in the whole duty cycle range.

(a) (b)
Figure 5. Influence of load R: (a) Output gain with various load R; (b) System efficiency with load R.
Figure 5. Influence of load R: (a) Output gain with various load R; (b) System efficiency with load R.

4.2. Influence of Coupling Coefficient (k) Variation on the Gain Ratio and Efficiency
4.2. Influence of Coupling Coefficient (k) Variation on the Gain Ratio and Efficiency
Because the WPT system is a loosely coupled system, the coupling coefficient will vary
Because the WPT system is a loosely coupled system, the coupling coefficient will vary
dynamically. It is necessary to analyze the influence of coupling coefficient variation.
dynamically. It is necessary to analyze the influence of coupling coefficient variation.
Figure 6a shows curves of voltage gain against switching duty cycle D using Equation (9) at
Figure 6a shows curves of voltage gain against switching duty cycle D using Equation (9) at
different coupling coefficients. It can be seen that the gain ratio increases as the switching duty cycle
different coupling coefficients. It can be seen that the gain ratio increases as the switching duty cycle D
D increases. The gain ratio is higher when the coupling coefficient is larger.
increases. The gain ratio is higher when the coupling coefficient is larger.
Figure 6b shows the curves of system efficiency against different operating coupling
Figure 6b shows the curves of system efficiency against different operating coupling coefficients.
coefficients. As the coupling coefficients k increases, the efficiency decreases while load R is larger.
As the coupling coefficients k increases, the efficiency decreases while load R is larger. Overall, the system
can keep running at efficiency above 75% on the condition of coupling coefficient and load variation.
Energies 2017, 10, 474 7 of 13
Energies 2017, 10, 474 7 of 13
Overall,
Energies the
2017, system
10, 474 can keep running at efficiency above 75% on the condition of coupling
7 of 13
Overall, the
coefficient andsystem can keep running at efficiency above 75% on the condition of coupling
load variation.
coefficient and load variation.

(a) (b)
(a) (b)
Figure 6. Influence of coupling coefficient: (a) Output gain; (b) System efficiency.
Figure 6. Influence of coupling coefficient: (a)
Figure 6. (a) Output
Outputgain;
gain;(b)
(b)System
Systemefficiency.
efficiency.

4.3. Comparison of Traditional WPT System

4.3.Comparison
4.3. ComparisonofofTraditional
TraditionalWPTWPTSystem
System
In order to compare this topology performance with traditional WPT system, this chapter
Inorder
In ordertoto compare
compare thisthis topology
topology performance
performance with with traditional
traditional WPT system,
WPT system, this chapter
this chapter presents
presents the voltage gain of four resonant networks (PP, PS, SP and SS) with the same resonant
presents
the voltagethe voltage
gain gain
of four of fournetworks
resonant resonant (PP,
networks
PS, SP(PP,
andPS,
SS)SP andthe
with SS) withresonant
same the same resonant
parameters.
parameters.
parameters.
The voltage gain
The voltage
and efficiency of
gain andofefficiency
of four
four compensation
compensationcircuits
circuitsare
arecompared
comparedagainst
againstload
load
The voltage gain and efficiency four compensation circuits are compared against load variation
variation range from 0 to 100 Ω in Figure 7.
variation
range fromrange from
0 to 100 Ω 0intoFigure
100 Ω 7.
in Figure 7.

Figure
Figure 7. Gain
Figure 7. Gain and
and efficiency
efficiency of
of four basic
four basic compensation
basiccompensation circuits.
compensationcircuits.
circuits.

InFigure
In
In Figure 7,
Figure 7, for
7, for secondary
for secondary series
secondary series topology
topology
topology including
including PS
including PS and
PS and SS,
and SS, this
SS, thiskind
this kindof
kind oftopology
of topologycannot
topology cannot
cannot
achieve high voltage gain due to its voltage source characteristic, and its efficiency is relativelylow
achieve
achieve high
high voltage
voltage gain
gain due to its voltage source
source characteristic,
characteristic, and
and its
its efficiency
efficiency isisrelatively
relatively low
low
on
on the
the light
light load
load condition.
condition. Secondary parallel
parallel topology
topology can
can achieve
achieve relatively
relatively
on the light load condition. Secondary parallel topology can achieve relatively high voltage gain high
high voltage
voltage gain
gain
(maximumgain
(maximum
(maximum gainequals
gain equals5.1)
equals 5.1)due
5.1) due
due to
totoitsits
its current
current
current source
source
source characteristic,
butbut
characteristic,
characteristic, but voltage
voltage gaingain
voltage gain
variesvaries
varies greatly
greatlygreatly
with
with
with load
load variation.
variation. For
For heavy
heavy load
load conditions,
conditions, its
its
load variation. For heavy load conditions, its voltage gain is low.voltage
voltage gain
gain is
islow.
low.
Comparedwith
Compared
Compared withthe
with the
the four
four
four basic
basic
basic compensation
compensation
compensation circuits,
circuits,
circuits, the
the proposed
the proposedproposed push–pull
push–pull circuit circuit
push–pull circuit
can can
can
operate
operate
operate at an adjustable
at an adjustable gain versus
gainload
versus load R
loadhigh with
R with high efficiency
high efficiency from the analyses A and B.
at an adjustable gain versus R with efficiency from the from the analyses
analyses A and B. A and B.
Energies 2017, 10, 474 8 of 13

5. Experimental Verification
Energies 2017, 10, 474 8 of 13
For Energies
the sake 2017, of verifying the performance of the proposed topology, a prototype system
10, 474 8 of 13 is built
up. The system has been
5. Experimental constructed according to the parameters provided in Table 1 and the device
Verification
photo is 5. Experimental
shown
For the insake
FigureVerification
8.
of verifying the performance of the proposed topology, a prototype system is built
up. TheFor the sake
system hasofbeen
verifying the performance
constructed ofto
according thethe
proposed topology,
parameters a prototype
provided system
in Table 1 andisthe
built
device
up. The system has been constructed according
Table 1. to theparameters.
System parameters provided in Table 1 and the device
photo is shown in Figure 8.
photo is shown in Figure 8.
Parameters
Table 1. System parameters. Values
Table 1. System parameters.
Resonant frequency
Parameters f (KHz) 31.45
Values
Parameters Values
Primary resonant
Resonant inductor
frequency LP (µH)
f (KHz)
Resonant frequency f (KHz)
30.38
31.4531.45
Primary inductor
Primary
Primary resistance
resonant
resonant inductorLPL
inductor R(PPμH (Ω)
( μH) ) 0.025
30.3830.38
Primary
Primary capacitor
inductor
Primary inductor CP (µF)
resistance
resistance RPR(PΩ( Ω ) ) 0.66
0.0250.025
Primary
Secondary resonant capacitor CC
inductor
Primary capacitor P ( ( μF
P μFL)S) (µH) 36.82
0.66 0.66
(SμH
S( μH
Secondary
Secondary
Secondary resonant
inductor inductor
inductorLSLR
resistance
resonant ) )
(Ω) 0.029
36.8236.82
Secondary inductor resistance R SR(SΩ Ω
) ) 0.029
Secondary resonant capacitor CS (µF)
Secondary inductor resistance ( 0.57
0.029
Secondary resonant capacitor CS ( μF ) 0.57 0.57
Secondary
Coupling resonant capacitor
coefficient k CS ( μF ) 0.157
Coupling coefficient
Coupling k 0.1570.157
System loadcoefficient
R (Ω) k
System load R ( Ω ) 50
50
System load R ( Ω ) 50

Figure
Figure 8. 8.Experimental
Experimental system
systemphoto.
photo.
Figure
Figure 9 shows the waveforms 8. Experimental
of the system photo.
push–pull switches gate-driving signals and anti-series
Figure 9 shows
switching the waveforms
gate-driving of resonant
signals. The the push–pull
voltage switches gate-driving
VCP and resonant current Isignals and anti-series
LP are shown in
Figure
Figure 10 9 shows
and the the waveforms
resonant voltage andofcurrent
the push–pull
waveformsswitches
are gate-driving
sinusoidal waves, signalsindicate
which and anti-series
that
switching gate-driving signals. The resonant voltage VCP and resonant current ILP are shown in
switching gate-driving signals. The resonant voltage VCP and resonant current ILP are shown in
Figure 10the system
and the can work under
resonant voltagethe state
andofcurrent
resonance.
waveforms are sinusoidal waves, which indicate that
Figure 10 and the resonant voltage and current waveforms are sinusoidal waves, which indicate that
the system can work
the system under
can work the the
under state of resonance.
state of resonance.

VgS1

VgS1
VgS 4

VgS 4
VgS2

VV
gS2gS 3

VgS3

Figure 9. Gate-driving signals’ waveforms.

Figure 9. Gate-driving signals’ waveforms.

Figure 9. Gate-driving signals’ waveforms.
 Energies 2017, 10, 474 9 of 13
Energies 2017, 10, 474 9 of 13
Energies 2017, 10, 474 9 of 13

VCP
VCP

I LP
I LP

Figure
Figure10.
10.Resonant
Resonantvoltage
voltageand
andresonant
resonantcurrent
currentwaveforms.
waveforms.
Figure 10. Resonant voltage and resonant current waveforms.
Figure 11 shows the waveforms of VdS2, VdS3 and VCP from top to bottom. It can be seen that the
Figure11
Figure 11shows
showsthe the waveformsofofVV VdS3
, V,dS3 and VCP from topbottom.
to bottom. canItcondition
canseen
be seen that
synthesized waves of VdS2waveforms
and VdS3 are exactly dS2dS2
halfand
of V CP from
the resonanttop wave
to VCP onIt the be that
of Dthe=
the synthesized
synthesized waves waves
of V of VdS2Vand
dS2 and
VdS3
dS3 are
are exactly
exactly half half
of theofresonant
the resonant
wave wave
V V theoncondition
CP on CP
the condition
of D of
=
0.6. The same result can be detected that the synthesized waves of VdS1 and VdS4 are exactly half of the
D
0.6.= 0.6. The
The same same result can be detected that the synthesized waves of V and V are exactly half
resonant waveresult
VCP. can When be the
detected
duty that
cyclethe synthesized
becomes waves
D = 0.8, the of VdS1 anddS1
waveforms VdS4
of are
VdS2exactly
dS4
, VdS3 and halfVof the
CP are
of the
resonant resonant wave V . When the duty cycle becomes D = 0.8, the waveforms of V , V and VCP
shown inwave VCP 12. When theand
duty cycle
are becomes
changingDwhen = 0.8,the
the duty
waveforms
cycle DofisVchanging.
dS2, VdS3 and VCP are
CP dS2 dS3
Figure and VdS2 VdS3 Figure 13
are
shown shown in
in Figure Figure 12 and
12 and VdS2 V and and V
dS2 VdS3 are are changing when the duty cycle D is
dS3 changing when the duty cycle D is changing. Figure 13 changing. Figure 13
shows that VO is controlled at 43 V for the condition of R = 50 Ω and D = 0.8, which achieves a gain of
shows
shows that
that V is controlled
VOOis controlled at 43
at input V
43 V forfor the condition
the condition of
of ItR = 50
R verifies Ω
= 50 Ω and and D = 0.8, which achieves a gain ofof
4.3 times compared with the voltage Uin = 10 V. thatDthe
= 0.8, which
system canachieves
realize aa gain
higher
4.3 timescompared
4.3 comparedwith withthe theinput voltageUUinin= =1010V.V.ItItverifies
inputvoltage verifiesthat
thatthe
thesystem
systemcan canrealize
realizeaahigher
higher
gaintimes
by regulating the duty cycle D.
gain by
gain Table regulating
by regulating the
thethe duty
duty cycle
cycle D. D.
2 presents experimental data of the proposed topology. The controlled gain range is
Table22presents
Table presentsthe theexperimental
experimentaldata dataofofthe the proposedtopology.
topology.The Thecontrolled
controlledgain gain rangeisis
from 1.6 to 7.3. With higher gain, the system can proposed
get higher output power. Furthermore,range system
from
from 1.6
1.6 to
to 7.3.
7.3. With
With higher
higher gain,
gain, the
the system
system can
can get
get higher
higher output
output power.
power. Furthermore,
Furthermore, system
system
efficiency can remain above 80%. Figure 14 shows that the experimental results of voltage gain
efficiency
efficiency can
can remain above 80%. Figure 14 shows that the experimental results of voltage voltage match
gain
match with theremain aboveresults
theoretical 80%. well,
Figureexcept
14 shows that the
that there experimental
is little differenceresults
at the of maximum gain
gain
with
match the theoretical results well, except that there is little difference at the maximum gain point. It is
point. Itwith the theoretical
is because power losses results well,
at the exceptside
primary thatwill
there is littleatdifference
increase the top gain at point.
the maximum gain
because power losses at the primary side will increase at the
point. It is because power losses at the primary side will increase at the top gain point.top gain point.

Vds3 Vds2
Vds3 Vds2

Figure 11. Waveforms of VdS2, VdS3 and VCp at D = 0.6.

Figure 11. Waveforms of VdS2, VdS3 and VCp at D = 0.6.
Figure 11. Waveforms of VdS2 , VdS3 and VCp at D = 0.6.
 Energies 2017, 10, 474 10 of 13
Energies 2017, 10, 474 10 of 13
Energies 2017, 10, 474 10 of 13

VCP
VCP

Vds3 Vds2
Vds3 Vds2

Figure 12.
Figure 12. Waveforms of V
Waveforms of VdS2, ,VVdS3 and
andVV
Cp at D = 0.8.
at D = 0.8.
dS2, VdS3
Figure 12. Waveforms of VdS2 dS3and VCp Cp
at D = 0.8.

VO
VO

V
Vinin

Figure 13. Waveforms of input voltage and output voltage.

Figure 13. Waveforms of input voltage and output voltage.
Figure 13. Waveforms of input voltage and output voltage.
Table 2. Experiment Results.
Table 2. Experiment Results.
Table 2. Experiment Results.
Input Voltage/Current Duty Cycle of Output Output Power
Input Voltage/Current DutyS1Cycle Gain Efficiency
(V/A) (D) of Output(V)
Voltage Output
(W)Power
Gain Efficiency
Input Voltage/Current
(V/A) Duty Cycle
S1 (D) Output
Voltage (V) Output (W) Gain
10/0.61
(V/A) of S0.5
1 (D) Voltage 16.2
(V) Power (W) 5.4 1.6 Efficiency
88%
10/0.61
10/1.09 0.5
0.6 16.2
21.7 5.4
9.5 1.6
2.17 88%87.4%88%
10/0.61
10/1.09 0.5
0.6 16.221.7 5.4 9.5 1.6 2.17 87.4%
10/1.96
10/1.09 0.7
0.6 21.7 28.9 9.5 16.9 2.17 2.89 87.4% 86%
10/1.96
10/2.80
10/1.96
0.7
0.75
0.7
28.9
28.9 34.5 16.9
16.9
23.8 2.89 2.89
3.45 86%85% 86%
10/2.80
10/2.80
10/4.7 0.75
0.75
0.8 34.5
34.5 43.1 23.8 23.8
39.5 3.45 3.45
4.31 85%84.1%85%
10/4.7
10/4.7
10/8.08 0.8
0.85 43.143.1
53.8 39.5 39.5 4.31
67.5 4.31
5.38 84.1%
84.1%
83.6%
10/8.08
10/8.08 0.85
0.85 53.853.8 67.5 67.5 5.38 5.38 83.6%
83.6%
10/15.2
10/15.2 0.9
0.9 72.3 72.3 123 123 7.3 7.3 80.9% 80.9%
10/15.2 0.9 72.3 123 7.3 80.9%
Energies 2017, 10, 474 11 of 13
Energies
Energies2017,
2017,10,
10,474
474 11
11of
of13
13

Figure
Figure 14.
14. Comparison
Comparison of
of the
the system
system gain
gain curve.
curve.
Figure 14. Comparison of the system gain curve.

6.
6. Discussion
Discussion
6. Discussion
In
In order
order to
to present
present aa close
close loop
loop control
control of
of the
the voltage
voltage gain,
gain, aa Proportion
Proportion Integration
Integration
In order to present a close loop control of the voltage gain, a Proportion Integration Differentiation
Differentiation
Differentiation (PID) control is applied to regulate the duty cycle D of the switches. The close
(PID) control is applied to regulate the duty cycle D of the switches. The close loop
loop
(PID) control is applied to regulate the duty cycle D of the switches. The close loop control structure
control
control structure
structure can
can be
be shown
shown inin Figure
Figure 15.
15.
can be shown in Figure 15.

Figure 15. Close

Figure15.
Figure 15. Closeloop
loopcontrol.
control.

The
The information
informationofof
Theinformation output
ofoutput
output voltage
voltage
voltage VOV Vis is
is measured
measured
OO measured andand
sentsent
and backback
sent back
to the to the
the primary
toprimaryprimary
side by side
side by
by an
an Radio an
Radio
Radio Frequency
Frequency Frequency
(RF)-link.(RF)-link.
(RF)-link. Furthermore,
Furthermore,
Furthermore, aa PID
a PID controllerPID controller
controller is
is utilizedis utilized
utilized
to controlto
to controldutythe
control
the the duty
duty
cycle of cycle
cycle
S3 and of
ofSSS43,3
and
and SS44,, according
according according to
to the
the difference
to the difference betweenbetween
difference VO and V
between O and
VOref . VVrefref..
and
A
Aload
A load switching
loadswitching
switchingtest test was
testwas carried
wascarried
carriedout out
outtoto evaluate
toevaluate
evaluatethe the controller’s
thecontroller’s performance.
controller’sperformance.
performance. In In this
In this test,
this test, load
test,load
load
condition
condition is
is set
set to
to switching
switching between
between 10
10 Ω
Ω and
condition is set to switching between 10 Ω and 30 Ω. The DC input voltage
and 30
30 Ω.
Ω. The
The DC
DC input
input voltage
voltage is
is set
set at
at 55 V.
V. The
The output
output
at 5 V. The output
reference voltage
referencevoltage
reference voltageis is set
isset
setatat 20
at20 V.
20V. The
V.The experimental
Theexperimental
experimentalresult result
resultcancan
canbebe shown
beshown
shownin in Figure
inFigure
Figure16. 16.
16.
As
Ascan
As can
canbe be seen
seeninin
beseen Figure
inFigure
Figure16,16,
16, there
there
there areare
are
two two
two
load load
load switching
switching
switching events
events
events in
in the the
the control
incontrol control process:
one isone
process:
process: one
from is
is
from 20 Ω to 10 Ω (first switching) and the other is from 10 Ω to
20 Ω to 10 Ω (first switching) and the other is from 10 Ω to 20 Ω (second switching). In the control
from 20 Ω to 10 Ω (first switching) and the other is from 10 Ω to 20
20 ΩΩ (second
(second switching).
switching). In
In the
the
control
control process,
process, process,
the output the
the output
outputis voltage
voltage voltage
kept is
stableis kept
kept
except stable
stable
for someexcept
except for
for some
switching some switching
switching The
disturbance. disturbance.
disturbance.
experimental The
The
experimental
experimental
results verify theresults
results
close verify
loop the
verify the close
close
control loop
loop control
performancecontrolof performance
performance of
of the
the PID controller. the PID
PID controller.
controller.
Energies 2017, 10, 474 12 of 13
Energies 2017, 10, 474 12 of 13

Figure 16.
Figure Experimental results
16. Experimental results of
of close
close loop
loop control.
control.

7. Conclusions
7. Conclusions

In order
ordertoto achieve controllable
achieve highhigh
controllable voltage gain output,
voltage this paper
gain output, proposed
this a novel current-fed
paper proposed a novel
push–pull topology for the WPT system. This method utilizes a bi-directional switch
current-fed push–pull topology for the WPT system. This method utilizes a bi-directional switch thatthat is added to
isolate
is addedthetoinverter withinverter
isolate the resonant network
with andnetwork
resonant guide theandpower
guide flow
the into
powertheflow
resonant
into tank. On the
the resonant
basis, On
tank. an energy storage
the basis, and injection
an energy storageswitching modeswitching
and injection is proposed to enhance
mode voltage
is proposed togain. A switching
enhance voltage
duty cycle
gain. is also proposed
A switching duty cycle to is
implement gain control.
also proposed This method
to implement can greatly
gain control. This improve
method canthe voltage
greatly
gain in the
improve theWPT system
voltage gainand maintain
in the a high system
WPT system efficiency
and maintain at the
a high sameefficiency
system time. Thisatisthe
important
same time.for
low DC
This voltage input
is important application
for low DC voltage including PV power supply
input application includingand PVUSB charger.
power supply and USB charger.

Acknowledgments:
Acknowledgments: This This research
research works
works isis support
support byby the
the National
National Natural
Natural Science
Science Foundation of China
Foundation of China
(51377187, 51377183) and the Chongqing International Science and Technology Cooperation Base Project
(51377187, 51377183)
(CSTC2015GJHZ40001). and the Chongqing International Science and Technology Cooperation Base Project
(CSTC2015GJHZ40001).
Author Contributions: The main idea of this paper is proposed by Qichang Duan and Yanling Li. Yanling Li
Author
wrote Contributions:
this paper. Xin DaiThe main
gave idea of this
experiment paper
design. Taois Zou
proposed by Qichang
performed Duanexperiments.
verification and Yanling Li. Yanling Li
wrote this paper. Xin Dai gave experiment design. Tao Zou performed
Conflicts of Interest: The authors declare no conflict of interest. verification experiments.

Conflicts of Interest: The authors declare no conflict of interest.

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