Beruflich Dokumente
Kultur Dokumente
ECX4236
Day School 02
(12th May 2016)
N. I Vithanage
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Lab Experiment 02
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Phase 02
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Implementing Phase
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Delays
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Delay Loops
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Time Calculations
• As a Counter:
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Delay Loop Implementation
MOV R3, #4
Outer Loop
L3: MOV R2, #3 Inner Outer Loop
L2: MOV R1, #2 Inner Loop
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Timers/ Counters - SFR
Timer SFRs
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Timers/ Counters - Modes
Timer Modes
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Using Timers
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Using Timers. cont.
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Using Timers. cont.
0
…………………..
…………………..
…………………..
…………………..
…………………..
65535
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Using Timers. cont.
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Using Timers. cont.
Case 02: Delay less than full range
Ex: Delay time = 20 ms
Period = 1.085 µs
Delay value = Delay Time/ Period
= 20 ms/ 1.085 µs = 18433.18
Reload Value = Full range – Delay Value
= 65535 – 18433 = 47103
= B7FFh
TH = B7h, TL = FFh
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Using Timers in Assembly
DELAY: MOV TMOD,#0001B Select the Timer Mode
MOV TH1,#4CH
Set The Timer
MOV TL1,#00H
CLR TF1 Clear Overflow bit
SETB TR1 Timer Run
LOOP: JNB TF1,LOOP Check Overflow bit
CLR TF1
Clear all Flags
CLR TR1
RET Returning to main program
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Thank You!
DS Wickramasinghe: dswic@ou.ac.lk
CJ Basnayakage: cjbas@ou.ac.lk
Phone: - Direct: 011 288 1437
Ext: 437
NI Vithanage: nivit@ou.ac.lk
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