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538 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 2, FEBRUARY 2015
Fig. 4. Measured output power versus output current with and without single-
capacitor DCR.
Fig. 3. Single-capacitor DCR validation setup.
TABLE I TABLE II
SSL PV CELL CHARGE MULTIPLIER FOR 3–2 DCR STRING SSL CAPACITOR CHARGE MULTIPLIER
FOR 3–2 DCR STRING
perfectly matched and each cell contains a constant photocur- during either phase
rent source generating a total charge of qph over a complete ϕ
− (qph /2)
|qc,i | qpv,i
switching period. For a photocurrent source in this two-phase ac,i = = . (11)
converter qout qout
1 2 qph Equation (11) can be used to determine the SSL charge multi-
qph = qph = . (4) pliers of the capacitors, which are summarized in Table II.
2
The capacitor charge multiplier vector can be generalized to
The output is represented by a constant current load drawing a DCR string with 2N − 1 cells, where there are N cells in the
a total charge of qout over a complete switching period. That is, load-connected string and N − 1 cells in the ladder-connected
qout is the sum of the output charges delivered during phase 1 string. In the general case, the output current to photocurrent
and phase 2, and therefore ratio and the capacitor charge multiplier expressions are shown
in (12) and (13), respectively
1 2 qout
qout = qout = . (5) 2N − 1
2 qout = · qph (12)
N
By using capacitor charge balance in steady state, we can
|qc,i | |N − i|
write ac,i = = . (13)
qout 4N − 2
1 2
qpv,i + qpv,i = qph (6) The SSL output impedance [16] of the DCR string can then
for i = 1, 2, . . . , 5. By Kirchhoff’s current law (KCL), we can be written as
further write (7) and (8) for the two phases
2N −1
(ac,i )2 1 N · (N − 1) 1
RSSL = = · · . (14)
1
qpv,1 1
+ qpv,2 1
= qpv,3 1
+ qpv,4 1
= qpv,5 =
qout
(7) i=1
Cd · fsw 12 2N − 1 Cd · fsw
2
qout In order to calculate percentage insertion loss, the ratio of the
2 2 2 2 2
qpv,1 = qpv,2 + qpv,3 = qpv,4 + qpv,5 = . (8) SSL output impedance to the load resistance must be calculated.
2
This can be found as an expression in terms of the performance
Solving this system of (6)–(8) iteratively yields the relation- of each cell in steady state, operating at its maximum power
ship between the photocurrent from each cell and the string point with voltage Vm p and current Im p . Using (12), which
output current, as shown effectively relates cell current to output current, and the fact that
5 the DCR string voltage equals N times the cell voltage as shown
qout = · qph . (9) in Fig. 5, the load resistance is
3
Each charge flow can then be expressed in terms of the output Vout N · Vm p N2 Vm p
RL = = = · . (15)
charge over a complete switching period. Following the conven- Iout ((2N − 1)/N ) · Im p 2N − 1 Im p
tion in [16], the normalized charge flow, or the charge multiplier The insertion loss fraction ILSSL can be calculated as the
will be defined as ratio of the SSL output impedance of the DCR string to the load
ϕ resistance
qx,i
aϕx,i = . (10)
qout RSSL 1 N −1 1 1 Im p
ILSSL = = · · · · (16)
RL 12 N fsw Vm p Cd
The SSL charge multiplier of each PV cell in the 3–2 DCR string
during the two phases is summarized in Table I. and the SSL efficiency of the array can be defined as one minus
The net charge flowing into any diffusion capacitance over the SSL insertion loss. Equation (16) represents a fundamental
a complete switching cycle in steady state will be zero. Each result that is dependent on technology and material choices. It
capacitor in Fig. 6 will experience an equal but opposite charge states that the SSL efficiency of a solar array configured as a
delivery during the two phases. The magnitude of the charge DCR string is effectively dictated by the ratio of the maximum
flows for the capacitors can therefore be expressed as the dif- power current to the diffusion capacitance, for large N. For il-
ference between the charge extracted from the solar cell, and lustration, assume the following rounded numbers for our solar
the charge generated by the photocurrent source within the cell cells under maximum illumination: a maximum power voltage
542 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 2, FEBRUARY 2015
at its maximum power operation. That is, the total power from
a series string can be written as
Pstring = (1 − |δi |) · Pm p . (24)
i
be required for every two solar cells. While the IC would only
need to make contacts to two solar cells, which keeps the inte-
gration cost at a minimum, it would have to power up from a
small forward voltage of a single diode. Alternatively, if more
than one pairs of MOSFETs and complementary gate drives are
integrated, the IC can balance multiple pairs of solar cells, and
access to a higher input voltage with the added advantage of
sharing the power management circuit. This leads to fewer ICs
per panel and can potentially reduce the overall incremental cost
per watt. However, the IC would have to make direct contacts
to more solar cells, which complicates wiring and increases in-
tegration costs. These tradeoffs will ultimately dictate the level
of integration as the PV market is highly cost-driven.
V. EXPERIMENTAL RESULTS
The circuit shown in Fig. 7(b) was characterized in the lab-
oratory with a power supply, an HP 6063B dc electronic load,
and a Tektronix TDS5034B oscilloscope to collect current and
voltage data. Specifically, the characteristic output power versus
output current curve is obtained by recording both the string out-
put voltage and the output current as the electronic load sweeps
the output current from 0 to 10 A at a slew rate of 1 A/s. As
the electronic load demands more current than the series string
can supply, the current saturates at the short-circuit current of
the string, as illustrated in Fig. 8. Furthermore, the effect of pro-
cess variation can be observed in the voltage waveform. That is,
if the short-circuit current of the individual cells are perfectly
matched, the string is expected to have a zero output voltage at
the short-circuit current. However, if there is mismatch between
the cells, cells with higher short-circuit circuit can maintain a
positive voltage as the string current is limited by the cells with
lower short-circuit current.
Fig. 9 shows the experimental output power measurement of a
five-cell series string with and without bypass diodes, compared Fig. 9. Experimental measurement of a 3–2 DCR string under various partial
to a 3–2 DCR string. From the five-cell series string measure- shading conditions compared to the five-series string: (a) uniform irradiance,
ment under uniform irradiance in Fig. 9(a), the maximum power (b) two cells 40% shaded, (c) one cell 40% shaded, and one cell 75% shaded.
CHANG et al.: CAPACITOR-LESS PHOTOVOLTAIC CELL-LEVEL POWER BALANCING USING DIFFUSION CHARGE REDISTRIBUTION 545
TABLE IV
MEASURED OUTPUT POWER COMPARISON AND EFFICIENCY SUMMARY
Configuration (N = 3) Power (W) Conversion Efficiency Power (W) Extracted Percentage Power (W) Extracted Percentage
current Im p and voltage Vm p of the cells can be extracted to be external energy storage components. In the limit where only the
1.31 A and 0.40 V, respectively. The diffusion capacitance can intrinsic solar cell diffusion capacitances are used for cell-level
then be calculated from Fig. 2(c) to be approximately 6.25 μF. power balancing, the finest achievable MPPT granularity can be
The DCR string has a switching frequency of 500 kHz, and the reached at the minimum possible cost for power electronics.
expected SSL conversion loss is 5.8% from (16). Assuming the With a reduced per-converter component count, i.e., no ex-
switch on resistance dominates the effective resistance, the ex- ternal capacitive or inductive energy storage, the proposed so-
pected FSL conversion loss is 4.1% from (20). Hence, the total lution can potentially become cost effective at the cell-level,
insertion loss can be calculated from (21) to be 7.1%. which has been cost prohibitive using the current state of the
The measured output power of the five-cell series string has art, including cascaded module-level power electronic (MLPE)
a peak at 2.63 W, and the measured output power of the 3–2 such as dc power optimizers [7], [8] and microinverters [9],
DCR string has a maximum of 2.49 W. This gives a measured and submodule-level DPP converters using switched-capacitor
efficiency of 94.7%, or a measured DCR insertion loss of 5.3%. [2], [3] or switched-inductor [4]–[6] techniques. In addition,
The lower measured insertion loss, compared to the calculated with power optimization granularity down to the cell level, sub-
7.1%, can be attributed to the recovery of losses from process stantial improvement in energy capture can also be achieved
variation as shown in (26). compared to module and submodule level solutions [15].
Fig. 9(b) and (c) illustrates the measured output power char- A fully scalable ladder-type DCR string architecture has been
acteristic curves under different shading conditions, where the presented along with the analysis method to characterize the in-
shading percentage is determined by measuring the change in sertion losses at the SSL and FSL. A proof-of-concept system
short-circuit current of the shaded cells. The series string is consisting of a 3–2 DCR string has been constructed and char-
shown to lose a significant portion of the string power even acterized. Experimental results show the DCR string extracting
when only a small percentage of the total area is shaded. With significantly more energy under various partial shading condi-
bypass diodes in place, the string is able to extract more power. tions compared to the traditional series string and series string
However, the resulting output power characteristic curve is non- with bypass diodes.
convex, i.e., with multiple maxima, which introduces additional The proposed approach requires that the DCR circuits be
constraints to the required MPPT algorithm. In the case of the integrated into the solar panels. This means that the proposed
DCR string, significantly more power can be extracted. More- technique is not a retrofit solution and must be incorporated into
over, the output power characteristic curve remains convex, the manufacturing process. While the additional wiring cost
which greatly reduces the complexity of the required MPPT is typically secondary compared to the cost of the ICs, changing
algorithm. the stringing pattern of the solar cell will likely present a barrier
The maximum measured power for each configuration is tab- to adoption. There is more room for work on manufacturing
ulated in Table IV, where the extracted percentage column il- strategies that enable ease of integration [26] or new paradigms
lustrates the ratio of power extracted to the total available power of solar cell fabrication that embed power electronics on the
under uniform irradiance for the same configuration. It can be same substrate [27]–[29]. Associated with these are innovations
seen that in the case of DCR, the extracted percentage follows in the areas of solar cell fabrication, chip packaging, intercon-
one minus the overall shading percentage quite closely, which nects, and panel lamination.
validates the effectiveness of the proposed power balancing
technique. ACKNOWLEDGMENT
The authors would like to thank Prof. M. el-Sayed at Kuwait
VI. CONCLUSION AND FUTURE CONSIDERATIONS University for helpful discussions.
A new cell-level power balancing scheme, DCR, has been
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no. 3, pp. 6–20, Sep. 2013. faculty in the Department of Electrical Engineering
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module and array mathematical modeling destined to simulation,” in Proc. ment in MIT’s Department of Mechanical Engineer-
IEEE Int. Symp. Ind. Electron., 2009, pp. 1624–162. ing. He currently a MacVicar Fellow and Professor of
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to modeling and simulation of photovoltaic arrays,” IEEE Trans. Power electronic drives. He is the author or coauthor of over 100 publications and
Electron., vol. 24, no. 5, pp. 1198–1208, May 2009. 15 U.S. patents in the fields of electromechanics and power electronics.