REG.

NO:

M.E./M.TECH. DEGREE EXAMINATIONS 2017 – ‘18

M.P.NACHIMUTHU M.JAGANATHAN ENGINEERING COLLEGE

An ISO 9001:2008 Certified Institution
CHENNIMALAI, ERODE – 638 112.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

INTERNAL TEST – III

M.E. VLSI DESIGN

Subject: AP5094 & Signal Integrity for High Speed Design Semester: II
Date : Branch: VLSI Design
Time : 1Hour 30 Minutes Maximum: 100 Marks
Answer ALL Questions
PART – A (10 x 2 = 20 Marks)

1. Define SPICE.
2. Write the expressions of capacitance per length of a microstrip and strip line.
3. State inductance principle No.2.
4. How to convert differential to common signals?
5. Mention the purpose of PDN.
6. How to stack printed circuit board layers?
7. What are the factors to estimate crosstalk?
8. State some rules for reducing connector emissions.
9. Define clock skew.
10. How to decouple clock receivers from the clock bus?
PART - B (13 x 5 = 65 Marks)

11. a. Describe in detail about non ideal current return path. (13)
(or)
b. Explain termination of odd and even mode transmission line pairs. (13)
12 a. Discuss the behavior model of the basic CMOS buffer. (13)
(or)
b. (i) Explain eye diagram. (7)
(ii)Explain the effect of crosstalk into the high speed bus with example. (6)
13. a. Differentiate differential mode radiation and common mode radiation. (13)
(or)
b. Describe S-parameters for signal integrity applications. (13)
14. a. Discuss low impedance clock distribution lines. (13)
(or)
b. Explain clock oscillators in brief. (13)
15. a. Discuss low impedance drivers. (13)
(or)
b. Explain clock oscillators in brief. (13)
PART – C (15 x 1 = 15 Marks)

16. a. Explain delay adjustments in detail. (15)

(or)
b. Explain noise radiated from a connector, with example. (15)

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