Synch Manual

PXI
NI-Sync User Manual
NI-Sync User Manual
October 2005
370926C-01
Support
Worldwide Technical Support and Product Information

ni.com
National Instruments Corporate Headquarters

11500 North Mopac Expressway Austin, Texas 78759-3504 USA Tel: 512 683 0100
Worldwide Offices
Australia 1800 300 800, Austria 43 0 662 45 79 90 0, Belgium 32 0 2 757 00 20, Brazil 55 11 3262 3599,
Canada 800 433 3488, China 86 21 6555 7838, Czech Republic 420 224 235 774, Denmark 45 45 76 26 00,
Finland 385 0 9 725 725 11, France 33 0 1 48 14 24 24, Germany 49 0 89 741 31 30, India 91 80 51190000,
Israel 972 0 3 6393737, Italy 39 02 413091, Japan 81 3 5472 2970, Korea 82 02 3451 3400,
Lebanon 961 0 1 33 28 28, Malaysia 1800 887710, Mexico 01 800 010 0793, Netherlands 31 0 348 433 466,
New Zealand 0800 553 322, Norway 47 0 66 90 76 60, Poland 48 22 3390150, Portugal 351 210 311 210,
Russia 7 095 783 68 51, Singapore 1800 226 5886, Slovenia 386 3 425 4200, South Africa 27 0 11 805 8197,
Spain 34 91 640 0085, Sweden 46 0 8 587 895 00, Switzerland 41 56 200 51 51, Taiwan 886 02 2377 2222,
Thailand 662 278 6777, United Kingdom 44 0 1635 523545
For further support information, refer to the Technical Support and Professional Services appendix. To comment
on National Instruments documentation, refer to the National Instruments Web site at ni.com/info and enter
the info code feedback.
© 2003–2005 National Instruments Corporation. All rights reserved.

Important Information
Warranty
The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects
in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National
Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives
notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be
uninterrupted or error free.
A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before
any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are
covered by warranty.
National Instruments believes that the information in this document is accurate. The document has been carefully reviewed for technical
accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent
editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected.
In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.
EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. CUSTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF
NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER. NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR
DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY
THEREOF. This limitation of the liability of National Instruments will apply regardless of the form of action, whether in contract or tort, including
negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments
shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover
damages, defects, malfunctions, or service failures caused by owner’s failure to follow the National Instruments installation, operation, or
maintenance instructions; owner’s modification of the product; owner’s abuse, misuse, or negligent acts; and power failure or surges, fire,
flood, accident, actions of third parties, or other events outside reasonable control.
Copyright
Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying,
recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National
Instruments Corporation.
Trademarks
National Instruments, NI, ni.com, and LabVIEW are trademarks of National Instruments Corporation. Refer to the Terms of Use section
on ni.com/legal for more information about National Instruments trademarks.
Other product and company names mentioned herein are trademarks or trade names of their respective companies.
Members of the National Instruments Alliance Partner Program are business entities independent from National Instruments and have no
agency, partnership, or joint-venture relationship with National Instruments.
Patents
For patents covering National Instruments products, refer to the appropriate location: Help»Patents in your software, the patents.txt file
on your CD, or ni.com/patents.
WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

(1) NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF
RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN
ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT
INJURY TO A HUMAN.
(2) IN ANY APPLICATION, INCLUDING THE ABOVE, RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE
IMPAIRED BY ADVERSE FACTORS, INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY,
COMPUTER HARDWARE MALFUNCTIONS, COMPUTER OPERATING SYSTEM SOFTWARE FITNESS, FITNESS OF COMPILERS
AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION, INSTALLATION ERRORS, SOFTWARE AND
HARDWARE COMPATIBILITY PROBLEMS, MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL
DEVICES, TRANSIENT FAILURES OF ELECTRONIC SYSTEMS (HARDWARE AND/OR SOFTWARE), UNANTICIPATED USES OR
MISUSES, OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER (ADVERSE FACTORS SUCH AS THESE ARE
HEREAFTER COLLECTIVELY TERMED “SYSTEM FAILURES”). ANY APPLICATION WHERE A SYSTEM FAILURE WOULD
CREATE A RISK OF HARM TO PROPERTY OR PERSONS (INCLUDING THE RISK OF BODILY INJURY AND DEATH) SHOULD
NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE. TO AVOID
DAMAGE, INJURY, OR DEATH, THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO
PROTECT AGAINST SYSTEM FAILURES, INCLUDING BUT NOT LIMITED TO BACK-UP OR SHUT DOWN MECHANISMS.
BECAUSE EACH END-USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS' TESTING
PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN
COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL
INSTRUMENTS, THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING
THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE
INCORPORATED IN A SYSTEM OR APPLICATION, INCLUDING, WITHOUT LIMITATION, THE APPROPRIATE DESIGN,
PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION.
Contents
About This Manual

Conventions ...................................................................................................................xiii
Related Documentation..................................................................................................xiv
Chapter 1
Introduction, Installation, and Configuration
About the NI-Sync Driver Software ..............................................................................1-1
Introduction....................................................................................................................1-1
Operating System Support...............................................................................1-2
Application Software and Programming Language Support...........................1-2
Device Support ................................................................................................1-2
Installing the Software ...................................................................................................1-3
Device and System Configuration .................................................................................1-3
Using Measurement & Automation Explorer..................................................1-4
Identifying Your PXI System ...........................................................1-4
Locating Your NI PXI-665x or NI PCI-1588 Devices .....................1-4
Chapter 2
Building and Programming Applications
The NI-Sync Instrument Driver .....................................................................................2-1
Creating a Windows Application Using LabVIEW ......................................................2-1
Developing an NI-Sync Application ...............................................................2-1
Example Programs...........................................................................................2-2
Creating a Windows Application Using LabWindows/CVI..........................................2-2
Creating a Windows Application Using Microsoft Visual C++....................................2-2
Special Considerations ....................................................................................2-3
NI-Sync Programming Flow..........................................................................................2-4
Initialize...........................................................................................................2-6
Configure Hardware ........................................................................................2-6
Accessing Attributes .........................................................................2-7
Connect Terminals...........................................................................................2-7
Clock Terminals................................................................................2-7
Trigger Terminals .............................................................................2-8
Software Trigger Terminals ..............................................................2-9
© National Instruments Corporation v NI-Sync User Manual

Contents
Start PTP ......................................................................................................... 2-10

Get 1588 Time ................................................................................................ 2-10
Create Future Time Event ............................................................................... 2-11
Enable Timestamp Trigger.............................................................................. 2-11
Create Clock.................................................................................................... 2-11
Configure and Perform Measurement............................................................. 2-12
Read Trigger Timestamp ................................................................................ 2-12
Clear Future Time Events ............................................................................... 2-12
Disable Timestamp Trigger ............................................................................ 2-13
Clear Clock ..................................................................................................... 2-13
Stop PTP ......................................................................................................... 2-13
Disconnect Terminals ..................................................................................... 2-14
Clock Terminals ............................................................................... 2-14
Trigger Terminals ............................................................................. 2-14
Software Trigger Terminals.............................................................. 2-14
Close................................................................................................................ 2-15
Utility .............................................................................................................. 2-15
Terminal Connection Information .................................................... 2-15
Instrument Driver Utility Functions ................................................. 2-16
Advanced ........................................................................................................ 2-17
Frequency Measurement................................................................... 2-17
FPGA Reconfiguration ..................................................................... 2-17
Chapter 3
Using NI-Sync with the LabVIEW FPGA Module
Introduction ................................................................................................................... 3-1
Developing FPGA Module Applications ...................................................................... 3-2
Switching Execution Targets .......................................................................... 3-2
Executing FPGA VIs ...................................................................................... 3-4
Communication with FPGA VIs..................................................................... 3-4
Interactive Front Panel Communication........................................... 3-4
Programmatic FPGA Interface Communication .............................. 3-5
Special Considerations .................................................................................................. 3-5
FPGA Device I/O Functions ........................................................................... 3-5
Arbitration ........................................................................................ 3-7
Trigger Input Synchronization to PXI_Clk10 .................................. 3-7
Connecting FPGA Device Digital Outputs to Physical Terminals... 3-8
Programmatic FPGA Interface Communication............................................. 3-9
External VISA Input ......................................................................... 3-9
NI-Sync User Manual vi ni.com

Contents
Chapter 4
Synchronizing Multiple NI PXI-4472 Modules
Theory of Operation: Synchronizing Data Acquisition Across Multiple NI PXI-4472
Modules.......................................................................................................................4-1
Synchronizing Signals for Multiple NI PXI-4472 Modules in a
Single Chassis...............................................................................................4-2
Delta-Sigma ADCs and the Oversample Clock ................................4-2
The NI PXI-4472 SYNC Pulse .........................................................4-4
The Acquisition Start Trigger ...........................................................4-6
Using the NI PXI-665x to Route Synchronization Signals between
Multiple Chassis ...........................................................................................4-7
Sharing the Oversample Clock between Chassis..............................4-7
Sharing the SYNC Pulse between Chassis .......................................4-9
Sharing the Acquisition Start Trigger between Chassis....................4-10
Configuring the Chassis.................................................................................................4-13
Configuration #1: One Chassis with Synchronized Acquisition
and One CPU ................................................................................................4-13
LabVIEW ..........................................................................................4-14
LabWindows/CVI .............................................................................4-14
What You Need to Get Started .........................................................4-15
Connecting the NI PXI-665x Device ................................................4-15
Connecting the NI PXI-4472 Devices ..............................................4-15
Configuring and Running the Software Example .............................4-15
Using the niSync_DSA Example Single Chassis VI ........................4-16
Using the niSync_DSA Example 1 Chassis [Low Level] VI ...........4-17
Using niSync_DSA_Example Single Chassis
(LabWindows/CVI Example Project) ............................................4-17
Configuration #2: Two or Three Chassis with Synchronized
Acquisition and One CPU ............................................................................4-18
LabVIEW ..........................................................................................4-18
LabWindows/CVI .............................................................................4-19
Connecting the MXI-3 Devices ........................................................4-22
Connecting the NI PXI-665x Devices...............................................4-22
Using the niSync_DSA_Example 2 or 3 Chassis Finite Acq VI and the
niSync_DSA_Example 2 or 3 Chassis Continuous Acq VI...........4-23
Using the niSync_DSA Example 2 Chassis [Low Level] VI ...........4-24
Using niSync_DSA_Example Dual Chassis Finite and
niSync_DSA_Example Dual Chassis Continuous Acq
(LabWindows/CVI Example Projects) ..........................................4-25
© National Instruments Corporation vii NI-Sync User Manual

Contents
Using niSync_DSA_Example Dual Chassis Finite GUI

(LabWindows/CVI Example Project)............................................ 4-26
Configuration #3: Four or More Chassis with Synchronized
Acquisition and One CPU ............................................................................ 4-26
What You Need to Get Started ......................................................... 4-27
Connecting the MXI-3 Devices ........................................................ 4-30
Connecting the NI PXI-665x ............................................................ 4-30
Connecting the NI PXI-4472 Devices .............................................. 4-31
Configuring and Running the Software Example............................. 4-31
Using the niSync_DSA_Example N Chassis VI .............................. 4-31
Configuration #4: Two Chassis with Synchronized Acquisition
and Two CPUs ............................................................................................. 4-33
Connecting to Ethernet ..................................................................... 4-35
Connecting the NI PXI-665x ............................................................ 4-36
Connecting the NI PXI-4472 Modules ............................................. 4-36
Running the Multi-CPU DSA Examples Programs ......................... 4-36
Chapter 5
NI PXI-5112 Theory of Operation ................................................................................ 5-1
Multiple Chassis ......................................................................................................... 5-2
Example Overview.......................................................................................... 5-2
Setting Up a Multichassis PXI System............................................. 5-4
Connecting the NI PXI-665x Devices .............................................. 5-5
Example Functionality .................................................................................... 5-7
Initialization and Error Checking ..................................................... 5-7
Configuring the 10 MHz Timebase .................................................. 5-8
Routing the Necessary Synchronization Signals .............................. 5-10
Configuring the NI PXI-5112 Synchronization
and Acquisitions ............................................................................ 5-12
Beginning the Acquisition ................................................................ 5-13
Closing and Error Checking ............................................................. 5-13
NI-Sync User Manual viii ni.com

Contents
Chapter 6
NI PXI-6115 Theory of Operation.................................................................................6-1
Multiple Chassis..........................................................................................................6-2
Example Overview ..........................................................................................6-2
Setting Up the Multichassis PXI System ..........................................6-4
Example Functionality.....................................................................................6-6
Initialization and Error Checking......................................................6-6
Configuring the NI PXI-665x Clocks ...............................................6-7
Routing the Necessary Synchronization Signals ..............................6-8
Configuring the NI PXI-6115 Synchronization
and Acquisitions.............................................................................6-12
Beginning the Acquisition ................................................................6-13
Closing and Error Checking..............................................................6-13
Chapter 7
Synchronizing Multiple NI MIO Modules
Theory of Operation.......................................................................................................7-1
Multiple Chassis..........................................................................................................7-2
Setting Up the Multichassis PXI System ..........................................7-4
Connecting the MIO Devices............................................................7-5
Example Functionality.....................................................................................7-6
Initialization and Error Checking......................................................7-6
Configuring the Scan Clock ..............................................................7-7
Routing the Necessary Synchronization Signals ..............................7-7
Configuring the MIO Synchronization and Acquisitions .................7-8
Beginning the Acquisition ................................................................7-9
Closing and Error Checking..............................................................7-9
© National Instruments Corporation ix NI-Sync User Manual

Contents
Chapter 8
LabVIEW FPGA Module Examples
Simple Event Counting.................................................................................................. 8-1
FPGA VI ......................................................................................................... 8-2
Host VI ............................................................................................................ 8-4
Pulse Width Measurement............................................................................................. 8-7
FPGA VI ......................................................................................................... 8-8
Host VI ............................................................................................................ 8-11
Period Measurement...................................................................................................... 8-15
FPGA VI ......................................................................................................... 8-16
Host VI ............................................................................................................ 8-19
PXI Clk10 Synchronous Input Trigger.......................................................................... 8-23
FPGA VI ......................................................................................................... 8-24
Host VI ............................................................................................................ 8-27
Chapter 9
NI PXI-5411 Theory of Operation ................................................................................ 9-1
Multiple Chassis ......................................................................................................... 9-2
Setting Up the Multichassis PXI System.......................................... 9-4
Connecting the NI PXI-665x Devices .............................................. 9-5
Example Functionality .................................................................................... 9-8
Initialization and Error Checking ..................................................... 9-8
Configuring the 10 MHz Timebase .................................................. 9-9
Routing the Necessary Synchronization Signals .............................. 9-10
Configuring the NI PXI-5411 Synchronization and Generations..... 9-13
Beginning the Signal Generation...................................................... 9-14
Closing and Error Checking ............................................................. 9-15
NI-Sync User Manual x ni.com

Contents
Chapter 10
IEEE 1588
Chapter 11
NI PCI-1588 LabVIEW Examples
Start PTP and Wait for Quality......................................................................................11-1
Time Stamp....................................................................................................................11-4
Generate Event...............................................................................................................11-7
Generate Clock ..............................................................................................................11-9
Appendix A
Technical Support and Professional Services
Glossary
Index
© National Instruments Corporation xi NI-Sync User Manual

About This Manual
The NI-Sync User Manual is for users of the NI-Sync driver software,
an application programming interface (API) for controlling NI PXI-665x
and NI PCI-1588 timing modules. This manual describes the fundamentals
of developing applications with NI-Sync. In addition, this manual includes
examples for using NI-Sync with specific measurement hardware.
Conventions
The following conventions appear in this manual:
<> Angle brackets that contain numbers separated by an ellipsis represent

a range of values associated with a bit or signal name—for example,
AO<3..0>.
» The » symbol leads you through nested menu items and dialog box options
to a final action. The sequence File»Page Setup»Options directs you to
pull down the File menu, select the Page Setup item, and select Options
from the last dialog box.
♦ The ♦ symbol indicates that the following text applies only to a specific
product, a specific operating system, or a specific software version.
This icon denotes a note, which alerts you to important information.
This icon denotes a caution, which advises you of precautions to take to

avoid injury, data loss, or a system crash.
bold Bold text denotes items that you must select or click in the software, such
as menu items and dialog box options. Bold text also denotes parameter
names.
italic Italic text denotes variables, emphasis, a cross reference, or an introduction

to a key concept. Italic text also denotes text that is a placeholder for a word
or value that you must supply.
monospace Text in this font denotes text or characters that you should enter from the
keyboard, sections of code, programming examples, and syntax examples.
This font is also used for the proper names of disk drives, paths, directories,
programs, subprograms, subroutines, device names, functions, operations,
variables, filenames, and extensions.
© National Instruments Corporation xiii NI-Sync User Manual

About This Manual
Related Documentation
The following documents contain information that you might find helpful
as you read this manual:
• PICMG 2.0 R3.0, CompactPCI Core Specification, available from
PICMG, available from www.picmg.org
• PXI Specification, Revision 2.1, available from www.pxisa.org
• NI PXI-665x User Manual, available from ni.com/manuals
• Getting Started with Multi-Chassis Synchronization Using the
NI PXI-665x, available from ni.com/manuals
• NI PCI-1588 User Manual, available from ni.com/manuals
NI-Sync User Manual xiv ni.com

Introduction, Installation, and
1
Configuration
This chapter provides an overview of the NI-Sync driver software and
explains how to install and configure NI-Sync for use with NI PXI-665x
and NI PCI-1588 timing modules.
About the NI-Sync Driver Software

NI-Sync is a library of VIs and functions for controlling NI PXI-665x and
NI PCI-1588 timing modules. Using NI-Sync, you can configure all aspects
of timing and synchronization for NI PXI-665x devices, including sharing
trigger signals and clocks in one or more chassis. In addition, you can
configure all aspects for NI PCI-1588 devices, including IEEE 1588
synchronization, trigger time stamping, and generation of synchronized
signals. You can use NI-Sync in conjunction with other measurement
software, such as NI-DAQmx, to create advanced high-channel-count
measurements that span multiple PXI chassis or an Ethernet network.
Introduction
The NI-Sync driver software includes the following:
• NI-Sync instrument driver API and device driver
• Hardware-specific example software, illustrating multichassis
synchronization for the following measurement devices:
– NI PXI-4472 modules
– NI PXI-6115/6120 modules
• Hardware-specific example software, illustrating IEEE 1588
synchronization for the following measurement device:
– NI PCI-1588 modules
© National Instruments Corporation 1-1 NI-Sync User Manual

Chapter 1 Introduction, Installation, and Configuration
When developing your application, refer to Chapter 2, Building and

Programming Applications, for information about creating an application
with your specific application development environment (ADE). Also,
refer to the appropriate hardware-specific chapter in this manual for
specific examples of using NI-Sync with your application.
Operating System Support

NI-Sync supports:
• Windows 2000/XP
• LabVIEW RT
The NI PCI-1588 supports:

• Windows 2000/XP Service Pack 2 or later
Application Software and Programming Language Support

Table 1-1 lists the application software versions that NI-Sync supports.
If you are not using National Instruments application software, refer to
Table 1-2.
Table 1-1. National Instruments Application Software Support
NI Application Software Versions NI-Sync Supports

LabVIEW 7.0 or later
LabVIEW RT Module 7.0 or later
LabWindows™/CVI™ 5.5 or later
Table 1-2 lists additional programming languages supported by NI-Sync.
Table 1-2. Additional Programming Language Support
Programming Language Versions NI-Sync Supports

ANSI C ✓
Microsoft Visual C++ 5.0 or later
Device Support
NI-Sync supports the NI PXI-665x family of timing modules and the
NI PCI-1588 device.
NI-Sync User Manual 1-2 ni.com

Installing the Software

The software package that ships with the NI PXI-665x and NI PCI-1588
provides the following items:
• NI-Sync driver software
• LabVIEW example code
• LabWindows/CVI example code
• NI PXI-665x User Manual and NI PCI-1588 User Manual
Complete the following steps to install your NI-Sync software:

1. Insert the NI-Sync CD into the CD-ROM drive of your computer.
2. Run the Setup.exe program to install the NI-Sync software on your
system.
Several high-level examples are provided to give you a starting point in

using the NI PXI-665x to synchronize data acquisition across multiple
PXI chassis with various National Instruments PXI modules and the
NI PCI-1588 to synchronize 1588 clocks across Ethernet networks.
Note Be sure to install the NI-Sync software before installing the NI PXI-665x or
NI PCI-1588 hardware.
Device and System Configuration

Before you begin using your NI PXI-665x or NI PCI-1588 devices, you
must ensure that your PXI system software is configured properly. NI-Sync
uses PXI configuration information to enable features such as chassis
identification, slot identification, and trigger terminal reservation. This
configuration information is enabled by identifying PXI system
components in Measurement & Automation Explorer (MAX).
Note The NI PCI-1588 device is actually two devices, a timing and synchronization
device and a Network Interface Card (NIC). In the Windows Device Manager, the timing
and synchronization device is enumerated in the NI Timing and Synchronization
Modules section as NI PCI-1588. The NIC is enumerated in the Network adapters
section as AMD PCNET Family PCI Ethernet Adapter. When configuring your
network connections in Windows, the local area connection associated with the AMD
PCNET Family PCI Ethernet Adapter is the one associated with the NI PCI-1588 device.

Using Measurement & Automation Explorer

MAX is a Windows-based application that you use to configure and view
National Instruments device settings under Windows operating systems.
Identifying Your PXI System

Double-click the Measurement & Automation Explorer icon on
your desktop to run MAX. In the Configuration pane, select My System»
Devices and Interfaces»PXI System. Using the PXI System view, you
can identify the controller and chassis in your PXI system. Refer to the PXI
System context help for detailed instructions on identifying your PXI
system components.
Locating Your NI PXI-665x or NI PCI-1588 Devices

Once you have identified your PXI system components, you can locate
your NI PXI-665x or NI PCI-1588 devices by browsing the PXI System
view (My System»Devices and Interfaces»PXI System). Instances
of the NI PXI-665x or NI PCI-1588 devices are displayed under their
corresponding chassis. By selecting an instance of the NI PXI-665x or
NI PCI-1588, you can view its attributes, including VISA Resource Name
and PXI slot number. Refer to Figure 1-1 for an example of the type of
device information available in MAX.
Note While the NI PCI-1588 is a PCI device rather than a PXI device, it is still displayed
under the PXI System view in MAX and is assigned a standard PXI VISA Resource Name.
Refer to Figure 1-2 for an example of a NI PCI-1588 device displayed in MAX.
Note Viewing NI PXI-665x or NI PCI-1588 device information in MAX is useful for

obtaining the VISA Resource Name for an instance of the NI PXI-665x or NI-PCI-1588.
The VISA Resource Name is used to create a session to a device using the NI-Sync API.
Refer to Chapter 2, Building and Programming Applications, for detailed information
about device initialization.

Figure 1-1. NI PXI-665x Device Information in MAX

Figure 1-2. NI PCI-1588 Device Information in MAX

Building and Programming
2
Applications
This chapter describes the fundamentals of building and programming
NI-Sync applications for LabVIEW, LabWindows/CVI, and Microsoft
Visual C++.
The NI-Sync Instrument Driver

The NI-Sync driver software includes an instrument driver API for
configuring attributes and programming the features of NI PXI-665x and
NI PCI-1588 devices. The NI-Sync instrument driver function library is
a C DLL. This DLL should be linked using the appropriate import library
for your application development environment.
The following sections provide guidelines for creating applications that use
the NI-Sync driver software.
Note If you are not using one of the tools listed, refer to your development tool reference
manual for details on creating applications that call C DLLs.
Creating a Windows Application Using LabVIEW

This section assumes that you are using LabVIEW 7.0 or later to manage
your code development and that you are familiar with the LabVIEW
environment basics.
Developing an NI-Sync Application

To develop an NI-Sync application with LabVIEW, complete the following
steps:
1. Open an existing or new LabVIEW VI.
2. From the Function Palette, locate the NI-Sync VIs at Instrument I/O»
Instrument Drivers»NI-Sync.
3. Select the VIs you want to use and drop them on the block diagram to
build your application.

Chapter 2 Building and Programming Applications
Example Programs
You can find LabVIEW example programs from the Windows Start menu
at Programs»National Instruments»NI-Sync»Examples. The examples
are organized by LabVIEW version number and measurement hardware.
Creating a Windows Application Using LabWindows/CVI

This section assumes that you are using LabWindows/CVI 5.5 or later
to manage your code development and that you are familiar with the
LabWindows/CVI environment.

To develop an NI-Sync application with LabWindows/CVI, complete the
following steps:
1. Open an existing or new project file.
2. Load the NI-Sync function panel at \VXIpnp\winnt\niSync.
3. Use the function panel to navigate the function hierarchy and generate
function calls with the proper syntax and variable values.
Example Programs
You can find LabWindows/CVI example programs from the
Windows Start menu at Start»Programs»National Instruments»
NI-Sync»Examples»CVI Examples. The examples are organized by
measurement hardware.
Creating a Windows Application Using Microsoft

Visual C++
This section assumes that you are using the Microsoft Visual C++ (MSVC)
ADE to manage your code development and that you are familiar with the
MSVC environment.


To develop an NI-Sync application with MSVC, complete the following
steps:
1. Open an existing or new Visual C++ project to manage your
application code.
2. Create files of type .c (C source code) or .cpp (C++ source code) and
add them to the project. Make sure to include the NI-Sync header file
in each source file:
#include "niSync.h"
3. Specify the directory that contains the NI-Sync header file under the
Preprocessor»Additional include directories settings in your
compiler. For MSVC 5.0/6.0, this setting is found under Project»
Settings»C/C++. The NI-Sync header file is in the \VXIpnp\winnt\
include directory.
4. Add the NI-Sync import library niSync.lib to the project under the
Link»General»Object/Library Modules setting. The NI-Sync
import library is in the \VXIpnp\winnt\lib\msc folder.
5. Add NI-Sync function calls to your application.
6. Build your application.
Example Programs
You can find C-based example programs from the Windows Start menu
at Start»Programs»National Instruments»NI-Sync»Examples»
CVI Examples. The examples are organized by measurement hardware.
Note While the C-based examples are written specifically for use with LabWindows/CVI,
they can be adapted for use with MSVC and other C/C++ compilers.
Special Considerations
When developing applications with MSVC, observe the following special
considerations:
• String Passing—To pass strings as arguments to functions, pass a
pointer to the first element of the character array. Be sure the string is
null terminated.

NI-Sync Programming Flow

Figure 2-1 shows the basic programming flow of typical NI-Sync
applications using NI PXI-665x devices. NI-Sync VIs and functions are
organized under the Initialize, Configure Hardware, Connect Terminals,
Disconnect Terminals, and Close categories to assist you in understanding
where you should call a function or VI in your applications. Functions and
VIs that do not fall into the programming flow categories are considered
Advanced or Utility functions that perform various tasks such as resetting
NI PXI-665x or NI PCI-1588 devices, returning the revision number of the
NI-Sync instrument driver and instrument firmware, and other functions.
Initialize
Configure Hardware
Connect Terminals
Utility
Configure and
Perform
Measurement
Advanced
Disconnect Terminals
Close
Figure 2-1. Basic Programming Flow of an NI-Sync Application

with NI PXI-665x Devices
Figure 2-2 shows the basic programming flow of typical NI-Sync

applications using NI PCI-1588 devices. NI-Sync VIs and functions are
organized under the Initialize, Configure Hardware, Start PTP, Get
1588 Time, Create Future Time Event, Enable Timestamp Trigger, Create
Clock, Read Trigger Time Stamp, Stop PTP, Clear Future Time Events,

Disable Timestamp Trigger, Clear Clock, and Close categories to assist you
in understanding where you should call a function or VI in your
applications. Functions and VIs that do not fall into the programming flow
categories are considered Advanced or Utility functions. These functions
perform various tasks such as resetting NI PXI-665x or NI PCI-1588
devices, returning the revision number of the NI-Sync instrument driver
and instrument firmware, and other functions.
Initialize
Configure Hardware
Start PTP
Get 1588 Time
Create Future Enable Timestamp Create

Time Event Trigger Clock
Read Trigger Timestamp
Clear Future Disable Timestamp Clear

Time Events Trigger Clock
Stop PTP
Figure 2-2. Basic Programming Flow of an NI-Sync Application

with NI PCI-1588 Devices

Initialize
For any application you write, you must first open a session to establish
communication with the NI PXI-665x or NI PCI-1588 device using the
Initialize VI or function.
LabVIEW VI C Function
niSync Initialize niSync_init
In addition to establishing a session with the timing module, niSync

Initialize can reset the device to a known state and verify that the NI-Sync
instrument driver is valid for a particular instrument. The Initialize VI or
function returns a ViSession handle you can use to identify the instrument
in all subsequent NI-Sync calls.
Note The Initialize VI and function take the VISA Resource Name corresponding to an
NI PXI-665x or NI PCI-1588 device and use this information to locate the instrument and
create a session to it. You can obtain the VISA Resource Name for an instance of the
NI PXI-665x or NI PCI-1588 using MAX. Refer to Chapter 1, Introduction, Installation,
and Configuration, for an example of using MAX with the NI PXI-665x and NI PCI-1588.
Note You can participate in the Precision Time Protocol (PTP) in “software-only” mode,
which does not require an NI PCI-1588 device. If you specify NISYNC::SYSTEMCLOCK
as the resource name, the computer clock is used as the clock when participating in
PTP. However, participating in PTP in this manner is much less accurate than using an
NI PCI-1588 device. Of course, a session created in this manner cannot enable time stamp
triggers or create clocks or future time events. In addition, if you are participating in PTP
using an NI PCI-1588, do not also attempt to participate in PTP in “software-only” mode
on this same NIC. A single NIC cannot participate in PTP in both modes at the same time.
The Initialize VI and function create a new instrument session. Any session
returned from Initialize may be used in multiple program threads.
Configure Hardware
Use Configuration VIs and functions to adjust settings of the timing and
synchronization features of the NI PXI-665x module, including DAC input
threshold voltage levels, DDS frequency, synchronization clock sources,
and other settings and features needed for timing operations. You can also
use Configuration VIs and functions to adjust setting of the 1588 clock of
the NI PCI-1588 device.

NI PXI-665x and NI PCI-1588 attributes are configured using a

LabVIEW property node or the niSync_SetAttribute and
niSync_GetAttribute functions.
Accessing Attributes
In LabVIEW, you can find NI PXI-665x and NI PCI-1588 attributes in the
niSync property node. To access these attributes, complete the following
steps:
1. Open a VI.
2. Make sure you are viewing the block diagram. Navigate the niSync
palette at Instrument I/O»Instrument Drivers»NI-Sync and drag
the property node to the block diagram.
3. Left-click the property node and select the attribute you want to use.
4. To configure additional attributes, resize the property node.
In C, attributes are accessed with the niSync_SetAttribute… and

niSync_GetAttribute… functions. These functions correspond to
a particular data type. For example, to set the PFI0 DAC voltage level
(type ViReal64), use niSync_SetAttributeViReal64.
Refer to the NI-Sync API Reference for a complete list of attributes.
Connect Terminals
After you have configured the NI PXI-665x timing module, you can
route signals between terminals using the Connect Terminals functions.
Connecting terminals forms the core of typical NI-Sync applications.
Source and destination terminals can be connected using a variety of
mechanisms. NI-Sync considers three types of terminals—clock terminals,
trigger terminals, and software trigger terminals.
Clock Terminals
Clock terminals include terminals associated with the 10 MHz PXI
reference clock (PXI_Clk10). Clock terminal connections are used to route
clock signals between the backplane and front panel of the NI PXI-665x
module. Refer to the NI PXI-665x User Manual for a complete discussion
of clock terminals.
Clock terminal connections have a variety of uses, including:

• Multichassis PXI_Clk10 synchronization
• PXI_Clk10 replacement with a high-precision onboard oscillator

Clock terminal connections are characterized by source and destination

terminals.
The following VI and function deal with clock terminal connections.
niSync Connect Clock niSync_ConnectClkTerminals
Terminals
Trigger Terminals
Trigger terminals include terminals associated with hardware trigger
lines. Trigger terminals can also carry clocks, but they are not associated
with any specific clock signal. Trigger terminals include the PXI trigger
lines (PXI_Trig[0:7]), the PXI star triggers (PXI_Star[0:12]), and the
NI PXI-665x front panel PFI lines (PFI[0:5]). Refer to the NI PXI-665x
User Manual for a complete discussion of trigger terminals.
You can use trigger terminals to route single digital pulses between chassis.
In addition, trigger terminals can carry and distribute clock signals. Typical
uses of trigger terminals include the following:
• Sharing a trigger signal to start data acquisition between multiple
chassis
• Sharing a “sync pulse” to align common clocks on multiple chassis
• Distributing high-speed clock signals (typically on PXI_Star
terminals)
Note Some trigger types are reservable. That is, they can be connected to only a single
source at a time. For example, PXI_Trig terminals use TTL drivers and should not be
driven by multiple signal sources. To solve this problem, NI driver software supports
reservation of PXI_Trig terminals so that only one source is active on a destination at any
given time. This reservation software integrates with other NI measurements software to
prevent multiple sources for a single PXI_Trig terminal.
Trigger terminal connections are characterized by a source terminal,

destination terminal, and synchronization clock. In addition, trigger
terminal signals can be inverted or synchronized to the rising or falling edge
of the specified synchronization clock. Trigger signals can also be routed
asynchronously.

The following VI and function deal with trigger terminal connections.
niSync Connect Trigger niSync_ConnectTrigTerminals
Terminals
Software Trigger Terminals

Software trigger terminals include those terminals associated with
software-initiated trigger pulses. Currently, the NI PXI-665x timing
module includes a single software trigger terminal, referred to as the Global
Software Trigger. The Global Software Trigger terminal can be connected
to any other trigger terminal (PXI_Trig, PXI_Star, and PFI). When the
software trigger terminal is connected, a pulse can be sent to all connected
destination terminals simultaneously.
Typical uses of the Global Software Trigger include the following:

• Generating a trigger signal to start data acquisition
• Generating a “sync pulse” to align common clocks on multiple chassis
• Resetting clocks (or divided clocks) to synchronize clock generation
across multiple NI PXI-665x modules
Software trigger terminal connections are characterized by a source

terminal (always set to the Global Software Trigger), a destination terminal
(any valid trigger terminal destination), and a synchronization clock. In
addition, the software trigger signal can be inverted, synchronized to the
rising or falling edge of the specified synchronization clock, or delayed by
an integer multiple of the synchronization clock period. Refer to the
NI PXI-665x User Manual for a complete discussion of the Global
Software Trigger.
The following VIs and functions deal with software trigger terminal
connections.
LabVIEW VIs C Functions

niSync Connect Software niSync_ConnectSWTrigToTerminal
Trigger
niSync Send Software niSync_SendSoftwareTrigger
Trigger

Start PTP
After you have configured the NI PCI-1588 device, you can start the
Precision Time Protocol (PTP). PTP synchronizes the clock on the
NI PCI-1588 according to the IEEE 1588 specification. For more
information regarding PTP and the IEEE 1588 specification, refer to
Chapter 10, IEEE 1588. In general, you should start PTP and ensure it
has been synchronized before performing any other operations with the
NI PCI-1588 device.
Note You may start PTP for only a specific NI PCI-1588 device in one session. However,
as long you have started PTP for a specific device, all sessions using that device leverage
the synchronized clock on the device.
Note When an NI PCI-1588 device is participating in PTP as a slave device, it may be

required to perform a macro phase adjustment. A macro phase adjustment is when the
1588 clock is adjusted by a significant amount and, therefore, the 1588 time no longer
atomically increments. This should not occur on a well designed and stable network. If this
occurs, future time events, clocks, and time stamps may be affected. If the 1588 time is set
forward, future time events and clock transitions that were missed occur immediately. If
the 1588 time is set backward, future time events and clock transitions are delayed.
Note If the 1588 clock participating in the PTP enters the faulty state, future time
events, clocks, and time stamps will no longer be synchronized with other 1588 devices
participating in the PTP. This should not occur on a well designed and stable network.
You can check for this condition by monitoring the 1588 clock state property.
The following VI and function deal with starting PTP.
LabVIEW VI C Functions
niSync Start PTP niSync_StartPTP
Get 1588 Time

After you have started PTP on the NI PCI-1588, you can query the device’s
1588 clock time.
Note While only one session may start PTP on a specific NI PCI-1588 device, all sessions
using that device may query the 1588 time.

The following VI and function deal with getting the 1588 time.
niSync Get 1588 Time niSync_Get1588Time
Create Future Time Event

You can change a signal level at any NI PCI-1588 device terminal at a
specific time by creating a future time event. When the 1588 clock on the
NI PCI-1588 device reaches the specified 1588 time, the signal level is
changed as specified. You can create multiple future time events that
change the signal levels on different terminals or that change the same
signal level to generate pulses.
The following VI and function deal with creating future time events.
niSync Create Future niSync_CreateFutureTimeEvent
Time Event
Enable Timestamp Trigger

You can generate a timestamp when a signal at any NI PCI-1588 terminal
changes its level by enabling a timestamp trigger. The timestamp is the
1588 clock time on the NI PCI-1588 device when the specified terminal
changes its state.
The following VI and function deal with enabling timestamp triggers.
niSync Enable niSync_EnableTimestampTrigger
Time Stamp Trigger
Create Clock
You can generate a clock at any NI PCI-1588 terminal. You can start and
stop the clock at a specific 1588 time. The clock is synchronized to the
1588 clock on the NI PCI-1588 device.

The following VI and function deal with creating clocks.
niSync Create Clock niSync_CreateClock
Configure and Perform Measurement

After making terminal connections, you are ready to perform your
measurement. Taking a measurement is an application-specific
operation that typically involves the use of a Measurements API
such as NI-DAQmx, NI-Scope, NI-FGEN, and so on. If you are
synchronizing measurements using multiple NI PXI-4472, NI PXI-5112,
NI PXI-6115/6120, or NI PXI-5411 modules, refer to the appropriate
chapter of this manual for detailed examples of using your measurement
device with NI-Sync.
Note If you are not using measurement devices discussed in this manual, refer to
the reference manuals for your measurements hardware for specific instructions on
configuring and performing a measurement.
Read Trigger Timestamp

After you have enabled a timestamp trigger, you can read all generated
timestamps. The timestamp is the1588 clock time on the NI PCI-1588
device when the specified terminal changes its state.
The following VI and function deal with reading trigger timestamps.
niSync Read Trigger niSync_ReadTriggerTimestamp
Timestamp
Clear Future Time Events

After you no longer want to generate future time events, they should be
cleared. This allows the terminal generating timestamps to be used for other
operations. Clearing future time events on a specific terminal clears all
future time events for that terminal.

The following VI and function deal with clearing future time events.
niSync Clear Future niSync_ClearFutureTimeEvents
Time Events
Disable Timestamp Trigger

After you no longer want to generate timestamps, they should be disabled.
This allows the terminal generating timestamps to be used for other
operations.
The following VI and function deal with disabling timestamp triggers.
niSync Disable niSync_DisableTimestampTrigger
Time Stamp Trigger
Clear Clock
After you no longer want to generate a clock, it should be cleared. This
allows the terminal generating the clock to be used for other operations.
The following VI and function deal with clearing clocks.
niSync Clear Clock niSync_ClearClock
Stop PTP
After you no longer want to synchronize the 1588 clock on the
NI PCI-1588, PTP can be stopped. However, PTP should not be stopped
if other operations are currently configured.
The following VI and function deal with stopping PTP.
niSync Stop PTP niSync_StopPTP

Disconnect Terminals
After a measurement has been performed, connected terminals should be
disconnected. This returns the PXI system to its premeasurement state and
avoids disrupting the activity of other timing and synchronization
applications. Terminals are disconnected by supplying the connected
source and destination terminals to Disconnect VIs or functions.
Terminals are disconnected according to their type.
Clock Terminals
Use the following VI or function to disconnect clock terminals.
niSync Disconnect Clock niSync_DisconnectClkTerminals
Terminals
Trigger Terminals
Use the following VI or function to disconnect trigger terminals.
niSync Disconnect niSync_DisconnectTrigTerminals
Trigger Terminals
Software Trigger Terminals

Use the following VI or function to disconnect software trigger terminals.
niSync Disconnect niSync_DisconnectSWTrigFromTerminal
Software Trigger
Note A special terminal value exists for disconnecting multiple terminals from a source
or destination terminal. Use the AllConnected terminal (NISYNC_VAL_ALL_CONNECTED)
to disconnect multiple sources or destinations. If this value is supplied as the source and
destination terminal, all connections of the specified terminal type are disconnected.
Note In addition to the explicit disconnect VIs and functions, you can use niSync Reset
to disconnect all connected terminals.

Close
When your program finishes, terminate the session with the Close VI or
function.
niSync Close niSync_close
The Close VI or function is essential for deallocating memory and freeing

other operating system resources. Every session you initialize must be
closed, even if an error occurs during program execution.
While debugging your application, it is possible to abort the application

without calling Close. While aborting execution should not cause
problems, it is not recommended for terminating your application.
Note Calling Close will not disconnect terminals that were connected while a session is
open. Terminals must be explicitly disconnected using Disconnect VIs/functions or by
resetting the module.
However, for an NI PCI-1588 session, calling Close stops, clears, and disables operations
configured within the session. That is, if you started PTP within the session, calling Close
stops PTP. Likewise, if you created a future time event within the session, it is cleared; if
you enabled a timestamp trigger, it is disabled; if you created a clock, it is cleared.
Utility
In addition to resource and terminal connection management, NI-Sync
includes several Utility VIs and functions for performing tasks such as
resetting the NI PXI-665x or NI PCI-1588, converting error codes to
messages, and obtaining information about existing terminal connections.
Terminal Connection Information

NI-Sync includes VIs and functions for obtaining information about
terminal connections.


niSync Get Clock niSync_GetClkTerminalConnectionInfo
Connection Info
niSync Get niSync_GetTrigTerminalConnectionInfo
Trigger
Connection Info
niSync Get SW niSync_GetSWTrigConnectionInfo
Trigger
Connection Info
Using these VIs and functions, you can determine if a given destination
terminal is connected. You also can determine the connection parameters,
such as synchronization clock, clock edge, and signal inversion.
Instrument Driver Utility Functions

In addition to terminal connection information, NI-Sync supports the
standard set of instrument driver utility functions.

niSync Reset niSync_reset
niSync Self-Test niSync_self_test
niSync Revision Query niSync_revision_query
niSync Error Message niSync_error_message
Refer to the NI-Sync API Reference for details regarding these functions.

Advanced
NI-Sync also includes advanced features, including frequency
measurement and FPGA reconfiguration.
Frequency Measurement
NI-Sync can measure the frequency of a signal at the PFI0 terminal of
an NI PXI-665x module. The following VI and function support this
operation.
niSync Measure Frequency niSync_MeasureFrequency
Frequency measurement is useful for verifying that clock signals are

properly connected. For example, a clock signal connected to PXI_Star3
could be measured by connecting the PXI_Star3 terminal to the PFI0
terminal and using the Measure Frequency VI or function.
FPGA Reconfiguration
Caution FPGA Reconfiguration is a sensitive operation that can damage your
NI PXI-665x module. Do not use this operation unless you are absolutely sure about
what you are doing.
The NI PXI-665x module includes a field programmable gate array

(FPGA) for managing the device’s timing and synchronization features.
For a detailed block diagram of the NI PXI-665x, refer to the NI PXI-665x
User Manual. In some special cases, you may want to program the FPGA
with an alternate bitstream file. The following VI and function support this
operation.
niSync Configure FPGA niSync_ConfigureFPGA

Using NI-Sync with the
3
LabVIEW FPGA Module
This chapter describes the fundamentals of using the NI-Sync instrument
driver in conjunction with LabVIEW and the LabVIEW FPGA Module to
develop advanced timing and triggering applications.
Introduction
With LabVIEW and the FPGA Module, you can create VIs that run on
National Instruments Reconfigurable I/O (RIO) devices. Reconfigurable
I/O devices, also known as FPGA devices, contain a reconfigurable FPGA
(Field-Programmable Gate Array) surrounded by fixed I/O resources.
The NI PXI-665x family of timing and triggering devices includes two
modules—the NI PXI-6653 and NI PXI-6652—that you can use as FPGA
devices with the FPGA Module.
With the FPGA Module and an NI PXI-6653 or NI PXI-6652 device,

you can configure the behavior of the reconfigurable FPGA to match the
requirements of your timing and triggering application. A VI you create to
run on an FPGA device is called an FPGA VI. Use the FPGA Module
to write FPGA VIs. Use FPGA VIs in conjunction with the NI-Sync
instrument driver to enable advanced timing and triggering applications.
This chapter includes a general overview of the FPGA Module and special
considerations for using it with the NI-Sync instrument driver. Refer to the
FPGA Module documentation for information about the FPGA Module
and FPGA VI development.

Chapter 3 Using NI-Sync with the LabVIEW FPGA Module
Developing FPGA Module Applications

This section provides an overview of using the FPGA Module with the
PXI-665x timing and triggering modules and NI-Sync instrument driver
software.
Switching Execution Targets

By default, LabVIEW selects the development computer as the execution
target. You must switch the execution target to access the FPGA Module
palettes, VIs, functions, and development tools. To select the NI PXI-6653
or NI PXI-6652 timing module as the execution target, select the PXI-665x
FPGA device from the Execution Target pull-down menu in the
LabVIEW dialog box, as shown in Figure 3-1.
Figure 3-1. Switching to the PXI-665x FPGA Device Execution Target

Each FPGA Device corresponding to an NI PXI-6653 or NI PXI-6652

module has a unique VISA Resource Name of the form RIOn::INSTR,
where n is the Reconfigurable I/O interface number of the FPGA device.
Use MAX to associate the VISA Resource Name for an FPGA Device with
its geographic location in the PXI development system, as shown in
Figure 3-2.
Figure 3-2. MAX RIO Device Settings
When you target the FPGA device in LabVIEW, the Embedded Project
Manager window appears. Refer to the FPGA Module documentation for
more information about managing FPGA VIs using the Embedded Project
Manager.
Note Even if the target NI PXI-6653 or NI PXI-6652 is not present, you still can target the
PXI-665x FPGA device to develop an FPGA VI.
Note You can also target NI PXI-6653 and NI PXI-6652 modules residing in remote
systems as FPGA devices using the Remote VISA protocol.

Refer to the FPGA Module documentation for information about good

programming techniques and the VIs, functions, and tools in the FPGA
Module that you need to create efficient FPGA VIs.
Executing FPGA VIs

After you create an FPGA VI, use LabVIEW to compile and download
the FPGA VI to the NI PXI-6653 or NI PXI-6652 FPGA device. Click
the Run button in the Embedded Project Manager window to
automatically compile, download, and run the FPGA VI on the NI
PXI-6653 or NI PXI-6652. Refer to the FPGA Module documentation for
information about compiling, downloading, and running FPGA VIs on
FPGA devices.
Communication with FPGA VIs

After you have an FPGA VI running on the FPGA device, you need
a way to communicate with that VI. Depending on the application
requirements, you can communicate with the FPGA VI interactively
or programmatically. Use Interactive Front Panel Communication to
communicate with the FPGA VI directly from the front panel of the FPGA
VI. Use Programmatic FPGA Interface Communication to communicate
with the FPGA VI from a VI running on the host computer. The VI running
on the host computer is called the host VI.
Interactive Front Panel Communication

Use Interactive Front Panel Communication to communicate with an
FPGA VI targeted to an NI PXI-6653 or NI PXI-6652 with no additional
programming. With Interactive Front Panel Communication, the host
computer displays the FPGA VI front panel, but this VI’s execution target
is selected as the NI PXI-6653 or NI PXI-6652. Refer to the FPGA Module
documentation for more information about communicating with the
NI PXI-6653 or NI PXI-6652 using Interactive Front Panel
Communication.
Note Because the NI PXI-6653 and NI PXI-6652 include internal muxes that you must
enable to allow FPGA VIs to access the fixed I/O resources available to the NI PXI-6653
and NI PXI-6652, including PXI_Trig, PXI_Star, and PFI terminals, you must use the
NI-Sync instrument driver with the FPGA VI applications to enable these connections.
Therefore, you usually need a separate NI-Sync application to connect internal FPGA VI
signals with the corresponding fixed I/O resources. However, because NI-Sync VIs cannot
run with LabVIEW Execution Target set to an FPGA device, you must give special

consideration to NI PXI-6653 or NI PXI-6652 FPGA VIs using Interactive Front Panel

Communication. Refer to the Special Considerations section of this chapter for more
information.
Programmatic FPGA Interface Communication

Use Programmatic FPGA Interface Communication to monitor and control
an FPGA VI programmatically with a separate VI targeted to and running
on the host computer. When you use Programmatic FPGA Interface
Communication, the host VI runs on the host computer and the FPGA VI
is programmatically downloaded to the NI PXI-6653 or NI PXI-6652.
Use the FPGA Interface functions available when you target LabVIEW for
Windows or an RT target to create a host VI that communicates with the
FPGA VI and performs other required functions, such as NI-Sync
instrument driver terminal connections. Refer to the FPGA Module
documentation for more information about creating host VIs.
Note Programmatic FPGA Interface Communication helps control FPGA VIs targeted to
an NI PXI-6653 or NI PXI-6652, because the NI-Sync instrument driver is usually required
to enable internal connections between FPGA VI internal I/O signals and the fixed
I/O resources available to NI PXI-6653 and NI PXI-6652 devices. Programmatic FPGA
Interface Communication allows multiple VIs to run on the host computer, a feature
that is not available when you target an FPGA device using Interactive Front Panel
Communication. Refer to the Special Considerations section of this chapter for more
information about using FPGA Interface Communication with the NI-Sync instrument
driver.
Special Considerations
This section describes special considerations when developing FPGA VIs
for the NI PXI-6653 or NI PXI-6652 using LabVIEW and the FPGA
Module.
FPGA Device I/O Functions

The FPGA Device I/O functions in the FPGA Module correspond to
the fixed I/O resources on the FPGA device. For the NI PXI-6653 and
NI PXI-6652, the fixed I/O resources include digital inputs and digital
outputs. When the FPGA VI runs on the FPGA device, it performs the
I/O operations in hardware. Refer to the FPGA Module documentation
for detailed information about using Device I/O functions.

An FPGA device might include multiple I/O resources of the same type.
Each individual I/O resource is a terminal on the FPGA device. You
can configure the FPGA Device I/O functions to read or write as many
terminals as are available on the FPGA device. Refer to Table 3-1 for a list
of all available I/O terminals for the NI PXI-6653 and NI PXI-6652.
Table 3-1. FPGA Device I/O Resources for

the NI PXI-6653 and NI PXI-6652
Terminal Description
Digital Inputs
PFIn Front panel PFI digital input channel n, where n
is the PFI front panel connector number.
PXI_Trign PXI backplane PXI_Trig digital input channel
n, where n is the PXI trigger line number.
PXI_Starn PXI backplane PXI_Star digital input channel n,
where n is the PXI Star trigger line number.
Note: The PXI-665x does not have access to the
PXI Star lines when not in Slot 2 of the PXI
chassis. Reading from PXI_Starn when not in
Slot 2 of the PXI chassis results in reading Local
Bus Left line n of the PXI backplane.
PXI_Clk10 PXI_Clk10 digital input channel.
Digital Outputs
PFIn_Internal Front panel PFI digital output n, where n is the
PFI front panel connector number. The internal
signal is not driven onto the PFIn output pin
until this internal terminal is connected to the
physical PFIn using the NI-Sync instrument
driver. Use the Digital Input function to read the
value you want to write to this internal signal.

Table 3-1. FPGA Device I/O Resources for

the NI PXI-6653 and NI PXI-6652 (Continued)
Terminal Description
PXI_Trign_Internal PXI backplane PXI_Trig digital output n, where
n is the PXI trigger line number. The internal
signal is not driven onto the PXI_Trign output
pin until this internal terminal is connected to
the physical PXI_Trign using the NI-Sync
instrument driver. Use the Digital Input function
to read the value you want to write to this
internal signal.
PXI_Starn_Internal PXI backplane PXI_Star digital output n,
where n is the PXI Star trigger line number.
The internal signal is not driven onto the
PXI_Starn output pin until this internal terminal
is connected to the physical PXI_Starn using the
NI-Sync instrument driver. Use the Digital Input
function to read the value you want to write to
this internal signal.
Note: The PXI-665x does not have access to the
PXI Star lines when not in Slot 2 of the PXI
chassis. Writing to PXI_Starn_Internal when
not in Slot 2 of the PXI chassis will result in
writing Local Bus Left line n of the PXI
backplane.
Arbitration
The NI PXI-6653 and NI PXI-6652 FPGA devices support arbitration on
the digital I/O resources. Configure the arbitration for the I/O resources
using the Arbitration tab of the Configure dialog box for the FPGA
Device I/O function you use. Refer to the FPGA Module documentation
for more information about resource arbitration.
Trigger Input Synchronization to PXI_Clk10

The NI PXI-6653 and NI PXI-6652 FPGA devices support synchronizing
trigger inputs to the PXI 10 MHz backplane clock (PXI_Clk10). Configure
triggers to be synchronized to this clock using the I/O Synchronization tab
of the Configure dialog box for the FPGA Device I/O function you use.
Select the Synchronize to PXI_Clk10 option to enable this feature.

Connecting FPGA Device Digital Outputs to Physical

Terminals
When connecting FPGA device digital output terminals on a NI PXI-6653
or NI PXI-6652, take special care to ensure that the digital outputs are
properly connected to the physical pins corresponding to the digital
outputs. This section explains how to interface between LabVIEW FPGA
digital outputs functions and the physical terminals corresponding to those
output functions.
Inside the NI PXI-6653 and NI PXI-6652 FPGA devices, output

multiplexers correspond to each destination terminal. When you place a
digital output function on an FPGA VI block diagram, you indicate to
connect the FPGA signal for the digital output to an internal pin
corresponding to that terminal. This internal pin, referred to as the
LabVIEW FPGA Trigger, is a source input to the output multiplexer
corresponding to the destination terminal. The LabVIEW FPGA trigger
can be any of the following NI-Sync inputs: PXI_Trign_Internal,
PXI_Starn_Internal, and PFI0_Internal. The NI-Sync instrument driver
controls connections through this output multiplexer.
PFI 0:5
PXI_Star 0:12
PXI_Trig0
PXI_Trig 0:7
LabVIEW FPGA Trigger
Enable via NI-Sync
Figure 3-3. Output Multiplexer for PXI_Trig0 Terminal
For example, consider an FPGA VI that needs to connect a signal to the

PXI_Trig0 terminal. To enable this connection, you must first include a
digital output corresponding to the PXI_Trig0_Internal terminal in the
FPGA VI block diagram. Refer to Figure 3-4 for an example.
Figure 3-4. FPGA VI Digital Output Function for PXI_Trig0
After compiling, downloading, and running this FPGA VI on an

NI PXI-6653 or NI PXI-6652 device, you must connect the LabVIEW
FPGA internal PXI_Trig0 terminal to the physical PXI_Trig0 terminal by

enabling the output multiplexer for the physical PXI_Trig0 terminal using
the internal LabVIEW FPGA terminal as the source. Refer to Figure 3-3 for
a block diagram of this multiplexer connection.
To enable the connection between the internal LabVIEW FPGA terminal

for PXI_Trig0 and the physical PXI_Trig0 terminal, use the NI-Sync
instrument driver, as shown in Figure 3-5. There is one internal source
terminal for each digital output that a LabVIEW FPGA block diagram can
connect to. These LabVIEW FPGA internal signals are connected to the
corresponding physical terminals using the NI-Sync Connect Trigger
Terminals VI.
Figure 3-5. NI-Sync VI for Enabling PXI_Trig0 Connection

from LabVIEW FPGA Digital Output
Programmatic FPGA Interface Communication

This section explains the basics of using FPGA Interface communication
from a host VI with a NI PXI-6653 or NI PXI-6652 and the NI-Sync
instrument driver. Refer to the FPGA Module documentation for more
information about using the FPGA Interface functions.
Because FPGA VIs running on NI PXI-6653 and NI PXI-6652 devices may

control digital output terminals, FPGA Interface communication provides
a convenient interface for controlling an FPGA VI and any required
NI-Sync terminal connections from the same host VI.
External VISA Input

When you use the Open FPGA VI Reference function to establish
communication with an FPGA VI, right-click the function and select
External VISA Input from the shortcut menu to add the VISA Resource
Name input to the Open FPGA VI Reference function, as shown in
Figure 3-6.
The VISA Resource Name you supply to this function is the VISA
Resource Name of the FPGA device you want to communicate with.
Use MAX to determine the VISA Resource Name of your NI PXI-6653
or NI PXI-6652. Refer to Figure 3-2 for an example.

Note You can use the same VISA Resource Name with both the Open FPGA VI
Reference function and the NI-Sync instrument driver Initialize function.
Figure 3-6. External VISA Input Option for Open FPGA VI Reference Function

Synchronizing Multiple
4
NI PXI-4472 Modules
The NI PXI-665x Timing and Synchronization Module enables you to pass
PXI timing and triggering signals between two or more PXI chassis. This
module is especially useful for synchronizing acquisitions involving large
numbers of NI PXI-4472 Dynamic Signal Acquisition modules. Tight
multichassis synchronization guarantees simultaneous sampling and
minimal interchannel phase mismatch in high-channel-count systems.
This chapter describes four typical hardware configurations where the

NI PXI-665x enables synchronization for NI PXI-4472 Dynamic Signal
Acquisition (DSA) modules in one or more PXI chassis. The necessary
hardware, signal connections, and example code are described for each
configuration.
NI highly recommends that you thoroughly review the Theory of

Operation: Synchronizing Data Acquisition Across Multiple NI PXI-4472
Modules section before running the application examples or starting your
application development. The main goal of this section is to familiarize you
with the NI PXI-4472 synchronization signals and with how the
NI PXI-665x hardware can extend this synchronization beyond a single
PXI chassis. After familiarizing yourself with the concepts described here,
move on to the LabVIEW or LabWindows/CVI example programs before
beginning your software development.
The NI PXI-665x User Manual, NI PXI-4472 documentation, and remote

chassis link (such as MXI-3) documentation might be useful to you as you
read this document. You can download these documents from
ni.com/manuals.
Theory of Operation: Synchronizing Data Acquisition

Across Multiple NI PXI-4472 Modules
The following sections provide low-level background information about
the electrical signals needed to synchronize NI PXI-4472 modules.
The Synchronizing Signals for Multiple NI PXI-4472 Modules in a Single

Chapter 4 Synchronizing Multiple NI PXI-4472 Modules
Chassis section describes the signals required to synchronize an acquisition

when all NI PXI-4472 modules reside in the same PXI chassis. No
NI PXI-665x is required in this case. The Using the NI PXI-665x to Route
Synchronization Signals between Multiple Chassis section discusses
synchronization where NI PXI-4472 modules are physically located in two
or more PXI chassis. In a multichassis system, two or more NI PXI-665x
modules generate and route the necessary signals to synchronize all
NI PXI-4472 channels in the system. The NI-Sync software package
includes application examples that address three multichassis cases as well
as a single-chassis case.
Synchronizing Signals for Multiple NI PXI-4472 Modules in a Single

Chassis
This section describes the synchronization between NI PXI-4472 modules
housed in a single PXI chassis. This section introduces three signals:
the oversample clock, the SYNC pulse, and the acquisition start trigger.
The Using the NI PXI-665x to Route Synchronization Signals between
Multiple Chassis section frequently refers to these signals.
Delta-Sigma ADCs and the Oversample Clock

The 24-bit A/D converters (ADCs) employed on the NI PXI-4472 belong
to a class of components called delta-sigma (or ∆Σ) ADCs. The advantages
of delta-sigma components as compared to other digitizers include high
dynamic range, excellent linearity, and digital filtering to remove aliased
frequency components from the data.
Most ADCs, including the successive approximation ADCs used in many

data acquisition (DAQ) devices, are timed by a sample clock. This clock is
simply a digital pulse train that drives the acquisition. In most cases, a
rising edge on the sample clock signal starts a conversion. When an ADC
is timed by a sample clock, the acquisition rate is equal to the frequency of
the sample clock. For example, a 10 kHz sample clock produces a 10 kS/s
acquisition rate.
One distinguishing feature of delta-sigma converters, including those on

the NI PXI-4472, is that they use an oversample clock to drive the
conversion. As the name implies, the physical frequency of the oversample
clock signal is greater than the sample rate. When a single NI PXI-4472
acquires data, the high-frequency oversample clock is locally generated by
a Direct Digital Synthesis (DDS) chip on the device. If two or more
NI PXI-4472 modules are run in a single PXI chassis, they must share the
oversample clock to provide a tightly synchronized acquisition.

When sharing this clock, one module becomes the “clock master,” and the
other modules become the “clock slaves.” The clock master module must
be placed in Slot 2 of the PXI chassis. The clock master uses the DDS chip
to produce the oversample clock and drive its own acquisition. The clock
master also exports the oversample clock to the PXI star trigger bus.
Figure 4-1 shows a LabVIEW code snippet that illustrates how to export
the oversample clock to a clock slave module in PXI Slots 3 and 4.
Figure 4-1. Exporting the Oversample Clock to PXI_Star
You now order each clock slave device to import the oversample clock from
PXI_Star to drive its ADCs. Figure 4-2 shows the LabVIEW code snippet
for this operation.
Figure 4-2. Importing the Oversample Clock to Drive Slave ADCs
On the NI PXI-4472, the ratio between the oversample (fos) clock and the
sample rate (fs) can have one of two possible values, depending on the
sample rate. Table 4-1 shows the possible values.
Table 4-1. Relationship between the Sample Rate and Oversample Clock
Sample Rate Oversample Clock

fs ≤ 51.2 kS/s fos = 256 × fs
fs > 51.2 kS/s fos = 128 × fs
The highest possible oversample frequency for the NI PXI-4472 occurs at

either fs = 51.2 kS/s or fs = 102.4 kS/s. In both cases, the oversample rate is
slightly faster than 13.1 MHz.

Most delta-sigma converters, including those on the NI PXI-4472, require

a very steady frequency for the oversample clock. The DDS chip on the
NI PXI-4472 has good frequency characteristics and fulfills this need.
However, arbitrarily changing frequencies, such as those from tachometers,
generally do not work well with delta-sigma ADCs. For this reason, the
NI PXI-4472 and other National Instruments DSA products do not support
external clocking from arbitrary signal sources. This constraint also applies
when you use one or more NI PXI-665x modules for synchronization with
NI PXI-4472 devices.
The NI PXI-4472 SYNC Pulse

As discussed in the Delta-Sigma ADCs and the Oversample Clock section,
the oversample clock is many times faster than the actual acquisition rate
of the NI PXI-4472. Using the concepts described in that section, you can
share the oversample clock between two or more NI PXI-4472 modules.
This sharing guarantees that both modules sample at the same frequency
and that there will be no drift between their acquisitions. However,
oversample clock sharing does not guarantee that the samples on both
modules are acquired at exactly the same time. Figure 4-3 illustrates the
oversample pulse trains on two NI PXI-4472 modules sampling at
102.4 kS/s. In this example, there is a delay between acquisition samples of
five oversample intervals, or about 350 ns. This delay may be any value up
to a whole sample interval, which is about 10 µs at this acquisition rate.
tp ≈ 70 ns
Data Returned
NI 4472 #1
Data Returned
NI 4472 #2
Sample Delay ≈ 350 ns
Figure 4-3. Sample Delay between NI PXI-4472 Modules After Receiving

a Shared Oversample Clock
The solution to the clock-delay issue is to configure the master device to

issue a SYNC pulse before the acquisition. The clock master sends a single
active-low, or inverted, pulse on the PXI_Trig5 line, the dedicated line for

the SYNC pulse. The ADCs in the clock master and clock slaves receive
this pulse nearly simultaneously. The SYNC pulse forces all the ADCs to
a reset state, emptying their digital filters and synchronizing their clock
dividers. After exiting the reset state, all NI PXI-4472 modules in the
chassis run at the same frequency and have minimal phase difference
between sample clocks. Figure 4-4 illustrates how this technique
minimizes the sample delay.
Data Returned
NI 4472 #1
Data Returned
NI 4472 #2
Figure 4-4. NI PXI-4472 Modules with Shared Oversample Clock

Using the SYNC Pulse
The NI PXI-4472 cannot acquire data while it is in the reset state that
occurs immediately after it receives the SYNC pulse. During this period,
the ADC returns only zeros. The length of the reset period Treset (in
samples) is a function of sample rate. Table 4-2 shows the possible lengths
of the reset period.
Table 4-2. Reset Period as a Function of Sample Rate
Sample Rate Reset Period (Treset )

fs ≤ 51.2 kS/s Treset = 8,960 samples
fs > 51.2 kS/s Treset = 17,920 samples
When all NI PXI-4472 modules are housed in a single chassis, the SYNC
pulse is automatically handled by NI-DAQ, the NI driver software for DAQ
hardware. Therefore, you do not need to make an explicit software call to
generate or route the SYNC pulse. However, you must make specific calls
to the NI PXI-665x modules in all chassis to properly generate and route
the SYNC pulse when configuring a multichassis system. These calls are
discussed in the Using the NI PXI-665x to Route Synchronization Signals
between Multiple Chassis section.

The Acquisition Start Trigger

After sharing the oversampling clock and issuing the SYNC pulse, the
ADCs on every NI PXI-4472 in the system run in lock-step. At this point,
the only remaining task is to synchronize the beginning of the data
acquisition on each NI PXI-4472.
In the Sharing the Oversample Clock between Chassis and Sharing the
SYNC Pulse between Chassis sections, clock master and clock slave
modules were discussed. Because the oversample clock is carried on the
PXI star trigger lines, the clock master module must always reside in Slot 2.
This concept of master and slave devices is also useful when discussing the
acquisition start trigger. Exactly one module should be the “trigger master,”
while all the other NI PXI-4472 modules are “trigger slaves.” However, the
trigger master can reside in any PXI slot; it is not limited to Slot 2.
Therefore, the clock master and trigger master are not necessarily the same
module.
First, configure all trigger slave NI PXI-4472 modules to start their

acquisitions on a digital trigger from a PXI_Trig line. You can
choose PXI_Trig<0..4> for the start trigger; the choice of PXI_Trig0 line
for this example is arbitrary. Figure 4-5 shows how to wire a trigger cluster
to the AI Start VI to accomplish this task.
Figure 4-5. Starting the Acquisition on a Trigger Slave
Next, direct the trigger master to export a pulse to PXI_Trig0 when it begins
acquiring. This pulse, in turn, triggers all the slaves. Figure 4-6 shows the
LabVIEW code snippet used to configure the trigger master.
Figure 4-6. Routing the Start Trigger and Starting the Acquisition on the Trigger Master

The code in Figure 4-6 uses immediate software triggering for the trigger
master NI PXI-4472. However, you could easily change the triggering
parameters on the trigger master AI Start VI to use external digital or
analog triggering.

Multiple Chassis
The Synchronizing Signals for Multiple NI PXI-4472 Modules in a Single
Chassis section discussed why the oversample clock, SYNC pulse, and
acquisition start trigger are necessary and addressed the software calls
needed to share these signals between NI PXI-4472 modules residing in a
single PXI chassis. This section explains how the NI PXI-665x enables you
to expand the channel count of your system by sharing these same three
signals among multiple chassis.
Sharing the Oversample Clock between Chassis

In a single-chassis synchronized DSA system, the clock master
NI PXI-4472 generates the oversample clock and distributes it to the clock
slave modules. When the DSA system consists of multiple PXI chassis,
the NI PXI-665x in the master chassis generates the oversample clock and
distributes it to all the NI PXI-4472 modules. Thus, every DSA device in a
multichassis system is a clock slave; you do not define a clock
master NI PXI-4472.
First, consider a system with either two or three chassis where each chassis
contains an NI PXI-665x in Slot 2 and several NI PXI-4472 modules. One
NI PXI-665x is defined as the NI PXI-665x master. This module uses its
DDS chip to generate the appropriate oversample clock. The NI PXI-665x
master is also responsible for distributing the oversample clock to all the
other “slave” chassis. Each NI PXI-665x (both master and slave) must route
the oversample clock to the PXI backplane so that it can drive the ADCs on
the NI PXI-4472 modules housed in the chassis. Refer to Figure 4-17 for
an illustration of the hardware setup for this configuration.
In this block diagram, the NI PXI-665x in the top chassis is the master,
while the NI PXI-665x modules in the other two chassis are slaves. The
master connects to both slaves. Notice that the master includes one cable
that “loops back” to itself. This loopback guarantees that the oversample
pulse train travels over a similar path before reaching the PXI star trigger
bus on both backplanes. As the pulse travels along the coaxial cable and
through the circuitry on the NI PXI-665x, it creates a significant

propagation delay. The loopback minimizes this timing difference and

ensures symmetry between the paths to the backplane of each chassis.
The code snippet shown in Figure 4-7 programs the master NI PXI-665x
to generate a frequency of 13.1072 MHz, the oversample frequency
corresponding to an NI PXI-4472 sampling rate of either 51.2 kS/s or
102.4 kS/s. The code then routes the signal to three front panel pins: PFI 1,
PFI 2, and PFI 4. PFI 1 is connected to PFI 0, while PFI 2 and PFI 4
connect to the NI PXI-665x modules in the second and third chassis,
respectively. PFI stands for Programmable Function Interface. These pins
are discussed in more detail in the NI PXI-665x User Manual.
Figure 4-7. Generating and Routing the Oversample Frequency
Next, both the master and slave NI PXI-665x modules must import the
oversample clock signal on PFI 0 and route it to the appropriate PXI star
trigger lines. This routing is an asynchronous operation. Asynchronous
routing means that the signal follows a short path from the PFI input to the
PXI star trigger bus and that the NI PXI-665x hardware does not actively
adjust the phase or timing of the signal. The code shown in Figure 4-8
routes the oversample clock from PFI 0 to NI PXI-4472 boards in Slots 3
through 5.
Figure 4-8. Routing the Oversample Clock Using the PXI Star Trigger Bus

All NI PXI-4472 modules in the system then import this oversample clock
from their local PXI star lines. The LabVIEW code snippet used to import
the clock is shown in Figure 4-9.
Figure 4-9. Importing the Oversample Clock from PXI_Star
Sharing the SYNC Pulse between Chassis

The SYNC pulse is an active-low signal on PXI_Trig5 that resets the
internal clock dividers in the NI PXI-4472 ADCs and minimizes phase
mismatch across devices. When all NI PXI-4472 modules are in a single
chassis, NI-DAQ automatically handles the SYNC signal. In a multichassis
DSA system, however, you must include code to explicitly handle the
SYNC pulse using the NI PXI-665x.
The master NI PXI-665x is responsible for issuing the SYNC. This signal
is an active-low pulse, so the NI PXI-4472 ADCs reset when they receive a
falling edge on PXI_Trig5.
All the generation and routing of the SYNC is performed synchronously

with the oversample clock. This synchronous routing means that the edges
of the SYNC pulse precisely line up with the edges of the oversample clock.
Synchronous routing allows the NI PXI-665x in the master chassis to issue
the SYNC directly to PXI_Trig5 without requiring a loopback scheme like
that of the oversample clock. Instead, the master NI PXI-665x actively
delays the pulse based on the cable length between chassis. The code
snippet in Figure 4-10 prepares the master to issue the SYNC pulse to PFI3
and PFI5 (physically cabled to PFI 1 on the two slave chassis) and to the
local PXI_Trig5 line. The code includes delay on the master to compensate
for propagation delay through 5 m of coaxial cable.

Figure 4-10. Compensating for Propagation Delay on the SYNC Pulse
Each slave NI PXI-665x then routes the incoming SYNC pulse on PFI1 to
the PXI_Trig5 line as shown in Figure 4-11.
Figure 4-11. Routing the SYNC Pulse
Note The previous code snippets illustrate how to set up the routing for the NI PXI-4472
SYNC pulse. They guarantee that when the pulse is generated, it propagates with minimal
skew to all the NI PXI-4472 modules in the system. A subsequent subVI that is not shown
in the code snippets actually issues the SYNC pulse.
Sharing the Acquisition Start Trigger between

Chassis
The last signal you must pass between chassis is the start trigger, used to
initiate the NI PXI-4472 acquisition. Unlike the oversample clock and the
SYNC pulse, the trigger is actually generated by an NI PXI-4472, not by
an NI PXI-665x. The trigger master (the NI PXI-4472 that generates the
trigger signal) can be any NI PXI-4472 residing in the master chassis.
As with the single-chassis case, this trigger master can initiate a system
acquisition based on an immediate software trigger or an external digital or
analog trigger.
The start trigger is passed asynchronously. Asynchronous routing means

there is no compensation for cable propagation time between the master
and slave chassis. The trigger signal is automatically resynchronized to
the sample clock (as opposed to the faster oversample clock) when it is

received on each NI PXI-4472 device. For cables shorter than about 30 m,

the trigger signal arrives within the same sample interval on both chassis,
guaranteeing tight synchronization. However, the trigger signal arrives one
sample later on the slave chassis for cables longer than about 30 m. There
are comments highlighting this effect in the DSA example programs. If you
do use long cables, the easiest solution is simply to acquire one more
sample on the master chassis than on the slaves and to discard the first
sample on the master. This “software data realignment” compensates for
the asynchronous trigger delay. If you notice a significant phase mismatch
between the same signal acquired on each chassis with long cables, you
should try to use the data realignment technique to correct the issue. This
behavior generally is easily noticeable if it is present, usually on the order
of several degrees. For example, consider the case of a 1 kHz tone acquired
at a sampling rate of 100 kS/s. A mismatch of exactly one sample
corresponds to a time difference of 10 µS, or 1% of a sine tone cycle.
Because 360 degrees comprise a full cycle, this error would show up as
3.6 degrees. Notice that the trigger delay never produces an error greater
than one sample interval. Thus, a 60 or 70 m cable still produces a single
sample mismatch, just as would a 30 m cable.
As in the single-chassis case, the trigger master NI PXI-4472 exports the

start trigger signal to PXI_Trig0 (here again, the choice of PXI_Trig line
for passing the trigger is arbitrary). This trigger starts the acquisition on all
NI PXI-4472 modules in the master chassis. The NI PXI-665x in the master
chassis is then responsible for asynchronously routing the start trigger from
PXI_Trig0 to its front panel pins PFI 3 and PFI 5. These same pins were
earlier used to propagate the SYNC pulse. Figure 4-12 shows the
LabVIEW code snippet used to export the start trigger signal.
Figure 4-12. Asynchronously Routing the Start Trigger to the PFI Pins
Each slave NI PXI-665x then routes the incoming pulse on PFI1 to

PXI_Trig0. Again, this operation is performed asynchronously.
Figure 4-13 shows the code snippet you need to route the signal.

Figure 4-13. Routing the Incoming Start Trigger to PXI_Trig0
With respect to the acquisition triggering, the NI PXI-4472 modules

operate exactly as they do in a single-chassis synchronized system. The
slaves digitally trigger from PXI_Trig0. Figure 4-14 shows the LabVIEW
code snippet that you can use to digitally trigger from PXI_Trig0.
Figure 4-14. Digital Trigger from PXI_Trig0 on Trigger Slave
The master exports its start trigger signal to PXI_Trig0. This operation is
shown in Figure 4-15.
Figure 4-15. Exporting a Start Trigger to PXI_Trig0 on Trigger Master
In this case, the master starts with an immediate software trigger. However,
you could easily modify the parameters for the AI Trigger Config VI on the
master to enable external digital or analog triggering.

Configuring the Chassis

The following sections provide information for configuring the hardware
for four use cases:
• Configuration #1: One Chassis with Synchronized Acquisition and
One CPU
• Configuration #2: Two or Three Chassis with Synchronized
Acquisition and One CPU
• Configuration #3: Four or More Chassis with Synchronized
Acquisition and One CPU
• Configuration #4: Two Chassis with Synchronized Acquisition
and Two CPUs
Determine which configuration you will use and refer to that section for
more information.
Note The following system configurations use 1 m SMB-SMB cables for sharing clock
and trigger signals between chassis. You can use longer cables if desired; refer to the
NI PXI-665x User Manual for the maximum cable length specifications. However, to attain
the tightest possible synchronization, it is important that you maintain equal length for all
cables in the system and compensate for cable propagation delays in your software.
Software compensation for the SYNC pulse is necessary for all cable lengths. Acquisition
start trigger compensation is needed for cables longer than about 30 m. The shipping
examples for multichassis DSA systems address cable compensation, and it is also
described in the Using the NI PXI-665x to Route Synchronization Signals between
Multiple Chassis section.
Configuration #1: One Chassis with Synchronized Acquisition and

One CPU
This configuration allows synchronization between NI PXI-4472 modules
housed in a single PXI chassis. The NI PXI-665x in PXI Slot 2 provides the
oversample clock and SYNC pulse for the modules. Notice that a single
chassis application does not actually require an NI PXI-665x. The same
requirements can be fulfilled (with somewhat simpler software) using only
NI PXI-4472 modules in a single chassis. These single-chassis examples
are included to provide tutorials or “stepping stones” before proceeding to
a multichassis system that requires the NI PXI-665x and the NI-Sync
driver.

The following LabVIEW and LabWindows/CVI example programs are

provided for this configuration.
LabVIEW
• The niSync_DSA Example Single Chassis VI—This example
illustrates a finite acquisition using an NI PXI-665x device to
synchronize two or more NI PXI-4472 devices in a single chassis.
It uses high-level VIs to control the NI PXI-665x and NI PXI-4472
modules.
• The niSync_DSA Example 1 Chassis [Low Level] VI—This example
illustrates a finite acquisition synchronizing NI PXI-4472 devices in a
single chassis. Unlike the other single-chassis LabVIEW example, this
program relies on low-level VIs to control the hardware. This produces
a larger and more intricate block diagram. The code is less modular
and hierarchical than in the high-level LabVIEW examples.
LabWindows/CVI
• Single Chassis Finite Acq—This example illustrates a finite
acquisition using an NI PXI-665x device to synchronize two or more
NI PXI-4472 devices in a single chassis. This program does not
include a LabWindows/CVI graphical user interface (GUI), so you can
quickly adapt it to work with Microsoft Visual C++ or other ANSI C
environments.

What You Need to Get Started

To set up and use Configuration #1, you need the following items:
❑ One PXI chassis

❑ CPU
The CPU can be an embedded PXI controller running
Windows 2000/XP, or it can be a desktop computer running
Windows 2000/XP with an installed remote chassis link (such as
MXI-3). The embedded controller or remote link module should
be installed in Slot 1 of the chassis.
❑ One NI PXI-6653 or NI PXI-6652 installed in Slot 2 of the PXI chassis

❑ Two or more NI PXI-4472 modules. Place the NI PXI-4472 modules
in any available PXI slot numbered 3 to 15.
Note Do not install the NI PXI-4472 in Slots 16, 17, or 18 of an 18-slot chassis. You
cannot route the oversample clock to those slots.
❑ One 1 m SMB-200 cable

❑ One 1 kHz sine source (function generator), for testing phase match
between chassis
Note The function generator is not required, but it is highly recommended for testing
purposes.
Connecting the NI PXI-665x Device

Use an SMB-200 cable to connect PFI 0 to PFI 1 on the NI PXI-665x.
This cable loops back to connect two external pins on the same device.
Connecting the NI PXI-4472 Devices

Connect the external sine signal to a single input channel on one
NI PXI-4472 in each chassis. The same signal should be fed to each chassis
to measure the phase mismatch and verify that the synchronization is
within specifications.
Configuring and Running the Software Example

After the hardware has been configured, launch MAX. Verify that all
NI PXI-4472 modules are recognized and properly functioning and that
the NI PXI-665x module is recognized.

Using the niSync_DSA Example Single Chassis VI

Like the other high-level NI-Sync DSA examples, this program relies on
modular subVIs to provide a level of abstraction from the driver calls that
directly control the NI PXI-665x and NI PXI-4472 devices. All the
high-level DSA examples share a nested configuration cluster labeled
Systems Settings. This is a flexible data structure that allows you to
precisely describe your hardware configuration before running the
example. Figure 4-16 shows the System Settings cluster for the
niSync_DSA Example Single Chassis VI.
1 2
1 NI PXI-665x Master 2 NI PXI-4472 Trigger Master 3 NI PXI-4472 Trigger Slaves
Figure 4-16. System Settings Cluster for the niSync_DSA Example Single Chassis VI
• NI PXI-665x Master—Enter the VISA Resource Name for the

NI PXI-665x in the master chassis. The control labeled 6653s in
master chassis is actually an array, although in this particular example
the array index control is not shown. The reason for this is that the
single-chassis configuration implies only a single NI PXI-665x in the
system.

• NI PXI-4472 Trigger Master—A single NI PXI-4472 is responsible

for issuing the acquisition trigger signal to start the data acquisition on
every NI PXI-4472 in the system. The trigger master can use any of its
three trigger modes (software trigger, external analog trigger, external
digital trigger on EXT Trig pin).
• NI PXI-4472 Trigger Slaves—This is an array of clusters with one
element per board. All NI PXI-4472 devices except the one responsible
for issuing the trigger are described here.
After filling in the System Settings cluster, you should set the desired
sampling rate and run the example. To test the quality of the
synchronization between NI PXI-4472 devices, connect a common 1 kHz
sine tone to the first input channel on the trigger master and the first input
channel on the first trigger slave. A phase mismatch result of less than 0.01°
indicates excellent synchronization.
Using the niSync_DSA Example 1 Chassis

[Low Level] VI
The niSync_DSA Example 1 Chassis [Low Level] VI is simpler and less
modular than the high-level single-chassis example described above. It
uses only a software trigger (the code does not illustrate analog or external
digital hardware triggering).
Enter all NI PXI-4472 device numbers in the array labeled 4472 Device
Numbers. Notice that the trigger master is defined as the first device
number appearing in this array. Next, fill in the PXI slot numbers for the
NI PXI-4472 devices (typically, the device numbers equal the slot
numbers).
To test the quality of the synchronization between NI PXI-4472 devices,

connect a common 1 kHz sine tone to the first input channel on the trigger
master and the first input channel on the first trigger slave. A phase
mismatch result of less than 0.01° indicates excellent synchronization.
Using niSync_DSA_Example Single Chassis

(LabWindows/CVI Example Project)
This simple example is configured to synchronize two NI PXI-4472
devices in one chassis using an NI PXI-665x to deliver the oversample
clock and SYNC pulse. This program does not include a LabWindows/CVI
GUI. Instead, it uses the Standard I/O window for user interaction.

The code contains several hardwired values that may need to be changed to
accommodate your particular hardware setup:
• The NI PXI-665x VISA Resource Name is set to PXI3::15::INSTR.
• The NI PXI-4472 devices are numbered 3 and 4 and reside in
PXI Slots 3 and 4.
• Data is acquired from the first channel on each NI PXI-4472. The
numChan variable controls how many channels (starting with ACH0)
should acquire data on each DSA device.
• The sampling rate is 102.4 kS/s.
These constants are defined at the beginning of the main code block and
should be changed as needed.
master and the first input channel on the first trigger slave. A phase
mismatch result of less than 0.01° indicates excellent synchronization.
When the program is run, the phase mismatch is displayed in the
I/O window.
Configuration #2: Two or Three Chassis with Synchronized Acquisition

and One CPU
This configuration enables synchronization between NI PXI-4472 modules
housed in two or three PXI chassis. It assumes that only one CPU controls
the acquisition. The CPU can be either a desktop PCI machine with a
MXI-3 link or an embedded PXI controller in the master chassis.
The following LabVIEW and LabWindows/CVI example programs are

provided for this configuration.
LabVIEW
• The niSync_DSA Example 2 or 3 Chassis Finite Acq VI—This
example illustrates a finite acquisition synchronized between two or
three chassis. It uses high-level VIs to control the NI PXI-665x and
NI PXI-4472 modules.
• The niSync_DSA Example 2 or 3 Chassis Continuous Acq VI—This
example illustrates a continuous acquisition synchronized between
two or three chassis. It uses high-level VIs to control the NI PXI-665x
and NI PXI-4472 modules.
• The niSync_DSA Example 2 Chassis [Low Level] VI—This example
illustrates a finite acquisition synchronized between two chassis.

Unlike the other examples for this configuration, it relies on low-level

VIs to control the hardware. This produces a larger and more intricate
block diagram. The code is less modular and hierarchical than the
high-level examples.
LabWindows/CVI
• Dual Chassis Finite Acq—This example synchronizes NI PXI-4472
modules across two chassis and performs a finite acquisition. You can
readily modify it to support three chassis. This program does not
include a LabWindows/CVI graphical user interface (GUI), so you can
quickly adapt it to work with Microsoft Visual C++ or other ANSI C
environments.
• Dual Chassis Continuous Acq—This example synchronizes
NI PXI-4472 modules across two chassis and performs a continuous
acquisition. You can readily modify it to support three chassis. This
program does not include a LabWindows/CVI GUI, so you can quickly
adapt it to work with Microsoft Visual C++ or other ANSI C
environments.
• Dual Chassis Finite Acq GUI—This example synchronizes
NI PXI-4472 modules across two chassis and performs a finite
acquisition. It includes a full LabWindows/CVI GUI.

❑ Two or three PXI chassis
Note The chassis containing either the embedded controller or the desktop MXI-3 link is
referred to as Chassis #1. The other chassis are referred to as Chassis #2 and Chassis #3
(if a third chassis is present). In the remainder of this section, the number of chassis present
is called N.
❑ CPU
Windows 2000/XP, or it can be a desktop computer running
Windows 2000/XP with an installed remote chassis link (such as
MXI-3). The embedded controller or remote link module should
be installed in Slot 1 of Chassis #1.

❑ One NI PXI-665x per PXI chassis

Install one NI PXI-665x in Slot 2 of each chassis. The board in the first
chassis must be an NI PXI-6653 or NI PXI-6652.
❑ One or more NI PXI-4472 per PXI chassis

Place the NI PXI-4472 modules in any available PXI slot
numbered 3 to 15.
❑ (N – 1) SMB-210 cables
❑ (N – 1) PXI-to-PXI MXI-3 kits
You should install a MXI-3 PXI module in Slot 1 of Chassis #2 (and
Chassis #3, in a three-chassis system). You can use either fiber-optic or
copper MXI-3 connections.
You also should install MXI-3 PXI modules in any available slot,
except Slot 2, of Chassis #1 (and Chassis #2), with Slot 8 being the
designated slot throughout this document.
❑ One 1 kHz sine source (function generator), for testing phase match
between chassis.
purposes.
Refer to Figure 4-17 for an illustration of the two configurations for a

three-chassis synchronized acquisition using the NI PXI-665x and the
NI PXI-4472.

PC as CPU Embedded PXI Controller

in Master Chassis
1 4 3 2 4
NI PXI-1042 NI PXI-1042
Chassis #1
(master)
2 1 5 1 5
Chassis #2
2 1 5 2 1 5
Chassis #3
1 MXI-3 Cable 3 Embedded PXI Controller 5 SMB-210 Cable

2 NI PXI-665x Module 4 SMB-200 Cable (1 m)
Figure 4-17. Three Chassis with Synchronized Acquisition

(With Either a PC or an Embedded PXI Controller)

Connecting the MXI-3 Devices

Referring to Figure 4-17, complete the following steps to connect the
MXI-3 devices.
1. If you are using a desktop computer, install a MXI-3 cable to connect
the PCI MXI-3 device to the PXI MXI-3 module in Slot 1 of
Chassis #1.
2. Connect the MXI-3 module in Slot 1 of Chassis #2 to the MXI-3
module in Slot 8 of Chassis #1.
♦ Three-chassis system only

device in Slot 8 of Chassis #2.
Refer to the Set Up Your PXI-MXI-3 System document, which is included

with the MXI-3 kit or available for download from ni.com/manuals, for
further details.
Connecting the NI PXI-665x Devices

1. Use an SMB-200 cable to connect PFI 0 to PFI 1 on the NI PXI-665x
of Chassis #1. This cable loops back to connect two external pins on
the same device.
2. Use an SMB-210 cable to connect PFI 2 and PFI 3 on Chassis #1 to
PFI 0 and PFI 1 of Chassis #2, respectively.
♦ Three-chassis system only

3. Use an SMB-210 cable to connect PFI 4 and PFI 5 of Chassis #1 to
PFI 0 and PFI 1 of Chassis #3, respectively.

to measure the phase mismatch and to verify that the synchronization is

After configuring the hardware, launch MAX. Verify that all NI PXI-4472
modules are recognized and properly functioning and that the NI PXI-665x
modules are recognized.

Using the niSync_DSA_Example 2 or 3 Chassis Finite

Acq VI and the niSync_DSA_Example 2 or 3 Chassis
Continuous Acq VI
These two example programs use similar hardware setups and code; the
only major difference between them is that one demonstrates a single-shot
finite acquisition while the other shows a continuous double-buffered
acquisition. Like the other high-level NI-Sync DSA examples, these
programs rely on modular subVIs to provide a level of abstraction from the
driver calls that directly control the NI PXI-665x and NI PXI-4472 devices.
All the high-level DSA examples share a nested configuration cluster
labeled Systems Settings. This is a flexible data structure that allows you
to precisely describe your hardware configuration before running the
example. Figure 4-18 shows the System Settings cluster for the
niSync_DSA_Example 2 or 3 Chassis Finite Acq VI and the
niSync_DSA_Example 2 or 3 Chassis Continuous Acq VI.
1 2 3
6 5 4
1 NI PXI-665x Master 4 NI PXI-4472 Trigger Slaves in Second/Third Chassis

2 Slave Chassis Array Index 5 NI PXI-4472 Trigger Master
3 NI PXI-665x in Slave Chassis 6 NI PXI-4472 Trigger Slaves in First Chassis
Figure 4-18. System Settings Cluster for the niSync_DSA_Example 2 or 3 Chassis

Finite Acq VI and the niSync_DSA_Example 2 or 3 Chassis Continuous Acq VI
• NI PXI-665x Master—Enter the VISA Resource Name for the

master chassis is actually an array. However, in this particular screen

two/three chassis configuration implies only a single NI PXI-665x in
the master chassis.
• Slave Chassis Array Index—Each slave chassis is described by an
element in this array of clusters. This configuration can support one or
two slave chassis.
• NI PXI-665x in Slave Chassis—This control is the VISA Resource
Name for the NI PXI-665x in each slave chassis. This is not an
array—the slave chassis should each have only one NI PXI-665x in
Slot 2.
• NI PXI-4472 Trigger Slaves in Second/Third Chassis—This is an
array describing each NI PXI-4472 in the slave chassis.
• NI PXI-4472 Trigger Master—A single NI PXI-4472 is responsible
for issuing the acquisition trigger signal to start the data acquisition on
every NI PXI-4472 in the system. This board must reside in the master
chassis. The trigger master can use any of its three trigger modes
(software trigger, external analog trigger, external digital trigger on
EXT Trig pin).
• NI PXI-4472 Trigger Slaves in First Chassis—This is an array of
clusters with one element per board. All NI PXI-4472 devices in the
master chassis except the trigger master are described here. The trigger
master is addressed in the NI PXI-4472 Trigger Master control.
Using the niSync_DSA Example 2 Chassis

[Low Level] VI
The niSync_DSA Example 2 Chassis [Low Level] VI is simpler and less
modular than the LabVIEW examples previously described for
synchronizing two or three chassis. This program uses only a software
trigger (the code does not illustrate analog or external digital hardware
triggering).
Enter all the NI PXI-4472 device numbers in the array labeled 4472 Device
Numbers. Notice that the trigger master is defined as the first device
number appearing in this array. The trigger master must reside in the first

(master) PXI chassis. Next, fill in the PXI slot numbers for the NI PXI-4472
devices (typically, the device numbers equal the slot numbers in the first
chassis but are different in the second chassis.).

master and the first input channel on the first NI-PXI-4472 in the slave
chassis. A phase mismatch result of less than 0.01° indicates excellent
synchronization.
Using niSync_DSA_Example Dual Chassis Finite and

niSync_DSA_Example Dual Chassis Continuous Acq
(LabWindows/CVI Example Projects)
These examples are configured to synchronize two NI PXI-4472 devices in
two separate PXI chassis. NI PXI-665x devices in Slot 2 of each chassis
share the oversample clock, SYNC pulse, and acquisition start trigger.
These programs do not include a LabWindows/CVI GUI; they use the
Standard I/O window for user interaction. The only substantial difference
between these programs is that the first demonstrates a single-shot finite
acquisition, while the second shows a double-buffered continuous
acquisition.
The code contains several hardwired values that may need to be changed to
accommodate your particular hardware setup:
• The VISA Resource Name of the NI PXI-665x in the master chassis is
set to PXI3::15::INSTR.
• The VISA Resource Name of the NI PXI-665x in the slave chassis is
set to PXI4::15::INSTR.
• The NI PXI-4472 in the master chassis is device number 3 and resides
in Slot 3.
• The NI PXI-4472 in the slave chassis is device number 13 and resides
in Slot 3.
• Data is acquired from the first channel on each NI PXI-4472. The
numChan variable controls how many channels (starting with ACH0)
should acquire data on each DSA device.
• The sampling rate is 102.4 kS/s.
These constants are defined at the beginning of the main code block and
should be changed as needed. If additional NI PXI-4472 devices are
required in either chassis, you can add code for them directly after the
existing functions to control the first slave NI PXI-4472. This hardware

configuration can support a second slave chassis if needed. To add a second

slave chassis, you can add code for its NI PXI-665x directly after the
existing functions to control the first slave NI PXI-665x.

connect a common 1 kHz sine tone to ACH0 on the trigger master and
trigger slave. A phase mismatch result of less than 0.01° indicates excellent
synchronization. When the program is run, the phase mismatch is displayed
in the I/O window.
Using niSync_DSA_Example Dual Chassis Finite GUI

(LabWindows/CVI Example Project)
This example is configured to synchronize two NI PXI-4472 devices in two
separate PXI chassis. NI PXI-665x devices in Slot 2 of each chassis share
the oversample clock, SYNC pulse, and acquisition start trigger. This
program includes a standard LabWindows/CVI GUI with callback user
interface callback functions. If additional NI PXI-4472 devices are required
in either chassis, you can add code for them directly after the existing
functions to control the first slave NI PXI-4472. Data is acquired from the
first channel on each NI PXI-4472. The numChan variable controls how
many channels (starting with ACH0) should acquire data on each DSA
device.
This hardware configuration can support a second slave chassis if needed.

To add a second slave chassis, you can add code for its NI PXI-665x
directly after the existing functions to control the first slave NI PXI-665x.
After running the program and setting the controls on the GUI to match
your hardware configuration, click the Acquire button to perform a
single-shot acquisition on both NI PXI-665x devices.

connect a common 1 kHz sine tone to ACH0 on the trigger master and
trigger slave. A phase mismatch result of less than 0.01° indicates excellent
synchronization. The phase mismatch between the two DSA boards is
displayed on the Phase Mismatch GUI indicator. Click Acquire to perform
additional single-shot acquisitions as desired.
Configuration #3: Four or More Chassis with Synchronized Acquisition

and One CPU
housed in four or more PXI chassis. Like the previous configuration, this
configuration assumes that only one CPU controls the acquisition, so there

is no separate embedded PXI controller for each chassis. This CPU may be
either a desktop PCI machine with a MXI-3 link or an embedded PXI
controller.
A LabVIEW example is provided for this configuration. The example

program is called niSync_DSA_Example N Chassis. It uses high-level
VIs to illustrate a finite acquisition.

❑ Four or more PXI chassis
Note The chassis containing either the embedded controller or the desktop MXI-3 link
is referred to as Chassis #1. The other chassis are referred to as Chassis #2 through
Chassis #N. In the remainder of the section, the number of chassis present is called N.
❑ CPU
Windows 2000/XP or a desktop computer running Windows 2000/XP
with a remote chassis link (such as MXI-3). Install the embedded
controller or remote link module in Slot 1 of Chassis #1.
❑ Several NI PXI-665x modules

You will need one module per chassis, plus an additional module for
every three chassis after the first three chassis. Table 4-3 shows the
relationship between chassis and modules.
Table 4-3. Number of Chassis and Required Number of NI PXI-665x Modules
Number of NI PXI-665x
Number of PXI Chassis Required
4 5
5 6
6 7
7 9
10 13

Install one NI PXI-665x in Slot 2 of each chassis. Install the remaining

NI PXI-665x modules in the leftmost available slots in the first chassis
(Slot 3, Slot 4, and so on).
Note All NI PXI-665x boards in the first chassis must be NI PXI-6653 or NI PXI-6652
devices.
❑ One or more NI PXI-4472 modules per chassis

Place the NI PXI-4472 modules in any of the available PXI slots
numbered 3 through 15.
❑ (N – 1) SMB-210 cables
❑ (N – 1) PXI-to-PXI MXI-3 kits
Install a MXI-3 PXI device in Slot 1 of each chassis except for
Chassis #1. Then install a MXI-3 PXI device in any available slot of
Chassis #1 through Chassis (N – 1). This slot is designated as Slot 8 for
the remainder of this document.
❑ One 1 kHz sine source (function generator), for testing phase

mismatch between chassis
purposes.
Refer to Figure 4-19 for an illustration of the two configurations for a

four-chassis synchronized acquisition using the NI PXI-665x and the
NI PXI-4472.

NI PXI-1042
Chassis #1 NI PXI-1042
(master)
4 4
3 3
1 5 1
2 2 2 2
Chassis #2
4 4
1 1
Chassis #3
4 4
1 1
2 2
Chassis #4
4 4
1 MXI-3 Cable 3 SMB-200 Cable (1 m) 5 Embedded PXI Controller

2 SMB-210 Cable 4 NI PXI-665x Module
Figure 4-19. Four Chassis with Synchronized Acquisition

Connecting the MXI-3 Devices

Referring to Figure 4-19, complete the following steps to connect the
MXI-3 devices:
1. If you are using a desktop computer, use a MXI-3 cable to connect the
PCI MXI-3 device to the PXI MXI-3 module in Slot 1 of Chassis #1.
module in Slot 1 of Chassis #2.
3. Daisy-chain all remaining chassis. Start by connecting the MXI-3
module in Slot 8 of Chassis #2 to the MXI-3 module in Slot 1 of
Chassis #3. Continue until each chassis is connected with a MXI-3
cable to Slot 1 of the next chassis.
Refer to the Set Up Your PXI-MXI-3 System document, which is included

with the MXI-3 kit or available for download from ni.com/manuals, for
further details.
Connecting the NI PXI-665x

1. Use an SMB-200 cable to connect PFI 0 to PFI 1 on the NI PXI-665x
in Slot 2 of Chassis #1. This cable “loops back” to connect two
external pins on the same device.
2. Use an SMB-210 cable to connect PFI 2 and PFI 3 on the NI PXI-665x
in Slot 2 of Chassis #1 to PFI 0 and PFI 1 of Chassis #2, respectively.
in Slot 2 of Chassis #1 to PFI 0 and PFI 1 on Chassis #3, respectively.
5. Follow the instruction that applies to your system:
♦ Five or more chassis system only

Use an SMB-210 cable to connect PFI 2 and PFI 3 on the NI PXI-665x
♦ Six or more chassis system only

Use an SMB-210 cable to connect PFI 4 and PFI 5 on the NI PXI-665x
♦ Seven or more chassis system only

A seven-chassis system requires three NI PXI-665x modules in the
first chassis. The previous steps have detailed all cable connections for
the first two NI PXI-665x modules in the master. The connections for

the third NI PXI-665x in the master chassis are identical to those for
the second, except that they pertain to an additional one-to-three slave
chassis. This configuration can be extended for up to 16 NI PXI-665x
modules in the master chassis, yielding a potential maximum of
48 chassis containing NI PXI-4472 modules.

to measure the phase mismatch and to verify that the synchronization is

After configuring the hardware, launch MAX. Verify that all NI PXI-4472
modules are recognized and functioning properly and that the NI PXI-665x
modules are recognized.
Using the niSync_DSA_Example N Chassis VI

This example uses high-level subVIs to illustrate a finite acquisition
synchronizing NI PXI-4472 devices in an arbitrary number of PXI chassis.
Like the other high-level NI-Sync DSA examples, these programs rely on
modular subVIs to provide a level of abstraction from the driver calls that
directly control the NI-PXI 665x and NI PXI-4472 devices. All the
high-level DSA examples share a nested configuration cluster labeled
Systems Settings. This is a flexible data structure that allows you to
precisely describe your hardware configuration before running the
example. The following screenshot shows the System Settings cluster for
the niSync_DSA_Example N Chassis VI.

1 2 3
6 5 4
1 NI PXI-665x Devices in Master Chassis 4 NI PXI-4472 Trigger Slaves in Additional Chassis

2 Slave Chassis Array Index 5 NI PXI-4472 Trigger Master
3 NI PXI-665x in Slave Chassis 6 NI PXI-4472 Trigger Slaves in First Chassis
Figure 4-20. System Settings Cluster for the niSync_DSA_Example N Chassis VI
• NI PXI-665x Devices in Master Chassis—Enter the VISA

Resource Names for the NI PXI-665x devices in the master chassis.
The N chassis configuration requires two or more NI PXI-665x
devices in the master chassis to connect to three or more slave chassis.
Notice that the first element in this array must refer to the NI PXI-665x
residing in PXI Slot 2 of the master chassis.
• Slave Chassis Array Index—Each slave chassis is described by an
element in this array of clusters. This configuration can support one or
two slave chassis.
Name for the NI PXI-665x in each slave chassis. This is not an
array—the slave chassis should each have only one NI PXI-665x in
Slot 2.
• NI PXI-4472 Trigger Slaves in Additional Chassis—This is an array
describing each NI PXI-4472 in the slave chassis.

• NI PXI-4472 Trigger Master—A single NI PXI-4472 in is

responsible for issuing the acquisition trigger signal to start the data
acquisition on every NI PXI-4472 in the system. This board must
reside in the master chassis. The trigger master can use any of its three
trigger modes (software trigger, external analog trigger, external
• NI PXI-4472 Trigger Slaves in First Chassis—This is an array of
clusters with one element per board. All NI PXI-4472 devices in the
master chassis except the trigger master are described here. The trigger
master is addressed in the NI PXI-4472 Trigger Master control.
Configuration #4: Two Chassis with Synchronized Acquisition

and Two CPUs
housed in two PXI chassis. It assumes that each PXI chassis is equipped
with its own embedded PXI controller. You also can use these examples
with two separate desktop PCs, each controlling a single chassis using a
remote chassis link (such as MXI-3) instead of embedded PXI controllers.
Three LabVIEW examples are provided for this configuration. All three of
the following example VIs are required to use this configuration:
• The niSync_DSA Example 2 or 3 Dual Chassis Dual Controller
[Master] VI—This example runs on the CPU of the master chassis.
It controls the hardware on this chassis to perform a synchronized
finite acquisition.
[Slave] VI—This example runs on the CPU of the slave chassis.
It controls the hardware on this chassis to perform a synchronized
finite acquisition.
[Main] VI—This example coordinates the execution of the slave
and master programs. It may be run on the master CPU or on a third
machine as desired.


❑ Two PXI chassis

❑ Two CPUs
Each PXI chassis should contain an embedded PXI controller running
Windows 2000/XP. Alternately, two desktop PCs with remote chassis
links (such as MXI-3) running Windows 2000/XP could control the
two chassis.
❑ Two NI PXI-665x modules

Install one NI PXI-665x in Slot 2 of each chassis.
The device installed in the master chassis must be an NI PXI-6653 or
NI PXI-6652.
❑ One or more NI PXI-4472 modules per chassis

Place the NI PXI-4472 modules in any of the available PXI slots
numbered 3 through 15.
❑ Two Ethernet ports

If the PXI controllers or desktop PCs have embedded Ethernet ports,
you can use these without additional hardware. If you have controllers
that do not contain built-in ports, such as the NI PXI-8170, install a
PXI Ethernet card, such as the NI PXI-8231, in an available slot in
each chassis.
❑ External Ethernet hub or common LAN

You can use any setup that allows each chassis to communicate with
the other chassis over the Ethernet.
❑ Two Ethernet cables

❑ One SMB-210 cable
❑ One 1 kHz sine source (function generator) for testing phase mismatch
between chassis

purposes.
Refer to Figure 4-21 for an illustration of the hardware configuration for

two synchronized chassis, each controlled by its own CPU.
NI PXI-1042
5
4
Chassis #1
3
2
NI PXI-1042
5
4
Chassis #2
1 7
1 Ethernet Cable 5 Embedded PXI Controller

2 SMB-210 Cable 6 External Ethernet Hub or Common LAN
3 SMB-200 Cable (1 m) 7 Ethernet Port
4 NI PXI-665x Module
Figure 4-21. Two Chassis with Synchronized Acquisition and Separate CPUs
(Embedded PXI Controllers)
Connecting to Ethernet
All chassis should be connected to a common LAN or Ethernet hub.

Connecting the NI PXI-665x

1. Use a 1 m SMB-200 cable to connect PFI 0 to PFI 1 on the
NI PXI-665x in Slot 2 of Chassis #1. This cable connects two external
pins on the same module.
Connecting the NI PXI-4472 Modules

to measure the phase mismatch and verify that the synchronization is

1. After the hardware has been configured, launch MAX. Verify that all
the NI PXI-4472 modules in the first chassis are recognized and
properly functioning and that the NI PXI-665x modules are
recognized. Repeat this procedure for the second chassis.
2. Check that each controller can recognize and communicate with the
others over the Ethernet.
Running the Multi-CPU DSA Examples Programs

Three LabVIEW example programs are included to illustrate
synchronizing NI PXI-4472 devices across two PXI chassis, each equipped
with its own PXI controller or MXI-3 connection to a PC. The three
programs are:
[Master] VI
[Slave] VI
[Main] VI
The master and slave examples must run on the CPU controlling the
appropriate chassis. If desired, these programs may be deployed on PXI
controllers running LabVIEW RT. The main program may be run on the
same computer with the master program. Alternately, it can be used on a
third machine that does not actually contain any PXI hardware. If you are

deploying the master and slave VIs on RT controllers, NI recommends

executing the main VI on a third machine running LabVIEW for Windows.
The main VI is the only program of the three that requires direct interaction
from the user. All parameters for acquisitions on the master and the slave
are entered on the front panel of the main VI. When the main VI runs, these
settings are transferred to the slave and master VIs through VI Server calls
by reference. After the master and slave are launched by the main VI, they
use a network software handshaking technique to maintain a deterministic
order of execution between the steps of hardware synchronization in each
VI. A fourth VI, also called by reference from the master and slave, serves
as the clearinghouse for communication between the master and slave
computers. This VI, the niSync_UTIL Network Com Engine VI, resides on
the same machine with the main VI. The master and slave use VI Server
calls by reference to pass information to and from the engine. These
examples are configured to use exactly one master and one slave chassis.
However, the network communication scheme illustrated in these examples
can support multiple slaves for systems requiring more than two chassis.
As previously outlined, the network communication scheme is built around

VI Server calls by reference. This requires that the VI Server security
settings on the computers running the master, slave, and main VIs must be
configured to allow remote calls by reference.
For each machine running LabVIEW for Windows, complete the following
steps to verify that the VI Server settings are configured correctly.
1. Select Tools»Options»VI Server: Configuration. Make sure that all
six check boxes (TCP/IP, ActiveX, and so on) are checked. This
enables VI Server control via TCP/IP.
2. Select Tools»Options»VI Server: TCP/IP Access.
a. Enter a wildcard (*) in the text box.
b. Click the Allow Access button.
c. Click Add and OK. This allows any computer to communicate
with the local machine via VI Server.
3. Select Tools»Options»VI Server: Exported VIs.
a. Enter a wildcard (*) in the text box.
b. Click the Allow Access button.
c. Click Add and OK. This exports all VIs on the local machine for
control via VI Server.

If you are running the master and slave VIs under LabVIEW RT, these same
settings are accessed from a Windows host machine under Tools»Network
x.x.x.x Options, where x.x.x.x is the IP address of the RT target.
After you verify the VI Server settings, you must open LabVIEW on the
machines running the master and slave VIs. (This step is unnecessary if the
master and slave are running on RT targets.)
Although the multichassis example setup uses distinct master, slave, and
main VIs, the user is required to interact directly with the main VI only.
VI Server handles the rest. Figure 4-22 shows the front panel for the
niSync_DSA Example 2 or 3 Dual Chassis Dual Controller [Main] VI.
1 2 3 4
7 6 5
1 NI PXI-665x Masters 5 NI PXI-4472 Trigger Slaves in Slave Chassis

2 IP Address for CPU Running Master VI 6 NI PXI-4472 Trigger Master
3 NI PXI-665x in Slave Chassis 7 NI PXI-4472 Trigger Slaves in Master
4 IP Address for CPU Running Slave VI
Figure 4-22. Front Panel for the niSync_DSA Example 2 or 3 Dual Chassis
Dual Controller [Main] VI
• NI PXI-665x Masters—Enter the VISA Resource Name for the

master chassis is actually an array. However, in this particular screen
two-chassis configuration implies only a single NI PXI-665x in the
master chassis.

• IP Address for CPU Running Master VI—Enter the IP address for

the master CPU here. IP information is needed to establish remote VI
Server communication between the main, master, and slave VIs.
Name for the NI PXI-665x in the slave chassis.
• IP Address for CPU Running Slave VI—Enter the IP address for the
slave CPU here. IP information is needed to establish remote VI Server
communication between the main, master, and slave VIs.
• NI PXI-4472 Trigger Slaves in Slave Chassis—This is an array
describing each NI PXI-4472 in the slave chassis.
• NI PXI-4472 Trigger Master—A single NI PXI-4472 in is
responsible for issuing the acquisition trigger signal to start the data
acquisition on every NI PXI-4472 in the system. This board must
reside in the master chassis. The trigger master can use any of its three
trigger modes (software trigger, external analog trigger, external
• NI PXI-4472 Trigger Slaves in Master—This is an array of clusters
with one element per board. All NI PXI-4472 devices in the master
chassis except the trigger master are described here. The trigger master
is addressed in the NI PXI-4472 Trigger Master control.

5
NI PXI-5112 Modules
NI PXI-5112 Theory of Operation

The NI PXI-5112 100 MHz, 100 MS/s digitizer can use a phase-locked
loop to synchronize its 100 MHz sample clock to a 10 MHz reference clock
such as PXI_Clk10. The high-precision oscillator on the NI PXI-665x can
supply this reference frequency to the PXI backplane.
Synchronizing multiple NI PXI-5112 modules requires the following

PXI timing and triggering features:
• PXI_Clk10—This is a 10 MHz clock with at least 100 ppm accuracy.
It is independently distributed to each PXI peripheral slot through
equal-length traces, with a skew of less than 1 ns between slots.
Multiple devices can use this common timebase for synchronization,
so each NI PXI-5112 can phase lock to a clock shared by the entire
system.
• PXI Trigger Bus—This bus features eight bidirectional lines that
link all PXI slots, providing interdevice synchronization and
communication. The skew from slot to slot is less than 10 ns in
a chassis with eight or fewer slots.
• PXI Star Trigger—This special trigger slot provides an independent
dedicated bidirectional line for each of up to 13 peripheral slots on a
single backplane. All lines are matched in length, which provides a low
slot-to-slot skew of less than 1 ns. A star trigger controller plugged into
this slot can route triggers and clocks among peripheral slots.
To synchronize multiple NI PXI-5112 modules, your system must be

configured as follows:
• All NI PXI-5112 devices must share a common timebase. The
NI PXI-5112 modules can achieve this by phase locking all
NI PXI-5112 modules in the system to the PXI_Clk10.
• All NI PXI-5112 devices must use a synchronization pulse (sync
pulse) to align the clock dividers on each NI PXI-5112. In a
single-chassis system, a master NI PXI-5112 device in Slot 2 of the

PXI chassis typically generates the sync pulse. For a multichassis

system, this example uses the NI PXI-665x to generate this pulse.
• To designate the start of an acquisition, a start trigger signal must
be distributed to all devices in the system.
Note When synchronizing multiple NI PXI-5112 devices, you must route the
asynchronous trigger and synchronization pulse on different trigger lines.
Using the NI PXI-665x to Route Synchronization Signals

between Multiple Chassis
Example Overview
The following section discusses the 5112 665x Example VI. This example
synchronizes up to four chassis containing NI PXI-5112 modules. The
NI PXI-665x shares the synchronization signals for the NI PXI-5112
described in the previous section. In this example, the high-precision
oscillator in the NI PXI-665x replaces the PXI_Clk10 backplane clock in
the master chassis, as well as the slave chassis. The NI PXI-665x master
module then uses its software trigger to send the NI PXI-5112 sync pulse
to all devices in the system. Finally, the master NI PXI-5112 module
triggers from one of its front panel input channels and sends this trigger to
the PXI backplane. The NI PXI-665x modules then route this signal from
the master chassis to all slave chassis and slave NI PXI-5112 modules.
Figure 5-1 shows the front panel for this example VI. The left side of the
panel contains a Chassis Config Information array, where each element
specifies the configuration information for an individual chassis. Within
each element, you can specify the acquisition characteristics as well as the
synchronization characteristics for a chassis.
The graph on the right displays the various signals acquired from each
NI PXI-5112 module. The Stop button at the bottom of the front panel
stops VI execution. The remaining front panel controls specify the
remaining trigger parameters, such as:
• Master Trigger Channel—the analog input channel that triggers the
master NI PXI-5112 module
• Trigger Level—the threshold level of the analog trigger
• Slave Board Delay—the phase delays for each slave NI PXI-5112
module in the master and slave chassis

The Slave Board Delays control is a two-dimensional array. The first

dimension controls which chassis the delays apply to, and the second
dimension of the array controls which particular NI PXI-5112 module
delay is being configured. For more information about the NI PXI-5112
modules and phase compensation, refer to the NI-Scope User Manual.
Figure 5-1. 5112 665x Example VI Front Panel


To get started and set up this example, you need the following hardware
and software:
❑ PC and remote chassis links (such as MXI-3) or PXI Embedded

Controller and Remote chassis link
❑ PXI chassis (up to four chassis may be used)

❑ Master NI PXI-665x
❑ Slave NI PXI-665x (one per chassis)
❑ NI PXI-5112 modules
❑ SMB cables
❑ BNC cables
❑ Clock splitter (if using more than two chassis)
Setting Up a Multichassis PXI System

The following section describes how to set up a multichassis system and
connect the MXI-3 devices:
1. Refer to your remote link (such as MXI-3) documentation for detailed
instructions on installation of PCI and PXI remote link modules.
2. If you are using a PC, install a PCI remote link device in your PC. If
you are using an embedded controller, install this controller into the
first PXI chassis.
3. For each chassis that needs to link to a secondary chassis, you need to
install a PXI remote link module in some slot (other than Slot 2). For
best performance, if you have a PXI chassis that contains a PCI-PCI
bridge, it is best to install the link to secondary chassis in the first bus
segment of the PXI chassis.
4. For each secondary chassis, install a PXI remote link module in Slot 1,
or the system controller slot, of the PXI chassis.
5. Connect your remote link cable from each PCI or PXI remote
link module to its corresponding PXI remote link module on the
secondary side.

For additional help, refer to the documentation for the remote links that you
are using in your system. If it is a National Instruments remote link such as
MXI-3, you can download this documentation from ni.com/manuals.

The following section describes how to properly connect the trigger and
synchronization signals between your master and slave NI PXI-665x
modules.
1. For each chassis in the multichassis system, install an NI PXI-665x
module in Slot 2 of the chassis. This allows the NI PXI-665x module
to replace the PXI_Clk10 reference clock with the onboard
high-precision oscillator, and allows this module control of the
PXI Star Trigger lines.
2. Use an SMB cable to connect Clk Out of the master NI PXI-665x
module to the Clk In of a slave NI PXI-665x module if using a single
secondary chassis, or to a clock splitter if using more than one
secondary chassis. If using more than one secondary chassis, connect
the output from the clock splitter to the Clk In of each slave
NI PXI-665x device.
3. Use SMB cables to connect the outputs of the master NI PXI-665x
module that will carry the sync pulse to each secondary chassis. For
this example, the sync pulse is routed out of the even-numbered front
panel PFI outputs, PFI 0, PFI 2, and PFI 4. Connect one front panel
PFI output for each slave chassis you are supporting to the front panel
PFI 0 of each slave NI PXI-665x module. As previously noted, you can
support up to three slave chassis for a total of four chassis with this
example.
module that will carry the start trigger to each secondary chassis. For
this example, the start trigger is routed out of the odd-numbered front
panel PFI outputs, PFI 1, PFI 3, and PFI 5. Connect one front panel
PFI output for each slave chassis you are supporting to the front panel
PFI 1 of the slave NI PXI-665x module for the slave chassis.


The following section describes how to properly connect the signals for
your data acquisition to the NI PXI-5112 modules in your system.
1. Connect the signals you are measuring to each NI PXI-5112 module in
your system. Each NI PXI-5112 module has two front panel BNC
inputs.
2. Be sure to connect a signal to the front panel BNC for the NI PXI-5112
that you designate as the “master” module, and be sure this is the
correct input channel that you designate as the “Trigger Channel” in
the example VI.

The following sections describe how to configure and run the 5112 665x
Example VI.
1. Set the configuration information for each chassis. Each Chassis
Config Info array element describes the configuration parameters
for each module in one chassis of the multichassis system. Scroll
through the array to enter the information for each chassis, up to four.
Designating information in any array element beyond the fourth in the
array results in an error, as this example only supports up to four
chassis.
a. Type in the NI PXI-665x resource name for each chassis (for
example, PXI1::15::INSTR). An NI PXI-665x module should
be installed in Slot 2 of each chassis. You can find these resource
names using Measurement & Automation Explorer (MAX).
b. Be sure that one chassis in your array is configured as the master
chassis by clicking the Master Chassis button. One and only one
chassis must be configured as the master in the array, or the
example generates an error. The chassis configured as the master
must contain the master NI PXI-5112 module.
c. Each element of the Chassis Config Info array contains an array
to hold the information about the NI PXI-5112 devices in that
chassis. Populate the instrument descriptor for each NI PXI-5112
module in the chassis (for example, one instrument descriptor in
the first chassis may be noted as DAQ::1). Use MAX to determine
the instrument descriptors for all your NI PXI-5112 modules.
d. For each NI PXI-5112 module you specify in a chassis, you must
also specify the slot number where it resides in the chassis,
minimum sample length, minimum record length, vertical range,
and whether the device is the NI PXI-5112 trigger master. The

NI PXI-5112 trigger master is configured to output the start

trigger when a specific signal level is detected on one of its input
channels. There must be one and only one NI PXI-5112 trigger
master in your multichassis PXI system. All parameters other than
Slot # and 5112 Trigger Master are NI-Scope parameters. For
more information about these parameters, refer to the
documentation for the NI-Scope software.
e. The last parameters you need to configure are the trigger
parameters for the Master PXI-5112 module and the delay
parameters for the slave NI PXI-5112 modules. The trigger
channel and trigger level denote the analog input channel on the
master NI PXI-5112 device that initiates the acquisition for the
NI PXI-5112 modules. The trigger level specifies the analog
voltage that trips the trigger, causing the master NI PXI-5112
device to send a start trigger to all slave NI PXI-5112 devices in
the system. The slave board delays for each slave NI PXI-5112
module allow you to adjust the phase of the acquired signals to
account for any cable delays or signal propagation delays in your
system.
f. After you make all the signal connections and configure all the
devices according to the previous steps, you can run the VI. The
stop button in the lower left of the front panel allows you to safely
stop VI execution.
Example Functionality
This section describes each subVI of the 5112 665x Example VI, including
the functionality of the NI-Sync VIs. A significant amount of NI-Scope
programming in this example is not discussed in this manual. Refer to the
NI-Scope documentation for more information about programming with
NI-Scope.
Initialization and Error Checking

This section describes error checking included in this example to verify that
configuration information is correct. This section also describes opening
references to and initializing devices in the system. The two subVIs
covered in this section are the 5112 665x Check VI, which verifies that the
user has properly configured the example, and the 5112 665x Init VI, which
opens sessions to all devices in the system.
The 5112 665x Check VI verifies that the user entered the appropriate
configuration information for the system. The first configuration rule
verified is that there are only four chassis specified in the system. If the user

enters information for more than four chassis, this VI generates an error,
and the rest of the example VI does not execute. This VI also verifies that
the number of masters in the system is correct. It checks that there is at least
one and only one master chassis for the system, and at least one and only
one master NI PXI-5112 module in the master chassis.
The 5112 665x Init VI walks through each device in the system and opens
a session to this device. This VI calls on the NI-Scope driver to open
sessions to the NI PXI-5112 devices. This VI uses the niSync Initialize VI
shown in Figure 5-2 to open sessions to the NI PXI-665x modules in the
system. This example specifies that the NI PXI-665x modules are reset on
initialization. This action clears any previous routes set on the board.
Figure 5-2. niSync Initialize VI Used to Open Sessions to NI PXI-665x Devices
If the NI-Scope driver or the NI-Sync driver cannot open a session to their
device, this VI passes along the error from their respective drivers, and the
example stops execution of any subsequent subVIs.
Configuring the 10 MHz Timebase

This section discusses the configuration of the shared 10 MHz timebase
in the system. For the purpose of this example, the master NI PXI-665x
module in the system uses its high-precision oscillator to replace the
PXI_Clk10 signal in each chassis. The clock from the high-precision
oscillator is routed to the PXI backplane and also out the front panel
Clk Out SMB output to be shared, usually via a clock splitter, with the other
chassis in the system. Each NI PXI-665x in a slave chassis is configured to
input this high-precision oscillator signal into its Clk In front panel SMB
input, and route this clock to replace the chassis-supplied PXI_Clk10
signal. This allows a single reference clock to be shared with all devices
in the system.

The section of code shown in Figure 5-3 is the clock configuration for the
master chassis. The synchronization clock for both the front panel and
backplane are set to be the PXI_Clk10 using a property node. Next, the
niSync Connect Clock Terminals VI is called to route the onboard oscillator
to PXI_Clk10 in the master chassis. Finally, the niSync Connect Clock
Terminals VI is called again to route the same oscillator signal to the front
panel Clk Out SMB.
Figure 5-3. NI-Sync VI Calls to Configure the Master NI PXI-665x Clock Outputs
The section of code shown in Figure 5-4 is the clock configuration for the
slave chassis. The slave NI PXI-665x devices are configured to receive a
clock at their Clk In SMB and route this clock to replace PXI_Clk10 in the
chassis. The niSync Connect Clock Terminals VI routes the signal on ClkIn
to the destination PXI_Clk10.
Figure 5-4. Clk10 Routing for Slave NI PXI-665x Devices

Routing the Necessary Synchronization Signals

This section discusses the NI PXI-665x trigger routing in this example.
The NI PXI-665x routes two synchronization signals. The first signal is the
NI PXI-5112 sync pulse. The master NI PXI-665x generates this pulse as a
software trigger and passes it to all NI PXI-5112 devices in all chassis. The
second signal is the NI PXI-5112 start trigger. The master NI PXI-5112
device generates this trigger and routes it through the NI PXI-665x
modules to all slave NI PXI-5112 devices in the system.
The 665x Route VI first determines whether the chassis it is configuring is

a master or slave chassis. After it determines the appropriate configuration
steps, it makes the routes for the chassis. Figure 5-5 shows the first
configuration step if the chassis is a master chassis. This step involves
setting up the synchronization signals to be sent to the master chassis. In
this case, it is only the SW trigger used by the sync pulse. The niSync
Connect Software Trigger VI is called to route the SW trigger to PXITrig0,
where the master NI PXI-5112 device expects to receive its sync pulse. This
pulse is specified to be synchronized to the full speed clock, which was
previously assigned as PXI_Clk10.
Figure 5-5. Master NI PXI-665x Configures

Software Trigger Routes for Master Chassis

The next few steps to configure the routes in the master NI PXI-665x
involve setting up the routes to output the sync pulse and start trigger for
each slave chassis. Figure 5-6 shows the code to create these routes for the
first slave chassis. These same calls are repeated for each slave chassis,
although the specific PFI outputs used change for each chassis. The niSync
Connect Software Trigger to Terminal VI routes the SW trigger used for the
sync pulse to the first slave chassis. The niSync Connect Trigger to
Terminal VI routes the start trigger generated by the NI PXI-5112 on the
backplane to the front panel PFI0 output to be sent to the first slave chassis.
This example does not resynchronize the start trigger; therefore, the
synchronization clock is left Asynchronous.
Figure 5-6. Master NI PXI-665x Configures Software Trigger Routes

and Start Trigger Routes for Slave Chassis
The final routing steps are for the NI PXI-665x modules in the slave
chassis. Each module must input the sync pulse on the PFI0 SMB input and
route it to PXI_Trig0. Then each slave NI PXI-665x must input the start
trigger on the PFI1 SMB input and route this signal to any star trigger line
where a device resides. The first step is to call the niSync Connect Trigger
Terminals VI with a source of PFI0 and a destination of PXI_Trig0. The
sync pulse is resynchronized to the synchronization clock, which in our
example is the PXI_Clk10. The same VI is called for the next route, but this
time with the source and destination of PFI1 and the appropriate PXI Star
Trigger, respectively. This route passes the trigger asynchronously as
specified in the call to the VI.

Figure 5-7. Slave NI PXI-665x Configures Routing for Sync Pulse

and Start Trigger Inputs to Slave Chassis
Configuring the NI PXI-5112 Synchronization and

Acquisitions
The next two VIs called in this example deal primarily with setting up
the acquisitions on the NI PXI-5112 devices. Refer to the NI-Scope
documentation for more detailed information about configuring and using
the NI-Scope software.
The first VI, the 5112 Sync Config VI, sets up all synchronization
parameters for the master and slave NI PXI-5112 devices in the system.
For this example, all NI PXI-5112 devices receive an external sync pulse
on PXI Trigger line 0. The master NI PXI-5112 device generates a start
trigger based on receiving a signal of the appropriate level on the channel
designated as the Trigger Channel. The master NI PXI-5112 module
outputs this trigger onto the PXI Trigger bus, where this trigger is then
routed to the rest of the chassis in the system. All slave NI PXI-5112
devices receive an external start trigger. If these slave NI PXI-5112
modules reside as slaves in the master chassis, they receive this trigger on
PXI Trigger line 1 on the backplane. If these slave NI PXI-5112 modules
reside as slaves in a slave chassis, they receive their start trigger on the
PXI Star Trigger for their particular slot.

The second VI, the 5112 Acq Config VI, sets all acquisition parameters for
the NI PXI-5112 devices in the system. This VI sets parameters such as the
acquisition rate and sample size. To simplify this example, it abstracts away
many of the configuration options the NI-Scope software provides. As
previously noted, more detailed information about these capabilities is
beyond the scope of this manual and is in the user documentation for your
NI-Scope software.
Beginning the Acquisition

The next section discusses initiating the actual acquisition. Two VIs in this
example handle this functionality. The first VI, the 5112 Start Acq VI,
initiates all NI PXI-5112 devices in the system. For the master
NI PXI-5112, initiating the acquisition means it then waits for the
appropriate trigger signal to be input on the specified trigger channel. For
slave NI PXI-5112 modules, initiating the acquisition means they wait for
a start trigger on the appropriate PXI Trigger Bus or PXI Star Trigger lines.
The second VI involved in beginning the acquisition, the 665x Send

Sync VI, involves firing the NI PXI-665x software trigger that all
NI PXI-5112 devices utilize for their sync pulse. Figure 5-8 shows the
NI-Sync code that fires the software trigger previously configured in
the example by calling the 665x Route VI.
Figure 5-8. Firing the Global Software Trigger on the Master NI PXI-665x
Closing and Error Checking

The final functionality in this example is closing references to devices and
reporting any errors that occurred during execution. 5112 665x Close VI
closes all references to the NI PXI-5112 and NI PXI-665x devices that were
opened during initialization. Figure 5-9 shows the call to the niSync
Close VI, which is called for each reference to an NI PXI-665x device
opened.

Figure 5-9. Closing Each Reference to an NI PXI-665x
The final VI is a standard LabVIEW VI that reports any errors detected

during execution. If an error is encountered during execution, no further
calls to the driver are executed, and the error location and message is passed
to the Simple Error Handler VI and reported with a pop-up dialog.

6
NI PXI-6115 Modules
Note There are two NI PXI-6115 examples included with the NI-Sync
software. The example described here uses a single host CPU. The example
6115_665x_Network_Example VI uses the same NI-Sync and NI-DAQ functionality,
but adds LabVIEW support for the remote VI calls and message passing that is necessary
to make the example run on several different host CPUs coordinated via an Ethernet
connection. This functionality is beyond the scope of this manual.

The NI PXI-6115 10 MS/s, 12-bit, multifunction DAQ module can use an
externally supplied scan clock to synchronize its acquisition. You can use
the Direct Digital Synthesis (DDS) clock on the NI PXI-665x as a source
for this clock.
You can synchronize multiple NI PXI-6115 modules with the following

PXI timing and synchronization features:
• PXI Trigger Bus (RTSI)—This bus features eight bidirectional lines
that link all PXI slots, providing interdevice synchronization and
communication. The skew from slot to slot is less than 10 ns in a
typical 8-slot chassis.
slot-to-slot skew of less than 1 ns. A star trigger controller such as the
NI PXI-665x can be plugged into the PXI star trigger controller slot to
route triggers and clocks among peripheral slots.

To synchronize multiple NI PXI-6115 devices, the following must be true:

• All NI PXI-6115 devices must share a common scan clock. The
NI PXI-6115 modules can achieve this by using an externally supplied
clock. This clock should be distributed over the star trigger lines to
minimize the skew between the scan clocks supplied to each module.
• All NI PXI-6115 devices must use a start trigger to signal the start of
the acquisition. You can use the PXI Trigger Bus to send a digital
trigger.

Example Overview
The following section discusses the example 6115 665x Example VI. This
example synchronizes up to three chassis of NI PXI-6115 modules. The
NI PXI-665x boards share the synchronization signals for the NI PXI-6115
described in the previous section. In this example, the DDS Clock from the
NI PXI-665x provides the scan clock to each NI PXI-6115 in the master
chassis, as well as in the slave chassis. The NI PXI-665x master module
then uses its software trigger to generate the NI PXI-6115 start trigger. The
NI PXI-665x modules then route this signal from the master NI PXI-665x
to all slave chassis and onto a PXI Trigger line where it can be received by
all NI PXI-6115 devices.
each element, you can specify the instrument descriptor for the
NI PXI-665x in the chassis and the device number and slot of each
NI PXI-6115 in the chassis.
NI PXI-6115 module. The remaining front panel controls specify the
details of the acquisition and apply to all NI PXI-6115 devices in the
system. These parameters are the analog input channels from which to
acquire, the sampling rate (Hertz), the record length (samples), and the
vertical range (volts). The graph is scaled automatically to fit the
acquisition parameters.
This example is a single-shot acquisition. Each time the VI runs, one

record of data is captured and displayed. Refer to your NI-DAQ user

documentation for more information about the NI PXI-6115 and

continuous acquisition.

You need the following hardware and software to get started and set up this
example.
❑ PC and remote chassis links (such as MXI-3) or PXI embedded

controller and remote chassis link
❑ Up to three PXI chassis

❑ Slave NI PXI-665x (one per chassis)

❑ SMB cables
Setting Up the Multichassis PXI System

Complete the following steps to set up the multichassis system and connect
the MXI-3 devices.
1. Install the PCI and PXI remote link modules. For detailed instructions,
refer to your remote link (such as MXI-3) documentation.
you are using an embedded controller, install this controller into the
first PXI chassis.
3. For each chassis that needs to link to a secondary chassis, install a
PXI remote link module in some slot other than Slot 2. For best
performance, if you have a PXI chassis that contains a PCI-PCI bridge,
install the link to secondary chassis in the first bus segment of the
PXI chassis.
5. Connect your remote link cable from each PCI or PXI remote link
module to its corresponding PXI remote link module on the secondary
side.
For additional help, refer to the documentation for the remote links you are
using in your system. If you are using National Instruments remote links
such as MXI-3, you can download the documentation from ni.com/
manuals.

Complete the following steps to properly connect the trigger and
modules.
to access the PXI Star Trigger lines.
2. Use an SMB cable to connect PFI 1 of the master NI PXI-665x module
to PFI 0 of the master NI PXI-665x module. This cable must be the
same length as the other SMB cables in the system. This wrapback
cable provides the master chassis with a DDS Clock that is in phase
with the DDS Clock provided to the slave chassis.

3. Use an SMB cable to connect the outputs of the master NI PXI-665x

module that carries the DDS Clock (scan clock) to each secondary
chassis. For this example, the scan clock is routed out of the odd
numbered front panel PFI outputs, PFI 1, PFI 3, and PFI 5. Connect
one front panel PFI output for each slave chassis you will support to
the front panel PFI 0 of the slave NI PXI-665x module for the slave
chassis. As previously noted, you can support up to two secondary or
slave chassis for a total of three chassis, including the master with this
example. Notice that PFI 1wraps back the scan clock for the master
chassis, as previously described. Be sure that all cables that distribute
the scan clock are of equal length.
module that carry the start trigger to each secondary chassis. For this
example, the start trigger is routed out the even numbered front panel
PFI outputs, PFI 2 and PFI 4. Connect one front panel PFI output for
each slave chassis you will support to the front panel PFI 1 of the slave
NI PXI-665x module.

For information about connecting input signals to the NI PXI-6115 devices
in the system, refer to the NI PXI-6115 User Manual included with the
hardware. You also can download this manual from ni.com/manuals.

Complete the following steps to configure and run the 6115 665x
Example VI.
1. Set the configuration information for each chassis. Each element of the
Chassis Config Info array describes the configuration parameters for
the modules in one chassis of the multichassis system. Scroll through
the array to enter the information for each chassis, up to three chassis.
Designating information in any array element beyond the third in the
array results in an error, as this example supports up to only three
chassis (that is, two slave chassis).
names using MAX.
chassis by clicking the Master Chassis button. There must be one
and only one chassis configured as the master in the array or the
example will generate an error.


module in the chassis (for example, you can describe one
instrument descriptor in the first chassis as DAQ::1). Use MAX to
determine the instrument descriptors for all NI PXI-6115
modules.
d. For each NI PXI-6115 module you specify in a chassis, you must
also specify the slot number where it resides in the chassis.
e. Configure the acquisition parameters for all NI PXI-6115 modules
in the system. These include the channels, sampling rate, record
length, and vertical range. For more information about these
parameters, refer to the NI-DAQ driver documentation.
f. After you make all your signal connections and configure all
the boards according to the preceding steps, run the VI. The VI
acquires one waveform from each channel of each NI PXI-6115
based on the acquisition parameters you specified. All waveforms
are displayed on the front panel graph.
This section discusses each 6115 665x Example VI subVI, including the
NI-Sync VIs. A significant amount of NI-DAQ programming in this
example is not discussed in this manual. Refer to the NI-DAQ driver
documentation more information on programming with this software.

This section covers error checking included in this example to verify that
configuration information is correct. This section also covers opening
references to and initializing devices in the system. The two subVIs
covered in this section are the 6115 665x Check VI, which verifies the user
has properly configured the example, and the 6115 665x Init VI, which
opens sessions to all devices in the system.
The 6115 665x Check VI verifies that you have entered the appropriate
configuration information for the system. This VI verifies that the number
of master chassis in the system is correct and that you have specified at least
one and only one master chassis for the system.

a session to this device. This VI calls on the NI-DAQ driver to open sessions
to the NI PXI-6115 devices. This VI also calls on the niSync Initialize VI,
shown in Figure 6-2, to open sessions to the NI PXI-665x devices in the
system. This example specifies that the NI PXI-665x modules be reset on
initialization, which clears any previous routes set on the board.
Figure 6-2. niSync Initialize VI Used to Open Sessions to NI PXI-665x Devices
If the NI-DAQ driver or the NI-Sync driver cannot open a session to a

device, this VI generates an error, and the other example subVIs do not try
to communicate with any device.
Configuring the NI PXI-665x Clocks

This section covers the configuration of the various system clocks on
the NI PXI-665x boards in the system. The master and slave chassis
NI PXI-665x boards must have a number of clock settings configured
for the example to work properly.
The section of code in Figure 6-3 shows the clock configuration for the
master chassis. The DDS frequency is set based on the user-specified
sample clock rate using a property node. The synchronization clock for the
front panel PFIs is set to be the DDS Clock, and the synchronization clock
for the backplane trigger lines is set to be the PFI0 signal using a pair of
property nodes. The PFI synchronization clock outputs the scan clock from
the front panel. The backplane synchronization clock synchronizes the start
trigger. The first clock divisor on the master NI PXI-665x is set to either 2
or 512 depending on whether the sample clock rate is greater than or less
than 100 kHz. This setting is necessary because the start trigger needs to be
at least 10 µs for the NI PXI-6115 devices to be guaranteed to receive it
properly. The NI PXI-665x in the master chassis use a divided version of
the master clock to create the greater than 10 µs pulse.

Figure 6-3. NI-Sync VI Calls to Configure the Master NI PXI-665x Clock Outputs
The section of code in Figure 6-4 shows the clock configuration for the
slave chassis. The slave NI PXI-665x devices use the signal connected to
PFI0 as the synchronization clock source for the board. This PFI0 signal is
the scan clock, which is generated on the master NI PXI-665x by the DDS
and routed to the slave NI PXI-665x with an SMB cable. The rear
synchronization clock synchronizes the start trigger signal on the PXI
backplane in each slave chassis.
Figure 6-4. Clock Configuration for Slave NI PXI-665x Devices

This section covers the NI PXI-665x trigger routing in this example.
It discusses two trigger and synchronization signals routed by the
NI PXI-665x. The first signal is the NI PXI-6115 scan clock. The master
NI PXI-665x generates this clock using the DDS and passes it to all
NI PXI-6115 devices in all chassis. The second signal is the NI PXI-6115
start trigger. The master NI PXI-665x generates this trigger and routes it
through the NI PXI-665x modules to all NI PXI-6115 devices in the
system.
The 665x Route VI executes in three steps. Figure 6-5 shows the first
setting up the scan clocks sent to the master chassis and both slave chassis.

The niSync Connect Trigger Terminals VI is called to route the

full-speed synchronization clock to PFI1, PFI3, and PFI5. Because the
synchronization clock for the PFI lines was specified earlier to be the
DDS Clock, this has the effect of outputting the DDS Clock to these three
PFI connectors. The NI PXI-665x devices in the slave chassis receive no
commands, while the master NI PXI-665x is setting up these routes. After
these three routes are set up, the 665x Route VI begins the next step.
Figure 6-5. Master NI PXI-665x Scan Clock Routing
The next step involves routing the scan clock signal from PFI0 in all chassis
to the appropriate star trigger line for each NI PXI-6115 in the chassis,
using the niSync Connect Trigger Terminals VI. This step is the same
whether the chassis is a master or slave chassis. A case structure converts
the NI PXI-6115 slot number to the appropriate star trigger number.
Note In all NI chassis, the star trigger number is the number of the slot minus three. Slot 3
in an NI PXI chassis is the first peripheral slot that receives a dedicated star trigger signal,
and the star trigger for this slot is PXI_Star0. This is because Slot 1 is reserved for the
system controller and Slot 2 is the Star Trigger Controller slot. PXI allows for up to 13 star
trigger lines (designated PXI_Star0 through PXI_Star12) per chassis, so in the largest
chassis, Slot 15 (PXI_Star12) receives the last available star trigger line.
This route is specified asynchronously because you should not synchronize

the incoming clock on PFI0 to any other clock in the system.

Note In general, you should not route external clocks synchronously. Synchronous
routing makes sense when you want route a trigger signal synchronous to an edge of the
synchronization clock or one of the divided clocks.
Figure 6-6. All NI PXI-665x Devices Route PFI0 to the Star Trigger Line
for Each Slot that Contains an NI PXI-6115
The final routing steps are to generate and distribute the start trigger.
The steps required depend on whether the NI PXI-665x being configured
is in the master chassis or one of the slave chassis. Figure 6-7 shows
the master chassis routing required for this step. The niSync Connect
Software Trigger to Terminal VI routes the software trigger to PFI2 and
PFI4, where it is sent to the slave chassis. The synchronization input for this
connection is specified as Divided Clock 1. Previously, the Clock Divisor 1
was set to be either 2 or 512, based on the scan clock frequency. The
NI PXI-665x issues the software trigger on a rising edge of a divided
version of the synchronization clock and holds the line high until the next
rising edge of this divided clock. This divided clock guarantees that the
start trigger is at least 10 µs in duration. For example, consider a 1 MHz
sample rate. The DDS is set to output a 1 MHz clock that is set as the
synchronization clock. The Clock Divisor 1 is set to 512, which means that
the Divided Clock 1 for the board is a 1 MHz/512 or 1.953 kHz clock.
The period of this clock is 512 µs, and this is also the width of the pulse
the software trigger generates, which meets the 10 µs requirement. The
full-speed clock would have produced a 1 µs wide pulse, which would
not have met the 10 µs requirement.

Note There are two clock dividers for the synchronization clocks on each NI PXI-665x.
You can set these dividers to divide by any power of 2 from 2 to 512.
The niSync Connect Trigger Terminals VI routes the trigger to the

PXI_Trig0 (RTSI0) line on the PXI backplane. For this route, the
synchronization input is the Full-Speed Synchronization Clock. This
means that when the pulse is sent on the PFI line, the NI PXI-665x waits
for the next rising edge of the full-speed synchronization clock before
allowing the signal to pass onto the PXI_Trig0 line on the backplane.
This gives the signal time to travel to the slave chassis.
Figure 6-7. Master NI PXI-665x Routing for the Start Trigger
Figure 6-8 shows the slave chassis routing required for this step. The
niSync Connect Trigger Terminals VI routes the incoming start trigger on
PFI1 to PXI_Trig0 (RTSI0) on the PXI backplane. For this route, the
synchronization input is the Full-Speed Synchronization Clock. This
means that when the pulse is received on the PFI line, the NI PXI-665x
waits for the next rising edge of the full-speed synchronization clock before
allowing the signal to pass onto the PXI_Trig0 line on the backplane.
Therefore, the slave chassis and the master chassis all send the start trigger
on the PXI_Trig0 backplane on the same rising edge of the scan clock. All
NI PXI-6115 devices receive the start trigger within the same sample clock
period and start the acquisition simultaneously.

Figure 6-8. Slave NI PXI-665x Routing for the Start Trigger

Acquisitions
The next VI called in this example deals primarily with setting up the
synchronization on the NI PXI-6115 devices. Refer to the NI-DAQ
documentation for more detailed information about configuration and
using the NI-DAQ driver software.
The 6115 Sync Config VI sets up all synchronization parameters for the
NI PXI-6115 devices in the system. For this example, all NI PXI-6115
devices receive an external scan clock on the PXI Star Trigger line. In the
NI-DAQ driver, RTSI6 is used to import a signal from the PXI Star Trigger
bus. All NI PXI-6115 devices also receive an external start trigger on the
PXI_Trig0 line (referred to in NI-DAQ as RTSI0).


This section discusses initiating the actual acquisition. The VI involved in
beginning the acquisition, the 665x Send Sync VI, fires the NI PXI-665x
software trigger that all NI PXI-6115 devices use as the start trigger.
Figure 6-9 shows the NI-SYNC code that fires the software trigger
previously configured in the example by calling the 665x Route VI.

reporting any errors that occurred during execution. The 6115 665x
Close VI closes all references to the NI PXI-6115 and NI PXI-665x devices
opened during initialization. Figure 6-10 shows the call to the niSync Close
VI for each reference to an NI PXI-665x device that was opened.

calls to the driver are executed. The error location and message are passed
to the Simple Error Handler VI and reported with a pop-up dialog.

Synchronizing Multiple NI MIO
7
Modules
Theory of Operation
You can synchronize multiple MIO devices (also known as E Series
devices) by sharing a common acquisition clock (scan clock) and having a
single start trigger initiate the data acquisition process. The NI PXI-665x
can supply both the scan clock and the start trigger through the PXI
backplane to the MIO devices.
You can synchronize multiple MIO devices using the following PXI
triggering and timing features:
link all PXI slots, providing interdevice synchronization and
communication. The skew from slot to slot is less than 10 ns in a
typical 8-slot chassis. You can use this to provide the start trigger.
slot-to-slot skew of less than 1 ns. A star trigger controller plugged into
this slot can route triggers and clocks among peripheral slots. You can
use this to provide the common acquisition clock.
To synchronize multiple MIO devices, the following must be true:

• All the MIO devices must share a common acquisition clock. The
NI PXI-665x device provides this clock via the star trigger lines.
• All the MIO devices must wait on a common start trigger. This start
trigger is distributed to all devices in the system.

Chapter 7 Synchronizing Multiple NI MIO Modules

Example Overview
The following section discusses the MIO_665x_Sync example. This
example synchronizes two chassis of MIO devices and was created using
LabWindows/CVI 7.0 and NI-DAQmx. The two NI PXI-665x modules
share the synchronization signals for the MIO devices, as described in the
previous section. In this example, the master NI PXI-665x generates a scan
clock and start trigger. The example provides an option for the MIO devices
to start an acquisition using either the global software trigger of the
NI PXI-665x device or an external trigger.
Figure 7-1 shows the example front panel. The graphs display the data
acquired by the devices in each chassis. For the purpose of this example,
each MIO device acquires from channel 1 continuously. On the left side of
the front panel, you specify the resource names of the master and slave
NI PXI-665x devices. You must specify these names correctly before any
configuration is done. You configure each device in turn, starting with the
MIO devices. After you correctly configure the devices, the other disabled
buttons are enabled.
The Acquire button is enabled after you configure all devices. This initiates
the acquisition on the MIO devices. Then, depending on the start trigger
selection, the NI PXI-665x master either generates the start trigger or you
must provide an external trigger. Pressing Stop stops the devices from
acquiring. You must provide a start trigger every time you start acquiring.

Figure 7-1. MIO_665x_Sync Example Front Panel

You need the following items to get started and set up this example:

❑ Two PXI chassis

❑ Slave NI PXI-665x
❑ MIO devices
❑ SMB cables
❑ 68-pin cables and breakout boxes


the MXI-3 devices:
you are using an embedded controller, install it in the first PXI chassis.
2. You must install a PXI remote link module in the primary chassis. If
you have a PXI chassis with a PCI-PCI bridge, for best performance
install the link to the secondary chassis in the first bus segment of the
PXI chassis. Otherwise, choose any slot above Slot 2.
3. For the secondary chassis, install a PXI remote link module in Slot 1,
or the system controller slot.
4. Connect your remote link cable from the slave chassis to the primary
chassis. If you are using a PC, also connect the remote link from the
primary chassis to the PC.
using in your system. For National Instruments remote links such as

modules:
to replace the PXI_Clk10 reference clock with the onboard
high-precision oscillator, and allows the module to control the PXI Star
Trigger lines.
2. Use an SMB cable to connect PFI2 of the master NI PXI-665x module
to a clock splitter. Then wire the output of the splitter to PFI0 of the
master and slave NI PXI-665x modules. PFI2 generates the scan clock,
which must be routed to each input via equal length cables.
3. For the purpose of this example, the master and slave NI PXI-665x
devices must receive the start triggers at their respective PFI1 inputs.
Connect your start trigger signals accordingly. If you intend to use the
master NI PXI-665x device as the start trigger generator, PFI3 will be
the source of the start trigger. Wire PFI3 from the master board to the
PFI1 inputs of the master and slave boards using a T-splitter.

Connecting the MIO Devices

For this example, connect the signals for your data acquisition to channel 1
of each MIO device in the master and slave chassis using the 68-pin
cables and breakout boxes. Refer to the your device user manual for more
information about the pin numbers needed to access channel 1. The devices
must be plugged into consecutive slots, starting from Slot 3.

Complete the following steps to configure and run the MIO_665x_Sync
example.
1. Type in the resource name of each NI PXI-665x device in the
appropriate control (for example, PXI1::15::INSTR). An
NI PXI-665x module should be installed in Slot 2 of each chassis.
You can find these resource names using MAX. Be sure to specify the
correct resource name for the master and slave chassis.
2. Click Configure MIO Devices. This brings up another dialog for
configuring the acquisition devices in the master and slave chassis
(refer to Figure 7-2).
a. For the configuration to work correctly, you must configure each
device string for the MIO Devices in MAX as Dev#, where # is the
number with which the board is associated. For example, if you
have three MIO Devices, the channel strings associated with them
in MAX should be Dev1, Dev2, and Dev3. These device numbers
are used in the Configure MIO Devices window.
b. In the configuration dialog, indicate the number of MIO devices
in each chassis. This updates the number of cells in the appropriate
tables. Enter the device numbers in the appropriate table. Each
table should have unique device numbers in each cell. Specify the
scan rate and the number of Samples per Channel. Click the
Configure! button.
3. Click Configure 665x Devices, which should be enabled now.
4. Before clicking Acquire, ensure that your start trigger connections are
set up as previously described. When you click Acquire, the devices
are configured to wait 10 s for the start trigger before timing out.
5. Click Stop to stop the acquisition. You can restart the acquisition if
needed by clicking Acquire.
6. Click Quit to close resources and exit the example.

Figure 7-2. Configure MIO Devices Dialog
This section discusses the MIO_665x_Sync example configuration
functions, including the NI-Sync functions. A significant amount of
NI-DAQmx programming in this example is not discussed in this manual.
Refer to the user documentation for NI-DAQmx for more information
about programming with this driver.

All configuration functions for this example are in the
MIO_665x_Sync_fn module.
Two main functions initialize the master and slave NI PXI-665x devices,
InitializeMaster665x() and InitializeSlave665x().
InitializeMaster665x() configures the master timing device by first

obtaining the instrument handle to the device via the resource name. The
front panel synchronization clock is routed to PFI2. The DDS Clock is
selected as the front panel synchronization clock, and PFI0 is selected as
the source for the backplane clock. Also, PFI3 is set as the global software
trigger source. This configuration is done at an early stage to keep any line
activity from triggering the MIO Devices.

InitializeSlave665x() obtains the instrument handle for the slave

device. PFI0 is selected as the source for the front and backplane
synchronization clocks.
Error handling is done using a macro ErrChk, defined in

MIO_665x_Sync_fn.h. To use this macro in a function, there must be a
local variable named error of type int and an Error: label that precedes
the error recovery code at the end of the function.
Configuring the Scan Clock

This section covers configuration of the scan clock that drives the
MIO device acquisition. For the purpose of this example, the
high-precision DDS Clock is the scan clock. The clock frequency is
configured in the ConfigureMaster665x() function using the
niSync_SetAttributeViReal64() function. Because the DDS Clock
is already specified as the front panel synchronization clock, and PFI2 is
connected to the front panel synchronization clock, a clock is now
generated at PFI2.

This section covers the NI PXI-665x trigger routing in this example. Two
essential routes are set up in each NI PXI-665x devices. These routes send
the scan clock and start trigger to each MIO device in the chassis. It is
assumed that the MIO devices are present in consecutive slots, starting
with Slot 3.
In the ConfigureMaster665x() and ConfigureSlave665x()

function, the scan clock is routed to each star trigger line from PFI0. This
is done using niSync_ConnectTrigTerminals(). This is set up for
each MIO device in each chassis:
sprintf (starTriggerBuffer, "PXI_Star%d",
deviceCounter);
ErrChk(niSync_ConnectTrigTerminals (instrumentHandle,
NISYNC_VAL_PFI0,
starTriggerBuffer,
NISYNC_VAL_SYNC_CLK_ASYNC,
NISYNC_VAL_DONT_INVERT,
NISYNC_VAL_UPDATE_EDGE_RISING));
For more information about which star trigger line is mapped to which slot,
refer to the PXI Specification, Revision 2.1.

Similarly, the start triggers are routed from PFI1 to PXI_Trig3 (RTSI 3 for
the MIO Devices). This occurs for the master and slave chassis:
ErrChk(niSync_ConnectTrigTerminals (instrumentHandle,
NISYNC_VAL_PFI1,
NISYNC_VAL_PXITRIG3,
NISYNC_VAL_SYNC_CLK_FULLSPEED,
NISYNC_VAL_DONT_INVERT,
NISYNC_VAL_UPDATE_EDGE_FALLING));
If an error is returned, the NI PXI-665x devices are reset, and the instrument
handle is closed, using nisync_reset() and nisync_close(),
respectively.
Configuring the MIO Synchronization and

Acquisitions
This section describes setting up the MIO devices to receive the external
clock and start trigger. For each MIO device in the chassis, you must create
and configure a DAQmx task. To keep track of the device names and the
number of devices in each chassis, the CHANNEL_ARRAY_STRUCT
structure is used.
The MIO device numbers are passed into the

ConfigureChassisSlaves() function. The device number is used to
configure the device for Continuous Acquisition at the user-specified scan
rate. The device also is configured to acquire using an external clock via the
PXI_Star Trigger (RTSI6) and a start trigger from RTSI3. The following
code configures each MIO device in each chassis:
ErrChk (DAQmxCreateTask("",&(*taskHandleArray)
[deviceCounter]));
//Create channel string to create DAQmx task.Reads from

channel 1
sprintf (channelStringBuffer, "Dev%d/ai1",
chassisSlaveChannels.physicalChannelArray[deviceCounter]);
ErrChk (DAQmxCreateAIVoltageChan
((*taskHandleArray)[deviceCounter],
channelStringBuffer,"", DAQmx_Val_Diff, minVoltage,
maxVoltage, DAQmx_Val_Volts, NULL));
//RTSI 6 is star trigger line for E-series devices

sprintf (channelStringBuffer, "/Dev%d/PXI_Star",

//Need to set the scan rate the same as the DDS clock
ErrChk (DAQmxCfgSampClkTiming
((*taskHandleArray)[deviceCounter], channelStringBuffer,
scanRate, DAQmx_Val_Rising,
DAQmx_Val_ContSamps, 100));
//RTSI 3 will receive the start trigger for the device

sprintf (channelStringBuffer, "/Dev%d/RTSI3",
ErrChk(DAQmxCfgDigEdgeStartTrig
((*taskHandleArray)[deviceCounter],
channelStringBuffer,DAQmx_Val_Rising));
At this point, the devices are configured and ready for an acquisition. The
task handles are returned as a parameter.

After you configure the MIO devices, you can initiate acquisition using the
DAQmxStartTask() function. The devices are then waiting to receive the
start trigger. They time out if they do not receive the start trigger in 10 s.
After they receive the start trigger, the devices use the external clock to
acquire data from channel 1.

Any errors that occur during configuration and acquisition are displayed
in a pop-up dialog box. All NI PXI-665x instrument handles are closed
using nisync_close(), and MIO sessions are closed using
DAQmxClearTask().

LabVIEW FPGA Module
8
Examples
This chapter covers examples that demonstrate the use of the LabVIEW
FPGA Module and NI-Sync. The four examples cover custom applications
such as event counting, pulse width measurements, period measurements,
and synchronous input triggers.
Simple Event Counting

Example Overview
This example shows a basic event counter that monitors digital inputs on
the NI PXI-6653 or NI PXI-6652. You can select the type of event to wait
on. The options are line state change, rising edge, or falling edge. This
example consists of the Simple Event Counting VI (the host VI), the
Simple Event Counting (FPGA) VI (a VI targeted at the NI PXI-6653 or
NI PXI-6652), and a LabVIEW Embedded Project (LEP) file, Simple
Event Counting.

Chapter 8 LabVIEW FPGA Module Examples
FPGA VI
Figure 8-1 shows the front panel of the VI targeted to the NI PXI-665x.
Figure 8-1. LabVIEW FPGA Target VI Front Panel
The following controls and indicators are on the FPGA VI front panel.
• Count PXI_Trig 0 Events—Initiates event counting.
• Event Type—Determines which of the following types of events to
wait for:
– Line State Change = 0
– Rising Edge = 1
– Falling Edge = 2
• PXI_Trig 0 Count—Displays the current event count.
• Stop Counting Events—Stops the VI.
• Done Counting Events—Reads TRUE when the VI has stopped.

The FPGA VI block diagram is shown in Figure 8-2.
Figure 8-2. Simple Event Counting (FPGA) VI Block Diagram
The first part of the block diagram shows a While Loop containing the
Start Count Trig 0 Boolean control. When the user clicks this control, the
While Loop stops, and the Single-Cycle Timed Loop starts counting events.
The Event Type control selects a case from the Case Structure that
contains the logic to determine whether the event occurred. The PXI_Trig0
output of the Digital Input function selects which digital input on the
NI PXI-665x to read. The second case statement selects whether to
increment the event counter due to the occurrence of an event from the
PXI_Trig0 digital input line. This current count is then written to the
numeric indicator PXI_Trig 0 Count. Finally, event counting stops when
the user clicks the Stop Counting Events Boolean control.

Host VI
Figure 8-3 shows the front panel for the host VI.
Figure 8-3. Simple Event Counting VI Front Panel
The following controls and indicators are on the VI front panel:

• VISA Resource Name—Contains the VISA resource name for the
NI PXI-665x that will be the execution target for the LabVIEW
FPGA VI.
• Input Line To Monitor—Determines which trigger or PFI input will
be monitored for events.
• Start Counting Events—Initiates event counting.
• Event Type—Determines which of the following types of events to
wait for:
– Line State Change = 0
– Rising Edge = 1
– Falling Edge = 2
• PXI_Trig 0 Count—Displays the current event count.
• STOP—Stops the VI running on the NI PXI-665x.

The first part of the host VI block diagram is shown in Figure 8-4.
Figure 8-4. Initial Configuration and Wait Functionality in the Host VI Block Diagram
The first part of the block diagram opens a reference to the FPGA VI.
Right-click Open FPGA VI Reference and select Select Target VI.
The Select Target VI dialog box appears. Select Simple Event Counting
(FPGA) VI and click the OK button. Next, configure the Open FPGA VI
Reference for an external VISA input by right-clicking the function and
selecting External VISA Input from the shortcut menu. You then can wire
the VISA Resource Name to this input, as shown in Figure 8-4. Finally,
you must select the type of LabVIEW FPGA target, in this case the
NI PXI-665x. To select the target type, right-click the Open FPGA VI
Reference and select FPGA»PXI-665x from the shortcut menu. The call
to the NI-Sync Initialize VI opens an NI-Sync session to the device. The
loop allows the user to select a trigger line to be monitored. After a trigger
line is selected via the Start Counting Events control, the loop exits after
the correct line is routed. The NI-Sync Connect Trigger Terminals VI
routes the user-selected input line to PXI_Trig0, which is the line the FPGA
VI monitors. The NI-Sync session is then closed and the Input Line to
Monitor control is disabled.

Figure 8-5 shows the next part of the host VI block diagram.
Figure 8-5. Host VI Block Diagram to Write Controls and Indicators

on the LabVIEW FPGA Target VI
In this part of the block diagram, first the Event Type numeric control
determines which type of event value should be written to the LabVIEW
FPGA target VI. In this case, Falling Edge is selected. The Read/Write
Control function then writes a value of 2 to the FPGA VI Event Type
control. In addition, the FPGA VI Start Count Trig 0 and Stop Counting
Events controls are written with the current values of the STOP and Start
Event Counting controls on the host VI. Finally, the Read/Write Control
function reads the PXI Trig 0 Count numeric indicator on the FPGA VI.
This loop is stopped when the user clicks the STOP button or an error
occurs.

Figure 8-6 shows the final part of the host VI block diagram.
Figure 8-6. Host VI Block Diagram for Closing the FPGA VI Session
This part of the block diagram executes when the While Loop finishes.
First, the Invoke Method function aborts the target VI in case it was not
properly stopped. Second, the reference to the FPGA VI is closed. Finally,
the Simple Error Handler VI reports any errors.
Pulse Width Measurement

Example Overview
This example measures the width of a pulse on one digital input on the
NI PXI-6653 or NI PXI-6652. This example consists of the Measure Pulse
Width VI (the host VI), the Measure Pulse Width (FPGA) VI (a VI targeted
to the NI PXI-6653 or NI PXI-6652), and a LabVIEW Embedded Project
(LEP) file, Measure Pulse Width.

FPGA VI
Figure 8-7 shows the front panel for the VI targeted to the NI PXI-665x.
Figure 8-7. Front Panel for the FPGA VI Targeted to the NI PXI-665x

• Start Waiting for Input Pulse—Initiates event counting.
• PFI0 In—Shows the current state of the PFI0 input.
• Loop Pulse Rising Edge—Shows the loop iteration count when the
rising edge of the pulse to be measured occurred.
• Current State—Shows the current state of the state machine for the
measurement. The state can be one of the following:
– State 0—Waiting for rising edge.
– State 1—Waiting for falling edge.
– State 2—Waiting for reset.
• Loop Pulse Falling Edge—Shows the loop iteration count when the
falling edge of the measured pulse occurred.
• Duration—Shows the number of loops that elapsed during the pulse.
• Loop Overflow—Shows whether an error occurred due to the
Single-Cycle Timed Loop counter overflowing.

• Restart State Machine—Restarts the state machine for a new

measurement.
• Abort—Stops the VI.
Figure 8-8 shows the block diagram for the FPGA VI while LabVIEW is
targeted to the NI PXI-665x.
Figure 8-8. Block Diagram for the FPGA VI Targeted to the NI PXI-665x
The first part of this block diagram shows a While Loop containing the
Start Waiting For Input Pulse Boolean control. When the user clicks this
control, the While Loop stops executing, and the Single-Cycle Timed Loop
begins counting events. The PFI0 output of the Digital Input function
determines which digital input line on the NI PXI-665x to read. The current
value of this line is displayed in the PFI0 In Boolean indicator. The initial
state of the state machine is –1, which is stored in a shift register on the
Single-Cycle Timed Loop. In state –1, the value of PFI0 is read and then
applied to the shift register to capture the initial value from the trigger line.

Then, in state 0, the value of PFI0 is read, and if the value is high, a rising
edge occurred. The current loop count is captured and stored in the shift
register labeled First, and the state machine proceeds to state 1.
In state 1, PFI0 is read, and logic determines whether the line state is low.
When the line state becomes low, a falling edge has occurred, the current
loop count is captured in the shift register labeled Second, and the state
machine proceeds to state 2. In state 2, the pulse duration is calculated from
the number of loop cycles elapsed and displayed in the Duration numeric
indicator. The state machine continues in state 2 until the user clicks the
Restart State Machine Boolean control. When this control becomes true,
the state machine resets to state –1, and the First and Second shift registers
are reinitialized. With each iteration, the loop counter is checked for an
overflow. The loop stops either when the user clicks the Abort Boolean
control or a loop overflow occurs. The Single-Cycle Timed Loop frequency
is 40 MHz. This is the FPGA system clock default frequency. You can
configure the FPGA system clock using the LEP file associated with the
FPGA project. Select Target»Build Options to change the Default Clock
Rate. You can modify clock codes from the default, although not all VIs
can meet timing constraints at all selectable frequencies. For this example,
the loop rate is important, as it allows the host side VI to calculate the
frequency in seconds.

Host VI
Figure 8-9 shows the LabVIEW host VI front panel for the Measure Pulse
Width example.
Figure 8-9. Host VI Front Panel for the Measure Pulse Width Example

• Start Waiting for Input Pulse—Initiates event counting.
measurement.
• VISA Resource Name—Opens a session to the FPGA VI target and
NI-Sync.
• Input Signal Line—Selects the signal to be routed to PFI0 for the
pulse width measurement.

• Pulse Duration (sec.)—Displays the duration of the measured pulse in

seconds.
• Trigger Line Selected—Initiates the route for the measurement after
the trigger line is selected.
Note The only valid signals for this input are PFI1-5 and PXI Trigger lines 0–7, as PFI0
is for the measurement. PXI Star lines are outputs and therefore not valid lines to read in
this example.
• Loop Pulse Rising Edge—Displays the loop iteration count when the
• Loop Pulse Falling Edge—Displays the loop iteration count when the
falling edge of the pulse to be measured occurred.
• Loop Overflow—Displays whether an error occurred due to the
• STOP—Stops the VI.

Figure 8-10 shows the first part of the LabVIEW VI running on the host.
Figure 8-10. Host VI Block Diagram Showing Device Configuration
The first part of the host VI involves opening sessions to the VI and device
for configuration. You must configure the Open FPGA VI Reference
function call for the appropriate VI to open. To do this, right-click this
function call and select Select Target VI from the shortcut menu. The
target VI selected is the Measure Pulse Width (FPGA) VI. Next, configure
the Open FPGA VI Reference for an external VISA input by right-clicking
the function and selecting External VISA Input from the shortcut menu.
You then can wire the VISA Resource Name to this input as shown in
Figure 8-10. Finally, you must select the type of LabVIEW FPGA target, in
this case the NI PXI-665x. To select the target type, right-click Open FPGA
VI Reference and select FPGA»PXI-665x. Next, a driver reference must
be opened to the board using NI-Sync. The niSync Initialize VI reads the
VISA Resource Name control to open this session. Next, you have a While
Loop that waits until the user indicates that the appropriate line to monitor

has been selected. The user clicks Trigger Line Selected, and the loop
exits. The session to NI-Sync is then closed, and the Input Trigger Line
control is disabled. The input signal to be measured is routed to PFI0, the
digital input that the FPGA target VI expects to measure using the NI-Sync
niSync Connect Trigger Terminals VI. Finally, the niSync Close VI is
called, as the NI Sync driver needs no more routes. Figure 8-11 shows the
main part of the host VI block diagram.
Figure 8-11. Main Loop in the Host VI for Pulse Width Measurement
The first call to Read/Write Control reads the current values of all
indicators on the FPGA VI. If a measurement has been started, when the
pulse arrives, the loop count and duration values are recorded in the FPGA
VI and can be read from the host. The host VI calculates the actual duration
in seconds based on the Single-Cycle Timed Loop period of 25 ns. The
second call to the Read/Write Control function writes the controls in the
FPGA targeted VI. When the user initiates the measurement by clicking the
Start Waiting for Input Pulse control, or when the user restarts the state
machine or aborts the VI, all these values are written to the FPGA targeted
VI using this function. The loop stops if the STOP Boolean control is
clicked or an error occurs.

Figure 8-12 shows the final part of the host VI for the Measure Pulse Width
example.
Figure 8-12. Host VI Abort and Close
This part of the block diagram executes when the loop finishes. First, the
Invoke Method function aborts the target VI in case it was not properly
stopped. Second, the reference to the FPGA VI is closed. Finally, the
Simple Error Handler VI reports any errors.
Period Measurement
Example Overview
This example measures the period of signal on one of the digital inputs on
the NI PXI-6653 or NI PXI-6652. This example consists of the Measure
Period VI (the host VI), the Measure Period (FPGA) VI (a VI targeted to
the NI PXI-6653 or NI PXI-6652), and a LabVIEW FPGA embedded
project, Measure Period.

FPGA VI

• Start Waiting for Input Period—Initiates measurement.
• PFI1 In—Displays the current state of the PFI1 input.
• Duration—Displays the number of loops that elapsed during the
period.
• Loop Overflow—Displays whether an error occurred due to the
• Loop Period Started—Displays the loop iteration count when the
• Current State—Displays the current state of the state machine for the
measurement.The state can be one of the following:
– State 0—Waiting for first rising edge
– State 1—Waiting for second rising edge
– State 2—Waiting for reset

• Loop Period Finished—Displays the loop iteration count when the

measurement.
• Abort—Stops the VI.
Figure 8-14 shows the block diagram for the VI targeted to the
NI PXI-665x.
Start Waiting For Input Period Boolean control. When the user clicks
this control, the While Loop stops executing, and the Single-Cycle Timed
Loop begins measuring periods. The PFI1 output of the Digital Input
function determines which digital input line on the NI PXI-665x to read.
The current value of this line is displayed in the PFI1 In Boolean indicator.
The initial state of the state machine is –1, which is stored in a shift register
on the Single-Cycle Timed Loop. In state –1, the value of PFI1 is read and
then applied to the shift register to capture the initial value from the trigger
line. Then, in state 0, the value of PFI1 is read to see if a rising edge
occurred. This is determined by looking at the previous value of the line,

which is stored in a shift register on the loop, and comparing it to the current
value. If a rising edge occurred, the loop count is captured and stored in the
shift register labeled First, and the state machine proceeds to state 1.
In state 1, PFI1 is read and logic determines whether another rising edge
has been seen. When this occurs, the current loop count is captured in the
shift register labeled Second, and the state machine proceeds to state 2.
In state 2, the period duration is calculated from the number of loop cycles
elapsed and displayed in the Duration numeric indicator. The state
machine continues in state 2 until the user clicks the Restart State
Machine Boolean control. When this control becomes true, the state
machine resets to state –1, and the First and Second shift registers are
reinitialized. On each iteration, the loop counter is checked for an overflow.
The loop stops when the user clicks the Abort Boolean control or a loop
overflow occurs.

Host VI
Figure 8-15 shows the front panel of the LabVIEW host VI for the Measure
Period example.
Figure 8-15. Host VI Front Panel for the Measure Period Example

• Start Waiting for Input Period—Initiates period measurement.
measurement.
• VISA Resource Name—Opens a session to the FPGA VI target and
NI-Sync.
• Input Signal Line—Determines the signal to be routed to PFI1 for the
pulse width measurement.
• Period Duration (sec.)—Displays the measured period duration in
seconds.

• Trigger Line Selected—Initiates the trigger route for the input line to
monitor.
Note The only valid signals for this input are PFI0, PFI 2-5, as PFI1 is for the
measurement and PXI Trigger lines 0–7. PXI Star lines are outputs and therefore are not
valid lines to read in this example.
• First Rising Edge—Displays the loop iteration count when the rising
edge of the pulse to be measured occurred.
• Second Rising Edge—Displays the loop iteration count when the
• Loop Overflow—Shows whether an error occurred due to the

The first part of the host VI opens a session to the VI and device for
configuration. You must configure the Open FPGA VI Reference function
call for the appropriate VI to open. To do this, right-click this function call
and select Select Target VI from the shortcut menu. The target VI selected
is the Measure Period (FPGA) VI. Next, configure the Open FPGA VI
Reference for an external VISA input by right-clicking the function and
selecting External VISA Input from the shortcut menu. You then can wire
the VISA Resource Name to this input, as shown in Figure 8-16. Finally,
you must select the type of LabVIEW FPGA target, in this case the
NI PXI-665x. To select the target type, right-click Open FPGA VI
Reference and select FPGA»PXI-665x. Next, a driver reference must be
opened to the device using NI-Sync. The niSync Initialize VI reads the
VISA Resource Name control to open this session. Next, the loop allows
the user to wait and select a trigger line to monitor. After the user selects
the line, the Trigger Line Selected control stops the loop when the
appropriate line is routed. The input signal to be measured is routed to PFI1,
the digital input that the FPGA target VI expects to measure using the
NI-Sync niSync Connect Trigger Terminals VI. Finally, the niSync Close
VI is called, and a property node disables the Input Signal Line control, as
the line cannot be changed during the measurement, as the NI Sync driver
needs no more routes.

Figure 8-17 shows the main part of the host VI block diagram.
Figure 8-17. Main Loop in the Host VI for Period Measurement
indicators on the FPGA VI. If a measurement has been started, when the
first rising edge arrives, the loop count and duration values are recorded in
the FPGA VI and can be read from the host. The host VI calculates the
actual duration in seconds based on the Single-Cycle Timed Loop period of
25 ns. The second call to Read/Write Control writes the controls in the
FPGA VI. When the user initiates the measurement by clicking the Start
Waiting for Input Period control, or when the user restarts the state
machine or aborts the VI, all these values are written to the FPGA targeted
VI using this function. The loop stops if the STOP Boolean control is
clicked or an error occurs.

Figure 8-18 shows the final part of the host VI for the Measure Pulse Width
example.
Invoke Method function aborts the FPGA VI in case it was not properly
PXI Clk10 Synchronous Input Trigger

Example Overview
This example captures a digital input line synchronous to PXI Clk10 on the
PXI backplane. After this input is received, this example generates a trigger
synchronously on the next PXI_Clk10 cycle. This example consists of the
PXI Clk10 Synchronous Input Trigger VI (the host VI), the PXI Clk10
Synchronous Input Trigger (FPGA) VI (a VI running on the NI PXI-6653
or NI PXI-6652), and an LEP file, PXI Clk10 Synchronous Input Trigger.

FPGA VI

• Start Waiting For Trigger—Initiates measurement.
• Duration of Trigger (PXI_Clk10 Cycles)—Shows the duration of the
generated trigger in cycles of PXI Clk10.
• PXI Clk10 Cycles To Delay Trigger—Denotes the trigger delay, if
desired, in cycles of PXI_Clk10.
• Current Loop—Shows the current cycle of the main loop in the
FPGA targeted VI. This is used primarily for debugging purposes.
• Loop to Generate Output Trigger—Displays the loop the VI expects
to send the output trigger. This output is used primarily for debugging
purposes and is valid only when the input trigger has been received.

• Current State—Shows the current state of the state machine for the
– State 0—Waiting for Trig In.
– State 1—Waiting to drive Trig Out.
– State 2—Waiting to stop driving Trig Out.
• PXI_Trig0 In—Shows the current state of the PFI0 input.
• PXI_Trig1 Out—Shows the current state of the PFI0 output.
• Reset State Machine—Restarts the state machine for generating
another trigger.
• Loop Overflow Occurred, State Machine Reset—Shows whether an
error occurred due to the Single-Cycle Timed Loop counter
overflowing, and it is necessary to restart the state machine by clicking
the Start Waiting For Trigger control again.
Figure 8-20 shows the block diagram for the VI targeted to the
NI PXI-665x.

Start Waiting For PXI_Trig 0 Boolean control. When the user clicks this
control, the While Loop stops executing, and the Single-Cycle Timed Loop
begins counting events. The current state machine state, the status of the
output trigger, and the loop count are all initialized at the beginning of the
loop. Case 0 is selected first. The PXI_Trig0 output of the Digital Input
function determines which digital input line on the NI PXI-665x to read.
The current value of this line is displayed in the Boolean PXI_Trig0 In
indicator. In state 0, the value of PXI_Trig0 is read to see if a rising edge
occurred. If a rising edge occurred, loop count is captured, the value of the
loop iteration to generate the trigger is calculated, and the state machine
proceeds to state 1.
In state 1, the state machine checks to see whether the current loop iteration
is the loop iteration calculated to be the time to generate the trigger. When
the iteration is reached, the output trigger value is assigned a True, the
current loop iteration is captured, and the iteration to stop generating the
trigger is calculated. The state machine then proceeds to state 2.
In state 2, that state machine checks the loop iteration to determine whether
the count at which to stop generating triggers has been reached. When this
count is reached, False is assigned to the trigger output value, and the state
machine proceeds to state 3.
In state 3, the state machine waits for the user to click the Reset State
Machine Boolean control. On each iteration, the loop counter is checked
for an overflow. When an overflow occurs, the user must restart waiting for
the input trigger by clicking the Start Waiting for Trigger Boolean
control. The loop stops when the user clicks the STOP Boolean control.

Host VI
Figure 8-21 shows the front panel of the LabVIEW host VI for the Measure
Period example.
Figure 8-21. Host VI Front Panel for the Measure Period Example

• VISA Resource Name—Opens a session to the FPGA VI target.
• Start Waiting For PXI Trig 0—Initiates trigger generator.
• PXITrig0 In—Displays the current state of the PFI0 input.
• Current State—Displays the current state of the state machine for the
– State 0—Waiting for Trig In.
– State 1—Waiting to drive Trig Out.
– State 2—Waiting to stop driving Trig Out.
• Line to Generate Output Trigger—Displays the line on which the
Clk10 synchronous trigger will be generated.

• Duration of Trigger (PXI Clk10 Cycles)—Displays the duration of

the generated trigger in cycles of PXI Clk10.
• PXI Clk10 Cycles To Delay Trigger—Denotes the trigger delay, if
desired, in cycles of PXI Clk10.
• Loop Overflow Occurred, State Machine Reset—Shows whether an
error occurred due to the Single-Cycle Timed Loop counter
overflowing, and it is necessary to restart the state machine by clicking
the Start Waiting For Trigger control again.
• Restart—Restarts the state machine for generating another trigger.
• Trigger Line Selected—Initiates the routing of the user-selected
trigger line.
• Current Loop—Shows the current cycle of the main loop in the
FPGA targeted VI. This is used primarily for debugging purposes.
• Loop to Generate Output Trigger—Displays the loop the VI expects
to send the output trigger. This output is used primarily for debugging
purposes and is valid only when the input trigger has been received.
• PXITrig1 Out—Shows the current state of the PFI0 input.
• Quit Program—Stops the VI.

The first part of the host VI involves opening sessions to the VI and device
for configuration. You must configure the Open FPGA VI Reference
function call for the appropriate VI to open. To do this, right-click this
function call and select Select Target VI. The FPGA VI selected is the
Measure Period (FPGA) VI. Next, configure the Open FPGA VI
Reference for an external VISA input by right-clicking and selecting
External VISA Input. You then can wire the VISA Resource Name to
this input, as shown in Figure 8-22. Finally, you must select the type of
LabVIEW FPGA target, in this case the NI PXI-665x. To select the target
type, right-click Open FPGA VI Reference and select FPGA»PXI-665x.
The niSync Initialize VI reads the VISA Resource Name control to open
a driver session to the device.
Next, an NI-Sync property node sets the rear synchronization clock used
for synchronizing the PXI backplane triggers. This clock is set to
PXI_Clk10 so that output triggers are synchronized to PXI Clk10. The

While Loop allows the VI to wait until the user selects a trigger line on
which to generate the PXI Clk10 synchronous trigger. After the user selects
the trigger line, clicking the Trigger Line Selected button stops the loop,
and the VI waits on a trigger. The output trigger from LabVIEW FPGA is
then routed to the PXI backplane trigger line 1 using the NI-Sync niSync
Connect Trigger Terminals VI. A synchronous route is specified by
designating that the Synchronization Clock is assigned the value
Full-Speed Clock. Finally, the niSync Close VI is called, as the NI Sync
driver needs no more routes.
Figure 8-23 shows the main part of the host VI block diagram.
Figure 8-23. Main Loop in the Host VI for Trigger Detection and Generation

indicators on the FPGA VI. With this function call as the current loop, the
current state of the state machine and trigger lines can be read, as well as
whether a loop overflow error occurred. The second call to Read/Write
Control writes the controls in the FPGA VI. When the user initiates the
target VI by clicking the Start Waiting for PXI Trig 0 control, or when
the user restarts the state machine or aborts the VI, all these values are
written to the FPGA VI using this function. The values for the trigger delay
and duration are also written via this function call. The loop stops if the
Quit Program Boolean control is clicked.
Figure 8-24 shows the final part of the host VI for the PXI Clk10
Synchronous Input Trigger example.
Invoke Method function aborts the FPGA VI in case it was not properly

9
NI PXI-5411 Modules

The NI PXI-5411 40 MS/s arbitrary waveform generator can use a
phase-locked loop to synchronize its sample clock to the PXI_Clk10. This
method is the same method used by the NI PXI-5112 digitizer previously
discussed in this manual. The high-precision oscillator on the NI PXI-665x
can supply this reference frequency to the PXI backplane.
You can synchronize multiple NI PXI-5411 modules with the following

PXI timing and triggering features:
• PXI_Clk10—This is a 10 MHz clock with at least 100 ppm accuracy.
It is independently distributed to each PXI peripheral slot through
equal-length traces with a skew of less than 1 ns between slots.
Multiple devices can use this common timebase for synchronization.
This allows each NI PXI-5411 to phase lock to a clock shared by the
entire system.
link all PXI slots, providing inter-device synchronization and
communication. The skew from slot to slot is less than 10 ns.
To synchronize multiple NI PXI-5411 modules, the following must be true:

• All NI PXI-5411 devices must share a common timebase. The
NI PXI-5411 modules can achieve this by phase locking all
NI PXI-5411 modules in the system to the PXI_Clk10.
• All NI PXI-5411 modules must use a synchronization pulse (sync
pulse) to align the clock dividers on each NI PXI-5411 module. In a
single-chassis system, the sync pulse is typically generated by a master
NI PXI-5411 module in Slot 2 of the PXI chassis.

• To designate the actual acquisition, a start trigger signal must be

distributed to all devices in the system. In a single-chassis system, the
start trigger is typically generated by a master NI PXI-5411 module in
Slot 2 of the PXI chassis.
Note When synchronizing multiple NI PXI-5411 modules, the asynchronous trigger and
the synchronization pulse must be routed on different bus lines.

Example Overview
The following section discusses the example 5411 665x Example VI.
This example synchronizes up to four chassis of NI PXI-5411 modules.
The NI PXI-665x shares the synchronization signals for the NI PXI-5411
described in the previous section. In this example, the high-precision
oscillator in the NI PXI-665x replaces the PXI_Clk10 in the master chassis,
as well as the slave chassis. The NI PXI-665x master module then uses its
software trigger to send the NI PXI-5411 sync pulse to all boards in the
system. Finally, the master NI PXI-5411 module triggers when given the
“initiate” command in software and sends this start trigger to the PXI
backplane. The NI PXI-665x modules then route this signal from the master
chassis to all slave chassis and slave PXI-5411 modules.
each element, you can specify the acquisition and synchronization
characteristics for a chassis.
NI PXI-5411 module. The Stop button at the bottom of the front panel
stops execution of the VI. The Update button updates the waveforms each
NI PXI-5411 in the system generates. The remaining front panel controls
specify the remaining trigger and signal generation parameters. For more
information about the NI PXI-5411 modules’ ability to do phase
compensation, refer to the NI-FGEN User Manual.


To set up and get started with this example, you need the following
hardware and software.

❑ PXI chassis (up to four chassis)

❑ Slave NI PXI-665x (one per slave chassis)
❑ SMB cables
❑ BNC cables

the MXI-3 devices:
1. Refer to your remote link (such as MXI-3) documentation for detailed
instructions about installation of PCI and PXI remote link modules.
2. If you are using a PC, install a PCI remote link device in your PC.
If you are using an embedded controller, install this controller into
the first PXI chassis.
3. For each chassis that needs to link to a secondary chassis, you need to
install a PXI remote link module in some slot other than Slot 2. For
best performance, if you have a PXI chassis that contains a PCI-PCI
bridge, it is best to install the link to secondary chassis in the first bus
segment of the PXI chassis.
5. Connect your remote link cable from each PCI or PXI remote
link module to its corresponding PXI remote link module on the
secondary side.
using in your system. For National Instruments remote links such as


modules.
module installed in Slot 2. This allows the NI PXI-665x module to
replace the PXI_Clk10 reference clock with the onboard
high-precision oscillator.
2. Use an SMB cable to connect Clk Out of the master NI PXI-665x
module to the Clk In of either one slave NI PXI-665x module if using
a single secondary chassis, or to a clock splitter if using more than one
secondary chassis. If using more than one secondary chassis, the
output from the clock splitter must be connected to the Clk In of each
slave NI PXI-665x device.
3. Use SMB cables to connect each secondary chassis to the outputs of
the master NI PXI-665x module that carries the sync pulse. For this
example, the sync pulse is routed out of the even-numbered front panel
PFI outputs, PFI 0, PFI 2, and PFI 4. Connect one of these front panel
PFI outputs from the master to the front panel PFI 0 of the slave
NI PXI-665x modules for the slave chassis. As previously noted, you
can support up to three secondary or slave chassis (for a total of four
chassis) with this example.
4. Use SMB cables to connect each secondary chassis to the outputs of
the master NI PXI-665x module that carries the start trigger. For this
example, the start trigger is routed out of the odd numbered front panel
PFI outputs, PFI 1, PFI 3, and PFI 5. Connect one of these front panel
PFI outputs from the master to the front panel PFI 1 of the slave
NI PXI-665x modules for the slave chassis.

Connect the signals from the NI PXI-5411 modules in your system via
a BNC cable to the destination for the signal you will generate. For more
information about connecting signals generated by the NI PXI-5411 to
other devices, refer to the user manual for your NI PXI-5411 hardware.


Figure 9-2 shows the front panel for the 5411 665x Example VI.

Complete the following steps to configure and run the 5411 665x
Example VI:
1. Set the configuration information for each chassis. Each element of
the Chassis Config Information array describes the configuration
parameters for the modules in one chassis of the multichassis system.
Scroll through the array to enter the information for each chassis, up to
four chassis. Designating information in any array element beyond the
fourth in the array results in an error, as this example supports up to
four chassis only (that is, three slave chassis).
names using MAX.
chassis by clicking the Master Chassis button. Configure one and
only one chassis as the master in the array, or the example
generates an error. The chassis configured as the master must
contain the master NI PXI-5411 module.
module in the chassis (for example, you may note one instrument
descriptor in the first chassis as DAQ::1). Use MAX to determine
the instrument descriptors for all of your NI PXI-5411 modules.
Use the Waveform input to specify the waveform each
NI PXI-5411 device generates. You can specify the type of
waveform, scaling, and the number of data points to be generated.
Finally, specify the gain for the waveform amplitude as well as
any DC offset necessary for the waveform.
Be sure one NI PXI-5411 is the trigger master by clicking the
5411 Trigger Master button. One and only one NI PXI-5411 in
the system must be selected as the trigger master.
d. Set the sample rate. This example uses a global sample rate, so
each arb uses the same value taken from the Sample Rate front
panel input.
e. After making your signal connections and configuring all modules
according to the previous steps, run the VI. Use the Stop button to
stop VI execution safely.

This section discusses each 5411 665x Example VI subVI, including the
NI-Sync VI functionality. A significant amount of NI-FGEN programming
in this example is not discussed in this manual. Refer to the user
documentation for the NI-FGEN driver for more information about
programming with this software.

This section discusses error checking included in this example to verify
configuration information is correct. It also discusses opening references to
and initializing devices in the system. The two subVIs in this section are the
5411 665x Check VI, which verifies that the user has properly configured
the example, and the 5411 665x Init VI, which opens sessions to all devices
in the system.
The 5411 665x Check VI verifies that you have entered the appropriate
configuration information for the system. First, the VI verifies that only
four chassis are specified in the system. If you enter information for more
than four chassis, this VI generates an error, and the rest of the example VI
does not execute. This VI also verifies that the number of masters in the
system is correct. It checks that you have specified at least one and only one
master chassis for the system. It also checks that there is at least one and
only one master NI PXI-5411 module in the master chassis.
a session to the device. This VI calls on the NI-FGEN driver to open
sessions to the NI PXI-5411 devices. It also calls on the niSync Initialize
VI, shown in Figure 9-3, to open sessions to the NI PXI-665x devices in the
system. This example specifies resetting the NI PXI-665x modules on
initialization to clear any previous routes on the board.
Figure 9-3. The niSync Initialize VI Used to Open Sessions to NI PXI-665x Devices

If the NI-FGEN driver or the NI-Sync driver cannot open a session to their
devices, this VI passes along the error from their respective drivers, and the
example stops execution of any subsequent subVIs.
Configuring the 10 MHz Timebase

This section discusses configuration of the shared 10 MHz timebase in the
system. For the purpose of this example, the master NI PXI-665x device in
the system uses its high-precision oscillator to replace the PXI_Clk10
signal supplied by each chassis. The clock from the high-precision
oscillator is routed to the PXI backplane and also out the front panel
Clk Out SMB output to be shared, usually via a clock splitter, with other
chassis in the system. Each NI PXI-665x device in a slave chassis is
configured to input this high-precision oscillator signal into its Clk In front
panel SMB input, and route this clock to replace the PXI_Clk10 signal the
chassis supplies. This allows a single reference clock to be shared with all
devices in the system.
Figure 9-4 shows the section of code for master chassis clock
configuration. The synchronization clock for both the front panel and
backplane are set to be the PXI_Clk10 using a property node. Next, the
niSync Connect Clock Terminals VI is called to route the onboard
oscillator to PXI_Clk10 in the master chassis. Finally, the niSync Connect
Clock Terminals VI is called again to route the same oscillator signal to the
front panel ClkOut SMB.
Figure 9-4. NI-Sync Calls to Configure the Master NI PXI-665x Clock Outputs

Figure 9-5 shows the section of code for the slave chassis clock
configuration. The slave NI PXI-665x devices are configured to
receive a clock at their Clk In SMB and route this clock to replace
PXI_Clk10 in the chassis. This time, the niSync Connect Clock Terminals
VI routes the signal on ClkIn to the destination PXI_Clk10.
Figure 9-5. Clk10 Routing for Slave NI PXI-665x Devices

This section discusses the NI PXI-665x trigger routing conducted in this
example, including two trigger and synchronization signals routed by the
NI PXI-665x. The first signal is the NI PXI-5411 sync pulse. This pulse is
generated by the master NI PXI-665x as a software trigger and passed to all
NI PXI-5411 devices in all chassis. The second signal is the NI PXI-5411
start trigger. This trigger is generated by the master NI PXI-5411 device
and routed through the NI PXI-665x modules to all slave NI PXI-5411
devices in the system.
The 665x_Route VI first determines whether the chassis it is configuring is

a master or slave chassis. After determining the appropriate configuration
steps to take, it makes the routes for the chassis. Figure 9-6 shows the first
setting up the synchronization signals to be sent to the master chassis (in
this case, only the SW trigger used by the sync pulse). The niSync Connect
Software Trigger VI routes the SW trigger to PXI Trigger line 0, where the
master NI PXI-5411 device expects to receive its sync pulse. This pulse is
specified in this VI to be synchronized to the full-speed clock, previously
assigned as PXI_Clk10.

Figure 9-6. Master NI PXI-665x Configures

Software Trigger Routes for Master Chassis
The next few configuration steps in the master NI PXI-665x involve setting
up the routes to output the sync pulse and start trigger for each slave
chassis. Figure 9-7 shows the code for these routes for the first slave
chassis. These same calls are repeated for each slave chassis, although the
specific PFI outputs used change for each chassis. The niSync Connect
Software Trigger VI routes the software trigger for the sync pulse to the
first slave chassis. The niSync Connect Trigger Terminals VI routes the
start trigger the NI PXI-5411 generates on the backplane to the front panel
PFI0 output to be sent to the first slave chassis. In this case, the start trigger
is not resynchronized, and therefore the synchronization clock is left
asynchronous.

Figure 9-7. Master NI PXI-665x Configures Software Trigger Routes

and Start Trigger Routes for Slave Chassis
Figure 9-8 shows the final routing steps, which concern the NI PXI-665x
modules in the slave chassis. Each module must be set up to input the sync
pulse on the PFI 0 SMB input and route it to PXI Trigger line 0. Then,
each slave NI PXI-665x must be configured to input the start trigger on
the PFI 1 SMB input and route this signal to any star trigger line where
a device resides. The first step is to call the niSync Connect Trigger
Terminals VI with a source of PFI0 and a destination of PXI_Trig0.
The sync pulse is set up to be resynchronized to the synchronization clock,
which in this example is the PXI_Clk10. For the next route the same
function is called, but this time with a source and destination of PFI1 and
the appropriate PXI Star Trigger, respectively. This route passes the trigger
asynchronously and is specified as such in the call to the VI.

Figure 9-8. Slave NI PXI-665x Configures Routing for Sync Pulse

and Start Trigger Inputs to Slave Chassis

Generations
The next two VIs called in this example deal primarily with setting up
output generations on the NI PXI-5411 devices. Refer to the NI-FGEN
documentation for more detailed information about configuration and
using the NI-FGEN software.
The first VI, the 5411 Sync Config VI, sets up all synchronization
parameters for the master and slave NI PXI-5411 devices in the system. For
this example, all NI PXI-5411 devices receive an external sync pulse on the
PXI Trigger bus line 0. The master NI PXI-5411 device generates a start
trigger based on receiving a signal of the appropriate level on the channel
designated as the Trigger Channel. The master NI PXI-5411 module
outputs this trigger to the PXI Trigger bus, where it is then routed to the
rest of the chassis in the system. All slave NI PXI-5411 devices receive an
external start trigger. All slave NI PXI-5411 modules receive their start
trigger on PXI Trigger line 1 on the backplane.

The second VI, the 5411 Gen Config VI, sets up all generation parameters
for the NI PXI-5411 devices in the system, such as the signal rate and
sample size. To simplify this example, it abstracts away many of the
configuration options the NI-FGEN software provides. As previously
described, more detailed information on these capabilities is beyond the
scope of this manual; you can find it in the user documentation for your
NI-FGEN software.
Beginning the Signal Generation

The next section discusses initiating the actual generation. Before this
can occur, the sync pulse must be sent to all NI PXI-5411 devices to align
all clock dividers already synchronized to the same system clock. The
665x Send Sync VI fires the NI PXI-665x software trigger which all
NI PXI-5411 devices use for their sync pulse. Figure 9-9 shows the
NI-Sync code that fires the software trigger previously configured in the
example by the 665x Route VI.
The VI in this example that handles this functionality is the 5411 Start
Gen VI. This VI initiates all NI PXI-5411 devices in the system. For the
master NI PXI-5411, initiating the generation means it begins signal
generation immediately on receipt of this software call and sends the start
trigger to the slave modules. Initiating the generation for slave NI PXI-5411
devices means they begin waiting for a start trigger on the appropriate
PXI Trigger Bus line.


reporting any errors that occurred during execution. The 5411 665x Close
VI closes all references to the NI PXI-5411 and NI PXI-665x devices
opened during initialization. Figure 9-10 shows the call to the niSync Close
VI that is called for each reference to an NI PXI-665x module opened.

calls to the driver are executed, and the error location and message are
passed to the Simple Error Handler VI and reported with a pop-up dialog.

IEEE 1588
10
IEEE 1588 specifies a technology to minimize clock skew to less than
a microsecond between networked devices. The NI PCI-1588 implements
the IEEE 1588 specification. For an overview of IEEE 1588 technology,
refer to the NI Developer Zone document at http://zone.ni.com/
devzone/conceptd.nsf/webmain/B40CBBA4A2B06A0B862570AF00
55BDBA.

NI PCI-1588 LabVIEW Examples
11
This chapter covers example LabVIEW VIs for use with the NI PCI-1588
and NI-Sync. The four examples cover applications such as starting the
Precision Time Protocol (PTP), time stamping, generating an event, and
generating a clock.
After installing NI-Sync, you can find additional 1588-related

example programs from the Windows Start menu at Programs»
National Instruments»NI-Sync»Examples.
Start PTP and Wait for Quality

Example Overview
This example shows how to reserve the 1588 clock on a device by starting
PTP and how to wait for the NI PCI-1588 clock to synchronize with other
1588 devices. The current 1588 time is displayed and updated after PTP is
started, the clock reaches a stable state, and the offset from master property
meets or exceeds the specified value for a period of time. You are not
required to start PTP on the NI PCI-1588 device to perform I/O operations.
However, if you want I/O operations performed by other examples to be
synchronized by PTP, you must leave this example running. Only one
session on the system can start PTP for a specific device. If multiple
NI PCI-1588 devices are installed in the system, each can participate in
PTP and can be managed by different sessions.

Chapter 11 NI PCI-1588 LabVIEW Examples
Figure 11-1 shows the Start PTP and Wait for Quality VI front panel.
Figure 11-1. Start PTP and Wait for Quality VI Front Panel
• Resource Name—An input that specifies the NI-VISA resource name
for the NI PCI-1588 device on which to start PTP.
• Is Preferred Master—A Boolean that specifies whether the
NI PCI-1588 is a member of the preferred master clock set. Clocks
in the preferred master clock set are favored over those not in the
set during the selection of the grandmaster clock. If you set the
“Is Preferred Master” property for one and only one 1588 device
participating in PTP, you can deterministically ensure that this
particular 1588 device becomes the master clock.
• Offset from Master Limit—An input for the Wait on Quality
example subVI. This value specifies the minimum offset from master
for this clock that is required before the 1588 Clock State, Offset from
Master, and Current 1588 Time indicators are updated. If the device is
chosen as the master, this input has no effect.
• 1588 Clock State—An output integer enumeration that specifies the
current 1588 clock state. The enumerated values for the property are
initializing, faulty, disabled, listening, pre-master, master, passive,
uncalibrated, and slave.
• Offset from Master—An output double that specifies the calculated
offset, in nanoseconds, from the master clock to the clock managed by

the session. You can use this property to determine when the clock is
sufficiently synchronized to continue with 1588-related operations. If
the device is chosen as the master, this value is not applicable.
• Current 1588 Time—An output LabVIEW time stamp that displays
the clock’s current 1588 time.
Figure 11-2 shows the Start PTP and Wait for Quality VI block diagram.
Figure 11-2. Start PTP and Wait for Quality VI Block Diagram
The subVIs execute in the following sequence when this VI runs:

1. niSync Initialize—Initializes a session to the specified device, which
is the first required step before PTP can be started or any I/O operation
can be performed with this device. This step requires a VISA resource
name for the device with which you want to start PTP or perform I/O
operations.
2. Set Is Preferred Master—Sets the Is Preferred Master property prior
to starting PTP. If you want to change the value of the Is Preferred
Master property from its default value of false, you should do so before
invoking the niSync Start PTP VI.
3. niSync Start PTP—Starts PTP on the device. This VI does not wait
or block to ensure that the clock enters a stable state.
4. Wait on Quality—Waits until the device’s clock state has become
master or slave and then waits until the offset from master property
meets or exceeds the specified value for a period of time. This is an
example that illustrates one way to wait for the clock on the device to
reach a stable state with a certain level of quality to ensure properly
synchronized I/O operations.

5. Read Clock State and Offset from Master Properties—Displays the

current clock state and, if the clock is a slave, its offset in nanoseconds
from the master clock. This is helpful to see if the device is in a master
or slave state. If the device is a 1588 slave, it also shows and updates
the offset from master property value to help monitor the current
synchronization quality.
6. niSync Get 1588 Time—Displays the clock’s current 1588 time.
7. niSync Stop PTP—Stops PTP. Once PTP is stopped, the device will
no longer be synchronized to other 1588 devices. All ongoing I/O
operations should be completed before stopping PTP. The 1588 clock
is now free to be reserved by another session.
8. niSync Close—If necessary, stops all ongoing operations associated
with this session and releases all resources reserved in the context of
this session.
Time Stamp
Example Overview
This example shows how to configure the NI PCI-1588 to time stamp a
trigger. The NI PCI-1588 can time stamp rising and/or falling edges of
signals on both the PFI and RTSI terminals. In this example, the trigger
must occur after the niSync Enable Time Stamp Trigger VI has executed,
but before the niSync Read Trigger Time Stamp VI times out. If you want
the time stamps to be based on a synchronized 1588 clock, run (and leave
running) the Start PTP and Wait for Quality example VI first. To perform
continuous time stamping or to time stamp multiple triggers, refer to the
Time Stamp Clock-Cont example VI.

Figure 11-3 shows the Time Stamp Trigger VI front panel.
Figure 11-3. Time Stamp Trigger VI Front Panel

for the NI PCI-1588 device on which to capture time stamps.
• Input Terminal—An input string enumeration that specifies the
terminal containing the digital signal that is the trigger. The
enumerated values for this input are PFI [0..2] and RTSI [0..7].
• Active Edge—An input integer enumeration that specifies the trigger
conditions. The enumerated values for this input are rising, falling, and
any.
• Detected Edge—An output integer enumeration that specifies the
detected trigger condition. The enumerated values for this output are
rising and falling.
• Trigger Time Stamp—An output LabVIEW time stamp that specifies
the time when the trigger associated with the specified terminal was
detected.

Figure 11-4 shows the Time Stamp Trigger VI block diagram.
Figure 11-4. Time Stamp Trigger VI Block Diagram

operations.
2. niSync Enable Time Stamp Trigger—Enables the NI PCI-1588 to
start time stamping on the specified input terminal. Any trigger that
occurs on the specified input terminal with the specified active edge is
time stamped and placed in a buffer that can later be read using the
niSync Read Trigger Time Stamp VI.
3. niSync Read Trigger Time Stamp—Reads the time stamp. The read
operation is a single-entry, destructive, blocking read. That is, the
oldest, nonread time stamp associated with the specified terminal is
returned. When a time stamp is read, it is removed from the buffer. The
VI does not return until a time stamp is available to be read or the
specified timeout elapses.
4. niSync Disable Time Stamp Trigger—Disables time stamping on the
specified terminal. The terminal is now free to be reserved for another
I/O operation.
this session.

Generate Event
Example Overview
This example shows how to configure the NI PCI-1588 to generate a single
event for controlling other operations. If you want the event to be based on
a synchronized 1588 clock, run (and leave running) the Start PTP and Wait
for Quality example VI first. To generate synchronized events on multiple
devices, you must communicate the time of the future time event to all
systems. To create a digital pulse, refer to the Generate Digital Pulse
example VI.
Figure 11-5 shows the Generate Event VI front panel.
Figure 11-5. Generate Event VI Front Panel

for the NI PCI-1588 device on which to generate the event.
• Output Terminal—An input string enumeration that specifies the
terminal generating the digital signal whose state is set to the specified
value. The enumerated values for this input are PFI [0..2] and
RTSI [0..7].
• Output level—An input integer enumeration that specifies the level to
set the digital signal to at the specified time. The enumerated values for
this input are high and low.

• Start Time Delay—An input that specifies the number of seconds to

add to the current time of the 1588 clock to produce a LabVIEW time
stamp that specifies when to change to the specified state of the digital
signal on the specified terminal.
• Event Time—An output LabVIEW time stamp that specifies the time
when the output level changes on the specified terminal.
Figure 11-6 shows the Generate Event VI block diagram.
Figure 11-6. Generate Event VI Block Diagram

operations.
2. niSync Get 1588 Time—Returns the current time of the 1588 clock
managed by this session, which is added to the specified delay to
calculate the time of the future time event.
3. niSync Create Future Time Event—Programs the output terminal to
change its state at the specified time to the specified output level.
Creating a future time event will immediately drive the specified
output terminal low until the future time event occurs.
4. Wait for Event—An example of how to wait for a future time event to
occur before closing the resource. Failing to wait for the future time
event to occur before calling the niSync Clear Future Time Events VI
causes the future time event to be canceled before it has occurred.

5. niSync Clear Future Time Events—Clears all future time events for
the specified terminal and tri-states the specified terminal. The
terminal is now free to be reserved for another I/O operation.
this session.
Generate Clock
Example Overview
This example shows how to configure the NI PCI-1588 to generate a clock.
This clock could be routed to devices via the RTSI bus or devices via the
PFI terminals to synchronize a system. The clock generation begins when
the current time of the 1588 clock reaches the specified clock start time. If
you want the clock to be based on a synchronized 1588 clock, run (and
leave running) the Start PTP and Wait for Quality example VI first.
Figure 11-7 shows the Generate Clock and Wait VI front panel.
Figure 11-7. Generate Clock and Wait VI Front Panel


for the NI PCI-1588 device on which to generate the clock.
• Output Terminal—An input string enumeration that specifies the
terminal generating the clock. The enumerated values for this input are
PFI [0..2] and RTSI [0..7].
• Desired Clock Frequency—An input that specifies the desired clock
frequency for the clock that is generated on the specified terminal. The
VI uses the clock frequency to calculate the closest integer high and
low ticks to divide down the 1588 clock.
• Start Time Delay—An input that specifies the number of seconds to
add to the current time of the 1588 clock to produce a LabVIEW time
stamp that specifies when to start the clock on the specified terminal.
• Clock Start Time—An output LabVIEW time stamp that displays the
time at which the clock starts.
• Current 1588 Time—An output LabVIEW time stamp that displays
the current 1588 time.
• Stop Button—Stops the clock and closes the session.
Figure 11-8 shows the Generate Clock and Wait VI block diagram.
Figure 11-8. Generate Clock and Wait VI Block Diagram


operations.
2. niSync Get 1588 Time—Returns the current time of the 1588 clock
managed by this session, which is added to the specified delay to
calculate the time when the clock starts.
3. Freq to Ticks—Converts the specified frequency to the corresponding
high period and low period ticks based on the resolution of the 1588
clock and a 50 percent duty cycle.
4. niSync Create Clock—Programs the output terminal to generate a
clock based on the 1588 clock and with the specified high and low
ticks. Other devices in a system could use the clock as a sample clock
or reference clock. Creating a clock will immediately drive the
specified output terminal low until the clock starts.
5. niSync Get 1588 Time—Returns the current time of the 1588 clock,
for determining if the clock has started.
6. niSync Clear Clock—Stops the clock for the specified terminal and
tri-states the specified terminal. The terminal is now free to be reserved
for another I/O operation.
this session.

Technical Support and
A
Professional Services
Visit the following sections of the National Instruments Web site at
ni.com for technical support and professional services:
• Support—Online technical support resources at ni.com/support
include the following:
– Self-Help Resources—For answers and solutions, visit the
award-winning National Instruments Web site for software drivers
and updates, a searchable KnowledgeBase, product manuals,
step-by-step troubleshooting wizards, thousands of example
programs, tutorials, application notes, instrument drivers, and
so on.
– Free Technical Support—All registered users receive free Basic
Service, which includes access to hundreds of Application
Engineers worldwide in the NI Developer Exchange at
ni.com/exchange. National Instruments Application Engineers
make sure every question receives an answer.
For information about other technical support options in your
area, visit ni.com/services or contact your local office at
ni.com/contact.
• Training and Certification—Visit ni.com/training for
self-paced training, eLearning virtual classrooms, interactive CDs,
and Certification program information. You also can register for
instructor-led, hands-on courses at locations around the world.
• System Integration—If you have time constraints, limited in-house
technical resources, or other project challenges, National Instruments
Alliance Partner members can help. To learn more, call your local
NI office or visit ni.com/alliance.
If you searched ni.com and could not find the answers you need, contact
your local office or NI corporate headquarters. Phone numbers for our
worldwide offices are listed at the front of this manual. You also can visit
the Worldwide Offices section of ni.com/niglobal to access the branch
office Web sites, which provide up-to-date contact information, support
phone numbers, email addresses, and current events.
© National Instruments Corporation A-1 NI-Sync User Manual

Glossary
Symbol Prefix Value

p pico 10 –12
n nano 10 –9
µ micro 10 – 6
m milli 10 –3
k kilo 10 3
M mega 10 6
G giga 10 9
T tera 10 12
Numbers/Symbols
1588 epoch A period of absolute time defined by the IEEE 1588 specification. The
current 1588 epoch is assigned the number 0 and started at 0 hours
1 January 1970. The length of a 1588 epoch is 232 seconds.
1588 grandmaster clock The 1588 clock to which all other 1588 devices in a specific PTP
subdomain are synchronized.
1588 master clock The 1588 clock to which other 1588 devices are synchronized if they are
directly connected to it (that is, they are not connected via a boundary
clock).
1588 time The time format specified by IEEE 1588. IEEE 1588 represents time as a
32-bit unsigned integer for the number of seconds and a 32-bit unsigned
integer for the number of nanoseconds since the 1588 epoch. From
1 January 1972 onward, 1588 time follows TAI time with an offset of
10 seconds.
% Percent.
± Plus or minus.
+ Positive of, or plus.
© National Instruments Corporation G-1 NI-Sync User Manual

Glossary
– Negative of, or minus.
/ Per.
° Degree.
Ω Ohm.
A
accumulator A part where numbers are totaled or stored.
ADE Application development environment.
asynchronous A property of an event that occurs at an arbitrary time, without

synchronization to a reference clock.
B
backplane An assembly, typically a printed circuit board (PCB), with 96-pin
connectors and signal paths that bus the connector pins. PXI systems
have two connectors, called the J1 and J2 connectors.
backplane The clock signal that is used to synchronize the RTSI/PXI triggers or
synchronization clock PXI_Star triggers on an NI PXI-665x.
bus The group of conductors that interconnect individual circuitry in a

computer. Typically, a bus is the expansion vehicle to which I/O or other
devices are connected. An example of a PC bus is the PCI bus.
C
C Celsius.
Clk In Clk In is a signal connected to the SMB input pin of the same name.
Clk In can serve as PXI_Clk10_IN or be used as a phase lock reference for
the OCXO.
Clk Out Clk Out is the signal on the SMB output pin of the same name. The OCXO
clock, DDS clock, or PXI_Clk10 may be routed to Clk Out.
NI-Sync User Manual G-2 ni.com

Glossary
clock Hardware component that controls timing for reading from or writing to
groups.
CompactPCI A Eurocard configuration of the PCI bus for industrial applications.
D
D/A Digital-to-analog.
DAC Digital-to-analog converter—an electronic device that converts a digital

number into a corresponding analog voltage or current.
DAQ Data acquisition—(1) collecting and measuring electrical signals from

sensors, transducers, and test probes or fixtures and inputting them to a
computer for processing; (2) collecting and measuring the same kinds of
electrical signals with A/D and/or DIO devices plugged into a computer,
and possibly generating control signals with D/A and/or DIO devices in the
same computer.
DC Direct current.
DDS Direct Digital Synthesis—a method of creating a clock with a

programmable frequency.
E
EEPROM Electrically erasable programmable read-only memory—ROM that can be
erased with an electrical signal and reprogrammed.
ESD Electrostatic discharge.
F
frequency The basic unit of rate, measured in events or oscillations per second using
a frequency counter or spectrum analyzer. Frequency is the reciprocal of
the period of a signal.
frequency tuning word A number that specifies the frequency.
front panel The physical front panel of an instrument or other hardware.

Glossary
G
GPS Global Positioning System—a system of satellites that broadcast accurate
times. GPS receivers acquire these times, which you can use to establish
geographic position. You can also use the time received as an accurate
clock source.
H
Hz Hertz—the number of scans read or updates written per second.
I
IEEE 1588 The IEEE specification that describes a synchronization protocol for clocks
of multiple devices connected via a network.
in. Inch or inches.
IP Internet Protocol—a packet-based protocol used to communicate between

multiple computer systems on a network. The IP is a low-level protocol on
top of which other, more reliable, protocols are often defined.
J
jitter The rapid variation of a clock or sampling frequency from an ideal constant
frequency.
L
LabVIEW A graphical programming language.
LED Light-Emitting Diode—a semiconductor light source.
M
master The requesting or controlling device in a master/slave configuration.

Glossary
Measurement & A controlled centralized configuration environment that allows you to

Automation configure all of your National Instruments DAQ, GPIB, IMAQ, IVI,
Explorer (MAX) Motion, VISA, and VXI devices.
N
NI-DAQ National Instruments driver software for DAQ hardware.
NIC Network Interface Card—a device that connects a computer system to a

network.
NTP Network Time Protocol—a protocol that synchronizes the clocks of

computers connected via an IP network. You may use NTP to synchronize
computer clocks over a very wide geographical area.
O
OCXO Oven-controlled crystal oscillator.
oscillator A device that generates a fixed frequency signal. An oscillator most often
generates signals by using oscillating crystals, but may also use tuned
networks, lasers, or atomic clock sources. The most important
specifications on oscillators are frequency accuracy, frequency stability,
and phase noise.
output impedance The measured resistance and capacitance between the output terminals of a
circuit.
P
PCI Peripheral Component Interconnect—a high-performance expansion bus
architecture originally developed by Intel to replace ISA and EISA. It is
achieving widespread acceptance as a standard for PCs and work-stations;
it offers a theoretical maximum transfer rate of 132 Mbytes/s.
PFI Programmable Function Interface.
PLL Phase-locked loop.
precision The measure of the stability of an instrument and its capability to give the
same measurement over and over again for the same input signal.

Glossary
propagation delay The amount of time required for a signal to pass through a circuit.
PTP Precision Time Protocol—the IEEE 1588-defined network protocol used to

synchronize the clocks of multiple devices connected via a network.
PXI A rugged, open system for modular instrumentation based on CompactPCI,

with special mechanical, electrical, and software features. The PXIbus
standard was originally developed by National Instruments in 1997, and is
now managed by the PXIbus Systems Alliance.
PXI star A special set of trigger lines in the PXI backplane for high-accuracy device
synchronization with minimal latencies on each PXI slot.
R
RTSI bus Real-Time System Integration bus—the NI timing bus that connects DAQ
devices directly, by means of connectors on top of the devices, for precise
synchronization of functions.
S
s Seconds.
skew The actual time difference between two events that would ideally occur
simultaneously. Inter-channel skew is an example of the time differences
introduced by different characteristics of multiple channels. Skew can
occur between channels on one module, or between channels on separate
modules (intermodule skew).
slave A computer or peripheral device controlled by another computer.
slot The place in the computer or chassis in which a card or module can be
installed.
Slot 2 The second slot in a PXI system which can house a master timing unit.
SMB Sub Miniature Type B—a small coaxial signal connector that features a
snap coupling for fast connection.
synchronous A property of an event that is synchronized to a reference clock.

Glossary
T
tCtoQ Clock to output time.
thold Hold time.
tpd Propagation delay time.
tsetup Setup time.
TAI International Atomic Time. Unlike UTC, TAI does not account for leap
seconds. Therefore, TAI is the time system employed by network standards
for which leap seconds may be problematic.
TRIG Trigger signal.
trigger A digital signal that starts or times a hardware event (for example, starting
a data acquisition operation).
U
UTC Coordinated Universal Time—the time system that accounts for leap
seconds and is employed by many network standards, including NTP.
V
V Volts.
VI Virtual instrument.

Index
Numerics C
5112 665x Check VI, 5-7 chassis configuration (figure)
5112 665x Close VI, 5-13 four chassis with synchronized
5112 665x Example VI, 5-2 acquisition, 4-29
front panel (figure), 5-3 three chassis with synchronized
5112 665x Init VI, 5-7 acquisition (with either a PC or an
5112 Acq Config VI, 5-13 embedded PXI controller), 4-21
5112 Start Acq VI, 5-13 two chassis with synchronized acquisition
5112 Sync Config VI, 5-12 and separate CPUs (embedded PXI
5411 665x Check VI, 9-8 controllers), 4-35
clearing a clock, 2-13
5411 665x Close VI, 9-15
clearing future time events, 2-12
5411 665x Example VI, 9-2
Clk10 routing for slave NI PXI-665x devices
front panel (figure), 9-3
(figure), 9-10
5411 665x Init VI, 9-8
clock configuration for slave NI PXI-665x
5411 Gen Config VI, 9-14
devices (figure), 6-8
5411 Start Acq VI, 9-14
clock terminals
5411 Sync Config VI, 9-13
connecting, 2-7
6115 665x Check VI, 6-6
disconnecting, 2-14
6115 665x Close VI, 6-13
closing a session, 2-15
6115 665x Example VI, 6-2, 6-5
closing each reference to an NI PXI-665x
front panel (figure), 6-3 (figure), 5-14, 9-15
6115 665x Init VI, 6-6
configuration, 1-1
6115 665x Network Example VI, 6-1 device and system, 1-3
6115 Sync Config VI, 6-12 Configure MIO Devices dialog (figure), 7-6
665x Route VI, 5-10, 5-13, 6-8, 9-10, 9-14 ConfigureChassisSlaves() function, 7-8
665x Send Sync VI, 5-13, 6-13, 9-14
ConfigureMaster665x() function, 7-7
ConfigureSlave665x() function, 7-7
A configuring
hardware, 2-6
accessing attributes, 2-7
measurements, 2-12
advanced features of NI-Sync, 2-17
connecting FPGA device digital outputs to
application software support, 1-2
physical terminals, 3-8
applications
connecting terminals, 2-7
building and programming, 2-1
conventions used in the manual, xiii
creating a clock, 2-11
creating a future time event, 2-11
© National Instruments Corporation I-1 NI-Sync User Manual

Index
creating Windows application F

using LabVIEW
firing the global software trigger on the master
developing NI-Sync application, 2-1 NI PXI-665x (figure), 5-13, 6-13, 9-14
example programs, 2-2 four chassis with synchronized acquisition
using LabWindows/CVI (figure), 4-29
developing NI-Sync application, 2-2 FPGA
example programs, 2-2 device I/O functions, 3-5
using Microsoft Visual C++, 2-2 device I/O resources (table), 3-6
developing NI-Sync application, 2-3 reconfiguration, 2-17
example programs, 2-3 VI digital output function for
special considerations, 2-3 PXI_Trig0, 3-8
VIs
communication with, 3-4
D interactive front panel
developing NI-Sync application, 2-1, 2-2, 2-3 communication, 3-4
device configuration, 1-3 programmatic FPGA interface
device support, 1-2 communication, 3-5
diagnostic tools (NI resources), A-1 executing, 3-4
disabling a timestamp trigger, 2-13 FPGA device I/O functions
disconnecting terminals, 2-14 arbitration, 3-7
documentation trigger input synchronization to
conventions used in manual, xiii PXI_Clk10, 3-7
NI resources, A-1 frequency measurement, 2-17
related documentation, xiv
drivers (NI resources), A-1
G
Generate Clock and Wait VI
E block diagram (figure), 11-10
enabling a timestamp trigger, 2-11 front panel (figure), 11-9
example NI-Sync programs for creating a generate clock example, 11-9
Windows application example overview, 11-9
using LabVIEW, 2-2 generate event example, 11-7
using LabWindows/CVI, 2-2 example overview, 11-7
using Microsoft Visual C++, 2-3 Generate Event VI
examples (NI resources), A-1 block diagram (figure), 11-8
execution targets, switching, 3-2 front panel (figure), 11-7
exporting oversample clock to PXI star getting 1588 time, 2-10
(figure), 4-3
external VISA input option for open FPGA VI
reference function (figure), 3-10
NI-Sync User Manual I-2 ni.com

Index
H overview, 8-23
simple event counting example
help technical support, A-1
FPGA VI, 8-2
host VI, 8-4
I overview, 8-1
IEEE 1588 overview, 10-1 using with NI-Sync
importing oversample clock to drive slave FPGA device I/O
ADCs (figure), 4-3 functions, 3-5, 3-7, 3-8
InitializeMaster665x() function, 7-6 introduction, 3-1
InitializeSlave665x() function, 7-6 programmatic FPGA interface
initializing, 2-6 communication, 3-9
installation, 1-1 external VISA input, 3-9
software, 1-3 special considerations, 3-5
instrument drivers (NI resources), A-1 LabWindows/CVI creating Windows
application using, 2-2
introduction, 1-1
K M
KnowledgeBase, A-1 master NI PXI-665x
configuring software trigger routes and
start trigger routes for slave chassis
L (figure), 5-11, 9-12
configuring software trigger routes for
LabVIEW
master chassis (figure), 5-10, 9-11
creating Windows application using, 2-1
routing for the start trigger (figure), 6-11
LabVIEW FPGA Module
scan clock routing (figure), 6-9
developing applications with NI-Sync
Master Trigger Channel, 5-2
communication with FPGA VIs, 3-4
MAX RIO device settings (figure), 3-3
executing FPGA VIs, 3-4
MAX. See Measurement & Automation
switching execution targets, 3-2
Explorer
period measurement example
Measure Period (FPGA) VI, 8-15
FPGA VI, 8-16
block diagram (figure), 8-17
host VI, 8-19
overview, 8-15
Measure Period VI, 8-15
pulse width measurement example
block diagram (figure), 8-20, 8-22, 8-23
FPGA VI, 8-8
host VI, 8-11
Measure Pulse Width (FPGA) VI, 8-7
overview, 8-7
PXI Clk10 synchronous input trigger
example
FPGA VI, 8-24
host VI, 8-27

Index
Measure Pulse Width VI, 8-7 example overview, 11-4

block diagram (figure), 8-13, 8-14, 8-15 NI PXI-4472
front panel (figure), 8-11 configuring the chassis, 4-13
Measurement & Automation Explorer four or more chassis with
identifying PXI system with, 1-4 synchronized acquisition and one
locating NI PXI-665x or NI PCI-1588 CPU, 4-26
with, 1-4 configuring and running the
NI PCI-1588 device information in software example, 4-31
(figure), 1-6 connecting the MXI-3
NI PXI-665x device information in devices, 4-30
(figure), 1-5 connecting the NI PXI-4472
using, 1-4 devices, 4-31
measurements connecting the
configuring and performing, 2-12 NI PXI-665x, 4-30
Microsoft Visual C++ getting started, 4-27
creating Windows application using, 2-2 using niSync_DSA_Example N
MIO_665x_Sync, 7-2 Chassis VI, 4-31
example front panel (figure), 7-3 one chassis with synchronized
acquisition and one CPU, 4-13
configuring and running
N software example, 4-15
National Instruments support connecting NI PXI-4472
and services, A-1 devices, 4-15
NI MIO modules connecting NI PXI-665x
device, 4-15
synchronizing multiple NI MIO
modules, 7-1 getting started, 4-15
theory of operation, 7-1 LabVIEW example, 4-14
NI PCI-1588 LabWindows/CVI
example, 4-14
device information
using niSync_DSA Example 1
in MAX (figure), 1-6
Chassis (Low Level) VI, 4-17
in Windows Device Manager
using niSync_DSA Example
(note), 1-3
Single Chassis VI, 4-16
LabVIEW examples, 11-1
using niSync_DSA_Example
generate clock example, 11-9
Single Chassis
example overview, 11-9 (LabWindows/CVI example
generate event example, 11-7 project), 4-17
example overview, 11-7 two chassis with synchronized
start PTP and wait for quality acquisition and two CPUs, 4-33
example, 11-1 configuring and running the
example overview, 11-1 software example, 4-36
time stamp example, 11-4

Index
connecting NI PXI-4472 modules with shared oversample clock

modules, 4-36 using the SYNC Pulse (figure), 4-5
connecting to Ethernet, 4-35 synchronizing data acquisition across
connecting to NI PXI-665x, 4-36 multiple NI PXI-4472 modules, 4-1
getting started, 4-34 synchronizing signals for multiple
LabVIEW example modules in a single chassis, 4-2
programs, 4-33 acquisition start trigger, 4-6
running the multi-CPU DSA delta-sigma ADCs and oversample
examples programs, 4-36 clock, 4-2
two or three chassis with NI PXI-4472 SYNC pulse, 4-4
synchronized acquisition and theory of operation, 4-1
one CPU, 4-18 NI PXI-5112
configuring and running the synchronizing multiple NI PXI-5112
software example, 4-22 modules, 5-1
connecting the MXI-3 theory of operation, 5-1
devices, 4-22 NI PXI-5411
connecting the NI PXI-4472 synchronizing multiple NI PXI-5411
devices, 4-22 modules, 9-1
connecting the NI PXI-665x theory of operation, 9-1
devices, 4-22 NI PXI-6115
getting started, 4-19 synchronizing data acquisition across
LabVIEW example multiple modules, 6-1
programs, 4-18 theory of operation, 6-1
LabWindows/CVI example NI PXI-665x
programs, 4-19 device information in MAX (figure), 1-5
using niSync_DSA Example 2 devices route PFI 0 on the Star Trigger
Chassis (Low Level) VI, 4-24 Line for each slot that contains an
using niSync_DSA_Example 2 NI PXI-6115 (figure), 6-10
or 3 Chassis Finite Acq VI and FPGA device I/O resources
niSync_DSA_Example 2 or 3 for (table), 3-6
Chassis Continuous
number of modules required per number
Acq VI, 4-23
of chassis (table), 4-27
using niSync_DSA_Example using to route synchronization signals
Dual Chassis Finite and between multiple chassis
niSync_DSA_Example Dual
sharing acquisition start trigger
Chassis Continuous Acq and
between chassis, 4-10
(LabWindows/CVI Example
sharing oversample clock between
Projects), 4-25
chassis, 4-7
using niSync_DSA_Example
sharing the SYNC pulse between
Dual Chassis Finite GUI
chassis, 4-9
(LabWindows/CVI example
project), 4-26

Index
using to route synchronization signals setting up a multichassis PXI system,

between multiple chassis (example), 5-4, 6-4, 7-4, 9-4
4-7, 5-2, 6-2, 7-2, 9-2 NI support and services, A-1
beginning the acquisition, 5-13, NI-Sync
6-13, 7-9 about, 1-1
beginning the signal generation, 9-14 application software support, 1-2
closing and error checking, 5-13, developing FPGA Module
6-13, 7-9, 9-15 applications, 3-2
configuring and running the software communication with FPGA VIs, 3-4
example, 5-6, 6-5, 7-5, 9-6 executing FPGA VIs, 3-4
configuring the 10 MHz timebase, switching execution targets, 3-2
5-8, 9-9 developing Windows application
configuring the MIO synchronization using LabVIEW, 2-1
and acquisitions, 7-8 using LabWindows/CVI, 2-2
configuring the NI PXI-5112 using Microsoft Visual C++, 2-3
synchronization and
device support, 1-2
acquisitions, 5-12
function calls to configure the master
configuring the NI PXI-5411
NI PXI-665x clock outputs (figure), 9-9
synchronization and
installing, 1-3
generations, 9-13
instrument driver API, 2-1
configuring the NI PXI-6115
synchronization and introduction, 1-1
acquisitions, 6-12 operating systems supported, 1-2
configuring the NI PXI-665x programming applications, 2-1
clocks, 6-7 programming flow, 2-4
configuring the scan clock, 7-7 advanced features, 2-17
connecting the MIO devices, 7-5 FPGA reconfiguration, 2-17
connecting the NI PXI-5112 frequency measurement, 2-17
devices, 5-6 clearing a clock, 2-13
connecting the NI PXI-5411 clearing future time events, 2-12
devices, 9-5 closing, 2-15
connecting the NI PXI-6115 configuring and performing
devices, 6-5 measurements, 2-12
connecting the NI PXI-665x configuring hardware, 2-6
devices, 5-5, 6-4, 7-4, 9-5 accessing attributes, 2-7
functionality, 5-7, 6-6, 7-6, 9-8 connecting terminals, 2-7
getting started, 5-4, 6-3, 7-3, 9-3 clock terminals, 2-7
initialization and error checking, 5-7, software trigger terminals, 2-9
6-6, 7-6, 9-8 trigger terminals, 2-8
routing the necessary creating a clock, 2-11
synchronization signals, 5-10, 6-8, creating a future time event, 2-11
7-7, 9-10 disabling a timestamp trigger, 2-13

Index
disconnecting terminals, 2-14 niSync Connect Software Trigger to

clock terminals, 2-14 Terminal VI, 5-11, 6-10
software trigger terminals, 2-14 niSync Connect Software Trigger VI, 2-9,
trigger terminals, 2-14 5-10, 9-10, 9-11
enabling a timestamp trigger, 2-11 niSync Connect Trigger Terminals VI, 2-9,
getting 1588 time, 2-10 5-11, 6-9, 6-11, 9-11, 9-12
initializing, 2-6 niSync Connect Trigger to Terminal VI, 5-11
NI PCI-1588 (figure), 2-5 niSync Create Clock VI, 2-12
NI PXI-665x (figure), 2-4 niSync Create Future Time Event VI, 2-11
reading a trigger timestamp, 2-12 niSync Disable Timestamp Trigger VI, 2-13
starting PTP, 2-10 niSync Disconnect Clock Terminals VI, 2-14
stopping PTP, 2-13 niSync Disconnect Software Trigger VI, 2-14
utility VIs, 2-15 niSync Disconnect Trigger Terminals VI, 2-14
instrument driver utility niSync Enable Timestamp Trigger VI, 2-11
functions, 2-16 niSync Error Message VI, 2-16
terminal connection niSync Get 1588 Time VI, 2-11
information, 2-15 niSync Get Clock Connection Info VI, 2-16
programming language support, 1-2 niSync Get Software Trigger Connection
using with LabVIEW FPGA Module, 3-1 Info VI, 2-16
connecting FPGA device digital niSync Get Trigger Connection Info VI, 2-16
outputs to physical terminals, 3-8 niSync Initialize VI, 2-6, 5-8, 6-7, 9-8
FPGA used to open sessions to NI PXI-665x
device I/O functions devices (figure), 5-8, 6-7
arbitration, 3-7 niSync Measure Frequency VI, 2-17
trigger input niSync Read Trigger Timestamp VI, 2-12
synchronization to niSync Reset VI, 2-16
PXI_Clk10, 3-7 niSync Revision Query VI, 2-16
introduction, 3-1 niSync Self-Test VI, 2-16
programmatic FPGA interface niSync Send Software Trigger VI, 2-9
communication, 3-9 niSync Start PTP VI, 2-10
external VISA input, 3-9 niSync Stop PTP VI, 2-13
special considerations, 3-5 NI-Sync VI for enabling PXI_Trig0
VI calls to configure the master NI connection from LabVIEW FPGA digital
PXI-665x clock outputs output (figure), 3-9
(figure), 5-9, 6-8 niSync_ClearClock function, 2-13
niSync Clear Clock VI, 2-13 niSync_ClearFutureTimeEvents
niSync Clear Future Time Events VI, 2-13 function, 2-13
niSync Close VI, 2-15, 5-13, 6-13, 9-15 niSync_close function, 2-15
niSync Configure FPGA VI, 2-17 niSync_ConfigureFPGA function, 2-17
niSync Connect Clock Terminals VI, 2-8, 5-9 niSync_ConnectClkTerminals function, 2-8

Index
niSync_ConnectSWTrigToTerminal niSync_GetClkTerminalConnectionInfo
function, 2-9 function, 2-16
niSync_ConnectTrigTerminals function, 2-9 niSync_GetSWTrigConnectionInfo
niSync_ConnectTrigTerminals() function, 7-7 function, 2-16
niSync_CreateClock function, 2-12 niSync_GetTrigTerminalConnectionInfo
niSync_CreateFutureTimeEvent function, 2-16
function, 2-11 niSync_init Function, 2-6
niSync_DisableTimestampTrigger niSync_MeasureFrequency function, 2-17
function, 2-13 niSync_ReadTriggerTimestamp
niSync_DisconnectClkTerminals function, 2-12
function, 2-14 niSync_reset function, 2-16
niSync_DisconnectSWTrigFromTerminal niSync_revision_query function, 2-16
function, 2-14 niSync_self_test function, 2-16
niSync_DisconnectTrigTerminals niSync_SendSoftwareTrigger function, 2-9
function, 2-14 niSync_SetAttributeViReal64() function, 7-7
niSync_DSA Example 1 Chassis niSync_StartPTP function, 2-10
(Low Level) VI, 4-17 niSync_StopPTP function, 2-13
niSync_DSA Example 2 or 3 Dual Chassis
Dual Controller (Main) VI, 4-36
front panel (figure), 4-38 O
niSync_DSA Example 2 or 3 Dual Chassis operating systems supported, 1-2
Dual Controller (Master) VI, 4-36 output multiplexer for PXI_Trig0 terminal
niSync_DSA Example 2 or 3 Dual Chassis (figure), 3-8
Dual Controller (Slave) VI, 4-36 oversample clock
niSync_DSA Example Single exporting to PXI star (figure), 4-3
Chassis VI, 4-16 importing to drive slave ADCs
system settings cluster for (figure), 4-16 (figure), 4-3
niSync_DSA_Example 2 or 3 Chassis NI PXI-4472 modules with shared
Continuous Acq VI oversample clock using the SYNC
system settings cluster for (figure), 4-23 pulse (figure), 4-5
niSync_DSA_Example 2 or 3 Chassis relationship with sample rate (table), 4-3
Continuous Acq.v, 4-23
niSync_DSA_Example 2 or 3 Chassis Finite
Acq VI, 4-23 P
system settings cluster for (figure), 4-23 performing measurements, 2-12
niSync_DSA_Example N Chassis VI, 4-31 period measurement example, 8-15
systems setting cluster for (figure), 4-32 FPGA VI, 8-16
niSync_EnableTimestampTrigger host VI, 8-19
function, 2-11 overview, 8-15
niSync_error_message function, 2-16 programmatic FPGA interface
niSync_Get1588Time function, 2-11 communication, 3-9

Index
programming applications, 2-1 simple event counting example, 8-1

programming examples (NI resources), A-1 FPGA VI, 8-2
programming flow, 2-4 host VI, 8-4
NI PCI-1588 (figure), 2-5 overview, 8-1
NI PXI-665x (figure), 2-4 Simple Event Counting VI, 8-1
programming language support, 1-2 block diagram (figure), 8-5, 8-6, 8-7
pulse width measurement example front panel (figure), 8-4
FPGA VI, 8-8 Slave Board Delay, 5-2
host VI, 8-11 slave NI PXI-665x configures routing for sync
overview, 8-7 pulse and start trigger inputs to slave chassis
PXI Clk10 Synchronous Input Trigger (figure), 5-12, 9-13
(FPGA) VI, 8-23 slave NI PXI-665x routing for the start trigger
block diagram (figure), 8-25 (figure), 6-12
front panel (figure), 8-24 software
PXI Clk10 synchronous input trigger example NI resources, A-1
FPGA VI, 8-24 installation, 1-3
host VI, 8-27 trigger terminals
overview, 8-23 connecting, 2-9
PXI Clk10 Synchronous Input disconnecting, 2-14
Trigger VI, 8-23 start PTP and wait for quality example, 11-1
block diagram (figure), 8-29, 8-30, 8-31 example overview, 11-1
front panel (figure), 8-27 Start PTP and Wait for Quality VI
R starting an acquisition on a trigger slave
reading a trigger timestamp, 2-12 (figure), 4-6
related documentation, xiv starting PTP, 2-10
reset period as a function of sample rate stopping PTP, 2-13
(table), 4-5 support technical, A-1
routing a start trigger and starting an system configuration, 1-3
acquisition on a trigger master (figure), 4-6 system settings cluster
niSync_DSA Example Single Chassis VI
(figure), 4-16
S niSync_DSA_Example 2 or 3 Chassis
sample rate and oversample clock, relationship Finite Acq VI and
between (table), 4-3 niSync_DSA_Example 2 or 3 Chassis
Simple Error Handler VI, 5-14, 6-13, 9-15 Continuous Acq VI (figure), 4-23
Simple Event Counting (FPGA) VI, 8-1 niSync_DSA_Example N Chassis VI
block diagram (figure), 8-3 (figure), 4-32

Index
T U
technical support, A-1 utility VIs, 2-15
three chassis with synchronized acquisition instrument driver utility functions, 2-16
(with either a PC or an embedded PXI terminal connection information, 2-15
controller) (figure), 4-21
time stamp example, 11-4
example overview, 11-4 W
Time Stamp Trigger VI Web resources, A-1
block diagram (figure), 11-6 Windows application
front panel (figure), 11-5 creating
training and certification (NI resources), A-1 using LabVIEW, 2-1
Trigger Level, 5-2 using LabWindows/CVI, 2-2
trigger master, routing a start trigger and using Microsoft Visual C++, 2-2
starting and acquisition on (figure), 4-6
trigger slave, starting an acquisition on
(figure), 4-6
trigger terminals
connecting, 2-8
disconnecting, 2-14
troubleshooting (NI resources), A-1
two chassis with synchronized acquisition and
separate CPUs (embedded PXI controllers)
(figure), 4-35

Synch Manual

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Synch Manual

Hochgeladen von

Copyright:

Verfügbare Formate

PXI

NI-Sync User Manual

NI-Sync User Manual

Worldwide Technical Support and Product Information

National Instruments Corporate Headquarters

© 2003–2005 National Instruments Corporation. All rights reserved.

WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

About This Manual

© National Instruments Corporation v NI-Sync User Manual

Start PTP ......................................................................................................... 2-10

NI-Sync User Manual vi ni.com

© National Instruments Corporation vii NI-Sync User Manual

Using niSync_DSA_Example Dual Chassis Finite GUI

NI-Sync User Manual viii ni.com

© National Instruments Corporation ix NI-Sync User Manual

NI-Sync User Manual x ni.com

© National Instruments Corporation xi NI-Sync User Manual

<> Angle brackets that contain numbers separated by an ellipsis represent

This icon denotes a note, which alerts you to important information.

This icon denotes a caution, which advises you of precautions to take to

italic Italic text denotes variables, emphasis, a cross reference, or an introduction

© National Instruments Corporation xiii NI-Sync User Manual

NI-Sync User Manual xiv ni.com

About the NI-Sync Driver Software

© National Instruments Corporation 1-1 NI-Sync User Manual

When developing your application, refer to Chapter 2, Building and

Operating System Support

The NI PCI-1588 supports:

Application Software and Programming Language Support

Table 1-1. National Instruments Application Software Support

NI Application Software Versions NI-Sync Supports

Table 1-2 lists additional programming languages supported by NI-Sync.

Table 1-2. Additional Programming Language Support

Programming Language Versions NI-Sync Supports

NI-Sync User Manual 1-2 ni.com

Installing the Software

Complete the following steps to install your NI-Sync software:

Several high-level examples are provided to give you a starting point in

Device and System Configuration

© National Instruments Corporation 1-3 NI-Sync User Manual

Using Measurement & Automation Explorer

Identifying Your PXI System

Locating Your NI PXI-665x or NI PCI-1588 Devices

Note Viewing NI PXI-665x or NI PCI-1588 device information in MAX is useful for

NI-Sync User Manual 1-4 ni.com

Figure 1-1. NI PXI-665x Device Information in MAX

© National Instruments Corporation 1-5 NI-Sync User Manual

Figure 1-2. NI PCI-1588 Device Information in MAX

NI-Sync User Manual 1-6 ni.com

The NI-Sync Instrument Driver

Creating a Windows Application Using LabVIEW

Developing an NI-Sync Application

© National Instruments Corporation 2-1 NI-Sync User Manual

Creating a Windows Application Using LabWindows/CVI

Developing an NI-Sync Application

Creating a Windows Application Using Microsoft

NI-Sync User Manual 2-2 ni.com

Developing an NI-Sync Application

© National Instruments Corporation 2-3 NI-Sync User Manual

NI-Sync Programming Flow

Figure 2-1. Basic Programming Flow of an NI-Sync Application

Figure 2-2 shows the basic programming flow of typical NI-Sync

NI-Sync User Manual 2-4 ni.com