Beruflich Dokumente
Kultur Dokumente
C8
C2
R2
C3 C5 C6 C7 R4
R3 C4
20 19 18 17 16 15 14 13 12 11
COMP
FB
BSTR
REF
IN
FT
OUTR
PGND
OL
AGND
U1 T1 HV
2
R1 MP1010B 1
CN1
PGND
OUTL
BSTL
BOS
C9
T/B
DR
EN
BR
IN
IL
10
1 2 3 4 5 6 7 8 9
J1
C12
5
BR
4
T/B
3 C13
EN
C14 R7
C11 C10 R5
C1 R8 R6
GND 2
C15
VBATT 1
FUSE
Pin Description
BR 1 20 AGND
IL 2 19 FB
BOS 3 18 OL
T/B 4 17 FT
EN 5 16 COMP
DR 6 15 REF
IN 7 14 IN
OUTL 8 13 OUTR
PGND 9 12 PGND
BSTL 10 11 BSTR
Note 1: For the MP1010BEF, connect the exposed paddle to AGND (Pin 20).
Feature Description
Brightness Control Excessive Secondary Current (Shorted Lamp and
UL safety specs): The FB pin (#19) is used to
The MP1010B can operate in three modes: detect whether excessive secondary current has
1. Analog Mode occurred. During normal operation the FB voltage is
a 1V p-p AC signal centered at zero volts D.C. If a
2. Burst Mode with a DC input fault condition occurs that increases the secondary
3. Burst Mode with an external PWM. current, then the voltage at FB will be greater than
1.2V. When that occurs, the IC regulates the FB
The three modes are dependent on the pin voltage to 2.4V p-p and a 120µA current source will
connections as per Table 1. inject into the FT pin. If the voltage at the FT pin
The MP1010B has a soft on and soft off feature to exceeds 1.2V, the chip will shut down.
reduce noise, when using burst mode dimming.
Lamp Startup
Table 1: Function Mode
The strike voltage of the lamp will always be
Function Pin Connection guaranteed at any temperature because the
Pin 1 Pin 4 Pin 3 MP1010B uses a resonant topology for switching
BR T/B BOS the outputs. The device will continue to switch at
Analog Mode 0 – 1.9V VREF AGND the resonant frequency of the tank until the strike
Burst Mode with R1 voltage is achieved. This eliminates the need for
VREF 0 – 1.8V
DC input voltage C1
external ramp timing circuits to ensure startup.
Burst Mode from
VREF PWM 1.5V
external source
Brightness Polarity: Fault Timer
Burst: 100% duty cycle is at 1.8V The timing for the fault timer will depend on the
Analog: 1.9V is maximum brightness sourcing current, as described above, and the
capacitor on the FT pin. The user can program the
Choosing the required burst repetition frequency time for the voltage to rise before the chip detects a
can be achieved by an RC combination, as defined “real“ fault. When a fault is triggered, then the
in component selection. internal drive voltage (VDR) will collapse from 6.2V
to 0V. The reference voltage will stay high at 5.0V.
Chip Enable
The chip has an on / off function, which is
controlled by the EN pin (#5). The enable signal
goes directly to a Schmitt trigger. The chip will turn
ON with an EN = High and OFF with an EN = Low.
Fault Protection
Open Lamp: The OL pin (#18) is used to detect
whether an open lamp condition has occurred.
During normal operation the OL pin is typically at
5V DC with an AC swing of +/- 2V. If an open lamp
condition exists then the AC voltage on the OL line
will swing below zero volts. When that occurs, the
IC regulates the OL voltage to 10V p-p and a 1µA
current source will inject into the FT pin. If the
voltage at the FT pin exceeds 1.2V, the chip will
shut down.
Packaging Information
0.0256(0.650)TYP
0.004(0.090)
0.010(0.250)
GATE PLANE
0.150(3.80)
PIN 1
0.165(4.19) 0.004(0.090)
IDENT. 0.169 0.244
0.177 0.260
0.105 (2.67) 0o-8 o
0.018(0.450)
0.118 (3.00) (4.300) (6.200) 0.030(0.750) DETAIL "A"
(4.500) (6.600)
0.030(0.750) 0.039(1.000)REF
0.007(0.190)
0.010(0.250)
NOTE:
1) Control dimension is in inches. Dimension in bracket is millimeters.
DETAIL "B"
NOTICE: MPS believes the information in this document to be accurate and reliable. However, it is subject to change
without notice. Please contact the factory for current specifications. No responsibility is assumed by MPS for its use or fit
to any application, nor for infringement of patent or other rights of third parties.