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A B C D E

1 1

Compal Confidential
2 2

ZIWB2/ZIWB3/ZIWE1
DIS M/B Schematics Document
Intel Boardwell U Processor with DDR3L

2014-02-10
3 3

LA-B092P
:1.0
REV:

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 1 of 53
A B C D E
A B C D E

For DIS
1 1

Jet LE(15W) PCIe X4


Topaz XT(25W) (Gen2)
Memory Bus
VRAM(DDR3L) 1GB/2GB/4GB
A-ch DDR3L-SO-DIMM X1
DDR3L 1600MHz (1.35V)

Memory Bus
eDP X1
B-ch DDR3L-SO-DIMM X1
(2 Lanes) DDR3L 1600MHz (1.35V)
eDP Panel

Left USB3.0 x2 Right USB2.0 x1 Int. Camera


DDI X1
Intel Broadwell U USB3.0 x2 USB30 Port 0,1 USB20 Port 0 USB20 Port 3

CRT Translator (2 Lanes) 15W


CRT Conn. ITE USB2.0 x7 Touch Screen Right USB2.0 x1 Finger Printer
2 IT6513 For E14 2
USB20 Port 2 USB20 Port 4
1168pin BGA USB20 Port 1
DDI X1
(4 Lanes)
HDMI Conn.
SATA X1 HDD Conn.
PCIe X1 SATA Port 0
LAN (1 Lanes)
PCIe Port 0
RJ45 Conn. Realtek
RTL8106E/RTL8111G SATA X1 ODD Conn.
10/100/GIGA SATA Port 1
PCIe X1
Card Reader (1 Lanes)
PCIe Port 2
Realtek Audio Codec
RTS5229-GR AZALIA Realtek
ALC233
PCIe X1
NGFF Conn. (1 Lanes)
3
WLAN / BT 3
USB2.0 X1 Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks
(1 Lanes) HP & MIC

PCIe Port 1
LPC BUS

Sub-borad SPI ROM EC


Nuvoton
15" 8MB NPCE288N
14"
DC-in/B Docking/B
For B15
Thermal Sensor Touch Pad Int. KBD APS
For E14
Power/B Battery/B LIS34ALTR

IO/B ODD/B
4 For E14 4

USB Charge

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 18, 2014 Sheet 2 of 53
A B C D E
1 2 3 4 5

Voltage Rails USB Port Table


3 External BOM Structure Table
USB 2.0 Port USB Port Item BOM Structure
+5VS 0 USB Port (Left Side) USB3.0 ZIWB2 (14") B14@
UHCI0
+3VS 1 USB Port (Left Side) USB3.0 ZIWB3 (15") B15@
power
plane +1.5VS 2 Touch Screen ZIWE1 (14") E14@
A UHCI1 A
+V1.05S_VCCP 3 Camera CPU_SA00006SM20 i5_4200U@
EHCI1
+5VALW +1.5V +VCC_CORE 4 CPU_SA00007AM00 QFSY@
UHCI2
+B +VGA_CORE 5 CPU_SA00006SU30 i3_4100U@
+3VALW +VCC_GFXCORE_AXG 6 CPU_SA000072Q10 i3_4005U@
UHCI3
+1.8VS 7 CPU_SA00006SX20 i3_4010U@
State +0.75VS 8 LAN 10/100 Transformer 100@
UHCI4
+1.05VS 9 USB Port (Right Side USB-BD) LAN GIGA Transformer GIGA@
10 Mini Card(WLAN) LAN Switch mode SWITCH@
EHCI2 UHCI5
11 Card Reader LAN RTL8106E-CG 8106ELDO@
12 LAN RTL8111GS-CG 8111GLDO@
UHCI6
13 LAN RTL8106EUS-CG 8106ESW@
LAN RTL8111GUS-CG 8111GSW@
S0 O O O O Audio_233 233@
Audio_233VB 233VB@
For B15 Docking@
S3 O O O X For B14, E14 NoDocking@
For Deep Sleep DS3@
S5 S4/AC
O O X X For No Deep Sleep NoDS3@
B
WLAN Support ISCT ISCT@ B
S5 S4/ Battery only
O X X X WLAN No Support ISCT NoISCT@
For Intel ZERO ODD ZODD@
S5 S4/AC & Battery
X X X X For No Intel ZERO ODD NoZODD@
don't exist
For Green CLK GCLK@
For No Green CLK NoGCLK@
For No Green CLK NoGCLKDIS@ Only in DIS Schematic
Green CLK IC For DIS GCLKDIS@
Green CLK IC For UMA GCLKUMA@
EC SM Bus1 address EC SM Bus2 address GPU support Single Rank SR@
Only in DIS Schematic
GPU support Dual Rank DR@
Device Address Device Address
Smart Battery 0001 011x Thermal Sensor 0100 1100
GPU Jet LE JET@
GPU Topaz XT TOPAZ@
For DIS PX@
PCH SM Bus address AMD-GPU SM Bus address For UMA UMA@
Camera COMS@
Device Address Device Address
DDR_JDIMM1 1010 000x A0h Internal thermal sensor 0100 0001 41h
DDR_JDIMM2 1010 010x A4h
APS (G-sensor) GS@
Touch Screen TS@
C HDMI HDMI@ C

SMBUS Control Table USB 2.0 USB2@


USB 3.0 USB3@
Thermal Full HD Panel (2 Lane) FHD@
SOURCE VGA BATT KB9012 SODIMM WLAN Sensor PCH
ENE EC 9012 9012@
SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X HDMI Royalty
Connector
45@
ME@
+3VALW
SMB_EC_CK2
SMB_EC_DA2
KB9012 V
+3VGS
X X X X +3VS
V V
+3VALW
VRAM indentify
Un-pop component for EMI
X76@
@EMI@
No USE
+3VS
PCH_SMBCLK
X X X V V X X @ESD@
Un-pop component for ESD
PCH
PCH_SMBDATA +3VALW +3VS +3VS DA600140000 PCB_14_DIS@
PCH_SML0CLK
PCH
PCH_SML0DATA +3VALW
X X X X X X X DA600141000
DA600140100
PCB_14_UMA@
PCB_15_DIS@
SML1CLK
SML1DATA
PCH
+3VALW +3VGS
V X V
+3VS
X X V
+3VS
X DA600141100 PCB_15_UMA@

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

D Full ON HIGH HIGH HIGH HIGH ON ON ON ON D

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF


Security Classification Compal Secret Data Compal Electronics, Inc.
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Notes List
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Wednesday, February 19, 2014 Sheet 3 of 53
1 2 3 4 5
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B092P
Date: Tuesday, February 18, 2014 Sheet 4 of 53
5 4 3 2 1
5 4 3 2 1

DAZ
DAZ14J00101
PCB 14I LA-B091P REV0 M/B DIS 3
PCB_B14_DIS@

DAZ
DAZ14L00101
PCB 14K LA-B091P REV0 M/B DIS 6
PCB_B15_DIS@

DAZ
DAZ14N00101
PCB 14K LA-B091P REV0 M/B DIS 6
PCB_E14_DIS@

DAZ
D D
DAZ14J00201
PCB 14I LA-B092P REV0 M/B UMA 3
PCB_B14_UMA@ UC1A BDW_ULT_DDR3L(Interleaved)

DAZ
DAZ14L00201
PCB 14K LA-B092P REV0 M/B UMA 6
PCB_B15_UMA@ C54 C45
<29> CPU_DP1_N0 C55 DDI1_TXN0 EDP_TXN0 B46 EDP_TXN0 <27>
<29> CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 <27>
DAZ CRT B58 A47
<29> CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 <27>
DAZ14N00201 C58 B47
<29> CPU_DP1_P1 B55 DDI1_TXP1 EDP_TXP1 EDP_TXP1 <27>
PCB 14K LA-B092P REV0 M/B UMA 6
PCB_E14_UMA@ A55 DDI1_TXN2 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
eDP
CPU_DP2_N0 C51 EDP_TXP3
<37> CPU_DP2_N0 DDI2_TXN0
CPU_DP2_P0 C50 A45 EDP_AUXN <27>
<37> CPU_DP2_P0 C53 DDI2_TXP0 EDP_AUXN B45
CPU_DP2_N1 EDP_AUXP <27>
<37> CPU_DP2_N1 DDI2_TXN1 EDP_AUXP
CPU_DP2_P1 B54
<37> CPU_DP2_P1 DDI2_TXP1
CPU_DP2_N2 C49 D20 EDP_COMP R1 1 2 24.9_0402_1%
HDMI <37> CPU_DP2_N2
CPU_DP2_P2 B50 DDI2_TXN2 EDP_RCOMP A43 CPU_INV_PWM
+VCCIOA_OUT
<37> CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
CPU_DP2_N3 A53 T1
<37> CPU_DP2_N3 B53 DDI2_TXN3
CPU_DP2_P3
<37> CPU_DP2_P3 DDI2_TXP3
EDP_COMP (R1):
Trace width=20 mils,Spacing=25mil,Max length=100mils
1 OF 19
BDW-ULT-DDR3L-IL_BGA1168
@

C C

UC1B BDW_ULT_DDR3L(Interleaved)

T2 D61
T3 K61 PROC_DETECT MISC
+1.05VS N62 CATERR J62 XDP_PRDY# T31
<35> H_PECI PECI PRDY K62 XDP_PREQ# T32
R2 1 2 62_0402_5% PREQ E60 XDP_TCK T4
PROC_TCK E61 XDP_TMS T5
R3 1 2 56_0402_5% H_PROCHOT#_R K63 JTAG PROC_TMS E59 XDP_TRST# T6
<35> H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI T7
PROC_TDI F62 XDP_TDO T8
PROC_TDO
R4 1 2 10K_0402_5% H_CPUPWRGD C61
PROCPWRGD PWR
J60 XDP_BPM#0
BPM#0 H60 XDP_BPM#1
BPM#1 H61 XDP_BPM#2
+1.35V BPM#2 H62 XDP_BPM#3
R5 1 2 200_0402_1% SM_RCOMP0 AU60 BPM#3 K59 XDP_BPM#4
R6 1 2 470_0402_5% R7 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_BPM#5
R8 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM#6
DIMM_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_BPM#7
<16,17> DIMM_DRAMRST# SM_DRAMRST BPM#7
DDR_PG_CTRL AV61
<16> DDR_PG_CTRL SM_PG_CNTL1
1

C238 DDR3 Compensation Signals (R9, R10, R11): 2 OF 19


100P_0402_50V8J BDW-ULT-DDR3L-IL_BGA1168
20 mils to comp signals
2

25 mils to non-comp signals


500 mil for Max trace length

B ESD ESD B

H_CPUPWRGD
1

UC1
C237 SA00007G030
100P_0402_50V8J Intel 2957U 1.4G 2M D0 2cBGA CPU
2

2957U@

UC1
SA00007G230
S IC CL8064701569500 QFAN D0 1.7G BGA
3558U@

UC1
SA00006SLA0
S IC CL8064701477202 QEVD C0 1.8G BGA
i7_4500U@

UC1
SA00006SMC0
S IC CL8064701477702 SR170 C0 1.6G C38!
i5_4200U@

UC1
SA00007AM00
S IC CL8064701614813 QFSY C0 1.6G BGA
QFSY@

UC1
SA00006SU30
S IC CL8064701476302 SR16P C0 1.8G C38!
i3_4100U@

UC1
SA000072Q50
S IC CL8064701478404 QEAR D0 1.7G C38
A i3_4005U@ A

UC1
SA00006SX80
S IC CL8064701478202 SR16Q C0 1.7G C38!
i3_4010U@

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(1/11) DDI,MSIC,XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 5 of 53
5 4 3 2 1
5 4 3 2 1

Interleaved Memory

D D

UC1C BDW_ULT_DDR3L(Interleaved) UC1D BDW_ULT_DDR3L(Interleaved)

<16> DDR_A_D[0..15]
DDR_A_D0 AH63 AU37 M_CLK_DDR#0 M_CLK_DDR#0 <16>
SA_DQ0 SA_CLK#0 <17> DDR_B_D[0..15]
DDR_A_D1 AH62 AV37 M_CLK_DDR0 DDR_B_D0 AP58 AM38 M_CLK_DDR#2
SA_DQ1 SA_CLK0 M_CLK_DDR0 <16> SB_DQ0 SB_CK#0 M_CLK_DDR#2 <17>
DDR_A_D2 AK63 AW36 M_CLK_DDR#1 DDR_B_D1 AR58 AN38 M_CLK_DDR2
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <16> SB_DQ1 SB_CK0 M_CLK_DDR2 <17>
DDR_A_D3 AK62 AY36 M_CLK_DDR1 M_CLK_DDR1 <16> DDR_B_D2 AM57 AK38 M_CLK_DDR#3 M_CLK_DDR#3 <17>
DDR_A_D4 AH61 SA_DQ3 SA_CLK1 DDR_B_D3 AK57 SB_DQ2 SB_CK#1 AL38 M_CLK_DDR3
SA_DQ4 SB_DQ3 SB_CK1 M_CLK_DDR3 <17>
DDR_A_D5 AH60 AU43 DDR_CKE0_DIMMA DDR_CKE0_DIMMA <16> DDR_B_D4 AL58
DDR_A_D6 AK61 SA_DQ5 SA_CKE0 AW43 DDR_CKE1_DIMMA DDR_B_D5 AK58 SB_DQ4 AY49 DDR_CKE2_DIMMB
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <16> SB_DQ5 SB_CKE0 DDR_CKE2_DIMMB <17>
DDR_A_D7 AK60 AY42 DDR_B_D6 AR57 AU50 DDR_CKE3_DIMMB
SA_DQ7 SA_CKE2 T13 SB_DQ6 SB_CKE1 DDR_CKE3_DIMMB <17>
DDR_A_D8 AM63 AY43 T9 DDR_B_D7 AN57 AW49 T10
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D8 AP55 SB_DQ7 SB_CKE2 AV50
SA_DQ9 SB_DQ8 SB_CKE3 T11
DDR_A_D10 AP63 AP33 DDR_CS0_DIMMA# DDR_CS0_DIMMA# <16> DDR_B_D9 AR55
DDR_A_D11 AP62 SA_DQ10 SA_CS#0 AR32 DDR_CS1_DIMMA# DDR_B_D10 AM54 SB_DQ9 AM32 DDR_CS2_DIMMB#
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <16> SB_DQ10 SB_CS#0 DDR_CS2_DIMMB# <17>
DDR_A_D12 AM61 DDR_B_D11 AK54 AK32 DDR_CS3_DIMMB#
SA_DQ12 SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# <17>
DDR_A_D13 AM60 AP32 T12 DDR_B_D12 AL55
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D13 AK55 SB_DQ12 AL32
SA_DQ14 SB_DQ13 SB_ODT0 T14
DDR_A_D15 AP60 AY34 DDR_A_RAS# DDR_A_RAS# <16> DDR_B_D14 AR54
<16> DDR_A_D[16..31] SA_DQ15 SA_RAS SB_DQ14
DDR_A_D16 AY58 AW34 DDR_A_WE# DDR_B_D15 AN54 AM35 DDR_B_RAS#
SA_DQ16 SA_WE DDR_A_WE# <16> <17> DDR_B_D[16..31] SB_DQ15 SB_RAS DDR_B_RAS# <17>
DDR_A_D17 AW58 AU34 DDR_A_CAS# DDR_B_D16 AK40 AK35 DDR_B_WE#
SA_DQ17 SA_CAS DDR_A_CAS# <16> SB_DQ16 SB_WE DDR_B_WE# <17>
C DDR_A_D18 AY56 DDR_B_D17 AK42 AM33 DDR_B_CAS# DDR_B_CAS# <17> C
DDR_A_D19 AW56 SA_DQ18 AU35 DDR_A_BS0 DDR_B_D18 AM43 SB_DQ17 SB_CAS
SA_DQ19 SA_BA0 DDR_A_BS0 <16> SB_DQ18
DDR_A_D20 AV58 AV35 DDR_A_BS1 DDR_A_BS1 <16> DDR_B_D19 AM45 AL35 DDR_B_BS0 DDR_B_BS0 <17>
DDR_A_D21 AU58 SA_DQ20 SA_BA1 AY41 DDR_A_BS2 DDR_B_D20 AK45 SB_DQ19 SB_BA0 AM36 DDR_B_BS1
SA_DQ21 SA_BA2 DDR_A_BS2 <16> SB_DQ20 SB_BA1 DDR_B_BS1 <17>
DDR_A_D22 AV56 DDR_B_D21 AK43 AU49 DDR_B_BS2
SA_DQ22 DDR_A_MA[0..15] <16> SB_DQ21 SB_BA2 DDR_B_BS2 <17>
DDR_A_D23 AU56 AU36 DDR_A_MA0 DDR_B_D22 AM40 DDR_B_MA[0..15] <17>
DDR_A_D24 AY54 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D23 AM42 SB_DQ22 AP40 DDR_B_MA0
DDR_A_D25 AW54 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D24 AM46 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D26 AY52 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D25 AK46 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D27 AW52 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D26 AM49 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D28 AV54 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D27 AK49 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D29 AU54 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D28 AM48 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D30 AV52 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D29 AK48 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D31 AU52 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDR_A_MA8 DDR_B_D30 AM51 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
<16> DDR_A_D[32..47] AY31 SA_DQ31 SA_MA8 AU40 AK51 SB_DQ30 SB_MA7 AY47
DDR_A_D32 DDR_A_MA9 DDR_B_D31 DDR_B_MA8
SA_DQ32 SA_MA9 <17> DDR_B_D[32..47] SB_DQ31 DDR CHANNEL B SB_MA8
DDR_A_D33 AW31 AP35 DDR_A_MA10 DDR_B_D32 AM29 AU46 DDR_B_MA9
DDR_A_D34 AY29 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D33 AK29 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D35 AW29 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D34 AL28 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D36 AV31 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D35 AK28 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D37 AU31 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D36 AR29 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D38 AV29 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D37 AN29 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D39 AU29 SA_DQ38 SA_MA15 DDR_B_D38 AR28 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
SA_DQ39 DDR_A_DQS#[0..1] <16> SB_DQ38 SB_MA15
DDR_A_D40 AY27 AJ61 DDR_A_DQS#0 DDR_B_D39 AP28 DDR_B_DQS#[0..1] <17>
DDR_A_D41 AW27 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D40 AN26 SB_DQ39 AM58 DDR_B_DQS#0
SA_DQ41 SA_DQSN1 DDR_A_DQS#[2..3] <16> SB_DQ40 SB_DQSN0
DDR_A_D42 AY25 AV57 DDR_A_DQS#2 DDR_B_D41 AR26 AM55 DDR_B_DQS#1
SA_DQ42 SA_DQSN2 SB_DQ41 SB_DQSN1 DDR_B_DQS#[2..3] <17>
DDR_A_D43 AW25 AV53 DDR_A_DQS#3 DDR_A_DQS#[4..5] <16> DDR_B_D42 AR25 AL43 DDR_B_DQS#2
DDR_A_D44 AV27 SA_DQ43 SA_DQSN3 AW30 DDR_A_DQS#4 DDR_B_D43 AP25 SB_DQ42 SB_DQSN2 AL48 DDR_B_DQS#3
SA_DQ44 SA_DQSN4 SB_DQ43 SB_DQSN3 DDR_B_DQS#[4..5] <17>
DDR_A_D45 AU27 AV26 DDR_A_DQS#5 DDR_A_DQS#[6..7] <16> DDR_B_D44 AK26 AN28 DDR_B_DQS#4
DDR_A_D46 AV25 SA_DQ45 SA_DQSN5 AW22 DDR_A_DQS#6 DDR_B_D45 AM26 SB_DQ44 SB_DQSN4 AN25 DDR_B_DQS#5
SA_DQ46 SA_DQSN6 SB_DQ45 SB_DQSN5 DDR_B_DQS#[6..7] <17>
DDR_A_D47 AU25 AV18 DDR_A_DQS#7 DDR_B_D46 AK25 AN21 DDR_B_DQS#6
<16> DDR_A_D[48..63] SA_DQ47 SA_DQSN7 SB_DQ46 SB_DQSN6
DDR_A_D48 AY23 DDR_A_DQS[0..1] <16> DDR_B_D47 AL25 AN18 DDR_B_DQS#7
AW23 SA_DQ48 AJ62 <17> DDR_B_D[48..63] AR21 SB_DQ47 SB_DQSN7
DDR_A_D49 DDR_A_DQS0 DDR_B_D48 DDR_B_DQS[0..1] <17>
DDR_A_D50 AY21 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D49 AR22 SB_DQ48 AN58 DDR_B_DQS0
SA_DQ50 SA_DQSP1 DDR_A_DQS[2..3] <16> SB_DQ49 SB_DQSP0
DDR_A_D51 AW21 AW57 DDR_A_DQS2 DDR_B_D50 AL21 AN55 DDR_B_DQS1
SA_DQ51 SA_DQSP2 SB_DQ50 SB_DQSP1 DDR_B_DQS[2..3] <17>
DDR_A_D52 AV23 AW53 DDR_A_DQS3 DDR_B_D51 AM22 AL42 DDR_B_DQS2
SA_DQ52 SA_DQSP3 DDR_A_DQS[4..5] <16> SB_DQ51 SB_DQSP2
DDR_A_D53 AU23 AV30 DDR_A_DQS4 DDR_B_D52 AN22 AL49 DDR_B_DQS3 DDR_B_DQS[4..5] <17>
DDR_A_D54 AV21 SA_DQ53 SA_DQSP4 AW26 DDR_A_DQS5 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AM28 DDR_B_DQS4
SA_DQ54 SA_DQSP5 DDR_A_DQS[6..7] <16> SB_DQ53 SB_DQSP4
DDR_A_D55 AU21 AV22 DDR_A_DQS6 DDR_B_D54 AK21 AM25 DDR_B_DQS5 DDR_B_DQS[6..7] <17>
B
DDR_A_D56 AY19 SA_DQ55 SA_DQSP6 AW18 DDR_A_DQS7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6 B
DDR_A_D57 AW19 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D58 AY17 SA_DQ57 AP49 +SM_VREF_CA DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA +SM_VREF_CA <16> SB_DQ57
DDR_A_D59 AW17 AR51 +SM_VREF_DQ0 DDR_B_D58 AK18
SA_DQ59 SM_VREF_DQ0 +SM_VREF_DQ0 <16> SB_DQ58
DDR_A_D60 AV19 AP51 +SM_VREF_DQ1 +SM_VREF_DQ1 <17> DDR_B_D59 AL18
DDR_A_D61 AU19 SA_DQ60 SM_VREF_DQ1 DDR_B_D60 AK20 SB_DQ59
DDR_A_D62 AV17 SA_DQ61 DDR_B_D61 AM20 SB_DQ60
SA_DQ62 Trace width >= 10mils SB_DQ61
DDR_A_D63 AU17 DDR_B_D62 AR18
SA_DQ63 DDR_B_D63 AP18 SB_DQ62
SB_DQ63

3 OF 19 4 OF 19
BDW-ULT-DDR3L-IL_BGA1168 BDW-ULT-DDR3L-IL_BGA1168

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(2/11) DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 6 of 53
5 4 3 2 1
5 4 3 2 1

D D

GCLK
RG3 1 GCLK@ 2 0_0402_5% PCH_RTCX1
<41> CPU_RTCX1_GCLK

PCH_RTCX1

R9 1NOGCLK@ 2 10M_0402_5% PCH_RTCX2


2

UC1E BDW_ULT_DDR3L(Interleaved)
R10
0_0402_5%
Y1 PCH_RTCX1 AW5
RTCX1
1

1 2 PCH_RTCX2 AY5
SM_INTRUDER# AU6 RTCX2 J5
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 <30>
32.768KHZ 12.5PF 9H03200031 PCH_INTVRMEN AV7 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0 <30>
NOGCLK@ PCH_SRTCRST# AV6 RTC B15
SJ10000HW00 PCH_RTCRST# AU7 SRTCRST SATA_TN0/PETN6_L3 A15
SATA_PTX_DRX_N0 <30> HDD
1 1 RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 <30>
C1 C2
12P_0402_50V_NPO 12P_0402_50V_NPO J8 SATA_PRX_DTX_N1 <30>
NOGCLK@ NOGCLK@ SATA_RN1/PERN6_L2 H8
2 2 SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1 <30>
HDA for AUDIO A17
SATA_TN1/PETN6_L2 B17
SATA_PTX_DRX_N1 <30> ODD
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <30>
RP1
<39> HDA_BITCLK_AUDIO 1 8 HDA_BIT_CLK AW8 J6
2 7 HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
<39> HDA_SYNC_AUDIO HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
3 6 HDA_RST# AU8 B14
<39> HDA_RST_AUDIO# HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1
C <39> HDA_SDOUT_AUDIO 4 5HDA_SDOUT HDA_SDIN0 AY10 C15 C
AU12 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
33_0804_8P4R_5% HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0

1
@EMI@ AW10 E5
C227 AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
22P_0402_50V8J
EMI AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17

2
I2S1_SCLK SATA_TP3/PETP6_L0
+RTCVCC
V1 PCH_GPIO34
1 2 0_0402_5% SATA0GP/GPIO34 U1 PCH_GPIO34 <10>
<35> ME_EN R11 SATA_ODD_PRSNT SATA_ODD_PRSNT <30,9>
R12 1 2 20K_0402_5% PCH_SRTCRST# HDA_SDIN0 SATA1GP/GPIO35 V6 PCH_GPIO36 +1.05VS_ASATA3PLL
<39> HDA_SDIN0 SATA2GP/GPIO36 PCH_GPIO36 <9>
AC1 PCH_GPIO37
SATA3GP/GPIO37 PCH_GPIO37 <10>
C3 1 2 1U_0402_6.3V6K PCH_JTAG_TRST# AU62
PCH_JTAG_TCK AE62 PCH_TRST A12
CLRP1 1 2 SHORT PADS PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
Clear ME PCH_TDI RSVD
PCH_JTAG_TDO AE61 K10 within 500 mils
PCH_JTAG_TMS AD62 PCH_TDO JTAG
RSVD C12 SATA_RCOMP R13 1 2 3.01K_0402_1%
R14 1 2 20K_0402_5% PCH_RTCRST# AL11 PCH_TMS SATA_RCOMP U3 PCH_SATALED#
RSVD SATALED PCH_SATALED# <33>
AC4
C4 1 2 1U_0402_6.3V6K AE63 RSVD
AV2 JTAGX
CLRP2 1 2 SHORT PADS RSVD
Clear CMOS

R15 1 2 1M_0402_5% SM_INTRUDER#


5 OF 19
BDW-ULT-DDR3L-IL_BGA1168
R16 1 2 330K_0402_5% PCH_INTVRMEN
+3VS
R17 1 @ 2 330K_0402_5%

INTVRMEN: PCH_SATALED# R18 1 2 10K_0402_5%


: Integrated VRM enable
(*) H:
: Integrated VRM disable
( ) L:

B B
RTC Battery
+RTCVCC +RTCBATT

W=20mils
R19 1 2 0_0402_5%

1
C5
1U_0402_6.3V6K

Safty suggestion remove EE side ,Keep PWR side

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(3/11) RTC,SATA,XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 7 of 53
5 4 3 2 1
5 4 3 2 1

GCLK
RG9 1 GCLK@ 2 0_0402_5% XTAL24_IN
<41> CPU_XTAL24_IN_GCLK

UC1F BDW_ULT_DDR3L(Interleaved)

XTAL24_IN

C43 A25 XTAL24_IN R21 2NOGCLK@ 1 1M_0402_5% XTAL24_OUT


C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
PCH_GPIO18 U2 CLKOUT_PCIE_P0 XTAL24_OUT NOGCLK@
<10> PCH_GPIO18 PCIECLKRQ0/GPIO18 Y2
K21 24MHZ_12PF_7V24000020
D
B41 RSVD M21 D
<40> CLK_PCIE_CR# A41 CLKOUT_PCIE_N1 RSVD C26 1 2 3.01K_0402_1% 1 3
Card Reader XCLK_BIASREF R22 +1.05VS_AXCK_LCPLL SJ10000DI00
<40> CLK_PCIE_CR CLKOUT_PCIE_P1 DIFFCLK_BIASREF 1 3
<40> CRCLK_REQ# Y5
PCIECLKRQ1/GPIO19 C35 RP3 4 5 10K_8P4R_5% GND GND
TESTLOW_C35 1 1
C41 CLOCK C34 3 6 C6 C7
<38> CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34 2 4
B42 AK8 2 7 15P_0402_50V8J 15P_0402_50V8J
LAN <38> CLK_PCIE_LAN AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 1 8 NOGCLK@ NOGCLK@
<38> LANCLK_REQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8 2 2
B38 AN15 CLKOUT_LPC0 R23 2 1 22_0402_5%
<31> CLK_PCIE_WLAN# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CK_LPC_KBC <35>
WLAN C37 AP15
<31> CLK_PCIE_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1
N1
<31> WLANCLK_REQ#
A39
B39
PCIECLKRQ3/GPIO21

CLKOUT_PCIE_N4
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
B35
A35 EMI
GPUCLK_REQ#_R U5 CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5
PCH_GPIO23 T2 CLKOUT_PCIE_P5
<10> PCH_GPIO23 PCIECLKRQ5/GPIO23
+3VS
+3VS 6 OF 19
RP4 BDW-ULT-DDR3L-IL_BGA1168
:DIMM1, DIMM2
SMB:
1

UMA@ 1 8
R26 2 7 PCH_GPIO32
PCH_GPIO32 <9> +3VS
10K_0402_5% 3 6
4 5
2

10K_8P4R_5% @ R27 2.2K_0402_5%

2
GPUCLK_REQ#_R UC1G BDW_ULT_DDR3L(Interleaved) Q1A 1 2 +3VS
2

LPC_AD0 AU14 AN2 PCH_GPIO11 SMBDATA 6 1


<35> LPC_AD0 LAD0 SMBALERT/GPIO11 PCH_GPIO11 <10> PCH_SMB_DATA <16,17>
PX@ LPC_AD1 AW12 AP2 SMBCLK
<35> LPC_AD1 AY12 LAD1 SMBCLK AH1
R28 LPC_AD2 LPC SMBDATA DMN65D6LDW-7 2N SOT363-6
<35> LPC_AD2 LAD2 SMBUS SMBDATA
10K_0402_5% LPC_AD3 AW11 AL2 PCH_GPIO60
<35> LPC_AD3 LAD3 SML0ALERT/GPIO60 PCH_GPIO60 <10>
LPC_FRAME# AV12 AN1 SML0CLK @ R29 2.2K_0402_5%
<35> LPC_FRAME#
1

LFRAME SML0CLK

5
AK1 SML0DATA Q1B 1 2
SML0DATA +3VS
C AU4 PCH_GPIO73 C
SML1ALERT/PCHHOT/GPIO73 AU3 PCH_GPIO73 <10> 3 4
SML1CLK SMBCLK
+3V_PCH SML1CLK/GPIO75 PCH_SMB_CLK <16,17>
AH3 SML1DATA
EMI @EMI@
1
PCH_SPI_CLK
PCH_SPI_CS0#
AA3
Y7
Y4
SPI_CLK
SPI_CS0
SML1DATA/GPIO74

CL_CLK
AF2
AD2 SMBDATA R31
DMN65D6LDW-7 2N SOT363-6

1 2 0_0402_5% PCH_SMB_DATA
C225 AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4
22P_0402_50V8J PCH_SPI_SI AA2 SPI_CS2 CL_RST SMBCLK R33 1 2 0_0402_5% PCH_SMB_CLK
2

PCH_SPI_SO AA4 SPI_MOSI


PCH_SPI_WP# Y6 SPI_MISO
R34 1 2 1K_0402_1% PCH_SPI_HOLD# AF1 SPI_IO2
R35 1 2 1K_0402_1% SPI_IO3

:Thermal IC, EC, dGPU


SML1:
7 OF 19
PCH_SPI_WP#_R R36 1 2 33_0402_5% PCH_SPI_WP# BDW-ULT-DDR3L-IL_BGA1168 +3VS

RP5 EMI
PCH_SPI_HOLD#_R 1 8 PCH_SPI_HOLD# @ R37 2.2K_0402_5%

2
PCH_SPI_CLK_R 2 7 PCH_SPI_CLK Q2A 1 2 +3VS
To SPI 8MByte ROM PCH_SPI_SI_R 3 6 PCH_SPI_SI From PCH
PCH_SPI_SO_R 4 5 PCH_SPI_SO SML1DATA 6 1
EC_SMB_DA2 <32,35>
33_0804_8P4R_5% DMN65D6LDW-7 2N SOT363-6

PCH_SPI_CS0#_R R38 1 2 0_0402_5% PCH_SPI_CS0# @ R39 2.2K_0402_5%

5
Q2B 1 2 +3VS
SML1CLK 3 4 EC_SMB_CK2 <32,35>
DMN65D6LDW-7 2N SOT363-6

SML1DATA R41 1 2 0_0402_5% EC_SMB_DA2

SML1CLK R42 1 2 0_0402_5% EC_SMB_CK2

B B

+3V_PCH
@
RP7
SMBCLK 1 8

EMI RP8
SMBDATA
SML1DATA
SML1CLK
2
3
4
7
6
5
1 8 PCH_SPI_CS0#_R
<35> EC_SPI_CS0#
2 7 PCH_SPI_CLK_R 2.2K_0804_8P4R_5%
<35> EC_SPI_CLK 3 6
From EC PCH_SPI_SI_R To SPI 8MByte ROM
<35> EC_SPI_MOSI
4 5 PCH_SPI_SO_R
(For share ROM) <35> EC_SPI_MISO
SML0CLK R46 1 2 499_0402_1%
1

@EMI@ 33_0804_8P4R_5% SML0DATA R47 1 2 499_0402_1%


EMI C226
22P_0402_50V8J
2

+3V_PCH

SPI ROM ( 8MByte )


U1 @
PCH_SPI_CS0#_R 1 8 +3V_ROM C8 1 2 .1U_0402_16V7K
PCH_SPI_SO_R 2 /CS VCC 7 PCH_SPI_HOLD#_R
PCH_SPI_WP#_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_R
4 /WP(IO2) CLK 5 PCH_SPI_SI_R
GND DI(IO0)
W25Q64FVSSIQ_SO8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(4/11) CLK,SPI,SMBUS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Wednesday, February 19, 2014 Sheet 8 of 53
5 4 3 2 1
5 4 3 2 1

(X)DS3 (O)DS3 (X)DS3


Function (X)SBA (X)SBA (O)SBA
ESD ESD R51 X O X
SYS_PWROK EC_RSMRST#
R55 O O X
R56 X X O
1

1
@ESD@
C239 C240 R58 X O X
100P_0402_50V8J 100P_0402_50V8J
2

2
D D
R52 X O X
R53 O X O
Note: SUSACK# and SUSWARN# can be tied together if
EC does not want to involve in the handshake mechanism DSWODVREN - On Die DSW VR Enable
for the Deep Sleep state entry and exit : Enable(DEFAULT)
(*) H:
: Disable
( ) L:
+RTCVCC
CAN be NC ,if not support Deep Sx
SUSWARN#_R R48 1 @ 2 0_0402_5% R49 1 2 330K_0402_5%
UC1H BDW_ULT_DDR3L(Interleaved) R50 1 @ 2 330K_0402_5%

SYSTEM POWER MANAGEMENT


DS3
DS3
+3VALW R51 1 DS3@ 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN R52 1 DS3@ 2 0_0402_5%
<35,46> SUSACK# SUSACK DSWVRMEN DPWROK_EC <35>
SYS_RESET# AC3 AV5 PCH_DPWROK R53 1NODS3@ 2 0_0402_5% EC_RSMRST#
<10> SYS_RESET# AG2 SYS_RESET DPWROK AJ5 2 1 10K_0402_5%
<35> SYS_PWROK SYS_PWROK R57
SYS_PWROK WAKE
1

<35> PCH_PWROK PCH_PWROK AY7 PCH_PCIE_WAKE# <31>


R54 R55 1 2 0_0402_5% APWROK_R AB5 PCH_PWROK
10K_0402_5% CPU_PLT_RST# AG7 APWROK V5 PCH_GPIO32
PLTRST CLKRUN/GPIO32 PCH_GPIO32 <8>
AG4
SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK <31>
2

AC_PRESENT SUSCLK/GPIO62 AP5 PM_SLP_S5#


<33,35> AC_PRESENT SLP_S5/GPIO63 PM_SLP_S5# <35>
EC_RSMRST# AW6
<35> EC_RSMRST# RSMRST
R58 1 DS3@ 2 0_0402_5% SUSWARN#_R AV4
<35> SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
<35> PBTN_OUT# PBTN_OUT# AL7 AJ6 PM_SLP_S4#
AJ8 PWRBTN SLP_S4 AT4 PM_SLP_S4# <35>
AC_PRESENT PM_SLP_S3#
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# <35>
DS3 PCH_GPIO72 AN4 AL5
T15 @ AF3 BATLOW/GPIO72 SLP_A AP4 SLP_SUS#
AM5 SLP_S0 SLP_SUS AJ7 SLP_SUS# <35>
PCH_GPIO29
SLP_WLAN/GPIO29 SLP_LAN
DS3
+3VS

RP10
1 8 SERIRQ 8 OF 19
SERIRQ <10,35> BDW-ULT-DDR3L-IL_BGA1168
C 2 7 PCH_GPIO36 PCH_GPIO36 <7> C
3 6 TPMPD# TPMPD# <10>
4 5 SATA_ODD_PRSNT SATA_ODD_PRSNT <30,7>
10K_8P4R_5% R59 2 1 0_0402_5%

RP11
1 8 +3VS
2 7 PCH_GPIO38 PCH_GPIO38 <10>
3 6 PCH_GPIO52 @

5
4 5 DGPU_HOLD_RST# U3
CPU_PLT_RST# 2

P
10K_8P4R_5% B 4
Y PLT_RST# <31,35,38,40>
1
A

1
G
RP12
1 8 PCH_GPIO68 PCH_GPIO68 <10,37> R60

3
2 7 DGPU_PWROK 100K_0402_5%
3 6 PCH_GPIO55 U74AHC1G08G-AL5-R_SOT353-5
4 5

2
10K_8P4R_5%

R61 1 2 2.2K_0402_5% DDI1_CTRL_CK


R62 1 2 2.2K_0402_5% DDI1_CTRL_DATA

UC1I BDW_ULT_DDR3L(Interleaved)

0_0402_5%
+3V_PCH R63 1 2 EDP_BKCTL B8 B9 DDI1_CTRL_CK
<27> INVPWM A9 EDP_BKLCTL DDPB_CTRLCLK C9 DDI1_CTRL_DATA
<27,35> ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA
C6 D9
<27> PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK HDMICLK_NB <28,37>
R64 1 2 10K_0402_5% SUSWARN#_R D11 HDMI DDC (Port C)
1 2 10K_0402_5% DDPC_CTRLDATA HDMIDAT_NB <28,37>
R65 PCH_GPIO72

DGPU_PWROK U6
P4 PIRQA/GPIO77 C5 DDI1_AUX_DN
B <10,35> DGPU_PWR_EN
DGPU_HOLD_RST# N4 PIRQB/GPIO78 DDPB_AUXN B6 DDI2_AUX_DN
DDI1_AUX_DN <29> DP Aux (Port B for VGA) B
N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5 DDI1_AUX_DP
DDI2_AUX_DN <37> DP Aux (Port C for Docking)
<10,31> WLBT_OFF#
T16 @ AD4 PIRQD/GPIO80 DDPB_AUXP A6 DDI2_AUX_DP
DDI1_AUX_DP <29> DP Aux (Port B for VGA)
+3VALW PME PCIE DDPC_AUXP DDI2_AUX_DP <37> DP Aux (Port C for Docking)
PCH_GPIO55 U7
PCH_GPIO52 L1 GPIO55
PCH_GPIO54 L3 GPIO52 C8
<10> PCH_GPIO54 GPIO54 DDPB_HPD DDI1_HPD <29> From VGA Trans.
R66 1 @ 2 10K_0402_5% PCH_GPIO29 PCH_GPIO51 R5 A8 DDPC_HPD R148 1 2 0_0402_5% TMDS_B_HPD <28,37> From HDMI
1 2 1K_0402_5% <10> PCH_GPIO51 L4 GPIO51 DDPC_HPD D6
R67 PCH_PCIE_WAKE# PCH_GPIO53 EDP_HPD <27> From eDP
<10> PCH_GPIO53 GPIO53 EDP_HPD

9 OF 19
BDW-ULT-DDR3L-IL_BGA1168

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(5/11) PM,GPIO,DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 9 of 53
5 4 3 2 1
5 4 3 2 1

D D

+3V_PCH

1
RP13
8 Docking_PRSNT#
ESD
2 7 PCH_GPIO47 H_THERMTRIP#
3 6 PCH_GPIO24

1
4 5 PCH_GPIO28
+1.05VS C241
10K_8P4R_5% 100P_0402_50V8J

2
GPIO15 : TLS Confidentiality for iAMT

1
@ RP14 UC1J BDW_ULT_DDR3L(Interleaved)
1 8 PCH_GPIO11
: Intel ME TLS with confidenCality
( ) H: R68
PCH_GPIO11 <8> : Intel ME TLS with no confidenCality
(*) L:
2 7 PCH_GPIO60 1K_0402_1%
PCH_GPIO60 <8>
3 6 PCH_GPIO26 (Have internal PD)
4 5 PCH_GPIO58

2
PCH_GPIO76 P1 D60 H_THERMTRIP#
10K_8P4R_5% +3V_PCH PCH_GPIO8 AU2 BMBUSY/GPIO76 THRMTRIP V4
AM7 GPIO8 RCIN/GPIO82 T4 KB_RST# <35>
SERIRQ SERIRQ <35,9>
<11> PCH_GPIO12 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ
R69 1 @ 2 PCH_GPIO15 AD6 AW15 PCH_OPIRCOMP 1 2
R288 1 2 10K_0402_5% 1K_0402_1% Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 R70
USB_OC1# <11,34> <30> ODD_EN GPIO16 RSVD
T3 AB21 49.9_0402_1%
<30> ODD_DA# GPIO17 RSVD
PCH_GPIO24 AD5
PCH_GPIO27 AN5 GPIO24
GPIO27 PCH_GPIO86: : Boot BIOS LocaCon
PCH_GPIO28 AD7
PCH_GPIO26 AN3 GPIO28 : LPC BUS
( ) H:
GPIO26 R6 PCH_GPIO83 : SPI BUS
(*) L:
@ RP16 PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84 +3VS
1 8 PCH_GPIO59 PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
2 7 PCH_GPIO8 PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86 R71 1 @ 2 1K_0402_1%
C C
3 6 PCH_GPIO43 PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_GPIO87 R72 1 2 1K_0402_1%
PCH_GPIO43 <11> GPIO59 GPIO GSPI1_CS/GPIO87
4 5 PCH_GPIO57 PCH_GPIO44 AK4 L5 PCH_GPIO88
PCH_GPIO47 AB6 GPIO44 GSPI1_CLK/GPIO88 N7 PCH_GPIO89
10K_8P4R_5% TPMPD# U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90
<9> TPMPD# GPIO48 GSPI_MOSI/GPIO90
DGPU_PRSNT# Y3 J1 PCH_GPIO91
@ RP9 TS_INT# P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92
<27> TS_INT# GPIO50 UART0_TXD/GPIO92
8 1 PCH_GPIO56 PCH_GPIO71 Y2 J2 PCH_GPIO93
7 2 PCH_GPIO14 PCH_GPIO13 AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1 PCH_GPIO94
6 3 PCH_GPIO46 PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
5 4 TS_Detect AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
<27> TS_Detect AG5 GPIO25 UART1_TXD/GPIO1 J3
Docking_PRSNT# PCH_GPIO2
<36,37> Docking_PRSNT# GPIO45 UART1_RST/GPIO2
10K_8P4R_5% PCH_GPIO46 AG3 J4 PCH_GPIO3
GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4
AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5
GPIO9 I2C0_SCL/GPIO5 SDIO_D0 / GPIO66 : Top-Block Swap Override
+3VALW AM2 G4 PCH_GPIO6
<11> PCH_GPIO10
PCH_GPIO33 P2 GPIO10 I2C1_SDA/GPIO6 F1 PCH_GPIO7
: DISABLED
(*) H:
R292 1 2 10K_0402_5% PCH_GPIO27 C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 PCH_GPIO64 : ENABLED(Have internal PD)
( ) L: +3VS
PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
<9> PCH_GPIO38 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 1 2 150K_0402_1%
PCH_GPIO66 R75
<35> EC_SCI# DEVSLP2/GPIO39 SDIO_D0/GPIO66
V2 E4 PCH_GPIO67
<39> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3 PCH_GPIO68
SDIO_D2/GPIO68 PCH_GPIO68 <37,9>
E2 PCH_GPIO69
SDIO_D3/GPIO69
10 OF 19
BDW-ULT-DDR3L-IL_BGA1168

+3VS
RP17
+3VS
RP18
BIOS Strap Pin
1 8 ODD_DA# 1 8 WLBT_OFF#
WLBT_OFF# <31,9>
2 7 PCH_GPIO23 2 7 Function GPIO1 Function GPIO54 Function GPIO64
B PCH_GPIO23 <8> B
3 6 KB_RST# 3 6 PCH_GPIO33
4 5 SYS_RESET# 4 5 PCH_GPIO76
SYS_RESET# <9> Reserved 1 NoDocking SKU 1 JET LE 0
10K_8P4R_5% 10K_8P4R_5% Reserved 0 Docking SKU 0 TOPAZ XT 1
@ RP19 RP20
1 8 PCH_GPIO65 1 8 PCH_GPIO34 +3VS +3VS +3VS
PCH_GPIO34 <7>
2 7 PCH_GPIO5 2 7 ODD_EN NoDocking@
3 6 PCH_GPIO67 3 6 PCH_GPIO37 R300 1 @ 2 10K_0402_5% PCH_GPIO1 R248 1 2 10K_0402_5% PCH_GPIO54 R245 1 TOPAZ@ 2 10K_0402_5% PCH_GPIO64
PCH_GPIO37 <7> PCH_GPIO54 <9>
4 5 4 5 PCH_GPIO71 R301 1 @ 2 10K_0402_5% R247 1 2 10K_0402_5% R246 1 JET@ 2 10K_0402_5%
Docking@
10K_8P4R_5% 10K_8P4R_5%

@ RP21
1 8 PCH_GPIO93
2 7 PCH_GPIO91 DGPU_PRSNT#
3 6 PCH_GPIO92 R304 1 @ 2 10K_0402_5% PCH_GPIO2
Function GPIO94 Function GPIO44
4 5 PCH_GPIO90 R305 1 @ 2 10K_0402_5% PCH_GPIO18
Function GPIO13 (GPIO49)
PCH_GPIO18 <8> Reserved 1 Zero ODD 1
10K_8P4R_5%
SG 0 0
Reserved 0 No Zero ODD 0
@ RP24 RP2
Reserved 0 1
1 8 PCH_GPIO88 8 1 PCH_GPIO87 +3VS +3VS
2 7 PCH_GPIO53 7 2 PCH_GPIO83
DIS Only 1 0
PCH_GPIO53 <9>
3 6 PCH_GPIO84 6 3 DGPU_PWR_EN R302 1 @ 2 10K_0402_5% PCH_GPIO94 R284 1 ZODD@ 2 10K_0402_5% PCH_GPIO44 UMA Only 1 1
DGPU_PWR_EN <35,9>
4 5 PCH_GPIO3 5 4 PCH_GPIO51 R303 1 @ 2 10K_0402_5% R285 1NOZODD@ 2 10K_0402_5%
PCH_GPIO51 <9>
10K_8P4R_5% 10K_8P4R_5% +3VS

RP26 @ RP25 R282 1 UMA@ 2 10K_0402_5% PCH_GPIO13


1 8 EC_SCI# 1 8 PCH_GPIO69 R283 1 PX@ 2 10K_0402_5%
2 7 PCH_GPIO85 2 7 PCH_GPIO4
3 6 PCH_GPIO0 3 6 PCH_GPIO7 R276 1 2 0_0402_5%
Function GPIO73
4 5 4 5 I2C_1_SCL <27>
PCH_GPIO89 PCH_GPIO6 R277 1 2 0_0402_5%
Single Rank 1
I2C_1_SDA <27> +3VS
10K_8P4R_5% 2.2K_0804_8P4R_5% Dual Rank 0 R73 1 UMA@ 2 10K_0402_5% DGPU_PRSNT#
A R74 1 PX@ 2 10K_0402_5% A
+3VS
R76 1 @ 2 1K_0402_5% HDA_SPKR
R286 1 SR@ 2 10K_0402_5% PCH_GPIO73 PCH_GPIO73 <8>
R287 1 DR@ 2 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(6/11) GPIO,LPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 10 of 53
5 4 3 2 1
5 4 3 2 1

D D

UC1K BDW_ULT_DDR3L(Interleaved)

F10 AN8
PERN5_L0 USB2N0 USB20_N0 <34>
E10
PERP5_L0 USB2P0
AM8
USB20_P0 <34>
Left USB2/3__I/O Port (Near End User)
C23 AR7
PETN5_L0 USB2N1 USB20_N1 <34>
C22
PETP5_L0 USB2P1
AT7
USB20_P1 <34>
Left USB2/3__I/O Port (Near HDMI CONN)(Debug Port)
F8 AR8
PERN5_L1 USB2N2 USB20_N2 <34> Right USB2__I/O Port (Sub Board)
E8 AP8
PERP5_L1 USB2P2 USB20_P2 <34> 2
R241 Docking@1 0_0402_5%
USB20_N3_D <36>
B23 AR10 USB20_N3 R243 2 E14@ 1 0_0402_5%
PETN5_L1 USB2N3 USB20_N3_U <34>
A23 AT10 USB20_P3 R244 2 E14@ 1 0_0402_5%
PETP5_L1 USB2P3 2 USB20_P3_U <34>
R242 Docking@1 0_0402_5%
USB20_P3_D <36>
H10 AM15
G10 PERN5_L2 USB2N4 AL15 USB20_N4 <27>
PERP5_L2 USB2P4 USB20_P4 <27> Touch Screen Card Reader (For G14/15)
B21 AM13
Right USB Port (For E14)
C21 PETN5_L2 USB2N5 AN13 USB20_N5 <27> Docking (For B15)
C
PETP5_L2 USB2P5 USB20_P5 <27> Camera C
E6 AP11
PERN5_L3 USB2N6 USB20_N6 <31>
F6 AN11 Bluetooth (NGFF)
PERP5_L3 USB2P6 USB20_P6 <31>
B22 AR13
PETN5_L3 USB2N7 USB20_N7 <34>
A21 AP13 Finger Print (For B14/E14/B15)
PETP5_L3 USB2P7 USB20_P7 <34>

<38> PCIE_PRX_DTX_N3 G11


F11 PERN3 G20
<38> PCIE_PRX_DTX_P3 PERP3 USB3RN1 USB3_RX1_N <34>
H20
LAN C22 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N3 C29 USB3RP1 USB3_RX1_P <34>
<38> PCIE_PTX_C_DRX_N3
C23 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P3 B30 PETN3 PCIE USB C33
Left USB2/3__I/O Port
<38> PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB3_TX1_N <34>
B34
USB3TP1 USB3_TX1_P <34>
F13
<31> PCIE_PRX_DTX_N4 PERN4
G13 E18
<31> PCIE_PRX_DTX_P4 PERP4 USB3RN2 USB3_RX2_N <34>
WLAN F18 USB3_RX2_P <34>
C18 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N4 B29 USB3RP2
<31> PCIE_PTX_C_DRX_N4
C19 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P4 A29 PETN4 B33
Left USB2/3__I/O Port
<31> PCIE_PTX_C_DRX_P4 PETP4 USB3TN2 USB3_TX2_N <34>
A33
G17 USB3TP2 USB3_TX2_P <34>
<36> USB3_RX3_N PERN1/USB3RN3
<36> USB3_RX3_P F17
PERP1/USB3RP3
USB2/3 Docking CAD note:
C30
(For B15) <36> USB3_TX3_N
C31 PETN1/USB3TN3 AJ10 USBRBIAS R77 1 2 22.6_0402_1%
Route single-end 50-ohms and max 450-mils length.
<36> USB3_TX3_P PETP1/USB3TP3 USBRBIAS AJ11 Avoid routing next to clock pins or under stitching capacitors.
F15 USBRBIAS AN10
<40> PCIE_PRX_DTX_N2 PERN2/USB3RN4 RSVD
Recommended minimum spacing to other signal traces is 15 mils
G15 AM10
<40> PCIE_PRX_DTX_P2 PERP2/USB3RP4 RSVD
Card Reader C20 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N2 B31
<40> PCIE_PTX_C_DRX_N2 PETN2/USB3TN4
(For B14/E14/B15) <40> PCIE_PTX_C_DRX_P2
C21 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P2 A31
PETP2/USB3TP4 AL3 USB_OC0# USB_OC0# <34>
OC0/GPIO40 AT1 USB_OC1#
+1.05VS_AUSB3PLL OC1/GPIO41 USB_OC1# <10,34>
AH2 PCH_GPIO42
E15 OC2/GPIO42 AV3 PCH_GPIO43
E13 RSVD OC3/GPIO43 PCH_GPIO43 <10>
R78 1 2 3.01K_0402_1% PCIE_RCOMP A27 RSVD
B27 PCIE_RCOMP
PCIE_IREF
B B

11 OF 19
BDW-ULT-DDR3L-IL_BGA1168

+3V_PCH
RP27
USB_OC0# 1 8
<10> PCH_GPIO10 2 7
PCH_GPIO42 3 6
4 5
<10> PCH_GPIO12
10K_8P4R_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(7/11) PCIE,USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 11 of 53
5 4 3 2 1
5 4 3 2 1

+CPU_CORE
UC1L BDW_ULT_DDR3L(Interleaved)
D D
L59 C36
+1.35V J58 RSVD VCC C40
RSVD VCC C44
AH26 VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
+1.05VS AR48 VDDQ VCC E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
VDDQ VCC

1
AY44 E35
+CPU_CORE AY50 VDDQ VCC E37
R79 VDDQ VCC E39
F59 VCC E41
10K_0402_5% VCC VCC
2 N58 E43
VCCST_PWRGD AC58 RSVD VCC E45
<35> VCCST_PWRGD RSVD VCC E47
VCCSENSE E63 VCC E49
AB23 VCC_SENSE VCC E51
T17 A59 RSVD VCC E53
E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
AD23 E57
AA23 RSVD VCC F24
AE59 RSVD VCC F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
N63 VIDALERT HSW ULT POWER VCC F40
<50> VR_SVID_CLK VIDSCLK VCC
H_CPU_SVIDDATA L63 F44
VCCST_PWRGD B59 VIDSOUT VCC F48
F60 VCCST_PWRGD VCC F52
<50> VR_ON 1 2 10K_0402_5% C59 VR_EN VCC F56
R80
VR_READY VCC G23
<50> VGATE VCC
D63 G25
CPU_PWR_DEBUG H59 VSS VCC G27
P62 PWR_DEBUG VCC G29
C C
P60 VSS VCC G31
P61 RSVD_TP VCC G33
N59 RSVD_TP VCC G35
N61 RSVD_TP VCC G37
T59 RSVD_TP VCC G39
AD60 RSVD VCC G41
AD59 RSVD VCC G43
+1.05VS AA59 RSVD VCC G45
SVID ALERT Place the PU AE60 RSVD
RSVD
VCC
VCC
G47
AC59 G49
RSVD VCC
1

resistors close to CPU AG58


RSVD VCC
G51
R81 +1.05VS U59 G53
75_0402_5% V59 RSVD VCC G55
RSVD VCC G57
R82 AC22 VCC H23
2

43_0402_1% +CPU_CORE AE22 VCCST VCC J23


2 1 H_CPU_SVIDALRT# AE23 VCCST VCC K23
<50> VR_SVID_ALRT# VCCST VCC K57
AB57 VCC L22
AD57 VCC VCC M23
AG57 VCC VCC M57
C24 VCC VCC P57
C28 VCC VCC U57
C32 VCC VCC W57
+1.05VS VCC VCC
SVID DATA Place the PU BDW-ULT-DDR3L-IL_BGA1168
12 OF 19

resistors close to CPU


2

R83
130_0402_1%
1

R84
1 2 H_CPU_SVIDDATA
<50> VR_SVID_DAT
0_0402_5% +1.35V
B B
VDDQ DECOUPLING

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
@

C24

C25

C26

C27

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1 @
+1.05VS

C28

C29

C30

C31

C32

C33
+CPU_CORE
2 2 2 2 2 2 2 2 2 2
2

R253: CPU_PWR_DEBUG
1

R86
R85 @
CRB mount
PU resistor should be close to CPU 150_0402_1%
Check list ,XDP use only
100_0402_1% CRB:
1

+1.35V : 470UF/2V/7343 *2 (Un-mount)


2

CPU_PWR_DEBUG
VCCSENSE 10UF/6.3V/0603 * 6
<50> VCCSENSE
2.2UF/6.3V/0402 * 4
2

R87 @
10K_0402_5%
<14,50> VSSSENSE
1
1

R88 PD resistor should be close to CPU


100_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(8/11) Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 12 of 53
5 4 3 2 1
5 4 3 2 1

+RTCVCC <1mA
+1.05VS +1.05VS_AUSB3PLL
41mA
@
D D
L1
2.2UH_LQM2MPN2R2NG0L_30%
1 2 1 1@
47U_0805_6.3V6M

22U_0603_6.3V6M
C37 C38

1U_0402_6.3V6K

.1U_0402_16V7K
1 1 1
1

2 2
C34

@ C35 @ C36
1U_0402_6.3V6K
R271 2 2 2
0_0402_5%
2

+1.05VS_ASATA3PLL
42mA +3V_PCH
63/62mA
1838mA
L2
2.2UH_LQM2MPN2R2NG0L_30%

1
1 2 +1.05VS
22U_0603_6.3V6M

47U_0805_6.3V6M

R89
1 1 1 0_0603_5%
C39

C40

@ C41 Close to M9 Close to K9, L10

2
1U_0402_6.3V6K
2 2 2
1 C42 1 C43 1 C44 1
@ C45

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+1.05VS_APLLOPI
57mA 1U_0402_6.3V6K
L3 2 2 2 2 +3V_PCH
2.2UH_LQM2MPN2R2NG0L_30%
1 2 UC1M BDW_ULT_DDR3L(Interleaved)
47U_0805_6.3V6M

22U_0603_6.3V6M

1
K9 +RTCVCC C49
1 1 1 VCCHSIO
@ @ C46 L10 .1U_0402_16V7K
VCCHSIO
C47

C48

1U_0402_6.3V6K M9
+1.05VS_ASATA3PLL +1.05VS_AUSB3PLL N8 VCCHSIO HSIO RTC AH11 2
2 2 2 P9 VCC1_05 VCCSUS3_3 AG10
VCC1_05 VCCRTC 18mA 658mA
B18 AE7 +VCCRTCEXT
B11 VCCUSB3PLL DCPRTC
VCCSATA3PLL
C
+1.05VS_AXCK_DCB
200mA +1.05VS_APLLOPI
1
+1.05VS
C
@ C50
Y20 SPI Y8
L4 VCCHDA=11mA RSVD VCCSPI .1U_0402_16V7K 1741/1632mA
2.2UH_LQM2MPN2R2NG0L_30% AA21 OPI
1 2 VCCDSW3_3= 114mA W21 VCCAPLL 2@
+3V_PCH +3VALW VCCAPLL +1.05VS
22U_0603_6.3V6M

47U_0805_6.3V6M

AG14
VCCASW AG13
1 1 1 Close to AH10 Close to AH14 VCCASW
C53
1

C51

C52

@ @ @ T18 J13 USB3


1U_0402_6.3V6K 2 DCPSUS3 1 1 1
2 C54 J11 C56 C57 C58
2 2 2 C55 1U_0402_6.3V6K VCC1_05 H11 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
R272
1U_0402_6.3V6K AH14 HDA VCC1_05 H15
0_0402_5%
@ 1 VCCHDA VCC1_05 AE8 2 2 2
VCC1_05
2

1 AF22
+1.05VS_AXCK_LCPLL
31mA VRM VCC1_05
@ T19 AH13 AG19 +PCH_VCCDSW C59 1 2 1U_0402_6.3V6K
L5 DCPSUS2 CORE DCPSUSBYP AG20
2.2UH_LQM2MPN2R2NG0L_30% DCPSUSBYP AE9 +1.05VS
1 2 +3VALW VCCASW AF9
VCCASW
22U_0603_6.3V6M

47U_0805_6.3V6M

AC9 AG8
+3VS AA9 VCCSUS3_3 GPIO/LPC
VCCASW AD10 T20 @
1 1 1 VCCSUS3_3 DCPSUS1
C62 Close to V8 AH10 AD8 T21 @ 1 C64 1 C65
VCCDSW3_3 DCPSUS1 +1.5VS
C60

C61

1U_0402_6.3V6K
@ V8 3mA @

22U_0603_6.3V6M
1U_0402_6.3V6K 1 VCC3_3
41mA C63 W9
2 2 2 22U_0603_6.3V6M VCC3_3 J15
THERMAL SENSOR VCCTS1_5 K14 2 2
2 VCC3_3 K16
+1.05VS_AXCK_DCB VCC3_3

+1.05VS_AXCK_LCPLL J18
K19 VCCCLK SERIAL IO U8
A20 VCCCLK VCCSDIO T9 +3VS +3VS
+1.05VS VCCACLKPLL VCCSDIO 17mA
J17
R21 VCCCLK
T21 VCCCLK LPT LP POWER
VCCCLK 1 C68 1 C69

1U_0402_6.3V6K

.1U_0402_16V7K
K18 SUS OSCILLATOR AB8 @ T22
+3V_PCH M20 RSVD DCPSUS4
1 1 RSVD
C66 C67 V21 +1.05VS
AE20 RSVD AC20 2 2
1U_0402_6.3V6K

1U_0402_6.3V6K

B
AE21 VCCSUS3_3 RSVD AG16 B
2 2 VCCSUS3_3 USB2 VCC1_05 AG17
VCC1_05 1 C71

1U_0402_6.3V6K
1
C70
22U_0603_6.3V6M
13 OF 19 2
2 BDW-ULT-DDR3L-IL_BGA1168
Close to R21 Close to J17
Close to AC9,AA9,
AE20,AE21

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(9/11) Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 13 of 53
5 4 3 2 1
5 4 3 2 1

D D

UC1N BDW_ULT_DDR3L(Interleaved) UC1O BDW_ULT_DDR3L(Interleaved) UC1P BDW_ULT_DDR3L(Interleaved)


H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
C C
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62 VSSSENSE
VSS VSS VSS VSS VSS VSS_SENSE VSSSENSE <12,50>
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18 BDW-ULT-DDR3L-IL_BGA1168
AH32 VSS VSS AN35 AU55 VSS VSS C20
AH34 VSS VSS AN36 AU57 VSS VSS C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
B
AH51 VSS VSS AN48 AV33 VSS VSS D18 B
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 VSS
BDW-ULT-DDR3L-IL_BGA1168

14 OF 19
BDW-ULT-DDR3L-IL_BGA1168

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(10/11) GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 14 of 53
5 4 3 2 1
1

UC1R BDW_ULT_DDR3L(Interleaved)

N23
UC1Q BDW_ULT_DDR3L(Interleaved) RSVD R23
RSVD T23
AT2 RSVD
RSVD U10
AU44 RSVD
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 RSVD
DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 AV44
DC_TEST_AY3_AW3 AY3 A4 @ T24 RSVD
DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 D15
T23 @ AY60 RSVD AL1
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 @ T25 RSVD AM11
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61 RSVD AP7
DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 F22 RSVD
T26 @ B2 A62 @ T27 RSVD AU10
DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 H22 RSVD
DC_TEST_A3_B3 B3 AV1 @ T28 RSVD AU15
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 J21 RSVD
DC_TEST_A61_B61 B61 AW1 @ T29 RSVD AW14
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 RSVD AY14
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3 RSVD
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62 18 OF 19
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 @ T30 BDW-ULT-DDR3L-IL_BGA1168
17 OF 19 DAISY_CHAIN_NCTF_AW63
BDW-ULT-DDR3L-IL_BGA1168

UC1S BDW_ULT_DDR3L(Interleaved)

AC60 AV63
AC62 CFG0 RSVD_TP AU63

CFG3
AC63
AA63
CFG1
CFG2
RSVD_TP
CFG Straps for Processor
CFG4 AA60 CFG3 C63
Y62 CFG4 RSVD_TP C62
Y61 CFG5 RSVD_TP B43
Y60 CFG6 RSVD CFG3
V62 CFG7 A51
CFG8 RSVD_TP

1
V61 B51
V60 CFG9 RSVD_TP R92
U60 CFG10 L60 1K_0402_1%
T63 CFG11 RSVD_TP @
T62 CFG12 RESERVED N60

2
T61 CFG13 RSVD
T60 CFG14 W23
A AA62
CFG15 RSVD
RSVD
Y22
AY15 OPI_COMP
A
U63 CFG16 PROC_OPI_RCOMP
AA61 CFG18 AV62
U62 CFG17 RSVD D58
CFG19 RSVD Physical Debug Enable (DFX Privacy)
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
A5 VSS 1: DISABLED
RSVD P20
CFG3 0: ENABLED; SET DFX ENABLED BIT
E1 RSVD R20
D1 RSVD RSVD IN DEBUG INTERFACE MSR
J20 RSVD
H18 RSVD
TD_IREF B12 RSVD CFG4
TD_IREF

1
19 OF 19
BDW-ULT-DDR3L-IL_BGA1168 R93
1K_0402_1%

2
2 1 CFG_RCOMP
R94 49.9_0402_1%
2 1 OPI_COMP
R95 49.9_0402_1%
2 1 TD_IREF
R96 8.2K_0402_5%
Display Port Presence Strap

1 : Disabled; No Physical Display Port attached


CFG4 to Embedded Display Port

0 : Enabled; An external Display Port device is


connected to the Embedded Display Port

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date HSW MCP(11/11) RSVD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B092P
Date: Tuesday, February 18, 2014 Sheet 15 of 53
A B C D E

+SM_VREF_DQ0 <6> DIMM1


<6> DDR_A_D[0..63]
D/DQ Signals link to CPU
+1.35V Reverse Type
<6> DDR_A_DQS#[0..7]
Near CPU

1
<6> DDR_A_DQS[0..7]
R97
1.8K_0402_1%
R98 +SM_VREF_DQ0_DIMM1
<6> DDR_A_MA[0..15]
0_0402_5% 10mils JDIMM1

2
DDR_A_BS0 1 2 1 2
<6> DDR_A_BS0 VREF_DQ VSS
DDR_A_BS1 3 4 DDR_A_D4
<6> DDR_A_BS1 VSS DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K
DDR_A_BS2 CMD Signals from CPU C72 DDR_A_D0 5 6 DDR_A_D5
<6> DDR_A_BS2 DQ0 DQ5
DDR_A_RAS# @ 0.022U_0402_16V7K 1 1 DDR_A_D1 7 8
<6> DDR_A_RAS# DQ1 VSS

C74
DDR_A_WE# 9 10 DDR_A_DQS#0
<6> DDR_A_WE#

1 2
VSS DQS0#

C73
DDR_A_CAS# R99 11 12 DDR_A_DQS0
1 <6> DDR_A_CAS# DM0 DQS0 1
1.8K_0402_1% 13 14
R100 @2 2 DDR_A_D2 15 VSS VSS 16 DDR_A_D6
M_CLK_DDR#0 @ DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
<6> M_CLK_DDR#0 24.9_0402_1%

2
M_CLK_DDR0 19 DQ3 DQ7 20
<6> M_CLK_DDR0 VSS VSS
M_CLK_DDR#1 Clock Signals from CPU DDR_A_D8 21 22 DDR_A_D12
<6> M_CLK_DDR#1

2
M_CLK_DDR1 DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
<6> M_CLK_DDR1 25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28
DDR_CKE0_DIMMA DDR_A_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST#
<6> DDR_CKE0_DIMMA DQS1 RESET# DIMM_DRAMRST# <17,5>
DDR_CKE1_DIMMA 31 32
<6> DDR_CKE1_DIMMA VSS VSS
DDR_CS0_DIMMA# CTL Signals from CPU DDR_A_D10 33 34 DDR_A_D14 1
<6> DDR_CS0_DIMMA# 35 DQ10 DQ14 36
DDR_CS1_DIMMA# DDR_A_D11 DDR_A_D15
<6> DDR_CS1_DIMMA# DQ11 DQ15
37 38 C75
DDR_A_D16 39 VSS VSS 40 DDR_A_D20
DQ16 DQ20 100P_0402_50V8J
PCH_SMB_DATA DDR_A_D17 41 42 DDR_A_D21 2
<17,8> PCH_SMB_DATA DQ17 DQ21 @ESD@
PCH_SMB_CLK SMBUS Signals link to CPU 43 44
<17,8> PCH_SMB_CLK 45 VSS VSS 46
DDR_A_DQS#2
DDR_A_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18
DDR_A_D19
51
53
55
VSS
DQ18
DQ19
DQ22
DQ23
VSS
52
54
56
DDR_A_D23

DDR_A_D28
ESD
DDR_A_D24 57 VSS DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDR_A_DQS#3
Layout Note: 63 VSS DQS3# 64 DDR_A_DQS3
Place near JDIMM1 65 DM3 DQS3 66
DDR_A_D26 67 VSS VSS 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
+1.35V VSS VSS +1.35V

+1.35V DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA


75 CKE0 CKE1 76
77 VDD VDD 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
BA2 A14
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

81 82
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
2 1 1 1 1 2
@ @ DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
A9 A7
C76

C77

C78

C79

87 88
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
2 2 2 2 DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD VDD 102 M_CLK_DDR1
M_CLK_DDR#0 103 CK0 CK1 104 M_CLK_DDR#1
105 CK0# CK1# 106
+1.35V DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1 +1.35V
DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
111 BA0 RAS# 112
VDD VDD

1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_A_WE# 113 114 DDR_CS0_DIMMA#


DDR_A_CAS# 115 WE# S0# 116 SA_ODT0 R101
@ @ 117 CAS# ODT0 118 1.8K_0402_1%
1 VDD VDD
@ DDR_A_MA13 119 120 SA_ODT1 +VREF_CA
1 1 1 1 1 1 1 1 A13 ODT1
C82

C83

C84

C85

C86

C87

C88

C89

+ C250 DDR_CS1_DIMMA# 121 122 R102

2
330U_D3_2.5VY_R6M 123 S1# NC 124 0_0402_5%
VDD VDD 10mils
125 126 1 2
2 2 2 2 2 2 2 2 2 TEST VREF_CA +SM_VREF_CA <6>

2.2U_0402_6.3V6M

0.1U_0402_25V6K
127 128
DDR_A_D32 129 VSS VSS 130 DDR_A_D36 @
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37 1 1 C93
DQ33 DQ37

C91

C92
133 134 0.022U_0402_16V7K
DDR_A_DQS#4 135 VSS VSS 136

1 2
DDR_A_DQS4 137 DQS4# DM4 138
DQS4 VSS

1
139 140 DDR_A_D38 2 2 @
DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 @ R103 R104
DDR_A_D35 143 DQ34 DQ39 144 1.8K_0402_1%
DQ35 VSS 24.9_0402_1%
145 146 DDR_A_D44
Layout Note: Layout Note: DDR_A_D40 147 VSS DQ44 148 DDR_A_D45

2
Place near JDIMM1.203,204 Place near JDIMM1.199 DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#5
153 VSS DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS VSS 158 DDR_A_D46
3
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 3

+0.675VS +3VS 161 DQ43 DQ47 162


DDR_A_D48 163 VSS VSS 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
VSS VSS
0.1U_0402_25V6K

0.1U_0402_25V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DDR_A_DQS#6 169 170


@ 1 @ 1 DDR_A_DQS6 171 DQS6# DM6 172
1 1 1 1 DQS6 VSS
C94

C95

2.2U_0402_6.3V6M

0.1U_0402_25V6K

@ Address : 00 173 174 DDR_A_D54


VSS DQ54
C96

C97

DDR_A_D50 175 176 DDR_A_D55


DQ50 DQ55
C98

C99

R105 1 2 0_0402_5% DDR_A_SA0 DDR_A_D51 177 178


2 2 2 2 2 2 179 DQ51 VSS 180 DDR_A_D60
R106 1 2 0_0402_5% DDR_A_SA1 DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS VSS 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
+0.675VS +3VS 195 DQ59 DQ63 196 +0.675VS
DDR_A_SA0 197 VSS VSS 198
199 SA0 EVENT# 200 PCH_SMB_DATA
DDR_A_SA1 201 VDDSPD SDA 202 PCH_SMB_CLK
203 SA1 SCL 204
VTT VTT
205 206
GND1 GND2

DDR3L SODIMM ODT GENERATION ARGOS_DS2RK-20401-TP4B


ME@
SP070014D00
+1.35V

R107
1 66.5_0402_1%
C100 1 2
+5VALW +1.35V SB_ODT0 <17>
.1U_0402_16V7K
4 R109 4
2 66.5_0402_1%
1

1 2
SB_ODT1 <17>
U4 R108
1 5 220K_0402_5% Q3 R110
NC VCC LBSS138LT1G_SOT-23-3 66.5_0402_1%
1

Interleaved Memory
2 D 1 2 SA_ODT0
<5> DDR_PG_CTRL
2

A 4 2
From CPU 3 Y G R111
GND 66.5_0402_1%
S
3

74AUP1G07GW TSSOP 5P BUFFER M_A_B_DIMM_ODT 1 2 SA_ODT1


Security Classification Compal Secret Data Compal Electronics, Inc.
For ODT & VTT Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
power control DDR_VTT_PG_CTRL <47>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L_DIMMA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B092P
Date: Tuesday, February 18, 2014 Sheet 16 of 53
A B C D E
A B C D E

+SM_VREF_DQ1 <6> DIMM2


<6> DDR_B_D[0..63]
D/DQ Signals link to CPU
+1.35V Standard Type
<6> DDR_B_DQS#[0..7]
Near User

1
<6> DDR_B_DQS[0..7]
R112
1.8K_0402_1%
R113 +SM_VREF_DQ1_DIMM2
<6> DDR_B_MA[0..15]
0_0402_5% 10mils JDIMM2

2
DDR_B_BS0 1 2 1 2
<6> DDR_B_BS0 VREF_DQ VSS
DDR_B_BS1 3 4 DDR_B_D22
<6> DDR_B_BS1 VSS DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K
DDR_B_BS2 CMD Signals from CPU C101 DDR_B_D23 5 6 DDR_B_D16
<6> DDR_B_BS2 DQ0 DQ5
DDR_B_RAS# @ 0.022U_0402_16V7K 1 1 DDR_B_D17 7 8
<6> DDR_B_RAS# DQ1 VSS

1
DDR_B_WE# 9 10 DDR_B_DQS#2
<6> DDR_B_WE#

1 2
VSS DQS0#

C102

C103
DDR_B_CAS# R114 11 12 DDR_B_DQS2
1 <6> DDR_B_CAS# DM0 DQS0 1
1.8K_0402_1% 13 14
R115 @2 2 DDR_B_D21 15 VSS VSS 16 DDR_B_D19
M_CLK_DDR#2 @ DDR_B_D18 17 DQ2 DQ6 18 DDR_B_D20
<6> M_CLK_DDR#2 24.9_0402_1%

2
M_CLK_DDR2 19 DQ3 DQ7 20
<6> M_CLK_DDR2 VSS VSS
M_CLK_DDR#3 Clock Signals from CPU DDR_B_D3 21 22 DDR_B_D4
<6> M_CLK_DDR#3

2
M_CLK_DDR3 DDR_B_D2 23 DQ8 DQ12 24 DDR_B_D5
<6> M_CLK_DDR3 25 DQ9 DQ13 26
DDR_B_DQS#0 27 VSS VSS 28
DDR_CKE2_DIMMB DDR_B_DQS0 29 DQS1# DM1 30 DDR3_DRAMRST#
<6> DDR_CKE2_DIMMB DQS1 RESET# DIMM_DRAMRST# <16,5>
DDR_CKE3_DIMMB 31 32
<6> DDR_CKE3_DIMMB VSS VSS
DDR_CS2_DIMMB# CTL Signals from CPU DDR_B_D0 33 34 DDR_B_D6 1
<6> DDR_CS2_DIMMB# 35 DQ10 DQ14 36
DDR_CS3_DIMMB# DDR_B_D1 DDR_B_D7
<6> DDR_CS3_DIMMB# DQ11 DQ15
37 38 C104
DDR_B_D12 39 VSS VSS 40 DDR_B_D13
DQ16 DQ20 100P_0402_50V8J
PCH_SMB_DATA DDR_B_D8 41 42 DDR_B_D9 2
<16,8> PCH_SMB_DATA DQ17 DQ21 @ESD@
PCH_SMB_CLK SMBUS Signals link to CPU 43 44
<16,8> PCH_SMB_CLK 45 VSS VSS 46
DDR_B_DQS#1
DDR_B_DQS1 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_B_D11
DDR_B_D14
DDR_B_D15
51
53
55
VSS
DQ18
DQ19
DQ22
DQ23
VSS
52
54
56
DDR_B_D10

DDR_B_D30
ESD
DDR_B_D31 57 VSS DQ28 58 DDR_B_D26
Layout Note: DDR_B_D25 59 DQ24 DQ29 60
Place near JDIMM2 61 DQ25 VSS 62 DDR_B_DQS#3
63 VSS DQS3# 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D27 67 VSS VSS 68 DDR_B_D29
DDR_B_D24 69 DQ26 DQ30 70 DDR_B_D28
71 DQ27 DQ31 72
+1.35V +1.35V VSS VSS +1.35V

DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
CKE0 CKE1
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

75 76
@ 1 @ 1 77 VDD VDD 78 DDR_B_MA15
1 1 NC A15
DDR_B_BS2 79 80 DDR_B_MA14
BA2 A14
C105

C106

C107

C108

81 82
DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11
2 2
2 2 2 2 DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD VDD 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD VDD 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
+1.35V M_CLK_DDR2 101 VDD VDD 102 M_CLK_DDR3
M_CLK_DDR#2 103 CK0 CK1 104 M_CLK_DDR#3
105 CK0# CK1# 106
VDD VDD
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_B_MA10 107 108 DDR_B_BS1


DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
111 BA0 RAS# 112
@ 1 @ 1 DDR_B_WE# 113 VDD VDD 114 DDR_CS2_DIMMB#
1 1 1 1 1 1 WE# S0#
C111

C112

C113

C114

C115

C116

C117

C118

DDR_B_CAS# 115 116 SB_ODT0


CAS# ODT0 SB_ODT0 <16>
117 118
DDR_B_MA13 119 VDD VDD 120 SB_ODT1
2 2 2 2 2 2 2 2 121 A13 ODT1 122 SB_ODT1 <16> +VREF_CA
DDR_CS3_DIMMB#
123 S1# NC 124
VDD VDD 10mils
125 126
127 TEST VREF_CA 128
VSS VSS

2.2U_0402_6.3V6M

0.1U_0402_25V6K
DDR_B_D32 129 130 DDR_B_D33
DDR_B_D35 131 DQ32 DQ36 132 DDR_B_D34
133 DQ33 DQ37 134
VSS VSS 1 1

C121
DDR_B_DQS#4 135 136
DQS4# DM4

C120
DDR_B_DQS4 137 138
139 DQS4 VSS 140 DDR_B_D39
DDR_B_D36 141 VSS DQ38 142 DDR_B_D37 @2 2
Layout Note: Layout Note: DDR_B_D38 143 DQ34 DQ39 144
Place near JDIMM2.203,204 Place near JDIMM2.199 145 DQ35 VSS 146 DDR_B_D44
DDR_B_D40 147 VSS DQ44 148 DDR_B_D41
DDR_B_D45 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_B_DQS#5
153 VSS DQS5# 154 DDR_B_DQS5
155 DM5 DQS5 156
+0.675VS +3VS DDR_B_D43 157 VSS VSS 158 DDR_B_D47
3
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46 3
161 DQ43 DQ47 162
DDR_B_D52 163 VSS VSS 164 DDR_B_D51
DQ48 DQ52
0.1U_0402_25V6K

0.1U_0402_25V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_25V6K

2.2U_0402_6.3V6M

DDR_B_D49 165 166 DDR_B_D55


@ 1 @ 1 167 DQ49 DQ53 168
1 1 1 1 Address : 01 VSS VSS
C122

C123

C126

@ DDR_B_DQS#6 169 170


+3VS DQS6# DM6
C124

C125

C127

DDR_B_DQS6 171 172


173 DQS6 VSS 174 DDR_B_D48
2 2 2 2 2 2 R116 1 2 0_0402_5% DDR_B_SA1 DDR_B_D50 175 VSS DQ54 176 DDR_B_D54
DDR_B_D53 177 DQ50 DQ55 178
R117 1 2 0_0402_5% DDR_B_SA0 179 DQ51 VSS 180 DDR_B_D56
DDR_B_D63 181 VSS DQ60 182 DDR_B_D57
DDR_B_D62 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_B_DQS#7
187 VSS DQS7# 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS VSS 192 DDR_B_D60
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D61
+0.675VS +3VS 195 DQ59 DQ63 196 +0.675VS
DDR_B_SA0 197 VSS VSS 198
199 SA0 EVENT# 200 PCH_SMB_DATA
DDR_B_SA1 201 VDDSPD SDA 202 PCH_SMB_CLK
203 SA1 SCL 204
VTT VTT
205 206
207 GND1 GND2 208
BOSS1 BOSS2

ARGOS_DS2SK-20401-TP4B
ME@
SP070014E00

4 4

Interleaved Memory
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L_DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B092P
Date: Tuesday, February 18, 2014 Sheet 17 of 53
A B C D E
1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_PCIE/DP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Tuesday, February 18, 2014 Sheet 18 of 53
1 2 3 4 5
1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31 SUN_MSIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Tuesday, February 18, 2014
Sheet 19 of 53
1 2 3 4 5
1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_Power/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Tuesday, February 18, 2014 Sheet 20 of 53
1 2 3 4 5
1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_Power
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Tuesday, February 18, 2014 Sheet 21 of 53
1 2 3 4 5
1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
SUN_MEM
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Tuesday, February 18, 2014 Sheet 22 of 53

1 2 3 4 5
1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_VRAM
Size Document Number
A Lower Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Tuesday, February 18, 2014 Sheet 23 of 53
1 2 3 4 5
1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_VRAM
Size Document Number
A Upper Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Tuesday, February 18, 2014 Sheet 24 of 53
1 2 3 4 5
1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_VRAM
Size Document Number
A Lower Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Tuesday, February 18, 2014 Sheet 25 of 53
1 2 3 4 5
1 2 3 4 5

A A

B B

C C

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SUN_VRAM
Size Document Number
A Upper Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B092P
Tuesday, February 18, 2014 Sheet 26 of 53
1 2 3 4 5
5 4 3 2 1

LCD Power Circuit W=60mils +3VS


Camera +3VS_CMOS
+3VS +LCDVDD_CONN

W=60mils U5 CMOS@
5 1 +LCDVDD_CONN Q4

4.7U_0603_6.3V6K
IN OUT LP2301ALT1G_SOT23-3
2

C128
GND 1 W=20mils W=20mils

D
3 1
4 3 1 1
EN OC CMOS@
SY6288C20AAC_SOT23-5 2 C129 C130 @

G
2
D D
.1U_0402_16V7K 10U_0603_6.3V6M
R119CMOS@ 2 2
150K_0402_5%
<9> PCH_ENVDD 4.7V
<35> CMOS_ON#

1
1
R120 C132 CMOS@
100K_0402_5% .1U_0402_16V7K
2 2

+3VS

5
U15
2
From PCH

P
<35,9> ENBKL B 4 DISPOFF#
1 Y
From EC <35> BKOFF# A

2
eDP CONN.

3
2
R124
C R211 U74AHC1G08G-AL5-R_SOT353-5 100K_0402_5% C
100K_0402_5%

1
+LEDVDD B+

1
R121
R123 1 2 0_0402_5% 0_0805_5%
1 2
1
@
C133
4.7U_0805_25V6-K
2

JLVDS1
1
2 1 41
3 2 G1 42
4 3 G2 43
R126 1 2 0_0402_5% EDP_HPD_R 5 4 G3 44
<9> EDP_HPD 5 G4
6 45
6 G5
1

7 46
<9> INVPWM 7 G6
DISPOFF# 8
R128 EDP_HPD_R 9 8
100K_0402_5% 10 9
W=60mils 11 10
+LCDVDD_CONN
2

12 11
13 12
eDP 14 13
C134 1 2 .1U_0402_16V7K EDP_AUXN_C 15 14
<5> EDP_AUXN 15
C135 1 2 .1U_0402_16V7K EDP_AUXP_C 16
<5> EDP_AUXP 17 16
C136 1 2 .1U_0402_16V7K EDP_TXP0_C 18 17
<5> EDP_TXP0 18
C137 1 2 .1U_0402_16V7K EDP_TXN0_C 19
<5> EDP_TXN0 20 19

EMI <5> EDP_TXP1


<5> EDP_TXN1
C138 1FHD@ 2 .1U_0402_16V7K
C139 1FHD@ 2 .1U_0402_16V7K
EDP_TXP1_C
EDP_TXN1_C
21
22
23
20
21
22
B
R125 2 1 0_0402_5% R293 1 2 0_0402_5% 24 23 B
<10> TS_Detect 25 24
Reserve T33 for Presence Detect <10> TS_INT#
26 25
<10> I2C_1_SDA 27 26
@
<10> I2C_1_SCL 27
4 L6 3 USB20_N5_R 28
<11> USB20_N5 4 3 28
USB20_P4_R 29
Touch Screen USB20_N4_R 30 29
Camera 1 2 USB20_P5_R 31 30
<11> USB20_P5 1 2 31
R122 1 2 0_0402_5% TS_RST# 32
<35> TS_DISABLE# 32
WCM-2012HS-900T +3VS R270 2 1 0_0603_5% +3VS_TS 33
34 33
+3VS_CMOS 34
R127 2 1 0_0402_5% USB20_N5_R 35
USB20_P5_R 36 35
37 36
Camera 38 37
<39> DMIC_CLK 38
DMIC <39> DMIC_DAT
39
39
40
+3VS 40
R129 2 1 0_0402_5%
2 1 E-T_0871K-F40N-00L
TS@ TS@ ME@
@ C242 C243 SP010011Z00
4 L7 3 USB20_N4_R .1U_0402_16V7K 10U_0603_6.3V6M
<11> USB20_N4 4 3 1 2
Touch Screen 1 2 USB20_P4_R
<11> USB20_P4 1 2
WCM-2012HS-900T Close JLVDS1
R130 2 1 0_0402_5%

+3VS_TS

R4452 1 2 100K_0402_5% TS_INT#

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B092P
Date: Tuesday, February 18, 2014 Sheet 27 of 53
5 4 3 2 1
5 4 3 2 1

EMI
D For NoDocking Near JHDMI1 D
For Docking Near JHDMI1
L8 HDMI@
C229 <37> HDMI_CLK+_CK C229 1 2 .1U_0402_16V7K HDMI_CLK+_CK_C 1 2 HDMI_CLK+_CONN
0_0402_5% 1 2
Docking@ NoDocking@ +5V_Display
C230 <37> HDMI_CLK-_CK C230 1 2 .1U_0402_16V7K HDMI_CLK-_CK_C 4 3 HDMI_CLK-_CONN For NoDocking U6
0_0402_5% 4 3
Docking@ NoDocking@ MURATA DLW21HN900HQ2L +5VS 3
W=40mils
+3VS OUT
1
L9 HDMI@ 1
C231 C231 1 2 .1U_0402_16V7K HDMI_TX0+_CK_C 1 2 HDMI_TX0+_CONN IN C140
<37> HDMI_TX0+_CK 1 2 1
0_0402_5% 2
GND

2
Docking@ NoDocking@ C141 .1U_0402_16V7K 2
C232 <37> HDMI_TX0-_CK C232 1 2 .1U_0402_16V7K HDMI_TX0-_CK_C 4 3 HDMI_TX0-_CONN R133
0_0402_5% 4 3 1M_0402_5% Q5 .1U_0402_16V7K 2 AP2330W-7_SC59-3
Docking@ NoDocking@ MURATA DLW21HN900HQ2L NoDocking@ NoDocking@

2
G
2N7002H_SOT23-3

1
L10 HDMI@
C233 C233 1 2 .1U_0402_16V7K HDMI_TX1+_CK_C 1 2 HDMI_TX1+_CONN 3 1
0_0402_5%
<37> HDMI_TX1+_CK 1 2 <37,9> TMDS_B_HPD For CRT and HDMI

2
Docking@ NoDocking@
C234 <37> HDMI_TX1-_CK C234 1 2 .1U_0402_16V7K HDMI_TX1-_CK_C 4 3 HDMI_TX1-_CONN R137
0_0402_5% 4 3
20K_0402_5%
Docking@ NoDocking@ MURATA DLW21HN900HQ2L NoDocking@

1
L11 HDMI@
C235 <37> HDMI_TX2+_CK C235 1 2 .1U_0402_16V7K HDMI_TX2+_CK_C 1 2 HDMI_TX2+_CONN
0_0402_5% 1 2
Docking@ NoDocking@ JHDMI1 ZZZ 45@
C236 <37> HDMI_TX2-_CK C236 1 2 .1U_0402_16V7K HDMI_TX2-_CK_C 4 3 HDMI_TX2-_CONN HDMI_DET 19
4 3 <37> HDMI_DET 18 HP_DET
0_0402_5% +5V_Display
Docking@ NoDocking@ MURATA DLW21HN900HQ2L 17 +5V
For Docking HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
Reserved HDMI Logo
13
HDMI_CLK-_CONN 12 CEC 20 RO0000003HM
C C
11 CK- G1 21
HDMI_CLK+_CONN 10 CK_shield G2 22
HDMI_TX0-_CONN 9 CK+ G3 23
8 D0- G4
HDMI_TX0+_CONN 7 D0_shield
HDMI_TX1-_CONN 6 D0+
5 D1-
HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
2 D2-
HDMI_TX2+_CONN 1 D2_shield
D2+
For NoDocking For NoDocking CONCR_099ATAC19NBLCNF
+3VS ME@
+3VS DC232001K00

R143 1NoDocking@2 2.2K_0402_5% HDMIDAT_NB


Q6A
R144 1NoDocking@2 2.2K_0402_5% HDMICLK_NB NoDocking@
2

DMN65D8LDW-7 2N SOT363-6 For NoDocking


<37,9> HDMICLK_NB 1 6 HDMICLK_R
For Docking RP29
5

HDMI_TX1+_CK_C 5 4
HDMI_TX1-_CK_C 6 3
R143 4 3 HDMIDAT_R HDMI_CLK+_CK_C 7 2
<37,9> HDMIDAT_NB
10K_0402_5% HDMI_CLK-_CK_C 8 1
Docking@ Q6B
R144 NoDocking@ 470 +-5% 8P4R
10K_0402_5% DMN65D8LDW-7 2N SOT363-6 NoDocking@
Docking@
RP30
HDMI_TX0+_CK_C 5 4
HDMI_TX0-_CK_C 6 3
+5V_Display For Docking HDMI_TX2+_CK_C 7 2
HDMI_TX2-_CK_C 8 1
R145 1 HDMI@ 2 2.2K_0402_5% HDMIDAT_R <37> HDMICLK_R
B B
<37> HDMIDAT_R 470 +-5% 8P4R
R146 1 HDMI@ 2 2.2K_0402_5% HDMICLK_R NoDocking@

+3VS

1
D
2
ESD S
G
Q7

3
NoDocking@
E14@ D1 E14@ D2 E14@ D3 2N7002H_SOT23-3
HDMIDAT_R 9 10 1 1 HDMIDAT_R HDMI_CLK-_CONN 9 10 1 1 HDMI_CLK-_CONN HDMI_TX0+_CONN 9 10 1 1 HDMI_TX0+_CONN

HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_CLK+_CONN 8 9 2 2 HDMI_CLK+_CONN HDMI_TX0-_CONN 8 9 2 2 HDMI_TX0-_CONN

HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX1-_CONN 7 7 4 4 HDMI_TX1-_CONN HDMI_TX2+_CONN 7 7 4 4 HDMI_TX2+_CONN

6 6 5 5 HDMI_TX1+_CONN 6 6 5 5 HDMI_TX1+_CONN HDMI_TX2-_CONN 6 6 5 5 HDMI_TX2-_CONN

3 3 3 3 3 3

8 8 8

L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B092P
Date: Wednesday, February 19, 2014 Sheet 28 of 53
5 4 3 2 1
5 4 3 2 1

+5VS +5VS_CRT

JP1
1 2
1 2
JUMP_43X39 Output Input Output Input
@
+1.8VS_CRT +1.8VS_RXVCC +1.8VS_CRT +1.8VS_DAC
+3VS +3VS_CRT

JP2 RT1 1 2 0_0402_5% RT2 1 2 0_0402_5%


1 2
1 2
Rated current 500mA, DC 0.1ohm Rated current 500mA, DC 0.1ohm
JUMP_43X39
@ Note: Depend on Note: Depend on
D D
Output Project, if Vp-p small Project, if Vp-p small
+3VS_CRT +1.8VS_CRT the 50mV change to 0 the 50mV change to 0
ohm ohm

1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_16V7K

1U_0402_6.3V6K
@ @

CT1

CT2

CT3

CT4
2 2 2 2
Output Input
+1.8VS_CRT +1.8VS_RXVDD

+3VS_CRT +1.8VS_RXVDD
RT3 1 2 0_0402_5%

1 1 1 1 1 1 1 Rated current 500mA, DC 0.1ohm

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
10U_0603_6.3V6M

4.7U_0603_6.3V6K
@
@ @ @ @

CT5

CT6

CT7

CT8

CT9

CT10

CT11
Note: Depend on
2 2 2 2 2 2 2 Project, if Vp-p small
the 50mV change to 0
ohm
ISPSDA_R RT4 1 2 0_0402_5%
ISPSCL_R RT5 1 2 0_0402_5% Pin.12 Pin.14 Pin.44 Pin.46

13
48

35
36

38
39

12
14
44
46
UT1

1
2
+5VS_CRT

DDCSCL

IVDD33
IVDD33
OVDD
OVDD

IVDD
IVDD
IVDD
IVDD
IVDDO
IVDDO
DDCSDA
RT6 1 2 0_0402_5% VGA_HPD 40
<9> DDI1_HPD HPD CT12
1

45 1 2 .1U_0402_16V7K
RT7 CT13 2 1 .1U_0402_16V7K CPU_DP1_C_P0 26 MCUVDDH
<5> CPU_DP1_P0 RX0P
4.7K_0402_5% CT14 2 1 .1U_0402_16V7K CPU_DP1_C_N0 27
<5> CPU_DP1_N0 RX0N +5VS
C CT15 2 1 .1U_0402_16V7K CPU_DP1_C_P1 29 47 RT8 C
<5> CPU_DP1_P1
2

2 1 .1U_0402_16V7K CPU_DP1_C_N1 30 RX1P MCURSTN 1 2


<5> CPU_DP1_N1
CT18
RX1N
Note: ISPSCL/ISPSDA for F/W update
1
28 22_0804_8P4R_5% @ 0_0402_5%
URDBG TT1
+3VS_CRT RT9 2 @ 1 1M_0402_5% CT19
RT10 2 @ 1 100K_0402_5% CT16 15 ISPSCL_R 4 5 CRT_CLK .1U_0402_16V7K
.1U_0402_16V7K ISPSCL 16 ISPSDA_R 3 6 2
ISPSDA

1
2 1 DDI1_AUX_C_DP 20 2 7 CRT_DATA
<9> DDI1_AUX_DP RXAUXP
2 1 DDI1_AUX_C_DN 19 23 1 8

OE#
P
<9> DDI1_AUX_DN RXAUXN VGADDCCLK 21 2 4
CT17 VSYNC CRT_VSYNC_1 RT18 1 2 33_0402_5% CRT_VSYNC_2
.1U_0402_16V7K VGADDCSDA A Y
RPT1

G
+3VS_CRT RT12 2 @ 1 100K_0402_5% DDI1_AUX_DP 18 3 VSYNC UT2 1
RT13 2 @ 1 1M_0402_5% DDI1_AUX_DN 17 DCAUXP VSYNC 4 HSYNC SN74AHCT1G125DCKR_SC70-5

3
DCAUXN HSYNC +1.8VS_DAC @ CT20
10P_0402_50V8J
2
+1.8VS_RXVCC
1 1

1U_0402_6.3V6K

.1U_0402_16V7K
@
25 10

CT21

CT22
+5VS
31 AVCC VDDC RT14
AVCC 2 2 1 2
1 1
IT6513FN
.1U_0402_16V7K
4.7U_0603_6.3V6K

+1.8VS_RXVCC
@

1
CT24

CT25

@ 0_0402_5%
22 CT23
2 2 PVCC 11 CRT_R
IORP .1U_0402_16V7K
2

1
+1.8VS_RXVDD 9 CRT_G

OE#
P
IOGP HSYNC 2 4 CRT_HSYNC_1 RT19 1 2 33_0402_5% CRT_HSYNC_2
24 A Y
Pin.25 DVDD18

G
8 CRT_B UT3
IOBP SN74AHCT1G125DCKR_SC70-5 1

3
41 @
NC/VGADETECT

8
7
6
5
+1.8VS_RXVCC CT26
5 1 2 RPT2 10P_0402_50V8J
32 RSET RT16 100_0402_1% 2
ASPVCC 75_0804_8P4R_1%
+5VS_CRT 7
RPT3

1
2
3
4
B VDDA +1.8VS_DAC B
1 8 CRT_DATA
2 7 CRT_CLK 6 1 2 CT27
3 6 PCSCL PCSDA 43 COMP .1U_0402_16V7K
4 5 PCSDA PCSCL 42 PCSDA
PCSCL 34 XTALIN_6511
XTALIN 33 XTALOUT_6511
2.2K_0804_8P4R_5% XTALOUT
PWDNB

PAD

IT6513FN_QFN48_6X6
37

49

+5VS_CRT

RT15 1 2 10K_0402_5% +5V_Display

CRT
ESD EMI LT1 6
JCRT1

FCM1608CF-470T07 0603 11
CRT_R 1 2 CRT_R_2 1
+5VS_CRT LT2 7
FCM1608CF-470T07 0603 CRT_DATA 12
CRT_G 1 2 CRT_G_2 2
DT1 E14@ LT3 8 G 16
CRT_HSYNC_2 6 3 CRT_DATA FCM1608CF-470T07 0603 CRT_HSYNC_2 13 17
I/O4 I/O2 1 2 3 G
CRT_B CRT_B_2
Reserve