15. Asynchronous Sequential Circuits 15.1.

Asynchronous Sequential Circuits

o Objectives o Review of basic circuit types:
This section deals with sequential circuits that are not n Combinational circuit: Inputs uniquely determine outputs
synchronized by a clock. The objectives are to: if all delays = 0.
n Develop models of behavior for these asynchronous n Sequential circuits: All others.
sequential circuits n Synchronous sequential circuit: Sequential circuit with at
n Use the models to illustrate some of the timing problems least one clocked flip-flop in every feedback loop.
that exist in these circuits n Asynchronous sequential circuit: All others
o Reading Assignment
n Chapter 9, sections 9.1 and 9.2

Elec 326 15.1 Asynchronous Sequential Circuits Elec 326 15.2 Asynchronous Sequential Circuits

o Definition: An asynchronous sequential circuit o Example - SR latch (Circuit 1)

(ASC) is a network containing only gates (no clocked
flip-flops) with the property that for some S X
Q
configuration of input signal values there is an output
signal that could be either 0 or 1. R
n Comments:
u All ASCs have at least one feedback loop. R S Q
Q = X' • R' and X = S' • Q'
u There are circuits with feedback loops that are combinational. Q = (S' • Q')' • R' 0 0 ?
u A circuit with clocked flip-flops could exhibits asynchronous = (S + Q) • R' 0 1 1
behavior. = S • R' + Q • R' 1 0 0
1 1 0
u An ASC can contain latches in addition to gates.

o This circuit is sequential since when R and S are both

0, the output Q could be either 0 or 1.
Elec 326 15.3 Asynchronous Sequential Circuits Elec 326 15.4 Asynchronous Sequential Circuits

1
 15.2. The Fundamental Mode ASC Model for
o Another ASC example (Circuit 2)
o Problems with Boolean expression model:
X Q n Boolean expressions are ambiguous
n Boolean expressions are inconsistent
n Both problems are due to feedback loops
Q = X'•Q' o Solution: Include an explicit delay element in each feedback
loop and assume that all of the delay of gates in a loop is
If X = 1, then Q = 0 modeled by a single delay at only one point in the loop.
If X = 0, then Q = Q' ** IMPOSSIBLE **
S X X Q*
Q* Q
Q
R
time

n The Boolean expression does not account for the delay of n This model, with exactly one delay element in each loop, is called the
Fundamental Mode ASC Model
the NOR gate.
n Comments:
u The exact value of the delay is frequently not important.
u The exact point where the delay is also not important for many
applications.

Elec 326 15.5 Asynchronous Sequential Circuits Elec 326 15.6 Asynchronous Sequential Circuits

o Properties of The Fundamental Mode ASC Model o Example 7474 D flip-flop (Circuit 3)
n Approach: Treat delays as D flip-flops
n Delay Element: Q(t+d) = Q*(t)
n State Variables: Represent delay element output signals X* X

n Internal state: A vector of state variable values Y* Y

Q Q
n Next-state variables: Represent delay element input
signals Z* Z
D D
n Next-state: A vector of values of next-state variables C C

n Input State: A vector of input variable values

n Excitation Equations: Expressions for the delay element X* = C•X + D•Z
input signals Y* = C•X + Y•Z
u Circuit 1: Q*(t) = S(t) R(t)' + Q(t) !R(t)' and Q(t+d) = Q*(t) Z* = C•X + D•Z + C' = X + D•Z + C'
u Circuit 2: Q*(t) = X(t)' !Q(t)' and Q(t+d) = Q*(t)

n Output Equations: Expressions for the circuit's output

signals
Elec 326 15.7 Asynchronous Sequential Circuits Elec 326 15.8 Asynchronous Sequential Circuits

2
o A Tabular Model of ASC Behavior o A Graphical Model of ASC Behavior
n Definition: ASC Transition Table n ASC transition graph
u Two-dimensional array 0
01
u Columns are labeled with input states 00,01
00,10,11 0 1 1 0 1
u Rows are labeled internal states Input Variable: X
Input Variables: RS 10,11 0,1
State Variable: Q
u Entry (i, j) is next-state for input j internal state i State Variable: Q

Circuit No. 1 Circuit No. 2

n Transition table examples
RS 10 00
11,10
Q 00 01 11 10 000
00,01
001
00,01
100
CD
0 0 1 0 0 XYZ 00 01 11 10
11,10 01,
1 1 1 0 0 00
11 11,10
Q* 000 001 001 000 000 00,01
001 001 101 101 000 Input Variables: CD
Circuit #1 011 011 111 111 010 010 101
State Variables: XYZ
01
001 001 001 000 000
X 100 001 001 111 111 00,01
10 11,10
Q 0 1 101 001 101 111 111
111 011 111 111 111 11,10
00
0 1 0 110 001 001 111 111 011 111 110
1 0 0 X*Y*Z* 00
01,11 01,11,10
Q*
Circuit #3
Circuit #2 Circuit No. 3
Elec 326 15.9 Asynchronous Sequential Circuits Elec 326 15.10 Asynchronous Sequential Circuits

o Column Transition Graphs o Differences from synchronous transition tables and

graphs:
000 100 000 001 100
n The state variables of synchronous circuit only change
001
when clock asserted. Input signal changes are ignored
between clock assertions
010 101 010 101 n The state variables of asynchronous circuit respond
immediately to input signal changes.
011 111 110
011 111 110 o Definition: An ASC is operated in fundamental mode
CD = 00
CD = 01
if input signal changes are constrained in the
following ways:
n Only one input signal is changed at a time, and
100
000 001 000
001 100 n Once an input signal has been changed, no input signal is
changed until the circuit reaches a stable state.
010 101
010
101 o If a well-designed ASC is operated in fundamental
mode, then the fundamental mode ASC model is
011 111 110
011 111 110
usually valid
CD = 10 CD = 11
n To be well-defined the combinational network (obtained by
breaking all loops) must be free of hazards.
Elec 326 15.11 Asynchronous Sequential Circuits Elec 326 15.12 Asynchronous Sequential Circuits

3
 15.3. ASC Timing Properties
o Some Basic Definitions
o Races in ASCs
n A Total State is an input state and internal state pair. n Definition: There is said to be a state variable race in a
u Note: n internal states and m input states gives m¥n total states.
total state if two of more state variables in that state are
excited.
n A state variable Q is quiescent for a given total state if Q = Q*.
u If there are two or more state variables trying to change, you may
n A state variable Q is excited for a given total state if Q ≠ Q*. not be able to predict the order of change.
u If the input and output of a delay element are different, the output must change.
Therefore, an excited state variable is one that is about to change. u The one that changes first wins the race.

u We don't know exactly when it will change.
n A total state is stable if all the state variables are quiescent in that total state.
n A total state is unstable if there is at least one excited state variable in that
total state.
u Stable total state: its entry in the transition table is the same as its row heading.
We usually circle that entry to indicate it is stable.
u Stable total states correspond to the nodes with self-loops
u The only way to leave a stable state is to change one or more input signals
u The behavior of a circuit can be significantly affected by which one
wins.
n Definition: A state variable race is said to be critical if the
final state reached depends on the order of state variable
changes.
n Definition: A state variable race is said to be non-critical if
the final state reached is independent of the order of state
variable changes.

Elec 326 15.13 Asynchronous Sequential Circuits Elec 326 15.14 Asynchronous Sequential Circuits

o Example: Circuit #3 CD
CD XYZ 00 01 11 10
XYZ 00 01 11 10
000 001 001 000 000
000 001 001 000 000 001 001 101 101 000
001 001 101 101 000 011 011 111 111 010
011 011 111 111 010 010 001 001 000 000
010 001 001 000 000 100 001 001 111 111
100 001 001 111 111 101 001 101 111 111
101 001 101 111 111 111 011 111 111 111
111 011 111 111 111 110 001 001 111 111
110 001 001 111 111 X*Y*Z*
X*Y*Z*
n State variable Z is excited in total state 00,000, so it will change from 0
n There are a 32 total states for the circuit. to 1 if the inputs are held at 00 long enough.
n You can indicate excited state variables in a total state with asterisks.
n CD,XYZ = 00,101 and CD,XYZ = 10,101 two different Total state 00,01*0* is unstable Y and Z are excited state variables.
total states with the same internal state 101. u If Y wins the race, the circuit goes to 00,000* and then 00,001.
u If Z wins the race, it goes to state 00,011, so we have a critical race in state
n All of the state variables in total state 00,001 are quiescent, 00,01*0*.
so that state is stable. u The race will never occur if the circuit is operated in fundamental mode.

Elec 326 15.15 Asynchronous Sequential Circuits Elec 326 15.16 Asynchronous Sequential Circuits

4
 15.4. A Detailed Gate Delay Model
CD
XYZ 00 01 11 10 o Definition: The gate-level delay model for an ASC is
000 001 001 000 000 obtained by inserting an imaginary delay element
001 001 101 101 000 after every gate in the circuit and assigning a state
011 011 111 111 010 variable to the output signal of each of these delays.
010 001 001 000 000
n This model is more important in providing insight into the
100 001 001 111 111
101 001 101 111 111
way ASCs work and the kinds of problems that can arise
111 011 111 111 111
than it is a useful method of analysis.
110 001 001 111 111 n This model can also be used to analyze the transient
X*Y*Z* behavior of loop-free circuits.
n The state space too large to be very useful. Circuit No. 3
n Total state 01,1*00* is a non-critical race with X and Z has 256 total states.
excited.
u If X changes first, the circuit goes to state 01,000*, then 01,0*01,
then 01,101. If Z changes first, it goes directly to 01,101.

Elec 326 15.17 Asynchronous Sequential Circuits Elec 326 15.18 Asynchronous Sequential Circuits

o Example - RS Flip-Flop
n Changing both inputs at the same time violates the
fundamental mode of operations, and this example will
show that the fundamental model is inadequate when that is RS
XQ 00 01 11 10
done.
S X* X 00 11 01 00 10
Q*
Q 01 01 01 00 00
R 11 00 00 00 00
10 10 00 00 10
Gate-Level delay Modelfor Circuit No. 1 X*Q*
X* = S'•Q' Q* = X'•R'
RS
XQ 00 01 11 10

00 11 01 00 10
01 01 01 00 00 u Consider setting both inputs to 1 and waiting until the circuit
reaches total state 11,00. Then change both inputs to 00.
11 00 00 00 00
u If both inputs are never changed from 1 to 0 at the same time, the
10 10 00 00 10 fundamental mode model is adequate.
X*Q*

Elec 326 15.19 Asynchronous Sequential Circuits Elec 326 15.20 Asynchronous Sequential Circuits

5
o Example - Gated Latch D
Q* Q

G
X* X

D
Q GD
Q 00 01 11 10 Detailed Model for Circuit No. 4
X* = G’ Q* = D•G + X•Q
G
0 0 0 1 0 GD
Circuit No. 4
1 1 1 1 0 XQ 00 01 11 10
Q* = D•G + G’•Q Q* 00 10 10 01 00
01 10 10 01 00
11 11 11 01 01
n There are two paths from input terminal G to output 10 10 10 01 00
terminal Q, and one goes through 2 gates, while the other X*Q*
goes through 3.
u State GD,XQ = 01,01 is a critical race state as both state variables are
n Assuming that there is only one delay element in the excited.
feedback path ignores any timing differences along these u This critical race will occur even if the circuit is operated in fundamental
paths. mode.
u The race in the gated latch is due to a hazard in the combinational logic of
the circuit.

Elec 326 15.21 Asynchronous Sequential Circuits Elec 326 15.22 Asynchronous Sequential Circuits

Q* G D
15.5. Review
Q

0 0 1 0 o We developed a method of analyzing asynchronous

Q 1 1 1 0
G sequential circuits.
Modified Circuit No. 4
o We added imaginary delay elements to account for
D
X* = G' Q* = D•G + X•Q + D•Q propagation delays of gates.
GD o To analyze circuits, we treated the added delay
XQ 00 01 11 10 elements as D flip-flops.
00 10 10 01 00 o Major difference between asynchronous and
01 10 11 01 00 synchronous circuit models.
11 11 11 01 01 n Synchronous - all state changes are initiated by the clock.
10 10 10 01 00 n Asynchronous - state changes initiated by changing any
X*Q* input signal.
o New concepts unique to asynchronous circuits:
u There is still a race in state 11,10, but it is not critical.
n total states
u There is also a race in state 00,01, but that state can only be reached
by violating fundamental mode operation n stable vs. unstable total states
n race states
Elec 326 15.23 Asynchronous Sequential Circuits Elec 326 15.24 Asynchronous Sequential Circuits

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o It is most accurate to add a delay element after each
gate.
o It is less accurate but more manageable to add delays
at a few select points.
o We need at least one delay element per feedback loop
- using exactly one gives the fundamental mode
model for an ASC.
o The fundamental mode model is not accurate enough
to answer some questions.
o To use the fundamental mode model, you must
operate circuit in fundamental mode.
o The combinational circuit part of an ASC must be
free of hazards.

Elec 326 15.25 Asynchronous Sequential Circuits