Design in Detail

LECTURE 4

MAY 2012
 Topics Covered

 Process
 Process statement
 Signal and variable assignment
 Common sequential statements in process
 If – else
 Case
 Loop, for, while
 Synthesis of combinational logic
 Processes
design entities

Process signal
boundary

process
 Process Statement

[process label] : process (sensitivity list)

begin
…
end process;
 Processes

architecture Version1 of AnEntity is

component AComponent ...
signal SignalA ...
begin
Label1: AComponent port map (...)
SignalA <= ....

process (X, ...)

Process begin
boundary ...
end process;

process (Y, ...)

begin
...
end process;

end Version1;
 Processes Terminology

 Process Concurrency
 Between processes, they are concurrent to each other.

 Concurrency is important when network modelling is concerned.

 A hierarchy of processes can be realized by having one process

internalizes the other process(es).

 Desired topology can be formed.

 Communication between network nodes, or top most hierarchy

process can be scheduled with the internal signals.
Network Modeling with Process
 Different Process Statement

-- with sensistivity list -- with wait statements

process (Sel, A, B) INITIALISE: process

begin begin
if Sel = '1' then Reset <= '0';
Output <= A and MASK; wait for 50 ns;
else Reset <= '1';
Output <= B; wait;
end if; end process INITIALISE;
end process;
-- label is optional

These process statement formats are mutually exclusive.

 Signal and Variable Assignment

 Signal assignment involves the use of

 “signal” declaration
 “ <= ”
 Variable assignment uses
 “variable” declaration
 “ := ”
 Signal Assignments

A S T F
B

process (A, B, S, T)
begin
S <= A nand B after 2 ns; -- synthesizer ignores delays
“after 2 ns”
T <= not S; -- small delay > 0
F <= T after 1 ns;
end process;
 Signal Assignments

2 ns
S
This may be true for other
timing simulator with
T different annotation

1 ns
F
 Variables

 Variables are generally used to store intermediate values.

 Variables are not to be used as ports.

 Variables are only visible within a process that declares

them.

 Immediate assignment of value makes them suitable to

mimic complex arithmetic process.
 Variables

A (V)
B
(V) F
C

process (A, B, C)
variable V: Std_logic;
begin
Every time this process is
invoked, the two V’s use
V := A nand B;
different memory segments. V := V nor C;
F <= not V;
end process;
 Signal vs Variable

 Signals can be used for inter-process communication

 They are generally used as ports.
 Signals always assigned with delay
 Internal signals generally connect to gates.
 Variables can only be used within a single process
 In general programming terms, they only use temporary
storage or memory that has to be released after use.
 Variables are assigned immediately
 This feature frees the programmer from doing housekeeping.
Common Sequential Statement
in Process
 If Statements

process (S1, S2, S3, A, B)

variable V: Std_logic;
begin

if S1 = '0' then
Highest V := A;
priority else
V := B;
end if;

Lower if S2 = '1' and S3 = '1' then

priority V := not V;
end if;

F <= V;
end process;
 If Implementation

S2
S3
S1
‘0’ (V)
A ‘0’ (V)
MUX F
MUX ‘1’
B ‘1’

Higher priority statement will be evaluated before

lower priority statement. Synthesizer will allocate
resources according to the order of evaluation.
 Elsif

process (S1, S2, S3, A, B, C, D)

begin
if S1 = '1' then
F <= A;
elsif S2 = '1' then
F <= B;
elsif S3 = '1' then
F <= C;
else
F <= 'D';
end if;
end process;
 Elsif Implementation

S3 S2
S1
D ‘0’
MUX ‘0’
C ‘1’ MUX ‘0’
B ‘1’ MUX F
A ‘1’

Priority implies multiple logic levels

 Incomplete Assignment

process (Enable, Data)

begin
if Enable = '1' then
Q <= Data;
end if;
end process;
Enable

Data ‘1’ Data

MUX Q LATCH Q
‘0’ Enable

Both are equivalently plausible implementation. This would make the

description implementation ambiguous.
FPGA’s and Transparent Latches

process (G, D)
begin
if G = '1' then
Q <= D;
end if;
end process;

D (D’.G)’
Q

D.G
G
Case Statements

case Sel is
when "00" =>
F <= A;
when "01" =>
F <= B;
when "10" =>
F <= C;
when "11" =>
F <= D;
end case;
Sel
A
B
C F
D
Case Statement Options
A <= '0';
B <= '1'

case Address is

-- Select a range of address values

when 0 to 7 =>
A <= '1';
when 8 to 15 =>
B <= '0';

-- Pick out a number of address values

when 16 | 20 | 24 | 28 =>
A <= '1';
B <= '0';

-- Mop up the rest

when others =>
null;
end case;
 For Loops

process (A, B) A(0)

variable V: std_logic; F(0)
B(3)
begin
V := '0'; A(1)
F(1)
for I in 0 to 3 loop B(2)
F(I) <= A(I) and B(3 - I);
V := V xor A(I); A(2)
F(2)
end loop; B(1)
G <= V; A(3)
end process; F(3)
B(0)
V
A(0)
A(1)
G
A(2)
A(3)
Other Loop Statements

for Parameter in Loop_Range loop

...
end loop;

while Condition loop

...
end loop;

Label1: loop
...
exit; -- jump out of loop
...
exit Label1; -- jump out of loop
...
next Label1; -- jump to top of loop
...
end loop Label1;
 Wait For

Stimulus: process ClockGen: process

begin begin
A <= "0000"; for I in 1 to 4 loop
B <= "1111"; Clock <= '0';
wait for 10 ns; wait for 5 ns;
A <= "0101"; Clock <= '1';
wait for 10 ns; wait for 5 ns;
B <= "1010"; end loop;
wait for 10 ns; wait;
A <= "1100"; end process;
B <= "0011";
wait;
end process;
Cannot be synthesised
Only used for stimulus generation in testbench
 Synthesis of Combinational Logic

 Combinational logic within a process statement

can use -
 Signal assignments
 Variable assignments

 If, case and loop statements

 Three rules
 Sensitivity list

 Complete assignment

 Feedback
Synthesis of Combinational Logic

process (A, B, C, D) -- Complete sensitivity list

variable V: std_logic_vector(3 downto 0);
begin
V(3) := A;
V(2) := B;
V(1) := C;
V(0) := D;
F <= 0; -- No incomplete assignment
for I in 0 to 3 loop
if V(I) = '1' then
F <= I;
exit;
end if;
end loop;
end process; -- No feedback
RTL
Description
RTL descriptions are
used for synchronous
designs and describe
the clock-by-clock
behavior of the design.

Register-to-Register transfer
 Parallelism

 Concurrency:
 multiple events or signal assignment at same moment.

 Example:
 Select <= 0 when s0 = ‘0’ and s1 = ‘0’ else
1 when s0 = ‘1’ and s1 = ‘0’ else
2 when s0 = ‘0’ and s1 = ‘1’ else
3;
 Concurrent Assignment

 Consider a 3-input OR gate…

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY or3 IS
PORT (a, b, c : IN std_logic;
D : OUT std_logic);
END or3;

ARCHITECTURE synth OF or3 IS

BEGIN
D <= a OR b OR c;
END synth;
 Concurrent Assignment

 Implementation is
 Technology library dependant
 Technology library contains models for gate level cells.
 Speed constraint dependant
 Maximum delay allowed can determine the logic level allowed in
the design.
 Clock speed also asserts constraint on setup and hold time.

 Design requirement dependant

 Design area could set the entire design process back to square 1.
 Limited resources, such as the number of macro cells available,
types of IO suitable for operation, determine the outcome of some
design to a large degree.
 Scheduling

 Keyword: after
 Example:
 x <= a after 0.5 ns when select = 0;

 Keyword: transport
 Example:
 X <= transport a after 1 ns;
Inverse Multiplexer
 Barrel Shifter

Depending on the selection signal, the output could be 0, 1, 2, 3 places shifted

version of the original input.
 Half-adder

 How does half-adder

come about?
 Full-adder

 How does full adder

come about?
 Full Adder from Half Adders

s2 = xi  yi  ci
c = ci  (xi  yi)

c2 = c1 + ci  (xi  yi)
= xi  yi + ci  (xi yi) + ci
 (xi yi)
2nd stage half = xi  yi + ci  xi + ci  yi
1st stage half adder
adder

s1 = xi  yi
c1 = xi  yi
Interpretation of 4 bit signed integers

2 places
for ‘0’ Squeeze in extra one number
Number
in
sequence
, but still 2
places for
‘0’.
The signed numbers wheel

Goal achieved: 4
binary bit with 16
combination can
represent 16
Advancing distinct numbers.
clockwise
for addition
The signed numbers wheel

Goal achieved: 4
binary bit with 16
combination can
represent 16
Advancing distinct numbers.
counter-
clockwise for
subtraction
Adder Subtractor
Ripple Carry Adder
Carry-Lookahead Adder
 Fundamentals of Carry-Lookahead Adder

 ci+1 = xiyi + xici + yici

 ci+1 = xiyi + (xi + yi)ci
 ci+1 = gi + pici
 gi = xiyi generate function
 pi = xi + yi propagate function
 ci+1 = gi + pi(gi-1 + pi-1ci-1)
 ci+1 = gi + pigi-1 + pipi-1ci-1
 ci+1 = gi + pigi-1 + pipi-1gi-2 + … + pipi-1 …p2p1g0 + pipi-1
…p1p0c0
 Alternative Implementation of Carry
Lookahead Adder
 Adder cell
 gi = xi  yi generate function
 pi = xi  yi propagate function
 sumi = pi  ci parallel summation term
 Lookahead carry module
 ci+1 = gi | pi  ci

 cnext_layer = ci

 gnext_layer = gi+1 | pi+1  gi

 pnext_layer = pi+1  pi
Kogg-Stone Adder
 Brent-Kung Adder

http://www.cs.cmu.edu/afs/cs/academic/class/15828-s98/lectures/0121/sld012.htm
 References

1. “VHDL: Programming by Example” by Douglas L.

Perry, 4th ed., McGraw Hill.