IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.
10, OCTOBER 2010
A Compact Model for Undoped Symmetric
Double-Gate Polysilicon Thin-Film Transistors
Junkai Huang, Wanling Deng, Xueren Zheng, and Xiaozhou Jiang
Abstract—A physics-based solution to the surface potential and
potential in the middle of the film for the symmetric undoped
or light-doped double-gate (DG) polysilicon thin-film transistors
(poly-Si TFTs) has been derived from the one-dimensional (1-D)
Poisson’s equation. The calculation of the channel potential ac-
counts for an exponential distribution of defect states’ density.
It provides a good description of surface potential over different
regions of operation. Comparison with numerical data shows that
the solution serves as a good approximation to potential under
different conditions. The characteristics of the drain current at
DG poly-Si TFTs based on terms of surface potential have been
described and modeled in this paper. The resulting drain current
characteristics show a good agreement with two-dimensional (2-D)
numerical device simulations with a minimum of parameters, and
also a good match to the DG poly-Si TFTs experimental data.
Index Terms—Double-gate polysilicon thin-film transistors (DG
poly-Si TFTs), drain current, modeling, surface potential.
I. I NTRODUCTION
R ECENTLY, polysilicon thin-film transistors (poly-Si
TFTs) have been regarded as one of the most potential ap-
plications in active-matrix liquid crystal display, active-matrix
organic light-emitting display, SRAMs for load device, etc. For
these applications, poly-Si TFTs with high performance are
required. In recent years, double-gate (DG) structures of poly-
Si TFTs [1], [2] have emerged because they are able to improve
the current drivability, short channel effects, and subthreshold
slope of these devices.
DG structures of poly-Si TFTs are analogous to DG
MOSFETs. Extensive research works have been devoted to the
modeling of the DG MOSFET S. For example, Y. Taur et al. [3]
and A. Ortiz-Conde et al. [4] have developed the core compact
models for the symmetric undoped DG silicon-on-insulator
devices, respectively [5]. While there are similarities between
poly-Si TFTs and their crystalline silicon counterparts, the
poly-Si grain boundary (GB) traps and intragrain defects in-
troduce many significant differences in electrical properties.
Although physics-based two-dimensional (2-D) model has ap-
peared for DG poly-Si TFTs [6], in the literature, only few com-
Manuscript received April 7, 2010; revised July 9, 2010; accepted July 10,
2010. Date of publication August 12, 2010; date ofcurrent version September 22,
2010. The review of this paper was arranged by Editor V. R. Rao.
J. Huang is with the Institute of Microelectronics, School of Electronic and
Information Engineering, South China University of Technology, Guangzhou
510640, China, and also with the Department of Electronic Engineering, Jinan
University, Guangzhou 510630, China (e-mail: hjk196310@126.com).
W. Deng and X. Jiang are with the Department of Electronic Engineering,
Jinan University, Guangzhou 510630, China.
X. Zheng is with the Institute of Microelectronics, School of Electronic and
Information Engineering, South China University of Technology, Guangzhou
510640, China.
Digital Object Identifier 10.1109/TED.2010.2060725
0018-9383/$26.00 © 2010 IEEE
2607
pact models are presented about the surface potential and drain
current of the DG poly-Si TFTs. Because of the application
advantages, the demand of an accurate and circuit-simulation-
compatible compact model for the DG poly-Si TFTs is really
an urgent task.
In the literature, it is believed that the high density of defects
in the GBs significantly affects the drain current characteristics.
The main problem for modeling the DG poly-Si TFTs is that
when solving the Poisson’s equation, the exponential density
of states (DOS), continuous in energy, should be taken into
account. In addition, applying Gauss’ law, the gate voltage as
a function of the potentials is formulated by transcendental
equation, which has no analytical solution.
In this paper, for the first time, approximation has been
developed to efficiently compute the surface potential in the
symmetric DG poly-Si TFTs using the regional approach. Fol-
lowing that, its verification with numerical simulations is given.
After that, using the surface potential calculation, drain current
model of the subthreshold region and above-threshold region
has been derived. The approach using surface potential has been
adopted but not the threshold-voltage-based one because it is
difficult to obtain an accurate expression for threshold voltage
and the drain current in subthreshold region is strongly surface-
potential-dependent. Finally, the proposed current model is
verified on the poly-Si devices using various experimental data.
II. P ROPOSED C ALCULATION OF S URFACE P OTENTIAL
FOR THE S YMMETRIC DG P OLY-Si TFTs
The symmetric n-type DG poly-Si TFTs with undoped or
light-doped body under analysis is shown in Fig. 1, where
tOX is the gate dielectric thickness, tpoly is the poly-Si film
thickness, ψ(x) is the electrostatic potential, ψs is the surface
potential, and ψ0 is the potential in the middle of the film. The
energy levels in Fig. 1 are referenced to the electron quasi-
Fermi level or the conduction band of the n+ source or drain.
The basic assumption we made is that continuous DOS with
exponential tails at the GBs is uniformly distributed throughout
the film because of a mixture of grains and amorphouslike
structures in poly-Si films with a large number of defects within
the grain volume [7]. Neglecting hole concentration, the 1-D
Poisson’s equation along the perpendicular direction of the
poly-Si film takes the form of
d2 ψ q −
= (n + NTA ) (1)
dx2 εsi
where q is the electron charge, εsi is the silicon permittivity,
−
NTA is the density of ionized traps, and the free charge density
2608 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010

the film, the electric field at the surface of the poly-Si layer
is calculated
COX
Fs = (VG − Vfb − ψs )
ε
si      
2q ψ0 − ψs ψs
= n0 φt 1 − exp exp
εsi φt φt
     1/2
ψ0 −ψs ψs
+ NT 0 φG 1−exp exp
φG φG
(6)

where NT 0 = gc1 (πkT / sin(πkT /E1 )) exp(−qφn − EC /E1 ),

n0 = ni exp(−φn /φt ), and φG = E1 /q.
The asymptotic behavior of ψs may be derived from (6)
by considering the corresponding dominant terms for different
bias condition. In the subthreshold region, since an exponential
DOS strongly affects its characteristics and most of the induced
charge is trapped in deep states, the dominant term in the right-
−
hand side (RHS) of (1) is the density of ionized traps NTA
[9]. Neglecting n term, we can obtain the following asymptotic
equation in subthreshold region:

COX 2q
(VG − Vfb − ψs ) =
εsi εsi
      1/2
ψ0 − ψs ψs
× NT 0 φG 1 − exp exp . (7)
Fig. 1. Schematic diagram of a symmetric DG poly-Si TFT cross section and φG φG
the corresponding band diagram.
In strong inversion region, when all the additional induced
n is given by charge is free charge, free charge dominates Poisson’s equation
  (1). Similar to MOSFET device, where the dominant term in the
−
ψ − φn RHS of (1) is the free charge density n, neglecting NTA term,
n = ni exp (2)
φt we get the other asymptotic equation

with φn is the channel potential and φt is the thermal voltage COX 2q
(VG − Vfb − ψs ) =
kT /q. εsi εsi
A single exponential DOS distribution in the upper half of       1/2
ψ0 − ψs ψs
the gap [8] is assumed, and therefore, the density of ionized × n0 φt 1 − exp exp . (8)
φt φt
acceptorlike traps can be expressed as [9]
  From (6)–(8), the electric field depends not only on ψs but
− πkT qψ − qφn − EC
NTA = gc1 exp (3) also on the difference of potentials at the surface and at the
sin(πkT /E1 ) E1 center of the layer, i.e., ψs − ψ0 . Numerical solutions to (1)–(5)
for some typical parameters are shown in Fig. 2. It is seen that
where gc1 is the states’ density, E1 is the inverse slope of states,
at low gate biases, while the poly-Si change remains small, the
and EC is the conduction band energy.
potential stays flat throughout the entire film thickness, closely
Straight application of Gauss’ law for the schematic structure
following the gate voltage everywhere, and ψs − ψ0 is a small
of Fig. 1 results in the following boundary conditions for the
value. As the gate voltage increases, ψ0 starts to depart from ψs
surface and the center of the poly-Si film:
and ψs becomes more and more significant.
 To obtain ψs and ψ0 in subthreshold region, we employ
dψ  COX
= (VG − Vfb − ψs ) (4) an iterative scheme described in the following. At the be-
dx x=tpoly /2 εsi
ginning, initial values of ψs and ψ0 are provided. Since in

dψ  subthreshold region ψs − ψ0 changes insignificantly, following
=0 (5)
dx x=0 the derivation of crystalline silicon MOSFET [10], ψs − ψ0 can
be roughly estimated as
where Vfb is the flatband voltage and COX is the unit-area gate
 
oxide capacitance. qNT 0 ψ0 /2φG tpoly
α = ψs − ψ0 = −2φG ln cos e .
Using the relation 2(∂ψ/∂x)(∂ 2 ψ/∂x2 ) = (∂/∂x)(∂ψ/ 2εsi φG 2
∂x)2 , and integrating from the surface toward the center of (9)
HUANG et al.: COMPACT MODEL FOR UNDOPED SYMMETRIC DOUBLE-GATE POLYSILICON THIN-FILM TRANSISTORS 2609

where ω is the first-order correction term of ψ0 . Using Schroder

series and substituting (9) into (7), one obtains
y/y 
ω(y, y  , y  ) = − (14)
1 − 0. 5yy  /y  /y 
where
εsi 4φG
y = (VGB − ψ00 + 2φG ln [cos(β)]) − · β tan(β)
COX tpoly
(15)

qNT 0 ψ00 /2φG tpoly
β= e (16)
2εsi φG 2

y  = ∂y/∂ψ00 , and y  = ∂ 2 y/∂ψ00

2
.
Since the initial guess of the potential in the middle of the
film ψ0 has been corrected, a more accurate value of α as
Fig. 2. Potential ψ as a function of position in the poly-Si film for various
a function of gate bias can be determined by (9), which is
values of VG . Parameters used for calculation are tpoly = 60 nm, φn = 0 V, assumed to be a constant value previously. As a consequence,
gc1 = 2 × 1018 cm−3 · eV−1 , E1 = 0.161 eV, tOX = 100 nm, and after a new α is obtained, the route of (10) is repeated to get a
Vfb = 0 V. more accurate result of ψsub . To further improve the accuracy
of ψsub , we denote
Using the principal branch of the Lambert W function [11] and 
ψsub0 = ψsub + ω (yW , yW 
, yW ) (17)
α given above, explicit solution of (7) can be found
 
   where ω(yW , yW , yW ) has the same function form as given in
A VGB
ψsub = VGB − 2φG W0 exp (10) (14), but here, we have
2φG 2φG
yW = (VG − Vfb − ψsub )2
where VGB = VG − Vfb and ψsub is the value of ψs in      
2qεsi −α ψsub
subthreshold − 2 n0 φt 1 − exp exp
COX φt φt
        
2qεsi NT 0 φG −α −α ψsub
A= 2 1 − exp + NT 0 φG 1 − exp exp
COX φG φG φG
(18)
and W0 (x) is the Lambert W solution of the transcendental
equation W0 (x) × exp[W0 (x)] = x. yW
= ∂yW /∂ψsub , and yW 
= ∂ 2 yW /∂ψsub
2
.
For the initial guess of α, ψ0 in the RHS of (9) is chosen as a It should be emphasized that the algorithm described above
typical constant ψ0con . Consequently, using ψsub from (10), one is capable to accurately calculate ψ0 and ψsub for a given gate
can find a new ψ0 by ψ0 = ψsub − α, which is denoted as ψ0f . voltage within the range of subthreshold region.
As we know, similar to MOSFET device, ψ0 can saturate to a In another case, in strong inversion region, when the Fermi
maximum value ψ0 max . Since the angle of the cosine function level moves toward conduction band of n+ source drain and the
in (9) cannot exceed π/2 [12], ψ0 max is given by concentration of free charge is much larger than that of trapped

   states, the first exponential term on the RHS of (6) is dominant.
2π 2 εsi φG 2π 2 εsi φt Furthermore, as the mobile charge near the poly-Si surfaces
ψ0 max=M in φG ln , φn +φt ln .
qNT 0 t2poly qni t2poly screens the gate field from the center of the film, ψ0 and ψs
(11) become decoupled. Therefore, the term exp[(ψ0 − ψs )/φt ] in
(8) turns out to be negligible and the surface potential in this
As a result, the behavior of ψ0 , defined as ψ00 , can be described case can be approximately expressed as
by using a smoothing function    1/2
COX 2q ψstr
1/m (VG − Vfb − ψstr ) = n0 φt exp
ψ00 = ψ0f / {1 + [ψ0f /(λψ0 max )]m } (12) εsi εsi φt
(19)
where m determines how sharply ψ0 changes to the maximum where ψstr denotes to be the surface potential in strong inver-
value, and λ is a parameter fitting the magnitude. sion. On the other hand, ψstr can be obtained by using the
To get more accurate values of ψs and ψ0 , correction terms Lambert W function [13], i.e.,
can be derived from (7). We define   
qεsi n0 VGB
ψstr = VGB − 2φt × W0 2 exp . (20)
ψ0 = ψ00 + ω (13) 2φt COX 2φt
2610 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010

One can improve the accuracy of ψstr by calculating the correc- where
tion term as we did for ψsub , i.e., (17) and ψstr0 = ψstr + ω.  
πkT −EC
When a device changes the operation region from subthresh- NTA0 = gc1 exp
old to strong inversion as VG is increased, we use the following sin (πkT /E1 ) E1
qni 2φG φt
smooth function to link the operation region: = × .
2qNTA0 (ψs − ψ0 ) /εsi 2φG − φt
ψstr0 ψsub0
ψs =  +   In subthreshold region, most of the induced charge is trapped
−(VG −VGT ) VG −VGT
1 + l1 exp l2 1 + l 1 exp l2 and the current is dominated by diffusion. The drain current
(21) Isub can be written in terms of carrier charge densities. Using
where ψs is the unified surface potential, l1 and l2 are fitting an expression similar to that of the standard MOSFET diffusion
parameters. VGT is corresponding to the condition of equal theory [16], Isub is modeled by
  
values of ψstr and ψsub , that is (7) and (8) intersect at VG = W 2φG φt  1 1
VGT , which leads to Isub = 2μeff exp − ψss
L 2φG − φt φ 2φG
t  
ln χ VDS
VGT = Vfb + × 1 − exp − (25)
1/φt − 1/φG ηφt
 where μeff is the effective mobility and η is the extracted
2qεsi n0 φt [1 − exp(−α/φt )] 2(φ φG−φ )
+ χ G t (22) constant.
COX Drain-induced barrier-lowering (DIBL) effect which is sig-
nificant to short-channel devices causes the threshold voltage
here, χ = NT 0 φG [1 − exp(−α/φG )]/n0 φt [1 − exp(−α/φt )].
of TFTs to decrease as drain bias is increased [17]. In the
To evaluate VGT , we roughly calculate α in (22) by (9), namely,
above described model, the DIBL effect can be included by
by making ψ0 in (9) equal to c1 ψ0 max . The typical value of c1
replacing (VG − Vfb ) in ψss of (25) by an effect gate voltage
is about 0.8.
(VG − Vfb ) + σVDS [18], where σ is an empirical parameter
which depends on channel length L.
III. D RAIN C URRENT M ODEL When VG is large enough, all the additional induced charge
We have simulated the DG poly-Si TFTs using MEDICI is free charge, and hence, the TFTs operate at strong inversion
[14], a powerful and physically based 2-D device simulator. The region. The band bending near the surface mostly attributes
structure used in MEDICI comprises of polycrystalline silicon to free charge. This implies that the behavior of DG poly-
film with exponential DOS distribution sandwiched in between Si TFTs in strong inversion is similar to that of crystalline
top and bottom gate oxide. It is found from MEDICI that in MOSFET S. Extending the current formulation of symmetric
the subthreshold region, the plots of ln(Ids ) and ψs in source DG MOSFET S[4], [5], we get the following drain current
end are parallel lines, that is, ln(Ids ) ∝ ψss , where ψss is the for the undoped or lightly doped DG poly-Si TFTs in strong
surface potential in source end which is the solution of (17) with inversion:
φn = 0. Whenever we are interested in the exact values in the W
subthreshold range, it might be preferable to use (17) instead to Ia = μeff [2COX (VG − Vfb )(ψsL − ψs0 )
L  2  
calculate the surface potential. − COX ψsL − ψs0
2
+ 4φt COX (ψsL − ψs0 ) (26)
The total inversion charge density inside the poly-Si film of a
symmetric DG poly-Si TFTs in subthreshold region Qi is given where ψsL and ψs0 are the surface potential in drain end
by using (7), i.e., and source end, respectively, which are the solution of (20)
with φn = VDS and φn = 0, respectively, and μeff is the gate-
ψs voltage-dependent field-effect mobility which includes the ef-
n
Qi = 2q dψ fects of the trap states. As shown in [2], the field-effect mobility
F
ψ0 of DG poly-Si TFTs increases as the gate voltage rises due to
the decrease of GBs’ potential barrier height. However, when
ψs gate bias is large enough and all the additional induced charge
n0 exp (ψ/φt )
= 2q       dψ. is free charge, mobility saturates, and at higher VG , mobility
ψ0
2qNT 0 φG
εsi 1 − exp ψφ0 −ψ
G
exp 2φψG degradation caused by phonon scattering and surface rough-
ness scattering occurs. Hence, the mobility model can be re-
(23) presented as
μ0 · exp(−Vb /φt )
Following the approximation used in [15] and taking exp(ε) ≈ μeff = μs + 2 (27)
1 + ε for small ε, the above integration is done and 1 + θ1 VGB + θ2 VGB
  12
we have Vb = (VGB − Vi )2 + (VQ − ρVdeff )2 − (VGB − Vi )
  
1 1 (28)
Qi = 2 exp − (ψs − φn ) (24)
φt 2φG Vdeff = VDS − (ψsL − ψs0 ) (29)
HUANG et al.: COMPACT MODEL FOR UNDOPED SYMMETRIC DOUBLE-GATE POLYSILICON THIN-FILM TRANSISTORS 2611

where μ0 is the saturation mobility which is a channel-length-

dependent parameter, μs is the low-gate-bias mobility, θ1 and
θ2 are mobility degradation parameters, VQ and Vi are extracted
potential barrier parameters, and ρ accounts for the DIBL ef-
fect [19].
Kink effect, which is much more pronounced in single-gate
poly-Si TFTs, is also observed in DG poly-Si TFTs when drain
bias is high [1]. In saturation, accounting for the kink effect, the
modeled multiplication factor Mk yields
 
−Bi
Mk = Ai [VDS − (ψsL − ψs0 )] exp
VDS − (ψsL − ψs0 )
(30)
where Ai and Bi are the kink-effect voltage parameter, and Ai
depends on channel length L.
As discussed before, we have modeled the drain current
in subthreshold and strong inversion region separately. We
can obtain a smooth drain current model valid in a wide Fig. 3. Solutions ψs and ψ0 of DG poly-Si TFTs as a function of gate voltages
range of operation by combining the currents calculated by as obtained from the numerical results of (1)–(5) (markers) and the results
of (13) and (21) (solid lines). The ψs results of the subthreshold and strong
separately accounting for each distribution. In addition, to inversion asymptotic approximations, (7) and (8), are also shown. Parameters
facilitate quick convergence in circuit simulators, the model used in simulation are listed in Table I. Numerical results of ψs for a single-gate
should be continuous. This is accomplished by the following TFT with the same parameters are also depicted.
expression:
TABLE I
 1/mx PARAMETERS FOR SIMULATIONS
1
IDS = (Mk + 1) (31)
1/(Isub )mx + 1/(Ia )mx

where parameter mx determines how sharply Ids changes from

subthreshold to strong inversion. Equation (31) uses smooth-
ing function to combine the drain current models in different
region, which is more and more accurate as the difference
between the two components gets larger. However, the model
is not physical and less precise in the region between the
subthreshold and strong inversion, because the drain current
model in this region should contain both drift and diffusion
components. Although the model has the drawback, it is a
tradeoff between accuracy and complexity. Furthermore, it is
beneficial for short computation time in circuit simulation.
Equation (31) is suitably approximated and the accuracy of the
transition region is adjusted by parameter mx.
The surface potential expression automatically includes the
pinchoff behavior in the saturation region. However, as the
channel length is reduced, in reality, saturation voltage is
smaller than pinchoff voltage because of carrier velocity satura-
tion. Therefore, for the calculation of surface potential ψsL , the
difference in saturation voltage can be taken into account by the
effective drain voltage Vdse . The smooth transition from ohmic
to saturation region can be modeled by the following smoothing
function [20]:
 1/DX
Vdse = VDS / 1 + [VDS /(ζVGB )]DX (32)
where parameter DX controls the transition from VDS to
saturation voltage, and here, ζ is an adjustable parameter
which has a channel length L dependence and reduces with
deceasing L [20].
IV. R ESULTS AND D ISCUSSION
The comparison of the proposed solution of ψs and ψ0 with
the numerical results of (1)–(5) is presented in Fig. 3 from
subthreshold to the strong inversion region. Parameters used in
simulation are listed in Table I. This plot highlights the good
agreement between the proposed calculation and the numerical
results. In subthreshold region, ψ0 closely follows ψs and both
of them vary linearly with the gate voltage. On other hand,
in the strong inversion region, ψs and ψ0 become saturated
gradually. Moreover, it can be clearly seen from Fig. 3 that ψs
can be approximately determined by (7) in subthreshold region
and by (8) in the strong inversion region, respectively. Com-
pared to those of single-gate TFTs of tpoly larger than 100 nm,
surface potential of DG poly-Si TFTs rises much more sharply
in subthreshold region due to the control of two gates.
As shown in Fig. 4, the poly-Si film thickness has signif-
icant effect on the surface potential in subthreshold region
particularly for thin-film devices, and ψs increases as the film
thickness decreases. While in strong inversion region, the film
thickness has little effect on the surface potential.
2612
Fig. 4. Variation of both ψs and ψ0 with VG calculated for tpoly of 20 nm
and 60 nm. Our model: lines; numerical results: markers. Parameters used in
simulation are listed in Table I except for tpoly .
Fig. 5. Variation of both ψs and ψ0 with VG calculated for gc1 = 2 ×
1018 eV−1 · cm−3 and gc1 = 2 × 1019 eV−1 · cm−3 . Our model: lines;
numerical results: markers. Parameters used in simulation but tpoly and gc1
are the same as Figs. 3 and 4.
It can be observed from Fig. 5 that, as an increase of gc1 , the
surface potential rises much less sharply in subthreshold region
with the curves stretching out, and the band bending of poly-Si
TFTs needs larger gate biases to reach the condition of strong
inversion, attributed to the higher density of trap states. This
prediction is consistent with the observation [21].
The results of (21) as a function of VG for different φn are
shown in Fig. 6. It is clear that it might be preferable to use (21)
to calculate the surface potential. As one can see from Fig. 3
to Fig. 6, a good agreement is achieved between the proposed
solution and numerical results.
To validate the model, drain current modeling is confronted
to MEDICI simulations. The following parameters are chosen
for MEDICI simulation in Fig. 7: tOX = 100 nm, gc1 = 2 ×
1018 cm−3 eV−1 , E1 = 0.161 eV, and L = 10 μm. In simula-
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
Fig. 6. Comparison between solution of (21) and numerical results of (1)–(5)
for different channel potentials. Parameters used in simulation are listed in
Table I except for φn .
tion, mobility is 300 cm2 V−1 s−1 (setting as a constant). The
parameters used for the proposed model are: mx = 0.4, η = 4,
and Vdse = 1 V. Other parameters are listed in Table I. Fig. 7
depicts the simulated long-channel drain current as a function
of gate voltage. It is observed in this figure that our model is
fairly good in predicting the results of 2-D numerical results,
but for weak conduction, the model exhibits small errors. When
examining the subthreshold and strong inversion currents sep-
arately, Fig. 7(a) illustrates their relative importance. Clearly,
the total currents for the above and below threshold operations
can be approximated by Isub and Ia , respectively. Fig. 7(b)
shows simulation results with various film thicknesses. The
poly-Si film thicknesses used were 40, 60, and 80 nm. A steeper
subthreshold region is observed for the TFT with 40-nm film,
whereas the curve stretches out for devices with 80-nm film.
This prediction is consistent with the observation in surface
potential calculation of different tpoly .
Furthermore, to support the proposed current model and to
stress its practicality, we compare our model with available
experimental data on DG poly-Si TFTs. The parameters used
in simulation are given in Table II. The first validation is shown
in Fig. 8(a) and (b). Fig. 8(a) depicts a plot of the modeled drain
current versus VG both in logarithmic and linear scale. We can
see from the figures that the new model is fairly good in pre-
dicting the drain current of the devices. The second validation is
achieved by comparing our model with experimental data [1] in
Fig. 9(a) and (b). When biased in subthreshold region, the DIBL
effect is much more pronounced in poly-Si TFTs associated
with grain barrier height decreasing with the drain voltage and
leading to an increase of drain current [17]. In Fig. 9(a), the
DIBL effect is properly modeled. In addition, the kink effect
is more noticeable in high drain biases and high-trap-density
devices [17]. As shown in Fig. 9(b), due to the higher drain
voltages and trap density than that in Fig. 8(b), kink effect has
a strong impact on Ids –VDS characteristics. In Figs. 8 and 9, it
can be clearly seen that our drain current model is valid.
HUANG et al.: COMPACT MODEL FOR UNDOPED SYMMETRIC DOUBLE-GATE POLYSILICON THIN-FILM TRANSISTORS 2613

TABLE II
PARAMETERS FOR SIMULATIONS

Fig. 7. Ids versus VG –Vfb curves calculated from the model and the 2-D
numerical iterations. (a) The poly-Si film thickness is 60 nm, and the results of
Isub from (25) and Ia from (26), are also shown. (b) Transfer characteristics
with various film thicknesses.

V. C ONCLUSION
In this paper, a compact and continuous analytical drain
current model was developed for a symmetric undoped or
lightly doped DG poly-Si TFTs. An accurate calculation of
surface potentials and potentials at the center of poly-Si layer
is done, and the accuracy of the calculation has been verified
by the thorough comparisons with numerical iterative results
under different conditions. Based on the approximation of
surface potentials, we have adapted DG MOSFET possibilities
to develop a compact drain current model suitable for circuit
simulator for DG poly-Si TFTs. Unique behaviors of surface
potential, mobility, and kink effect have been taken into account
in the current model. The long-channel I–V curves constructed
by our model are in complete agreement with the 2-D numerical
results with a minimum number of fitting parameters. Com-
pared with experimental data, the drain current characteristics Fig. 8. Comparison of drain current between model results and experimental
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The authors would like to thank Prof. Z. Chen of the De- Mar. 2008.
partment of Electronic Engineering, Jinan University, for his
valuable discussions and suggestions.

R EFERENCES
[1] S. Zhang, R. Han, J. K. O. Sin, and M. Chan, “A novel self-aligned
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[3] Y. Taur, X. Liang, W. Wang, and H. Liu, “A continuous, analytic drain- Junkai Huang received the B.S. degree in applied
current model for DG MOSFETs,” IEEE Electron Device Lett., vol. 25, physics and the M.S. degree in semiconductor device
no. 2, pp. 107–109, Feb. 2004. from Jinan University, Guangzhou, China, in 1985
[4] A. Ortiz-Conde, F. J. García-Sánchez, and J. Muci, “Rigorous analytic so- and 1990, respectively.
lution for the drain current of undoped symmetric dual-gate MOSFETs,” He is presently with the Institute of Microelectron-
Solid State Electron., vol. 49, no. 4, pp. 640–647, Apr. 2005. ics, South China University of Technology, China.
[5] A. Ortiz-Conde, F. J. García-Sánchez, J. Muci, S. Malobabic, and He is also a Professor in Jinan University, China,
J. J. Liou, “A review of core compact models for undoped double-gate where he is currently the Vice Dean of College of
SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 131– Information Science and Technology, and the Direc-
140, Jan. 2007. tor of Department of Electronic Engineering. He has
[6] A. Sehgal, T. Mangla, S. Chopra, M. Gupta, and R. S. Gupta, “Physics over 50 scientific publications. His principle research
based threshold voltage extraction and simulation for poly-crystalline thin interests are thin-film transistors modeling, simulation, and ICs design.
HUANG et al.: COMPACT MODEL FOR UNDOPED SYMMETRIC DOUBLE-GATE POLYSILICON THIN-FILM TRANSISTORS 2615

Wanling Deng received the B.S. and Ph.D. degrees
in electrical engineering from South China Univer-
sity of Technology, Guangzhou, China, in 2003 and
2008, respectively.
Since 2008, she has been working at the Depart-
ment of Electronic Engineering, Jinan University, as
a Faculty Member. Her research interests are poly-Si
TFTs devices and physics, particularly poly-Si TFTs
modeling.
Xiaozhou Jiang received the B.S. degree in micro-
electronics from Xiamen University, Xiamen, China,
in 2007. She is currently working toward the M.S.
degree in the Department of Electronic Engineering,
Jinan University, Guangzhou, China.
She is currently engaged in the numerical simula-
tion of poly-Si TFTs.

Xueren Zheng was born in Guangdong, China, in

1946. He received the B.S. degree in semiconductor
specialty from South China University of Technol-
ogy (SCUT), Guangzhou, China, in 1969.
From 1986 to 1987, he was a Senior Research
Assistant with the University of Hong Kong, Hong
Kong, where he was involved in the characteristics
and reliability of MOSFET S and thermally nitrided
thin oxides. Since 1998, he has been a Professor
with the School of Electronic and Information En-
gineering, SCUT. He is currently the Director of the
Institute of Microelectronics, SCUT. He has published more than 80 technical
papers. His current research interests include MOSTFTs modeling and IC
design.