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our review and analysis to bulk devices, thus excluding silicon- II. D EVICE AND P ROCESS
on-insulator implementations [42]–[46]. A RCHITECTURE C ONSIDERATIONS
A conventional symmetric long-channel transistor is shut off
An asymmetric MOSFET can be generally described as a
over the entire length of its uniformly doped channel at gate
planar MOSFET having the following: 1) a laterally nonuni-
biases below the threshold voltage. At a closer analysis, the
form body profile (channel asymmetry) with or without
current flow in the channel only needs to be interrupted at
2) different source and drain regions (source/drain asymmetry).
a single location between the source and drain for the drain
Laterally nonuniform body profiles are typically implemented
current to be turned off. This can be done by providing the
with halo implants on the source-side of the channel, while
necessary threshold doping at that location.
different source and drain regions are created with different
In a systematic 2-D computer simulation analysis of the
masked implants over the source and drain regions or their
laterally nonuniformly doped long-channel MOSFET,
extensions.
Stockinger et al. [24] varied the position of the maximum
Attempting to build MOSFETs with channel asymmetry at
channel doping between the source and drain (i.e., the position
the minimum printable gate length typically involves aligning
where the channel current is interrupted), demonstrating that
of one mask edge to a position around the middle of the
the best drive/leakage performance is obtained when the
polygate regions, which is already printed at the limits of the
maximum channel doping is near the source and calling that
lithography capability. Although this has been the most typical
transistor structure “the peak device.”
implementation in research/development efforts, applying it to
The situation is more subtle in short-channel devices where
manufacturing is not a trivial task.
the graded nature of the channel doping differentiates the
A more realistic approach to exploiting the advantages of
asymmetric transistors from their symmetric counterparts.
asymmetric MOSFETs is to implement them for the secondary
Lundstrom’s scattering theory of the short-channel MOSFET
bias voltage of a given CMOS process, which is typically
[47]–[49] can be used in the analysis, as later discussed.
referred to as dual voltage or dual gate oxide (DGO) CMOS
Several circuit applications have been reported [50]–[63].
[64], [65]. The secondary voltage capability is obtained with
Yet, many subtleties of internal operation, compact modeling,
a longer gate and a thicker gate oxide than those of the pri-
and optimal use have largely remained uncovered, which has
mary bias voltage. For example, in a scaled CMOS process
precluded their entering into the mainstream circuit design.
designed for a 1.2-V primary power supply voltage, having
This paper reviews the physics, technology, and modeling of
0.13-μm minimum gate length and ∼2-nm physical gate oxide
complementary asymmetric MOSFETs specifically integrated
thickness, the asymmetric MOSFETs would be implemented
for analog and mixed-signal applications, with new insights
with gate lengths of 0.25 μm or more and a gate oxide of
from a recent development of a manufacturing process.
∼6 nm, allowing a secondary bias voltage of 2.5 V or more.
A brief discussion of the available choices in devising an
Obviously, aligning the mask edges of the halo or source/
asymmetric MOSFET architecture in terms of device, process,
drain extension implants to positions around the middle of the
and power supply voltages in Section II leads to our preferred
gate is no longer a lithography challenge at gate lengths that are
empty well implementation, used for illustration throughout the
at least two times larger than the minimum printable values.
entire paper.
Another major architecture consideration is the choice of the
Section III presents a top-level review of the advantages and
type of the doping profile of the well in which transistors are
challenges of asymmetric MOSFETs, in comparison with their
built. Typically, the well profiles of symmetric DGO transistors
symmetric counterparts, intentionally keeping the discussion at
in a scaled CMOS process are made of a high-energy main well
a qualitative level.
that is subsequently filled with lower energy implants designed
The manufacturing of the asymmetric and symmetric
to fend off the channel punch-through (antipunch-through im-
MOSFETs in the aforementioned preferred architecture is out-
plant) and to insure the nominal threshold voltage of the process
lined in Section IV, followed by a discussion of the limits
(threshold adjust implant). For CMOS processes with gate
in boosting the drive capability of the asymmetric MOSFETs
lengths larger than 0.25 μm, the halo implants are not required,
in Section V. Section VI analyzes the device physics of the
so that the threshold voltage VT is roughly determined as
asymmetric transistors in greater depth, using a combination
of drift-diffusion TCAD and physical reasoning based on the VT = αQV T Adjust + βQAP T (1)
scattering theory of the short-channel MOSFETs.
Section VII is dedicated to the analysis, based on statistically where QV T Adjust and QAP T are the areal doses of the
validated silicon data, of the switching speed performance and threshold adjust and antipunch-through implants, respectively,
scaling, followed by a similar analysis of the small-signal and α and β are locally calibrated geometry- and energy-
speed in Section VIII. The variability, matching, and noise dependent coefficients measured in voltage/dose units. The
are discussed in Section IX. All these analyses are carried out contribution of the main well implant has been neglected in (1)
comparatively for asymmetric and symmetric MOSFETs. due to the typical retrograde nature of this implant in modern
The challenges of and solutions to the compact modeling of CMOS processes, which implies that little or no dopant from
the asymmetric transistors are briefly discussed in Section X. this well reaches within the depth of the depletion region under
Section XI describes the implementation of high-voltage the channel.
extended-drain transistors in our preferred architecture, illus- The simplest and most widely used way to convert a nonhalo
trating their cost and reliability advantages. symmetric MOSFET to an asymmetric, or graded-channel,
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs 2365
The aforementioned process architecture has been preferred A. Greatly Improved Hot-Carrier Reliability
in the process development used for illustration in this paper,
with the observation of a substantial increase of the channel With no halo at the drain side of the channel and with a
mobilities through diminished carrier-impurity scattering (next deeper lightly doped extension, the electric field in the drain
section). This architecture will be heretofore referred to as region, in normal operation, is lower than in a symmetric tran-
empty-well architecture for brevity.1 sistor. Therefore, at high drain voltages, the transistor operates
farther away from the avalanche breakdown condition at the
drain-well junction, hence with fewer hot carriers around the
III. S TRUCTURE AND F IRST-O RDER P HYSICAL surface.
M ODELING OF A SYMMETRIC MOSFETs The aforementioned improvement is substantial. For a
The basic device structure of an n-channel MOSFET with quantitative illustration, our typical 3-V/0.3-μm asymmetric
channel and source–drain asymmetry using the empty-well n-channel transistors built in empty-well architecture measure
architecture is described in Fig. 1. around 400 years extrapolated hot-carrier lifetimes for either
The channel asymmetry is created by using a halo implant VT or IDsat (drain saturation current) degradation. These
only on the source-side, while the source–drain asymmetry is lifetimes compare to 25 and 10 years in typical 3-V/0.4-μm
created by using a deep and lightly doped drain extension (deep symmetric transistors, for VT and IDsat , respectively, at the
LDD, or DLDD) and a conventional or more heavily doped same threshold voltage and voltage stressing conditions. The
source extension. Optionally, the n-channel transistors can be large reliability margin of the asymmetric transistors points to
isolated from the p-type substrate with a deep n well. The the possibility to use them at subminimum DGO gate lengths,
p-channel structure is perfectly complementary to its n-channel e.g., 0.25 instead of 0.3 μm, for improved speed performance,
counterpart except that it does not have, nor does it need, a deep as discussed later in Section VII.
well isolation.
In a first-order compact model representation, this transistor B. Increased Drain Saturation (“Drive”) Current
can be seen as a combination of a threshold transistor, Q1 ,
In long-channel devices, at a given gate voltage overdrive, the
representing the portion of the channel containing the graded
main-channel transistor of the two-transistor model, Q0 , having
channel implant, and a main-channel transistor, Q0 , represent-
a weakly doped channel, is in a stronger inversion condition
ing the rest of the channel, with the channels connected in
than the threshold transistor Q1 . Therefore, it contributes with a
smaller channel resistance to the total resistance of the channel
1 In sub-0.25-μm symmetric MOSFETs using halo implants, the threshold
in comparison with the situation when the entire channel is
adjust implant can be safely dropped [66], which actually improves the switch-
ing speed. The antipunch-through implant can be dropped too, but severe long- doped at the level required for setting the threshold voltage.
range reverse-short-channel effects make this option less attractive. Compared at the same gate voltage overdrive and drain voltage,
2366 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
Fig. 5. Simplified representation of the process architecture used in manufacturing transistors with channel and source–drain asymmetry in empty-well
architecture.
Fig. 9. Distribution of the electric potential and lateral electric field at the surface of an (a) symmetric and (b) asymmetric n-channel MOSFET built in the
empty-well architecture described in Section IV. Shaded areas indicate depletion regions. Notice the strong electron extracting field at the inside edge of the
source-channel depletion region of the asymmetric MOSFET.
our empty-well process using the TSuprem IV process simulator region, as expected in the absence of a halo doping there. A
[72] with coefficients calibrated to the actual profiles described strong electron extracting field is present at the channel edge
by corroborated spreading-resistance probe and secondary ion of the source-channel depletion region, which reduces back-
mass spectroscopy characterization. scattering of the electrons that have surmounted the potential
Fig. 9(a) and (b) represent the distribution of the electric barrier.
potential and longitudinal electric field at the surface, calcu- In view of the scattering theory, the source/source-
lated with the drift-diffusion equations using the Medici device extension/source-halo region can be seen as a near-ballistic
simulator [73] for VG = VT + 0.2 V and VD = 1.5 V, along transistor corresponding to the threshold transistor Q1 of the
with simplified 1-D representations of the device structure two-transistor compact model in Fig. 2. The function of a local
at the surface for the symmetric and asymmetric transistors, drain for this transistor is provided by the built-in field of
respectively. The source-channel portion of each device is the graded halo doping, which extracts the electrons over the
subdivided into Source (S), Source Extension (SE), and Source source-channel barrier. From there on, the extracted electrons
Halo (SH) regions of substantially different doping, in order are taken over by the conventional long-channel field-effect
to ease understanding of the field structure in terms of the mechanism of the main channel transistor Q0 in the two-
classical transistor theory. Similarly, the drain-channel portions transistor compact model.
are divided into Drain (D) and Drain Extension (DE) regions. In the aforementioned physical interpretation, it is important
At low current levels, the drift-diffusion simulations are to realize that the drive current of the asymmetric transistor is
believed to be fairly accurate, regardless of the drift-diffusion- limited by the carrier emission over the barrier and the scatter-
versus-scattering discussion, considering that the field is elec- ing phenomena taking place in transistor Q1 . In particular, the
trostatically determined by the doping structure and the applied magnitude of the built-in field in the source halo region, desir-
voltages. ably as high as possible, controls the channel backscattering (or
Starting with the simpler field situation of the symmetric reflection) coefficient r and ultimately the drive current of the
transistor [Fig. 9(a)], one can identify the essential features whole transistor.
of the field distribution. The two peaks of the longitudinal It is interesting to calculate the drain current of transistor
electric field, Ex , at the source end of the channel can be easily Q1 in the scattering-limited ballistic mode, with the reflection
associated with the n+ (Source)/n (Source Extension) high- coefficient of the electrons calculated as
low junction and the n (Source Extension)/p (Body) junction,
respectively. The same identification applies to the drain end of 1 − v vT
r= ≈ 0.18. (6)
the channel. 1 + v vT
Continuing with the asymmetric transistor [Fig. 9(b)], one
notices a third field peak at the source end of the channel, In the aforementioned equation, the average velocities v are
which is associated with the p+ (Source Halo)/p (Body) high- calculated by the drift-diffusion simulator from the local current
low junction. No additional feature is noticed in the drain densities, and vT is the thermal velocity in silicon, roughly
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs 2371
(0.25 μm) gate length transistors that are still hot-carrier reli- [36], [52]. This has been primarily associated with the increased
able, in our empty-well architecture (10 years threshold lifetime transconductance of the asymmetric transistors, as already
versus 400 years for the conventionally defined minimum gate stated in Section II.
length of 0.3 μm). The ring oscillators built with the conser- An improvement of up to 20% has also been reported,
vatively defined minimum-gate-length asymmetric transistors based on device simulations, for the maximum frequency of
switch 35% faster than those built with symmetric devices. The oscillation, fmax [36].
similar comparison using subminimum gate lengths (0.25 μm) In our empty-well implementation, the measured fT im-
asymmetric devices yields a 64% speed advantage. provement in asymmetric transistors is higher than in the
In this earlier comparison, the minimum gate lengths of the aforementioned estimations due to the additional advantages
symmetric n-channel MOSFETs are slightly larger than those of a reduced channel doping, which favors increased carrier
of the asymmetric ones, i.e., 0.4 μm versus 0.3 μm. This the mobilities and reduced gate capacitances. Fig. 12 compares
due to the hot-carrier lifetime requirements, as the symmetric the silicon results of the fT measurements for asymmetric and
transistors, having no halo implants, are built on more heavily symmetric transistors at the same gate overdrive voltage. One
doped wells (see Fig. 6). Hence, a speed comparison at the can observe that, for similar gate lengths, the cutoff frequency
same gate length is in order, which is done by the extrapolation of asymmetric transistors is substantially higher than that of
of the available ring oscillator results down to 0.3 μm gate their symmetric counterparts.
lengths using Taur’s scaling equation [68]. The input and output For a comparison at exactly the same gate length, we have
capacitances of the inverter stage, Cin and Cout are assumed chosen L = 0.4 μm. The maximum cutoff frequency fT max is
to be constant in the small range of gate lengths of interest. directly available at this gate length for the symmetric transistor.
The saturation current densities per unit width in each point of The corresponding value of fT max for the asymmetric transis-
the plot are obtained from 10-μm wide transistor test structures tors was interpolated on the trend line, between the available
available on the same die with the ring oscillator structure. gate lengths, as shown in the inset of Fig. 12.
This same-gate-length comparison is included in Table I and This same-gate-length comparison results in a 1.5 times
shown in Fig. 11, revealing a 24% switching speed advantage of higher fTmax of the asymmetric transistor. However, with their
inverter stages built with asymmetric transistors over symmetric large margin in hot-carrier reliability and drain–source leakage,
counterparts having the same gate lengths. Table I and the chart the asymmetric transistors can be built at substantially smaller
in Fig. 11 also include the ring oscillator data for the high- gate lengths than 0.4 μm and even than their nominal minimum
speed asymmetric MOSFETs built at subnominal gate lengths gate length of 0.3 μm. For example, at 0.25 μm gate lengths,
that still do not compromise the hot-carrier reliability. In this the asymmetric transistors are more than two times faster than
case, the speed improvement over the ring oscillator built with 0.4 μm symmetric counterparts, while still remaining compara-
symmetric transistors is 51%. ble in hot-carrier lifetime and drain–source leakage.
Even more important than the aforementioned is the compar-
ison at low currents in the subthreshold regime. From Fig. 12,
VIII. S MALL -S IGNAL S PEED P ERFORMANCE
one can observe a 3.5 times increased cutoff frequency at
The small-signal cutoff frequency of transistors with channel zero gate overdrive. This makes the asymmetric transistors
asymmetry has been analyzed in detail by device simulations particularly attractive in low-power high-frequency applica-
that estimate up to 36% improvement in comparison with tions, where they can compete with SiGe-base bipolar junction
symmetric transistors of otherwise similar construction [33], transistors designed for the same voltage range.
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs 2373
Fig. 15. Measured and modeled output characteristics of n- and p-channel Fig. 16. Normalized transconductance, gm . L versus VGS for 10-μm-wide
transistors with with L = 5 μm and W = 10 μm, at VB = 0 V. 3-V asymmetric transistors of short and long channels (L = 0.3 and 1 μm,
respectively) at VD = 0.1 V, VB = 0 V.
Fig. 19. (a) Cross-section of an n-channel high-voltage extended-drain MOSFET implemented in the conventional architecture with the electron flow and the
depletion region structure in forward conduction at high drain voltage. Drain breakdown occurs near the surface (simulation-based line drawing). (b) Cross-section
of an n-channel high-voltage extended-drain MOSFET implemented in the empty-well architecture (XD-MOSFET) with the electron flow and the field structure
in forward conduction at high drain voltage. Drain breakdown occurs in the bulk of the silicon structure, where the doping concentrations are at or near peak
values (simulation-based line drawing).
XII. C ONCLUSION
The physics, technology, and modeling of complementary
asymmetric MOSFETs have been reviewed, covering both the
advantages (primarily switching speed, high-frequency behav-
ior, voltage gain, and reliability) and the problems (primarily
variability and noise) of this type of transistors, with the con-
clusion that both asymmetric and symmetric devices need to be
offered in the same process for uncompromised circuit design.
The essential features of the asymmetric transistors have
been illustrated with statistically validated transistor data from
a recent manufacturing implementation, where the transistors
for the secondary power supply voltage (DGO transistors)
are offered in asymmetric and symmetric constructions. This
implementation uses empty wells, i.e., retrograde wells with no
Fig. 20. Experimental output I–V characteristics of n- and p-channel high- dopant fillers at surface and source-side-only halo implants for
voltage extended-drain MOSFET having balanced threshold voltages at |VT | ≈ threshold voltage and punch-through control.
0.5 V, implemented in the empty-well architecture (XD-MOS). The availability of silicon and simulation data for asymmetric
and symmetric transistors built in the same process and having
n-well added under the structure to isolate the drain from the similar threshold voltages has allowed an in-depth comparison
substrate. of their operation leading to the observation of a DGIBL in
The output characteristics of experimental n- and p-channel asymmetric transistors. This effect contributes to the observed
XD-MOSFETs are shown in Fig. 20 for LW W = LOV = larger drain saturation current, at similar overdrive gate volt-
0.5 μm and L = 1.0 μm, where the distance between the source ages. It also increases the variability of asymmetric transistors
edge of the gate and the drain well, L, is conventionally defined and of transistors containing halo implants, in general.
as the channel length for both types of transistors. In addition, the GISL has been analyzed and shown to
Unlike the more common high-voltage extended-drain be a limiting factor to the degree of asymmetry that can be
MOSFETs, the characteristics of these transistors do not de- accepted in applications where the source and drain electrodes
pend, over the range of practical interest, on the gate over- change bias polarity and the body and source regions are not
lap parameter LOV . Their breakdown voltage is controlled permanently connected together.
by the well-to-well separation LW W , increasing as LW W is Compact modeling of asymmetric transistors has been briefly
increased. It eventually saturates at a limit value when the discussed and illustrated with compared model and silicon char-
intensification of the electric field associated with the proximity acteristics for output I–V characteristics, transconductance, out-
of the p-well vanishes and the breakdown moves up to the put conductance, maximum voltage gain, and gate capacitances.
surface. As a side benefit, the empty-well process architecture en-
The threshold voltages are fairly well balanced through the ables construction of complementary high voltage extended-
use of the same halo implants that control the threshold volt- drain MOSFETs for a third higher power supply voltage at
ages of the secondary-voltage (DGO) asymmetric MOSFETs. superior manufacturability and hot-carrier reliability compared
Further performance optimization can be obtained through to extended-drain transistors built with conventional (i.e., filled)
parameters L, LW W , and LOV . wells.
BULUCEA et al.: PHYSICS, TECHNOLOGY, AND MODELING OF COMPLEMENTARY ASYMMETRIC MOSFETs 2377
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pp. 1985–1991, Dec. 1986. DMOS transistors (1987–1990), and VLSI devices (1991 to present). In the
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Custom Integr. Circuits Conf., 1989, pp. 14.6.1–14.6.4. Technology Symposium and the Bipolar Circuits and Technology Meeting
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“Optimized 60-V lateral DMOS devices for VLSI applications,” in VLSI E LECTRON D EVICES L ETTERS. He is an honorary member of the Romanian
Symp. Tech. Dig., 1991, pp. 115–116. Academy.
2380 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010
Sandeep R. Bahl (S’84–M’93–SM’99) received the Tikno Harjono received the B.S. and M.S. degrees
B.S. degree from Rensselaer Polytechnic Institute, in electrical engineering from Santa Clara Univer-
Troy, NY, in 1985, and the M.S. and Ph.D. degrees sity, Santa Clara, CA, in 1988 and 1990, respectively.
in electrical engineering from the Massachusetts He was a Research Intern at Xerox Palo Alto
Institute of Technology, Cambridge, in 1988 and Research Center, Palo Alto, CA, while he was work-
1993, respectively. ing toward the M.S. degree. In 1990, he joined the
From 1993 to 2005, he worked with Hewlett Device Modeling Group at Signetics/Philips Semi-
Packard and Agilent Technologies in Palo Alto, CA. conductors, Sunnyvale, CA. From 1996 to 1999, he
Since 2005, he has been with National Semiconduc- worked with Sipex Corporation, Milpitas, CA. In
tor Corporation, Santa Clara, CA. He made contri- 1999, he joined the Advanced Process Technology
butions to electronic and optical devices in III–V Development Group of National Semiconductor
materials and silicon. Among these, he conducted the research phase of the Corporation, Santa Clara, CA, as a Device Engineer.
InGaP HBT, which is now used in Agilent products, and codeveloped the next- Mr. Harjono is a member of Tau Beta Pi.
generation analog CMOS process at National Semiconductor Corporation. He
has authored or coauthored 32 journal articles and conference presentations
and holds 16 patents. His current interest is the development of energy-efficient
transistor technology for power applications.
Dr. Bahl was a recipient of the STAR awards at both Hewlett-Packard and
Agilent Technologies and received the Best Student Paper Award at the Indium
Phosphide and Related Materials Conference. He is a member of Tau Beta Pi
and Eta Kappa Nu and is an officer of the Santa Clara, CA chapter of the IEEE Vijay Krishnamurthy received the B.Tech. degree
Electron Devices Society. in electrical engineering from the Indian Institute
of Technology, Chennai, India, in 1997, and the
Ph.D. degree in electrical and computer engineer-
ing from Purdue University, West Lafayette, IN, in
William D. French was born in Northern Ireland,
in 1967. He received the B.Eng. and Ph.D. degrees 2002, where he worked on design and optimization
from the Department of Electrical and Electronic of large-area high-speed MSM photodetectors on
Engineering, Queen’s University of Belfast, Belfast, intermediate temperature grown GaAs.
Northern Ireland, in 1989 and 1993, respectively. His In 2000, he was with the IBM T.J. Watson Re-
Ph.D. thesis was on the 2-D simulation of silicon-on- search Center, Yorktown Heights, NY and worked on
insulator MOSFETs. noise characterization of photoreceivers for 10-GB
He was a Research Fellow in Queen’s University Ethernet applications. Since 2004, he has been with National Semiconductor
on high-speed silicon-on-insulator bipolar transistors Corporation, Santa Clara, CA. His current work and research interests include
before joining Silvaco International, Santa Clara, CA compact modeling of DMOS/HV-MOS devices for power switching appli-
in 1995 as an Applications Engineer for Technology cations and low-frequency noise characterization and modeling of advanced
CAD (TCAD). In 2004, he joined National Semiconductor Corporation, Santa CMOS devices.
Clara, as a TCAD Device Engineer and is currently the Manager of the TCAD Dr. Krishnamurthy was the recipient of the IEEE Lasers and Electro-Optics
group. He is responsible for the process and device simulations for all process Society Graduate Student Fellowship in November 2000.
development within National Semiconductor Corporation. His interests include
submicrometer CMOS process and device physics, LDMOS design, bipolar
device physics, and RF spiral inductor simulation and design.
Jeng-Jiun Yang (M’96) received the B.S. degree in chemistry from National
Taiwan University, Taipei, Taiwan, in 1978, and the Ph.D. degree in physical Jon Tao received the B.S. and M.S. degrees in elec-
chemistry from the University of California, Los Angeles, in 1984. trical engineering from Peking University, Beijing,
In 1982, she was a Guest Scientist at the Max Plank Institut für Quantenoptik, China, in 1984 and 1987, respectively, and the Ph.D.
Garching, Germany. Between 1984 and 1987, she held postdoctoral research degree in electrical engineering from the University
positions with the Department of Chemistry, Oregon State University, Corvallis, of California, Berkeley, in 1995.
and AT&T Bell Laboratories, Murray Hill, NJ. Since 1987, she has been From 1987 to 1990, he was an Assistant Professor
working with the IC industry of the Silicon Valley, CA, as a Professional with the Institute of Microelectronics, Peking Uni-
Contributor at Integrated Device Technology, Santa Jose, CA (1987–1997), versity. From 1995 to 2006, he worked for Siliconix,
Maxim Integrated Products, Sunnyvale, CA (1997), and National Semiconduc- Advanced Micro Devices, and RF Micro Devices in
tor Corporation, Santa Clara, CA (1997 to present). Her experience in the field the fields of process technology, process integration,
includes CMOS process development, device physics, device bench/electronic device reliability, RFCMOS, and passives modeling
characterization, and ESD/latch-up engineering. and characterization. Since 2006, he has been with National Semiconductor
Corporation, Santa Clara, CA. His area of interest is active and passive
devices physics, modeling, characterization, and spiral inductors in CMOS
Pascale Francis received the M.S.E.E. and Ph.D. technologies. He has published over 40 journal and conference papers, and is
degrees in electrical engineering from the Catholic the holder of several patents related to device physics and process technologies.
University of Louvain, Louvain-la-Neuve, Belgium,
in 1991 and 1996, respectively. Her doctoral research
was on gate-all-around SOI/CMOS device character-
ization and modeling in harsh environments, such as
high temperature and irradiation.
In 1996, she was the recipient of a fellowship from
the Japanese Association of University Women and
Courtney Parker (M’91) received the B.S. and M.S.
spent three months with the NEC Research Laborato-
degrees in electrical engineering from the University
ries, Tsukuba, Japan. She then joined National Semi-
of Maine, Orono, in 1989 and 1991, respectively, and
conductor Corporation, Santa Clara, CA, where she held various positions since
1996 in process and device characterization and modeling. She is currently a the M.B.A. degree from the University of Southern
Senior Engineering Manager in the Spice Modeling group. Her interests span Maine, Portland, in 2010.
multiple areas, such as deep submicrometer CMOS for analog applications, He is currently an Integration Engineer with the
high-frequency passive devices (inductors, transformers, varactors, etc.), high- Process Development Group of National Semicon-
voltage and high-power silicon LDMOS transistors, GaN HEMTs, etc. She ductor Corporation, Santa Clara, CA, with a focus on
authored or coauthored more than 20 publications in IEEE or international submicrometer CMOS and BiCMOS technologies.
journals and conferences.