Sie sind auf Seite 1von 10

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 5, MAY 2010

1265

The Electrothermal Large-Signal Model of Power MOS Transistors for SPICE

Janusz Zare˛bski, Senior Member, IEEE , and Krzysztof Gorecki´

, Senior Member, IEEE

Abstract —In this paper, the isothermal model of power MOS transistors offered by the producer of these devices and the elec- trothermal model of these devices proposed by the authors are pre- sented. The results of experimental verification of both the models are given as well.

Index Terms —Electrothermal effects, modeling, MOSFETs, simulation program with integrated circuit emphasis (SPICE).

I. INTRODUCTION

C URRENTLY, MOS transistors are commonly used in lin- ear and switched electronic circuits. The computer anal-

ysis of such circuits is of a great importance for engineers, because it allows investigating a lot of properties of such circuits without their fabrication. To obtain fully credible re- sults of the simulations, the device models, especially MOS- FETs models of proper accuracy and acceptable complexity, as well as computer tools accepting the form of these models are needed. To reduce the complexity of the device model, only the most important physical phenomena influencing its terminal charac- teristics and parameters have to be taken into account in the process of model formulating. One of the most important physical phenomenon that affects the power MOS transistor properties is self-heating, resulting from the conversion of electrical energy into heat, and thus leading, in the real cooling conditions, to the junction (inner) temperature rise above the ambient one. The power MOS tran- sistor characteristics determined in the self-heating conditions, such as the nonisothermal characteristics, can differ from the isothermal characteristics corresponding to the ideal cooling conditions [1]. To simulate the nonisothermal characteristics, the electrother- mal model (ETM) constituting a connection of the electrical model, the thermal model, and the dependence of the electrical power dissipated into the device on the terminal currents and voltages has to be used [1]. There are a lot of computer programs for electronic circuits analysis, e.g., SABER or APLAC and some kinds of simulation

Manuscript received May 28, 2009; revised September 24, 2009. Current version published May 7, 2010. This work was supported by the Polish Ministry of Science and Higher Education in 2007–2009 under Research Project N N510 3425 33. Recommended for publication by Associate Editor E. Santi. The authors are with the Department of Marine Electronics, Gdynia Mar- itime University, Gdynia 81-225, Poland (e-mail: zarebski@am.gdynia.pl; gorecki@am.gdynia.pl). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2009.2036850

program with integrated circuit emphasis (SPICE) programs, e.g., PSPICE, IS-SPICE, and HSPICE. The models of semicon- ductor devices—including power MOS transistors are available (built-in) in these programs. APLAC allows performing the elec- trothermal analysis, but the ETM of the power MOS transistor is not available in this program [2]. For a long time, SPICE has been a comfortable, commonly used tool for the analysis of electronic circuits. Unfortunately, SPICE built-in MOSFET models of various efficiency (levels) [3]–[7], formulated for low-power devices, are the isothermal models, which means that self-heating is not included in these models. Apart from this, a lot of isothermal macromodels made by MOSFETs producers can be found on their Websites [8]–[10]. On the other hand, electrothermal macromodels of the power MOSFETs are also available both in papers, e.g., [11] and [12] and on the Internet, e.g., [13] and [14]. These macromodels formulated for SABER or SPICE programs are of the hybrid or the global form [1], [15]. The hybrid macromodel consists of the isothermal built-in model and the additional added ele- ments, describing the changes of the device terminal currents and voltages due to self-heating. The electrothermal hybrid models of MOS transistors were proposed in [11], [12], [14], and [16]–[18]. These models are based on the Shichman– Hodges model [11], [18], the Dang model [14], [16], the EKV model [12], or the Berkeley short-channel IGFET model (BSIM) model [17]. In turn, the electrothermal global models are com- posed of controlled current or voltage sources and passive ele- ments, describing nonisothermal characteristics of the consid- ered device, e.g., [13] and [19]. Unfortunately, these ETMs are dedicated to low-power planar devices in the integrated circuits [11], [12], [14] or to one kind of unipolar devices— CoolMOS transistors [13]. In spite of great complexity of some macromodels, the impor- tant physical phenomena are not included, which results in the unacceptably great inaccuracy of the macromodels, e.g., [20] and [21]. The former ETMs of MOS transistors worked out by the authors are dc models [19], [22], [23]. In this paper, the new large-signal ETM of power MOS transistors, appropriate for both the dc and transient analy- sis of electronic circuits with this device by SPICE, is pre- sented. The accuracy of this model was confirmed by mea- surements of the selected vertical diffused MOS (VDMOS) and TrenchMOS transistors. The obtained results of the cal- culations and measurements were additionally compared with the calculation results performed with the use of the isother- mal model available on the device producer Websites [9],

[10].

0885-8993/$26.00 © 2010 IEEE

1266

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 5, MAY 2010

TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 5, MAY 2010 Fig. 1. Network representation of the

Fig. 1.

Network representation of the proposed model (ETM) of the power MOS transistor.

II. FORM OF THE ETM OF THE POWER MOS TRANSISTOR

Zare˛bski and Gorecki´ proposed the dc ETM of the power MOS transistor in [22]. This model is based on the modified Shichman–Hodges model. To formulate the ETM of the considered device, two kinds of dependences are necessary. They represent:

1 the electrical model along with the parameters depending on the junction temperature;

2 the thermal model describing the dependence of the junc- tion device temperature on the electrical power dissipated into the device. The network representation of the new ETM of MOS transis- tor is presented in Fig. 1. As seen, the electrical model contains the elements responsible for the dc characteristics shape and the device electrical inertia. In turn, the thermal model is of the form of the Cauer network [1], [24], [25], where the control current source G p th represents the thermal power dissipated in the device, as described by the formula

p th = i D v DS + i G v GS

(1)

where v GS and v DS denote the gate-source and the drain-source voltages, respectively, whereas i D and i G are the drain and the

gate currents, respectively. The elements R th and C th repre- sent the thermal resistance and the thermal capacitance of the considered device, respectively. The dc component of the drain current is a sum of the currents of the controlled current sources G 1 and G 2 , representing the ideal component of the channel current I dr and the subthreshold current I P , respectively. The channel current I dr is given by (2), as shown at the bottom of this page, where W and L denote the width and the length of the channel, respectively, V t is the threshold voltage, λ is the parameter of the output conductance, KP is the parameter of transconductance, and V GS and V DS are the gate-to-“inner” source voltage and the “inner” drain-to-“inner” source voltage, respectively. The “inner” potential is equal to the external one if the resistance of the proper part of the MOS transistor is equal to zero. As it results from (2), the dependence describing the I dr cur- rent is given by splines, whereas the efficiencies of the controlled generators existing in SPICE have to be described by means of a combination of the SPICE standard functions. Therefore, (2) has to be transformed into the form given by the composition of the standard functions accepted by SPICE. The circumstantial description of (2), by means of the function LIMIT—available

I dr =

0,

for V GS V t 0

W

2L KP (1 + λV DS ) V DS [2 (V GS V t ) V DS ] ,

W

2L KP (1 + λV DS )(V GS V t ) 2 ,

for V DS V

GS V t

for 0 < V GS V t < V

DS

(2)

´

ZARE˛BSKI AND G ORECKI: ELECTROTHERMAL LARGE-SIGNAL MODEL OF POWER MOS TRANSISTORS FOR SPICE

1267

in SPICE is given in [19]. As a result, the expression describing the current I dr of the form

I dr =

V

DS

W

2L KP (1 + λ |V DS |) LIMIT LIMIT (V GS , V

DS |

|V

GD )

V t , 0, |V DS | 2 (LIMIT (V GS , V

LIMIT (LIMIT (V GS , V GD , U max ) V t , 0, |V DS |)

GD , U max ) V t )

(3)

can be formulated. In (3), the maximum value of the LIMIT function U max =1 kV is arbitrarily used. In turn, the subthreshold current I p is given by the formula

I p = I P 0 T j

T 0 exp hT j Y [1 exp (10 |V DS |)] (4)

U

go

where

Y =

0,

exp V

for V GS < PHI

GS PHI

n p hT j

1,

exp V t PHI n p hT j

+ 1.5 1,

for PHI < V

GS < V t

for V GS > V t .

(5)

In (5), PHI is described by the dependence

PHI = PHI 0 (1 + a PHI (T j T 0 )) (6)

where I P 0 , n p , PHI 0 , and a PHI are the model parameters, whereas T 0 denotes the reference temperature. In the model, the threshold voltage and the parameter of transconductance depend on the junction temperature as follows:

(7)

V t =

V t0 (1 + a (T j T 0 ))

KP = KP 0

T 0 1.5

T j

(8)

where U go = 1.206 V for silicon, V t0 , KP 0 , and a are the tem- perature independent parameters. The current of the controlled current source G Db represents the current of the device body diode. This current is a sum of three components: the saturation current I S , the generation current I g , and the breakdown range current I BR , described by the following formulae:

I S = I 0

T j

T 0 1.5 exp hT j

U

go

(9)

I g = I G T T 0 exp

j

U go hT j

m

g

1 V

4

SD

VJ

2

+ 10 3 (10)

I BR = I Z exp V

SD U p (1 + a p (T j T 0 ))

NhT j

(11)

where I 0 , I Z , U p , a p , N, I G , VJ, and m g are the model parameters. In (11), the linear dependence of the breakdown voltage on the temperature is assumed.

The output currents of the controlled sources G RD , G RS , and G RDD , which model the series resistances of the drain, the source, and the body diode, respectively, are described by the following formulae:

G RD =

G RS =

G RDD =

v

RD

R D0 (1 + α RD (T j T 0 ))

v RS

R S0 (1 + α RS (T j T 0 ))

v RDD

R DD0 (1 + α RDD (T j T 0 ))

(12)

(13)

(14)

where v RD , v RS , and v RDD are the voltages on the current sources G RD , G RS , and G RDD , respectively, R D0 , R S0 , and

R DD0 denote the series resistances of the drain, the source, and the body diode, respectively, at the reference temperature T 0 and α RD , α RS , and α RDD are the temperature coefficients of the resistances changes. The resistance of the cutoff channel is modeled by the resis- tance R ds , whereas the leakage conductance of the body diode and the SiO 2 layer is modeled by the resistors R ds1 and R gs , respectively. The capacitances between the device terminals are described by the networks composed of parallelly connected controlled current source and the branch of the series connection of the two elements—the linear capacitor and the voltage source of the zero voltage. Therefore, the capacitance between the gate and the source C GS is modeled by the elements: C 1 , V CGS , and G CGS , the capacitance between the gate and the body C GB is modeled by the elements: C 3 , V CGB , and G CGB , the capacitance between the gate and the drain C GD is modeled by the elements: C 2 , V CGD , and G CGD , and the capacitance be- tween the drain and the source C DS is modeled by the elements:

C 4 , V CDS , and G CDS . The currents of the respective controlled current sources are expressed as the product of the current of the proper voltage source and the nonlinear capacitance situated between the considered pair of the terminals, decreased by the capacitance of the linear capacitor and finally divided by this capacitance. In the considered model, the device capacitances are de- scribed by the authors’ empirical dependences of the form (15)–(20), as shown at the bottom of the next page, where t OX is the thickness of the layer SiO 2 , C GDO is the gate– drain capacitance for the unit of the channel length, C GSO is the gate-source capacitance for the unit of the channel width, C GBO is the gate-body capacitance for the unit of the channel length, C DSO is the drain-body capacitance for the zero drain-body voltage, MJ is the parameter describ-

ing the doping profile of the drain-body junction, ε 0 is the permittivity of free space, ε OX is the relative permittivity of silicon dioxide, V GSmin , V GSmax , V GDmax , V GBmin , V GBmax , C G1 , C G2 , C B1 , and C B2 are the other model parameters. Equations (15)–(17) and (19) describing the capacitances of an MOS transistor are of the form that results from the modifica- tion of the Meyer model [5]. The (18) describes the capacitance of the body diode. The values of the model parameters are ob- tained empirically.

1268

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 5, MAY 2010

TABLE I

VALUES OF THE DC MODEL PARAMETERS OF THE TRANSISTORS MTD20N06V AND MTD15N06V

P ARAMETERS OF THE T RANSISTORS MTD20N06V AND MTD15N06V III. C ALCULATIONS AND M EASUREMENTS R

III. CALCULATIONS AND MEASUREMENTS RESULTS

The accuracy of the proposed model was estimated by com- parison of the results of the simulations by the proposed model and the measurements of both the dc characteristics and the dependences of capacitances on the proper voltages. These re- sults were also compared with the simulations results obtained by the literature macromodel [9], [10]. The high-voltage VD- MOS transistor IRF840 [26] and the low-voltage TrenchMOS transistor MTD20N06V [27] were chosen for investigations.

A. DC Characteristics

The values of the parameters describing the dc part of the electrical model are given in Tables I and II for the transistors MTD20N06V and MTD15N06V, and the transistor IRF840, re- spectively. These parameters values were obtained mainly from the measurements. The thermal resistance R th of the transistor MTD20N06V is equal to 5 K/W (TrenchMOS on the heat sink) and 83 K/W (TrenchMOS operating without the heat sink).

C GS =

C GD =

C GB =

C GS0 W,

if V

GS < V GS min + V DS

C GS0 W + C ox

3

C GS0 W + C ox

C GS0 W + C ox

4

C GD0 W,

(C G1 (V GS V DS ) + C G2 ) ,

4

,

if V

GS < V GS max + V

0.75 +

V

GS V

if V

if V GS min + V

DS < V

GS < V GS max + V DS

DS and V DS < 0

if V

(15)

DS 2 ,

DS

GS < V GS max + V

V GS max 2 ,

DS and V DS > 0

2V GS + V

GS < V GD max + V DS

C GD0 W + 1.3C ox 1

C GD0 W + 6C ox V GS V t ,

C GB0 L + C ox ,

1

C GB0 L+C ox

C GB0 L + C ox Min 0.5 V

 

C GB0 L + C ox 0.5 V

GS + V GD max V DS

V

GS < V t

2(V

GS + V GD max V

DS )

if V

GS > V t

if V GD max + V DS < V

(16)

if V GB < V GB min and V DS < (V GS + 1) 2 + 1

V DS (V GS + 1V ) 2 1V 1V

V

DS

2

,

2

+ 0.33

if V

GS <V GB min and V DS

> (V GS +1V ) 2 1V +1V

(17)

GS < V GB max

GS + 0.5V

V GB min

2

2V V

1.25V 2 , 1 ,

DS

V

2

DS +

if V GB min < V

GS + 0.5V

V GB min

2V V

+ 1.25V 2 ,

DS

+ 0.33

if V

GS > V GB max

2

DS

V

C DS = C DSO 1 + V

DS

VJ

MJ + I S T t

hT j

exp V

DS

hT j

+ C BDX

(18)

C BDX =


0,

if V GS > 0.4V

0.8C ox 1

V GS + 0.4V V

DS

)+0.4V 2 ,

2(V GS 0.4V V

DS

if V GS < 0.4V

(19)

C ox = ε 0 ε ox LW

t

OX

(20)

´

ZARE˛BSKI AND G ORECKI: ELECTROTHERMAL LARGE-SIGNAL MODEL OF POWER MOS TRANSISTORS FOR SPICE

1269

TABLE II

VALUES OF THE DC MODEL PARAMETERS OF THE TRANSISTOR IRF840

OF THE DC M ODEL P ARAMETERS OF THE T RANSISTOR IRF840 Fig. 2. Transfer characteristics
OF THE DC M ODEL P ARAMETERS OF THE T RANSISTOR IRF840 Fig. 2. Transfer characteristics

Fig. 2. Transfer characteristics of the transistor MTD20N06V operating with- out the heat sink.

the transistor MTD20N06V operating with- out the heat sink. Fig. 3. Output characteristics of the transistor

Fig. 3. Output characteristics of the transistor MTD30N06V operating without the heat sink.

The thermal resistance R th of the IRF840 transistor is equal to 4.5 K/W (VDMOS on the heat sink) and 50 K/W (VDMOS operating without the heat sink). The transfer characteristics i D (V GS ) and the output charac- teristics i D (V DS ) of the chosen transistors are considered. In these characteristics, the solid and dashed lines denote the sim- ulation results obtained with the use of the new ETM and the model from [9], and [10] LMOD, respectively, whereas the points (circles and squares) correspond to the measurements. The results of investigations shown in Figs. 2–6 correspond to the MTD20N06 V transistor operating without and with the heat sink, respectively. In Fig. 2, the curve denoted as R th = 0 was measured by the pulse method implemented in the measuring

measured by the pulse method implemented in the measuring Fig. 4. Output characteristics of the transistor

Fig. 4.

Output characteristics of the transistor MTD20N06V situated on the

heat sink.

of the transistor MTD20N06V situated on the heat sink. Fig. 5. Calculated and measured dependences of

Fig. 5. Calculated and measured dependences of the inside temperature on the voltage v DS of the transistor MTD20N06V situated on the heat sink.

S of the transistor MTD20N06V situated on the heat sink. Fig. 6. heat sink. Transfer characteristics

Fig. 6.

heat sink.

Transfer characteristics of the transistor MTD15N06V situated on the

1270

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 5, MAY 2010

TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 5, MAY 2010 Fig. 7. Output characteristics of the

Fig. 7.

Output characteristics of the transistor MTD15N06V situated on the heat sink.

set, described in [28]. Therefore, this curve corresponds to the ideal cooling conditions of the device. As seen from Fig. 2, due to self-heating, the section of the negative slope exists in each of the measured and calculated characteristics. The high value of the device thermal resistance caused that the maximum value of the drain current cannot exceed 400 mA, which secures the device operation inside its safe operation area (SOA). In turn, as it results from Fig. 3, at small values of the voltage v GS , the output characteristics are anticoincidential. It is worth mentioning that due to self-heating, the value of the drain current increases even a few times in reference to the analogous current value obtained from the isothermal analysis. The obtained (with the use of LMOD) characteristics i D (v DS ) in the considered range of changes of the voltage v GS practically covers the x- axis due to the fact that the underthreshold current in the model LMOD was omitted. One can easily observe from Fig. 4 that the output characteris- tics shapes obtained from the measurements and the electrother- mal analyses differ from the isothermal characteristics, mostly in the range of the voltage v GS , slightly exceeding the value of the transistor threshold voltage. On these characteristics, there exist electrothermal breakdown points, at which the differential output resistance changes its sign from positive to negative. In Fig. 5, the dependences of the device inner temperature on the voltage v DS calculated by the electrothermal device model and measured by the pyrometer PT-3S are compared. As seen, the electrothermal breakdown occurs at the device inner tem- perature equal to about 40 C. A violent increase of the device inner temperature T j in the electrothermal breakdown range can cause a failure in the investigated device. The transfer characteristics corresponding to two values of the drain-source voltage are shown in Fig. 6. As seen, due to self-heating, the characteristics are pushed to the left by about 3 mV/K. On the other hand, in the range of high values of the drain current, self-heating causes the nonisothermal character- istics to be deflected to the right. This results from an increase in the device series resistances while increasing the device inner temperature caused by self-heating and the changes of the device operating point from the saturation region to the nonsaturation one. Note that the isothermal characteristics calculated from the model LMOD at two values of the voltage v DS practically overlap.

two values of the voltage v D S practically overlap. Fig. 8. Output characteristics of the

Fig. 8. Output characteristics of the transistor IRF840 situated on the heat sink in the linear region.

The output characteristics of the transistor MTD15N06V placed on the heat sink are presented in Fig. 7. The influence of the device control voltage v GS on the considered characteristics is shown in detail in Fig. 7(a). It is seen that for the voltage v GS less than the device threshold voltage V t , the output character- istics are the ambiguous ones, which means that there exists a section on the characteristic of the negative slope. In turn, at the voltage v GS higher than the voltage V t , the output charac- teristics of the high positive slope are observed. The slope of these characteristics increases with an increase in the control voltage value. Note that unlike the nonisothermal characteris- tics obtained by ETM, the slope of the output characteristics calculated with the use of the model LMOD is equal to zero. In turn, Fig. 7(b) shows that the output characteristics cor- responding to the cutoff device channel (v GS = 0) depend on the temperature very strongly. As seen, the values of the drain current obtained from the ETM and the measurements are less even more than three orders of magnitude than the results from the model LMOD. Note that the ETM also includes an increase in the breakdown voltage of the body diode with an increase in the temperature, which is omitted in the model LMOD. The output characteristics in the nonsaturation (linear) range of the transistor IRF840 placed on the heat sink at two values of temperature are shown in Fig. 8. As seen, an increase in the ambient temperature causes an increase in the device ON resis- tance, which means that the linear characteristics corresponding

´

ZARE˛BSKI AND G ORECKI: ELECTROTHERMAL LARGE-SIGNAL MODEL OF POWER MOS TRANSISTORS FOR SPICE

1271

LARGE-SIGNAL MODEL OF POWER MOS TRANSISTORS FOR SPICE 1271 Fig. 9. Output characteristics of the transistor

Fig. 9.

Output characteristics of the transistor IRF840 in the reverse mode.

to the range of small values of the device-dissipated power (see the shading area on the considered characteristics) are pushed to the right. Additionally, self-heating causes the deviation of the considered characteristics from linearity. Note that the charac- teristics calculated by the model LMOD are linear in the whole considered range of the drain current. The output reverse characteristics of the transistor IRF840 placed on the heat sink and operating without it are presented in Fig. 9. As seen, the characteristics corresponding to the voltage V GS = 0 are of the shape of the p-n diode characteristics, but the characteristics of the transistor without the heat sink are displaced to the left, as compared to the characteristics of the transistor placed on the heat sink. In turn, at V GS = 5 V, the drain current is the sum of the channel current and the current flowing through the body diode. Comparing the slopes of the device output characteristics corresponding to the normal and the inverse mode, it is seen that the series resistances of the drain and the source of the considered transistor are much greater than the series resistance of the body diode. Fig. 10 illustrates the influence of the ambient temperature on the transfer characteristics of the transistor IRF840 in the low-current range. As seen, an increase in the ambient temper- ature causes the displacement of the considered characteristics to the left. In the range of low values of the voltage V GS , the channel leakage determines the value of the drain current. It is worth mentioning that the subthreshold current is the dominant component of the drain current up to 100 mA. Since in the model LMOD, the subthreshold voltage phenomenon is not in- cluded, the calculated characteristics with the use of this model differ from the measurements not only quantitatively, but also qualitatively.

B. Dynamic Characteristics

The dynamic properties of the power MOS transistors are de- termined by the capacitances placed between their terminals, the device gate charge waveform, and the device switching times. To estimate the accuracy of the dynamic properties of the pre- sented ETM, the proper characteristics of the transistor IRF840 were investigated.

characteristics of the transistor IRF840 were investigated. Fig. 10. Transfer characteristics of the transistor IRF840.

Fig. 10.

Transfer characteristics of the transistor IRF840.

Fig. 10. Transfer characteristics of the transistor IRF840. Fig. 11. Measurements sets for measuring of capacitances

Fig. 11. Measurements sets for measuring of capacitances (a) C iss and (b) C oss .

Two device capacitances—the input capacitance C iss and the output capacitance C oss were considered. These capacitances were measured in the measuring sets shown in Fig. 11. The voltage sources V GS and V DS assure the proper values of the device operating points, the sources of V 1sin and V 2sin excite the device by the harmonic signal of the frequency f g = 50 kHz and the amplitude V gs = V ds = 50 mV. The capacitors C G and C D assure the shorting for the alternating signal component, whereas the inductors L G and L D , open for the same component of the signal. The values of the considered capacitances are calculated from the simple dependences of the form

C iss =

C oss =

I g V gs 2πf g

I d V ds 2πf g

(21)

(22)

where I g and I d denote the amplitude of the alternating compo- nents of currents of the gate and the drain, respectively, whereas V gs and V ds are the amplitudes of the alternating components of the gate-source and drain-source voltages, respectively. The values of the ETM parameters describing the capaci- tances of the transistor IRF840 are given in Table III. In Figs. 12–15, the calculated and measured dependences of the device input (see Figs. 12 and 13) and output (see Figs. 14 and 15) capacitances on the voltages v DS and v GS are presented. As seen, the substantial qualitative and quantitative differ- ences between the results of the measurements and calculations with the use of the model LMOD are visible in the considered characteristics. On the other hand, the model ETM ensures a

1272

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 5, MAY 2010

TABLE III

VALUES OF THE DYNAMIC PARAMETERS OF THE TRANSISTOR IRF840

OF THE D YNAMIC P ARAMETERS OF THE T RANSISTOR IRF840 Fig. 12. Calculated and measured
OF THE D YNAMIC P ARAMETERS OF THE T RANSISTOR IRF840 Fig. 12. Calculated and measured

Fig. 12. Calculated and measured dependences of the input capacitance of the transistor IRF840 on the voltage v DS .

of the transistor IRF840 on the voltage v D S . Fig. 13. Calculated and measured

Fig. 13. Calculated and measured dependences of the input capacitance of the transistor IRF840 on the voltage v GS .

of the transistor IRF840 on the voltage v G S . Fig. 14. Calculated and measured

Fig. 14. Calculated and measured dependences of the output capacitance of the transistor IRF840 on the voltage v DS .

of the transistor IRF840 on the voltage v D S . Fig. 15. Calculated and measured

Fig. 15. Calculated and measured dependences of the output capacitance of the transistor IRF840 on the voltage v GS .

of the transistor IRF840 on the voltage v G S . Fig. 16. Calculated and measured

Fig. 16.

Calculated and measured gate charge curves of the transistor IRF840.

very good agreement between the calculations and measuring results. The transistor input capacitance is of the constant value for nonnegative values of the voltage V GS and the voltage V DS higher than a few volts. At V GS < 0, a decrease in the value of the capacitance C iss with an increase in the voltage v DS is observed. The minimum of the dependence C iss (v GS ) for the voltage V GS ≈ −0.5 V occurs. In turn, the device output capacitance is practically of the constant value for v GS < 0 (see Fig. 15), whereas the essential changes of this capacitance at v GS > 0 and v DS < 2 V (see Fig. 14) are observed. The gate charge is of a great importance in the device com- mutation. In Fig. 16, the calculated and measured curves of the gate charging of the transistor IRF840 at the gate current equal to 1 mA and different values of the drain currents are shown. As seen, the obtained characteristics are of the similar shape,

´

ZARE˛BSKI AND G ORECKI: ELECTROTHERMAL LARGE-SIGNAL MODEL OF POWER MOS TRANSISTORS FOR SPICE

1273

LARGE-SIGNAL MODEL OF POWER MOS TRANSISTORS FOR SPICE 1273 Fig. 17. Calculated and measured waveforms of

Fig. 17.

Calculated and measured waveforms of the terminal voltages of the transistor IRF840 operating in the switch network.

of the transistor IRF840 operating in the switch network. Fig. 18. on the peak-to-peak value of

Fig. 18.

on the peak-to-peak value of the supply voltage.

Calculated and measured dependences of the body-diode storage time

but qualitative differences are visible. From the model LMOD, the extortionate value of the rise time of the voltage v GS was obtained. In Fig. 17, the calculated and measured time dependences of the voltage v GS [see Fig. 17(a)] and the voltage v DS [see Fig. 17(b)] existing in the simple switch with the transistor IRF840 are shown. In the investigated network, the drain-supply voltage E D is equal to 21 V, the gate resistance R G = 100 Ω and the gate is excited by the pulse rectangular train voltage of the frequency 115 kHz and the pulse amplitude changing from 10 to 10 V (see picture in picture). As it is seen, the calculation results obtained by ETM fit well the measurements. The short pulses visible in the measured dependence v DS (t) result from the overvoltage on the parasitic inductances, omitted in the proposed model. The dependence of the body-diode storage time in the tran- sistor IRF840 on the peak-to-peak value of the device supply voltage at two ambient temperatures are presented in Fig. 18. The investigations were performed for the gate shorted with the source and the resistor 100 was in a series connection with the transistor. The considered circuit was supplied by the pulse rectangular train of the frequency 64 kHz. As seen, the storage time t S increases with an increase in the ambient temperature. The dependence t S (V rr ) possesses the local maximum. The values of the time t S obtained from the model ETM fit much better the calculations by the model LMOD, which differ from the measurements even more than

80%. The higher value of the storage time obtained from the model LMOD results from the uncorrected modeling of the device input capacitance. The value of this capacitance is too high, which is shown in Figs. 12 and 13.

IV. CONCLUSION

The authors’ ETM of the MOS power transistor has been pro- posed. The ETM was implemented to PSPICE version 9.0 as a subcircuit. The model was verified by means of the comparison of the measured and SPICE calculated characteristics. A good agreement between the ETM simulations and the experimental results is observed both for the dc and the dynamic characteris- tics. The important advantage of the model is its simple form, simple interpretation of the parameters, and simple method of their estimation. It was also proved that due to self-heating, the MOS transistor characteristics can change not only quantitatively, but also qual- itatively and the macromodel proposed by ON Semiconductor is of poor accuracy. The investigations performed for different kinds of transistors showed that the proposed ETM is the uni- versal one, ensuring the characteristics of great accuracy both for the low-voltage and high-voltage power MOS transistors. The presented results of the investigations show new (not known so far) features of power MOS transistors. Especially, they show a high value of the drain current determining the boundary between the saturation and the subthreshold ranges, the ambiguity of the output characteristics corresponding to the values of the control voltage v GS less than the value of the device threshold voltage, and the form of the dependence of the device input and output capacitances on the voltage at its terminals different from the known dependences corresponding to the planar low-power MOS transistors.

REFERENCES

[1] J. Zare˛bski, “Modelling, simulations and measurements of electrother- mal characteristics in semiconductor devices and electronic circuits,” (in Polish) presented at the Proceedings of the Gdynia Maritime Acad., Gdynia, 1996. [2] K. Gorecki´ and J. Zare˛bski, “Modelowanie nieizotermicznych charak- terystyk wybranych elementow´ połprzewodnikowych´ w programie APLAC,” (in Polish) Elektronizacja, Not-Sigma, no. 12, pp. 19–22, 2001. [3] H. Shichman and D. A. Hodges, “Modeling and simulation of insulated- gate field-effect transistor switching circuits,” IEEE J. Solid-State Cir- cuits, vol. SC-3, no. 3, pp. 285–289, Sep. 1968.

1274

[4] A. Vladimirescu and S. Lui, “The simulation of MOS integrated circuits using SPICE2,” Electron. Res. Laboratory, Univ. California, Berkeley, Memo. M80/7, Feb. 1980. [5] P. Antognetti and G. Massobrio, Semiconductor Device Modeling With SPICE. New York: McGraw-Hill, 1993.

[6]

B. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, “BSIM: Berkeley short-channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 558–566, Aug. 1987.

[7] M. Bucher, C. Lallement, C. Enz, F. Theodoloz, and F. Krummenacher (1997, Sep.). The EPFL–EKV MOSFET model equations for simu- lation technical report: Model version 2.6. Electon. Lab., Swiss Fed- eral Inst. Technol. (EPFL), Lausanne, Switzerland [Online]. Available:

http://legwww.epfl.ch/ekv/pdf/ekv_v262.pdf

[8] J. C. Bowers and H. A. Neinhaus, “SPICE2 computer models for

HEXFETs,” in HEXFET Power MOSFET Databook, Reprint, Interna- tional Rectifier Corporation #HDB-3, Application Note 954 A, 1993, pp. A153–A160. International Rectifier website. [Online]. Available: http://www.i-r.com

[9]

[10] MTD15N06V SPICE model. [Online]. Available: http://www.onsemi.

com/site/products/summary/04450,MTD15N06V,00.html#appsmodels

[11] E. Schurack, T. Latzel, and A. Gottwald, “SPICE-simulation of nonlinear

effects in filed-effect-transistors caused by thermal power feedback,” in Proc. IEEE ISCAS , Chicago, IL, 1993, vol. 2, pp. 1116–1119. [12] C. Lallement, F. Pecheux, and W. Grabinski, “High level description of thrmodynamical effects in the EKV 2.6 MOST model,” in Proc. 9th Int.

Conf. Mixed Des. Integr. Circuits Syst. (MIXDES) , Wrocław, 2002, pp. 45–

50.

[13] Pspice Libraries for CoolMOS Power Transistors. [Online]. Available:

http://www.infineon.com [14] A. Laprade, S. Pearson, S. Benczkowski, G. Dolny, and F. Wheatley, “A revised MOSFET model with dynamic temperature compensation,” Fairchild Semiconductor Corporation, South Portland, ME, Application Note 7533, 2003.

[15] J. Zare˛bski, “Tranzystory MOS mocy,” (in Polish ) Fundacja Rozwoju Akademii Morskiej w Gdyni, Gdynia, 2007.

[16]

FET subcircuit with associated thermal waveforms of the L 2 FET: A 5 volt gate drive power MOSFET,” in Proc. Power Electron. Intell. Motion Power Qual. Conf. (PCIM) , Vorspann, 2002, pp. 271–276. [17] C. C. Liu, E. T. Carlen, K. D. Wise, and C. H. Mastrangelo, “Simulation of electrothermal MOS circuits using Saber,” in Proc. Tech. Int. Conf. Model. Simul. Microsyst. , Santa Clara, 1998, pp. 239–244. [18] K. Gorecki´ and J. Zare˛bski, “Modeling nonisothermal characteristics of switch-mode voltage regulators,” IEEE Trans. Power Electron., vol. 23,

F. Giovanni, G. Bazzano, and A. Grimaldi, “A new PSPICE power MOS-

no. 4, pp. 1848–1858, Jul. 2008. [19] J. Zare˛bski, K. Gorecki,´ and D. Bisewski, “A new electrothermal model of the power MOSFET for SPICE,” in Proc. 11th Int. Conf. Mixed Des. Integr. Circuits Syst. (MIXDES), Szczecin, 2004, pp. 89–93.

[20]

J. Zare˛bski and K. Gorecki,´ “Modelling CoolMOS transistors in SPICE,”

Inst. Electr. Eng. Proc. Cicuits, Devices Syst., vol. 153, no. 1, pp. 46–52,

2006.

[21] K. Gorecki´ and J. Zare˛bski, “Modelling CoolMOSC3 transistor charac- teristics in SPICE,” Int. J. Num. Model. Electron. Netw., Devices Fields , vol. 23, no. 2, pp. 127–139, 2010.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 5, MAY 2010

[22] J. Zare˛bski and K. Gorecki,´ “Modelling TrenchMOSFETs in SPICE,” in Proc. 15th IEEE Int. Conf. Electron, Circuits Syst. (ICECS) , Malta, 2008, pp. 73–76. [23] J. Zare˛bski, “The compact d.c. electrothermal model of power MOSFET for SPICE,” Int. J. Num. Model. Electron. Netw., Devices Fields , vol. 23, no. 2, pp. 140–150, 2010. [24] P. E. Bagnoli, C. Casarosa, M. Ciampi, and E. Dallago, “Thermal resis- tance analysis by induced transient (TRAIT) method for power electronic devices thermal characterization. I. Fundamentals and theory,” IEEE Trans. Power Electron., vol. 13, no. 6, pp. 1208–1219, Nov. 1998. [25] V. Szekely, “A new evaluation method of thermal transient measurement results,” Microelectron. J., vol. 28, no. 3, pp. 277–292, 1997. [26] IRF840 – 8A, 500V, 0.850 Ohm, N-Channel Power MOSFET. Catalogue data, Fairchild Semiconductor, South Portland, ME, 2002.

[27] MTD20N06V TMOS V TM Power Field Effect Transistor DPAK for Sur- face Mount N–Channel Enhancement–Mode Silicon Gate. Technical data, Motorola Semiconductor, Hong Kong, 1996. [28] K. Gorecki´ and J. Zare˛bski, “Układ do automatycznego pomiaru nieizoter- micznych charakterystyk statycznych elementow´ połprzewodnikowych,”´ (in Polish ) Metrologia i Systemy Pomiarowe , vol. VII, no. 1, pp. 45–57,

2000.

Janusz Zare˛bski (M’05–SM’06) received the M.Sc. and Ph.D. degrees in elec- tronics from the Technical University of Gdansk,´ Gdansk,´ Poland, in 1978 and 1986, respectively, and the D.Sc. degree from the Institute of Electron Technol- ogy, Warsaw, Poland, in 1997. He is currently the Head of the Department of Marine Electronics, Gdynia Maritime University, Gdynia, Poland, where he has been a Full Professor since 2008. His research interests include areas of modeling, analysis, and measure- ments of semiconductor devices and electronic circuits, particularly including thermal effects.

Krzysztof Gorecki´ (M’05–SM’06) was born in Poland, in 1966. He received the M.Sc. and Ph.D. degrees in electronics from the Technical University of Gdansk,´ Gdansk,´ Poland, in 1990 and 1999, respectively and the D.Sc. degree from Technical University of Łod´ z,´ Lod´ z,´ Poland, in 2008. He is currently an Associate Professor with the Department of Marine Elec- tronics, Gdynia Maritime University, Gdynia, Poland. His research interests include areas of modeling, analysis, and measurements of semiconductor de- vices and electronic circuits, particularly including thermal effects.