Multigate device

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A multigate device or multiple gate field effect transistor(MuGFET) refers to a MOSFET

which incorporates more than one gate into a single device. The multiple gates may be controlled
by a single gate electrode, wherein the multiple gate surfaces act electrically a single gate, or by
independent gate electrodes. A multigate device employing independent gate electrodes is
sometimes called a Multiple Independent Gate Field Effect Transistor or MIGFET.
Multigate transistors are one of several strategies being developed by CMOS semiconductor
manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to
as extending Moore's Law.[1] Development efforts into multigate transistors have been reported
by AMD, Hitachi, IBM, Infineon, Intel, TSMC, Freescale, UC Berkeley and others and the ITRS
predicts that such devices will be the cornerstone of sub-32 nm technologies.[2] The primary
roadblock to widespread implementation is manufacturability, as both planar and non-planar
designs present significant challenges, especially with respect to lithography and patterning.
Other complementary strategies for device scaling include channel strain engineering, silicon-on-
insulator-based technologies, and high-k/metal gate materials.

[edit] Industry need

Planar transistors have been the core of integrated circuits for several decades, during which the
size of the individual transistors has steadily decreased. At the current pace of scaling, the
industry predicts that planar transistors will reach feasible limits of miniaturization by 2010,
concurrent with the widespread adoption of 32 nm technologies. At such sizes, planar transistors
are expected to suffer from undesirable short channel effect, especially "off-state" leakage
current, which increases the idle power required by the device.

In a multigate device, the channel is surrounded by several gates on multiple surfaces, allowing
more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced
current in the "on" state, also known as drive current. These advantages translate to lower power
consumption and enhanced device performance. Nonplanar devices are also more compact than
conventional planar transistors, enabling higher transistor density which translates to smaller
overall microelectronics.

[edit] Integration challenges

The primary challenges to integrating nonplanar multigate devices into conventional

semiconductor manufacturing processes include:

 Fabrication of a thin silicon "fin" tens of nanometers wide

 Fabrication of matched gates on multiple sides of the fin
[edit] Varieties
Dozens of multigate transistor variants may be found in the literature. In general, these variants
may be differentiated and classified in terms of architecture (planar vs. non-planar design) and
number of channels/gates (2, 3, or 4).

[edit] Planar double gate transistors

Planar double-gate transistors employ conventional planar (layer by layer) manufacturing

processes to create double-gate devices, avoiding more stringent lithography requirements
associated with non-planar, vertical transistor structures. In planar double-gate transistors the
channel is sandwiched between two independently fabricated gate/gate oxide stacks. The primary
challenge in fabricating such structures is achieving satisfactory self-alignment between the
upper and lower gates.[3]

[edit] Flexfet

Flexfet is a planar, independently-double-gated transistor with a damascene metal top gate

MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. This device
is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source
and drain extensions; non-epi raised source and drain regions; and gate-last flow. Flexfet is a true
double-gate transistor in that (1) both the top and bottom gates provide transistor operation, and
(2) the operation of the gates is coupled such that the top gate operation affects the bottom gate
operation and vice versa.[4] Flexfet was developed, and is manufactured, by American
Semiconductor, Inc.

[edit] FinFETs

A double-gate FinFET device.

The term FinFET was coined by University of California, Berkeley researchers (Profs.
Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor) to describe a nonplanar, double-gate
transistor built on an SOI substrate,[5] based on the earlier DELTA (single-gate) transistor design.
[6]
The distinguishing characteristic of the FinFET is that the conducting channel is wrapped
around a thin silicon "fin", which forms the body of the device. The dimensions of the fin
determine the effective channel length of the device.

In current usage the term FinFET has a less precise definition. Among microprocessor
manufacturers, AMD, IBM, and Motorola describe their double-gate development efforts as
FinFET development whereas Intel avoids using the term to describe their closely related tri-gate
[1] architecture. In the technical literature, FinFET is used somewhat generically to describe any
fin-based, multigate transistor architecture regardless of number of gates.

A 25-nm transistor operating on just 0.7 Volt was demonstrated in December 2002 by Taiwan
Semiconductor Manufacturing Company. The "Omega FinFET" design, named after the
similarity between the Greek letter "Omega" and the shape in which the gate wraps around the
source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and
0.88 ps for the P-type.

[edit] Tri-gate transistors (Intel)

Schematic view (L) and SEM view (R) of Intel tri-gate transistors

Tri-gate or 3-D are terms used by Intel Corporation to describe their nonplanar transistor
architecture planned for use in future microprocessor technologies. These transistors employ a
single gate stacked on top of two vertical gates allowing for essentially three times the surface
area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume
far less power than current transistors.

In the technical literature, the term tri-gate is sometimes used generically to denote any
multigate FET with three effective gates or channels.

[edit] Gate-all-around (GAA) FETs

Gate-all-around FETs are similar in concept to FinFETs except that the gate material surrounds
the channel region on all sides. Depending on design, gate-all-around FETs can have two or four
effective gates. Gate-all-around FETs have been successfully built around silicon nanowire.[7]

[edit] See also

 Tetrode transistor
 Pentode transistor