Full adder

module full_adder(cout,sum,a,b,cin);

input a,b,cin;

output sum,cout;

wire c1,c2;

half_adder HA1(c1,s,a,b);

half_adder HA2(c2,sum,s,cin);

assign cout=c1|c2;

endmodule

module half_adder(c,s,a,b);

input a,b;

output c,s;

assign s=a^b;

assign c=a&b;

endmodule

Full subtractor
module full_subtractor(bout,diff,a,b,bin);

input a,b,bin;

output diff,bout;

wire b1,b2;

half_adder HA1(b1,d,a,b);

half_adder HA2(b2,diff,d,bin);

assign bout=b1|b2;
endmodule

module half_subtractor(bo,d,a,b);

input a,b;

output bo,d;

wire anot;

not(anot,a);

assign d=a^b;

assign bo=anot&b;

endmodule

Jk flipflop
module jk_flipflop(j,k,clk,q,qnot);

input j,k,clk;

output q,qnot;

reg q;

assign qnot=~q;

always@(posedge clk)

case({j,k})

2'b00:q=q;

2'b01:q=1'b0;

2'b10:q=1'b1;

2'b11:q=~q;

endcase

endmodule

4:2 encoder
module encoder4_2(i,o);

input [7:0]i;

output[2:0]o;

or g1(o[2],i[4],i[5],i[6],i[7]);

or g2(o[1],i[2],i[3],i[6],i[7]);

or g3(o[0],i[1],i[5],i[3],i[7]);

endmodule

1:16 demux
module demux16(i,s3,s2,s1,s0,o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1,o0);

input i,s3,s2,s1,s0;

output o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1,o0;

wire s3bar,s2bar,s1bar,s0bar;

not n1(s3bar,s3);

not n2(s2bar,s2);

not n3(s1bar,s1);

not n3(s0bar,s0);

and a1(o0,s3bar,s2bar,s1bar,s0bar);

and a2(o1,s3bar,s2bar,s1bar,s0);

and a3(o2,s3bar,s2bar,s1,s0bar);

and a4(o3,s3bar,s2bar,s1,s0);

and a5(o4,s3bar,s2,s1bar,s0bar);

and a6(o5,s3bar,s2,s1bar,s0);

and a7(o6,s3bar,s2,s1,s0bar);

and a8(o7,s3bar,s2,s1,s0);

and a9(o8,s3,s2bar,s1bar,s0bar);

and a10(o9,s3,s2bar,s1bar,s0);

and a11(o10,s3,s2bar,s1,s0bar);
and a12(o11,s3,s2bar,s1,s0);

and a13(o12,s3,s2,s1bar,s0bar);

and a14(o13,s3,s2,s1bar,s0);

and a15(o14,s3,s2,s1,s0bar);

and a16(o15,s3,s2,s1,s0);

endmodule

Binary to gray
module binary_gray(b3,b2,b1,b0,g3,g2,g1,g0);

input b3,b2,b1,b0;

output g3,g2,g1,g0;

assign g3=b3;

assign g2=b2^b3;

assign g2=b1^b2;

assign g2=b0^b1;

endmodule

Exor using nand

module exor_using_nand(z,a,b);

input a,b;

output z;

wire w1,w2,w3;

nand n1(w1,a,b);

nand n2(w2,a,w1);

nand n3(w3,w1,b);

nand n4(z,w2,w3);

endmodule
T flipflop using dflipflop
module tflipflop(q,t,clk,rst);

input t,clk,rst;

output q;

wire dt;

assign dt=q^t;

dflipflop dff(q,dt,clk,rst);

endmodule

module dflipflop(q,d,clk,rst);

output q;

input d,clk,rst;

reg q;

always@(posedge clk or negedge rst)

begin

if(~rst)

q=1'b0;

else q=d;

end

endmodule

Xnor using nor

module xnor_using_nor(z,a,b);

input a,b;

output z;

wire w1,w2,w3;
nor n1(w1,a,b);

nor n2(w2,a,w1);

nor n3(w3,w1,b);

nor n4(z,w2,w3);

endmodule

4 bit universal shift register

module universal_shift_register(a,i,select,serial_right_in,serial_left_in,clr,clk);

input [3:0]i;

input [1:0]select;

input clr,clk;

input serial_right_in,serial_left_in,clr,clk;

output [3:0]a;

reg [3:0]a;

always @(posedge clk or negedge clr)

begin

if (~clr)

a=4'b0000;

else

case(select)

2'b00:a=a; //no change

2'b01:a={serial_right_in,a[3:1]}; //shift right

2'b10:a={a[2:0],serial_left_in}; //left shift

2'b11:a=i;
//parallel load input

endcase

end

endmodule
2:1 mux using three state buffer
module mux2_1(out,a,b,select);

input a,b,select;

output out;

tri out;

assign out=select?a:1'bz;

assign out=select?1'bz:b;

endmodule

4 bit pipelined parallel adder

module pipeline(x,y,clk,rst,out);

input [3:0]x;

input [3:0]y;

input clk;

input rst;

output [4:0]out;

wire Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15,Q16,Q17,Q18,Q19,Q20,Q21;

wire cin1,cout1,cout2,cout3,cout4;

assign cin1=0;

add a1(x[0],y[0],sum1,cin1,cout1);

DFF d1(sum1,clk,rst,Q1);

DFF d2(Q1,clk,rst,Q2);

DFF d3(Q2,clk,rst,Q3);

DFF d4(cout1,clk,rst,Q4);

DFF d5(x[1],clk,rst,Q5);
DFF d6(y[1],clk,rst,Q6);

add a2(Q5,Q6,sum2,Q4,cout2);

DFF d7(sum2,clk,rst,Q7);

DFF d8(Q7,clk,rst,Q8);

DFF d9(cout2,clk,rst,Q9);

DFF d10(x[2],clk,rst,Q10);

DFF d11(y[2],clk,rst,Q11);

DFF d12(Q10,clk,rst,Q12);

DFF d13(Q11,clk,rst,Q13);

add a3(Q10,Q11,sum3,Q9,cout3);

DFF d14(sum3,clk,rst,Q14);

DFF d15(cout3,clk,rst,Q15);

DFF d16(x[3],clk,rst,Q16);

DFF d17(y[3],clk,rst,Q17);

DFF d18(Q16,clk,rst,Q18);

DFF d19(Q17,clk,rst,Q19);

DFF d20(Q18,clk,rst,Q20);

DFF d21(Q19,clk,rst,Q21);

add a4(Q20,Q21,sum4,Q15,cout4);

assign out[0]=Q3;

assign out[1]=Q8;

assign out[2]=Q14;

assign out[3]=sum4;

assign out[4]=cout4;
 endmodule

module DFF(D,clk,rst,Q);

input D;

input clk;

input rst;

output reg Q;

always@(posedge clk or negedge rst)

begin

if(~rst)

Q=1'b0;

else

Q=D;

end

endmodule

module add(a, b, sum,cin,cout);

input a;

input b;

input cin;

output sum;

output cout;

wire c1;

assign sum=a^b^cin;

assign c1 = (a&b)|(a^b)&cin;

assign cout=c1;

endmodule
XOR using NAND GATE

.model qm1 pmos level=1

.model qm2 nmos level=1

v105

.subckt nand in1 in2 out1 1

m1 out1 in1 1 1 qm1

m2 out1 in2 1 1 qm1

m3 out1 in1 3 3 qm2

m4 3 in2 0 0 qm2

.ends nand

xnand1 a1 b1 c1 1 nand

xnand2 a1 c1 c2 1 nand

xnand3 c1 b1 c3 1 nand

xnand4 c2 c3 c4 1 nand

v1 a1 0 PULSE (0 5 0 1ms 1ms 7.5 15)

v2 b1 0 PULSE (0 5 0 1ms 1ms 5 10)

.tran 10ms 40s

.print tran v(c4) v(a1) v(b1)

XOR using NOR GATE

.model qm1 pmos level=1

.model qm2 nmos level=1

v105

.subckt nor in1 in2 out1 1

m1 2 in1 1 1 qm1

m2 out1 in2 2 2 qm1

m3 out1 in1 0 0 qm2

m4 out1 in2 0 0 qm2

.ends nor

xnor1 a1 a1 c1 1 nor

xnor2 b1 b1 c2 1 nor

xnor3 c1 b1 c3 1 nor

xnor4 a1 c2 c4 1 nor

xnor5 c3 c4 c5 1 nor

xnor6 c5 c5 c6 1 nor

v1 a1 0 PULSE (0 5 0 1ms 1ms 7.5 15)

v2 b1 0 PULSE (0 5 0 1ms 1ms 5 10)

.tran 10ms 40s

.print tran v(c6) v(a1) v(b1)

OPAMP DIFFERENTIATOR/INTEGRATOR

.subckt opamp 1 2 3

rin 1 2 2meg

rout 6 3 75

e1 4 0 1 2 100

r1 4 5 1meg

c1 5 0 3nf

eout 6 0 5 0 1

.ends opamp

v1 ia 0 PULSE (0 5 0 1ms 1ms 5 10)

ri1 ia i2 33k

rif i2 i3 330k

ci1 i2 i3 10uf

x1 i1 i2 i3 opamp

r2 i1 0 33k

r1 i3 b 1k

c2 b 2 10uf

rf 2 3 100k

c1 2 3 1pf

x2 0 2 3 opamp

.tran 1ms 40s

.print v(3) v(ia) v(i3)

.end