922 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 59, NO.

12, DECEMBER 2012

Low-Power Level Shifter for

Multi-Supply Voltage Designs
Marco Lanuzza, Member, IEEE, Pasquale Corsonello, Member, IEEE, and Stefania Perri, Senior Member, IEEE

Abstract—In this brief, a new low-power level shifter (LS) is

presented for robust logic voltage shifting from near/sub-threshold
to above-threshold domain. The new circuit combines the multi-
threshold CMOS technique along with novel topological modifi-
cations to guarantee a wide voltage conversion range with limited
static power and total energy consumption. When implemented in
a 90-nm technology process, the proposed design reliably converts
180-mV input signals into 1-V output signals, while maintaining
operational frequencies above 1-MHz, also taking into account
process-voltage-temperature variations. Post-layout simulation re-
sults demonstrate that the new LS reaches a propagation delay less
than 22 ns, a static power dissipation of only 6.4 nW, and a total
energy per transition of only 74 fJ for a 0.2-V 1-MHz input pulse.
Index Terms—Level shifter (LS), multi-supply voltage design,
Fig. 1. Conventional DCVS level converter.
sub-threshold operation, ultra-low power.

I. I NTRODUCTION the higher power supply domain [5]. The issue is particularly
compounded when the VDDL is lowered below the transistor’s

E NERGY efficiency is one of the most important issues to

address in today’s System-on-a-Chip designs. Among the
techniques known in the literature to reduce power consump-
tion, those based on power supply voltage reduction are con-
sidered very effective even though they can severely penalize
speed performances [1], [2].
An alternative approach, known as the multi-supply voltage
domain technique [3], consists of partitioning the design into
separate voltage domains (or voltage islands), each operating
at a proper power supply voltage level depending on its timing
requirements. Time-critical domains run at higher power supply
voltage (VDDH) to maximize the performance, whereas non-
critical sections work at lower power supply voltage (VDDL)
to improve power efficiency. For extremely low-power appli-
cations, the presence of sections of the system operating in a
sub-threshold regime is a valuable option [4].
A key challenge in the design of efficient multiple-supply
circuits is minimizing the cost of the level conversion between
different voltage domains while maintaining the overall robust-
ness of the design. To such a purpose, level shifter (LS) circuits
have to be used.
To down-convert from a higher voltage (within the oxide
breakdown limits) to a lower voltage domain, CMOS inverters
are usually adequate [4]. On the contrary, more complex LS
topologies are required to up-convert signals from the lower to
Manuscript received July 13, 2012; revised September 12, 2012; accepted
October 18, 2012. Date of publication December 24, 2012; date of current
version February 1, 2013. This brief was recommended by Associate Editor
M. Alioto.
Authors are with the Department of Electronics, Computer Science, and
Systems, University of Calabria, Arcavacata di Rende 87036, Italy (e-mail:
p.corsonello@unical.it).
Color versions of one or more of the figures in this brief are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2012.2231037
threshold voltage. In fact, in such a case, balancing the input
section driving capability of the LS with sections of the circuit
working at the VDDH voltage level requires proper design
techniques [4], [6]–[10].
This paper deals with a novel low-power LS designed to
convert near-threshold or sub-threshold voltages to above-
threshold voltage levels. When implemented with the 90-nm
ST Microelectronics CMOS technology, the new design suc-
cessfully converts input voltages as low as 0.18 V to the 1-V
nominal output voltage, with a delay of 21.8 ns and consuming
only 6.4 nW of static power for VDDL = 0.2 V.
The remainder of the paper is organized as follows. Section II
provides a brief review of existing LS circuits. The proposed
topology is then presented in Section III and Section IV dis-
cusses and evaluates obtained results. Finally, in Section V
conclusions are drawn.
II. R ELATED W ORKS
The traditional LS topology is the differential cascade volt-
age switch (DCVS) circuit, as shown in Fig. 1. It includes a
half-latch formed by two PMOS transistors (MP2 and MP3)
and a pair of NMOS devices controlled by the differential
low-voltage input signals A and AN. When the input voltage
A (AN) goes from low (high) to high (low), MN2 (MN3) is
turned on (off). As a consequence, the voltage at node NH
(NL) is pulled down, leading MP3 (MP2) to be turned on.
This occurs when NH (NL) voltage reaches VDDH-Vth,MP3
(VDDH-Vth,MP2 ). Once MP3 (MP2) is turned on, the node NL
(NH) starts to be charged, weakening MP2 (MP3). Thus, the
positive feedback accelerates the voltage level conversion. It
should be noted that the DCVS-LS behaves as a ratioed circuit
and there is a contention between MP2 (MP3) and MN2 (MN3)

1549-7747/$31.00 © 2012 IEEE

LANUZZA et al.: LOW-POWER LEVEL SHIFTER FOR MULTI-SUPPLY VOLTAGE DESIGNS
transistors. As a consequence, pull-up and pull-down strengths
need to be properly balanced to assure correct functionality.
This requirement is difficult to achieve in practice when input
signals have sub-threshold voltage levels [4].
Lütkemeier et al. estimated that a NMOS-to-PMOS ratio of
∼2400 is needed to design a fully functional DCVS-LS that
converts 200 mV input into 1-V output signals, using a 90-nm
CMOS process technology [10].
In order to address this issue, several solutions have been
proposed in recent years. In [6], an architecture using four
DCVS cascaded circuits is employed to convert voltages from
200 mV to 1.2 V. Unfortunately, each conversion stage uses
its own VDDH (i.e., 0.3, 0.4, 0.6, and 1.2 V), thus requiring
multiple power regulators to generate intermediate VDDHs.
This introduces large power penalties.
The LS proposed by Wooters et al. [7] uses only two stages:
the first one exploits a DCVS circuit with an always-on diode-
connected NMOS transistor at the top, whereas the second stage
is a traditional DCVS circuit for achieving rail to rail swing.
Such a strategy avoids intermediate power lines, but does not
allow high-speed performance to be achieved.
The solution presented by Chen et al. [4] reduces the drive
strength of the half-latch pull-up network within the conven-
tional DCVS structure through two PMOS current limiters.
This LS circuit can convert sub-threshold input signals with
reasonable pull-down transistors sizing, but, as its main draw-
back, it requires an always “on” reference path for the current
limiters, which leads to an increased static power dissipation,
particularly when the input signal voltage is raised in the above-
threshold voltage domain.
The possibility of exploiting a dynamic threshold MOS
(DTMOS) configuration [11] to implement the NMOS devices
of the conventional DCVS circuit was explored by Chavan et al.
[8]. The resulting LS topology uses pull-down devices that,
when turned on, exhibit improved drive strengths with respect
to the pull-up networks. Unfortunately, owing to individual
body connections needed for each transistor, this technique is
easily practicable only in SOI CMOS.
In [9], diode-connected and off-biased PMOS transistors are
used to limit the drive strength of the pull-up network. More-
over, the multi-threshold CMOS design technique is applied to
tradeoff speed and power consumption. However, owing to the
presence of the always off-biased PMOS transistors, such an
approach is not easily scalable, particularly in terms of both
static power and dynamic energy consumption [10].
The LS proposed in [10] is based on a current mirror circuit.
However, when the input voltage signal is high, the output
node of the current mirror floats, thus negatively impacting the
overall power consumption [12].
III. P ROPOSED LS
The proposed LS was designed using the commercial 90-nm
CMOS ST Microelectronics process technology. The latter pro-
vides the designer with low-voltage threshold (lvt), standard-
voltage threshold (svt), and high-voltage threshold (hvt)
transistors. As shown in Fig. 2, the novel circuit consists of an
input inverter, a main voltage conversion stage, and an output
inverting buffer.
923
Fig. 2. Novel level shifter design.
To provide fast differential low-voltage input signals, the
input inverter was created using lvt devices. To increase the
strength of the pull-down network of the main voltage conver-
sion stage, it was also designed by using lvt transistors.
The cross-bar current flowing through the nodes NH and NL
at the beginning of their high to low transition [13] could be
of concern. Thus, to reduce this effect, two lvt PMOS devices
(MP2 and MP3) are adopted.
MP4 and MP5 were chosen as hvt transistors. This helps in
weakening the pull-up networks of the main voltage conversion
stage, thus reducing contention at NH and NL nodes. This
choice also reduces the leakage current flowing through the
pull-up networks when they are turned off. Finally, to ensure
reliable voltage conversion, two diode-connected hvt PMOS
devices (MP6 and MP7) were placed between the pull-up logics
and the supply rail VDDH . These devices limit the pull-up
strength, but also lead to considerable reduced static power.
We now briefly describe the running of the proposed circuit
with particular attention to the differences between the new
architecture and the conventional DCVS one. A high to low
transition of the main input causes MP4 being turned on. Its
drain current brings the diode-connected MP6 device into the
saturation region. This creates a voltage drop (i.e., Vth,MP6 )
across MP6 terminals that produces a correspondent bulk-
source voltage drop on MP4. Due to the bulk effect, this
increases the MP4 threshold voltage. The reduced voltage level
(VDDH-Vth,MP6 ) on the source terminal of MP4 limits its VGS ,
thus further weakening the MP4 action. All the above effects
reduce the contention on the node NH, thus allowing faster
discharging to be achieved.
When MP4 is turned on, MP5 is consequently turned off.
In this case, the small leakage current flowing through MP5
is not enough to turn MP7 on. For this reason, MP5 results
power gated from the VDDH power rail, leading to a significant
reduction in its sub-threshold current. The diode-connected
MP7 device participates in minimizing the leakage current, also
by increasing the threshold voltage of MP5. In fact, MP7 causes
the source of transistor M5 to be at lower voltage than the bulk
node and thereby reduces the sub-threshold leakage current due
to the bulk effect.
924 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 59, NO. 12, DECEMBER 2012
TABLE I
T RANSISTORS S IZES
Fig. 3. Layout of the proposed LS.
The above-described strategy significantly differs from those
adopted in other LS designs that exploit diode-connected tran-
sistors [7].
Since MP6 limits the output range of the main conversion
stage to [0 V, VDDH − VTp ], an output inverter is connected
to node NH, to assure a rail-to-rail conversion. The pull-down
of such an inverter uses an svt device, whereas its pull-up is
designed by exploiting an hvt PMOS transistors stack, thus lim-
iting the leakage current flowing through the pull-up network of
the output inverter, when NH is high. Opposite and substantial
threshold voltage variations on MP6 and MP8-MP9 could, in
theory, cause the latter transistors to go in weak inversion,
thus increasing the static power dissipation. However, simu-
lations discussed in Section IV do not highlight this effect as
significant.
In Table I, the transistors’ sizes used in the design of the
proposed LS are reported. Transistors with a channel length
of 0.20 μm (twice the minimum allowed channel length) were
used in the main voltage conversion stage and the output-
inverting buffer, to reduce sub-threshold leakage currents. On
the contrary, since the leakage current is a minor issue for the
input inverter, it has been made with minimum channel length
devices, thus enhancing speed.
It is worth noting that the right branch of the main voltage
conversion stage is downsized with respect to the left one
because of the reduced load on the node NL.
Fig. 3 illustrates the physical design of the proposed
LS. It exploits the double-cell-height layout strategy de-
Fig. 4. PVT analysis of the propagation delay (in log scale) versus VDDL.
scribed in [14]. Power supplies are available through the top
and the bottom metal-1 rails, while a shared ground rail travels
at the center of the cell. The width of the ground rail is twice the
width of the other rails in order to have consistent abutment with
neighboring single-height standard cells. Note that the use of
the double-height layout strategy allows well-sharing between
PMOS transistors driven by the same power supply in different
standard-cell rows, thus leading to more compact system lay-
outs [14]. Signals routing have been realized using only metal
layers 1 and 2, thereby keeping the other metal layers available
for interconnections on higher abstraction levels. The obtained
layout dimensions are 4.5 μm × 8.1 μm.
IV. R ESULTS AND D ISCUSSIONS
The Cadence Spectre tool was employed for the post-layout
analysis. Simulations for three process-voltage-temperature
(PVT) corners were performed considering the input signal
frequency of 1 MHz, input signal rise- and fall-times of 10 ns,
and 100 fF of capacitive load.
The typical case corner involves typical-NMOS and PMOS
transistors, a 1-V high supply voltage, and a temperature of
25 ◦ C. The worst case (WC) corner was determined consid-
ering that, in a sub-threshold running condition, the weakly
driven pull-down NMOS transistors have to overpower the
corresponding pull-up PMOS devices. Thus, the slow-NMOS
fast-PMOS are used in this case together with an increased
VDDH (1.1 V) that further worsens the contention between
pull-up and pull-down at nodes NH and NL. Moreover, a
temperature of −25 ◦ C was considered, which implies weaker
transistor operation in the sub-threshold region. Finally, for
the best case condition fast-NMOS, slow-PMOS, VDDH =
0.9 V and a temperature of 125 ◦ C was assumed. Obtained
simulation results are shown in Fig. 4. The novel circuit op-
erates correctly for VDDL as low as 0.18 V for all PVT
corners. When VDDL ≤ 0.35 V (i.e., the sub-threshold region
is reached for the chosen technology process), the propagation
delay exponential increases. However, the running frequency of
the proposed circuit is always maintained above 1 MHz.
Fig. 5 shows the plot of the operating frequency as a function
of VDDL. It is interesting to note that it increases exponentially
with VDDL in the deep sub-threshold region because, in such
operating conditions, the strength of the pull-down transistors
MN2 and MN3 exponentially depends on VDDL. Then, after
LANUZZA et al.: LOW-POWER LEVEL SHIFTER FOR MULTI-SUPPLY VOLTAGE DESIGNS
Fig. 5. Operating frequency versus VDDL at the typical PVT corner.
Fig. 6. Energy-per-transition (@ 1 MHZ) and static power versus VDDL at
the typical PVT corner.
a further but slower increment in the near-threshold zone, it
saturates toward 100 MHz. This happens because the balancing
between the pull-up and pull-down strengths is altered when
VDDL scaling requirements are low (a large voltage level
conversion is not required).
Fig. 6 illustrates the total energy dissipated per transition as
a function of VDDL, when an input signal with a frequency of
1 MHz is assumed. The static power consumption versus
VDDL is reported in the same figure.
The designed circuit shows a relatively wide flat energy
minimum (for the VDDL ranging from 200 to 400 mV). The
consumed energy significantly rises when VDDL = 180 mV
because short circuit effects become dominant. The static
power dissipation of the proposed circuit ranges from 6.3 nW
(@VDDL = 180 mV) to 11.5 nW (@VDDL = 0.75 V). These
results confirm the benefits brought by the static current limit-
ing design strategies used.
Fig. 7 reports results from a 10 000-run Monte Carlo (MC)
simulation performed considering both inter-die and intra-die
variations. The delay [Fig. 7(a)] and the static power dissipation
[Fig. 7(b)] are log-normally distributed, consistent with the sub-
threshold regime. With respect to the circuit described in [10],
the proposed LS shows a delay standard deviation 14.7% lower.
Fig. 8 shows 1000-iteration MC simulation results of the
minimum VDDL allowable for successful up-conversion to 1 V.
Three process corners and operating temperatures were con-
sidered: 1) fast-NMOS and slow-PMOS at 125 ◦ C, 2) typical-
NMOS and typical-PMOS at 25 ◦ C, and 3) slow-NMOS and
fast-PMOS at −25 ◦ C. Even under extreme process and temper-
ature variations, the designed circuit can support reliable level
conversion from the WC of 180 mV.
If necessary, the VDDL can be further lowered by increasing
the pull-down to pull-up strength ratio of the main voltage
conversion stage through proper devices sizing [4] or by using
925
Fig. 7. Monte Carlo simulation results@ VDDH = 1 V, VDDL = 200 mV,
and T = 25 ◦ C. (a) Delay distribution. (b) Static power distribution.
an additional input buffer power supplied at a voltage level
higher than that of the input signal [7].
The characteristics of the new LS are compared in Table II
with previously proposed designs. The LS proposed in [12] has
been realized using a 0.35-mm process. However, it exhibits a
quite low-power consumption. Unfortunately, this is obtained
at the expense of a very high propagation delay. On the con-
trary, thanks to the use of the DTMOS technique, the circuits
proposed by Chavan and MacDonald [8] exhibit considerable
speed, but they dissipate higher energy. The last four rows
of Table II reports data from circuits designed using a 90-nm
process, thus they can be directly compared. In particular, the
circuit discussed in [4] and implemented in a 90-nm technology
process by Lütkemeier et al. shows the highest delay and energy
per transitions.
Based on the results shown in [12], we decided to replicate
the current mirror-based circuit presented in [10] exploiting the
90-nm ST Microelectronics CMOS technology. For the sake of
fair comparison, the output buffer was designed as suggested
in the original paper [10] and the complete LS was simulated
in the same operating conditions as the proposed circuits. The
replicated [10]∗∗ shows the lowest delay and quite low energy
per transition. However, it is worth noting that, in both the
original paper [10] and our replication, layout effects are not
taken into account. Unfortunately, since the output node of the
current mirror floats when the input voltage signal is high, a
detrimental effect on sub-threshold leakage of the output buffer
occurs. This leads to a large static power dissipation of the
complete LS architecture (20.3 nW@ 0.2 V).
The proposed design, benefiting from specific sub-threshold
leakage-reduction design techniques, achieves static power as
low as 6.4 nW@ 0.2 V, an energy dissipated per transitions of
only 74 fJ for a 0.2-V 1-MHz input pulse, and a delay of 21.8 ns
(or 484 FO4). Furthermore, it requires only 36.5 μm2 of silicon
926 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 59, NO. 12, DECEMBER 2012
Fig. 8. Distribution of minimum VDDL for successful up-conversion to 1 V.
TABLE II
C OMPARATIVE R ESULTS
area, or 11 times the area of a minimum-sized standard cell
inverter in the chosen technology. Silicon areas required by [7]
and [12] are estimated to be 16 and 52 times the respective
inverter standard cell. Finally, the novel LS requires ≈16% less
active area than the solution proposed in [10].
V. C ONCLUSION
We have presented a new low-power LS suitable for
robust logic voltage shifting from near/sub-threshold to above-
threshold domain. The proposed circuit exploits proper de-
sign strategies to limit energy and static power consumption.
Thanks to these features, when used for sub-threshold to above-
threshold voltage conversion, the proposed design exhibits the
lowest static power and energy consumption with respect to
previously proposed LSs that use similar design parameters.
Moreover, even though the novel LS is optimized for low
power consumption, it also reaches high-speed performances
and supports a wide voltage conversion range.
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