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Structure: To use this pattern parameters are defined in a single location such
as the top level testbench module and then those parameter values are shared
between the design under test (DUT) and the UVM test which contains the
environment and the rest of the UVM testbench.
parameter GEN_PARITY = 0;
initial begin
run_test("test1");
end
endmodule
The green highlighted code is where the shared parameters are defined. The
yellow highlighted code is the instantiation of the DUT with the shared
parameters passed through. The blue highlighted code is first where the shared
parameters are passed to the uvm_test. Then the call to run_test() creates
an instance of the uvm_test with the correct parameter values set.
test_base_c;
"test1") type_id;
return type_id::get();
endfunction
return type_id::get();
endfunction
BUS_WIDTH, GEN_PARITY);
return type_name;
endfunction
...
endclass : test1
The code in blue is code that is added to the default expansion of the
`uvm_component_param_utils() macro. The “test1” string added to the
uvm_component_registry typedef is what registers this class with the
string based factory. The other additions are convenience code which is
included with when non-parameterized classes use the
`uvm_component_utils() factory registration macro.
Consequences: By using this pattern the full set of parameters that a design
requires can easily be shared with the testbench. This allows for easy
modification of those parameters to fully verify the entire parameter state
space of the design.
“Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the
Morning” from DVCon USA 2016
“Parameters and OVM — Can’t They Just Get Along?” from DVCon USA
2011