2011 24th Annual Conference on VLSI Design
A 1.8GHz Digital PLL in 65nm CMOS
Biman Chattopadhyay, Anant S Kamath, and Gopalkrishna Nayak
Analog Interfaces and Sub-systems
Texas Instruments India Pvt. Ltd.
Bangalore, India
Abstract-A 1.8GHz high-accuracy, ring-oscillator based Digital
Phase Lock Loop (DPLL), suitable for Serializer-Deserializer
(SERDES) applications like HDMI, eSATA and USB2.0 is
presented here. Sigma-Delta (ΣΔ) dithering followed by passive
filtering, along with Temperature Compensation is used to ensure
frequency accuracy and low accumulated jitter, over a large
temperature range. A re-circulating delay line based Time to
Digital Converter (T2D) is used to handle large phase differences
between the reference and feedback clocks. The DPLL is built in
65nm technology, and provides up to 1.8GHz output, with a phase
noise of –87dBc/Hz at 1 MHz offset, and a frequency accuracy of
+/-100ppm. It supports input frequencies in the range 0.7MHz to
50MHz, occupies a core area of 0.11 sq mm, and does not require
external components.
I. INTRODUCTION
Digital Phase Locked Loops (DPLLs) have become very
popular because they have several advantages over conventional
analog (Charge Pump) PLLs: scalability, digital bandwidth
control, faster relock times, and area saving and reference spur
elimination due to removal of the analog loop filter [1] [2] [3].
Though LC tank based DPLLs have been used extensively for
high precision applications such as RF and Serializer-
Deserializer (SERDES), ring-oscillator based DPLLs are more
popular for low precision applications, for example, as clock
source to a digital processor.
The frequency accuracy of LC DPLLs is usually improved
by ΣΔ dithering performed on a capacitor array that is part of
the LC tank [3]. The low sensitivity of the LC tank to
temperature variations, coupled with occasional re-calibration,
allows the ΣΔ capacitor array to have a small equivalent
frequency range, thus limiting the jitter produced due to ΣΔ
operation. LC tank based PLLs have a few disadvantages,
however. The low tuning range, coupled with errors involved in
inductor modeling implies that LC tanks are difficult to design.
Post-silicon trimming is often required. LC tanks pick up noise
(through magnetic coupling), leading to integration issues when
there are multiple PLLs operating at different frequencies, and
also on noisy Systems-on-Chip (SOCs). Most importantly,
inductors take up valuable silicon area, and require several
metal layers.
Despite the disadvantages, the use of LC tanks is imperative
for RF applications, where low close-in phase noise is a must.
For SERDES applications, however, close-in phase noise is
not critical. This is because low-frequency noise of both the
Transmitter (TX) and Receiver (RX) PLLs is tracked by the RX
Clock-Data-Recovery (CDR) loop by adjusting the RX
sampling clock. SERDES standards, therefore, specify a high-
1063-9667/11 $26.00 © 2011 IEEE
DOI 10.1109/VLSID.2011.32
pass-filter (HPF) mask: the TX integrated jitter is calculated
after applying the HPF mask on the TX output phase noise.
Fig.1. shows a typical SERDES link and the CDR HPF seen by
the TX and RX PLL phase noise. For High-Definition
Multimedia Interface (HDMI) and external-Serial-ATA
(eSATA) standards the HPF corner frequencies are at 4MHz
and 1.1MHz respectively. For USB2.0, the HPF is implicit: the
TX eye is specified over a 1us packet.
Fig.1. SERDES link and CDR HPF
From the above discussion, it is evident that using an LC
DPLL for SERDES applications is overkill. Ref [1] presented a
high-accuracy 480MHz Digital PLL based on a ring-oscillator
DCO. The present work proposes an optimum generic DPLL
architecture especially for SERDES applications, while also
extending the work done in [1] to present a 1.8GHz ring-
oscillator based SERDES DPLL. ΣΔ operation on a current
DAC, followed by a Current Controlled Oscillator (ICO),
provides frequency accuracy. Temperature compensation helps
reduce the range required by the ΣΔ DAC, allowing for passive
filtering of ΣΔ noise. As an improvement over previous work, a
re-circulating Time-to-Digital Converter (T2D) is used to
handle large phase differences at the Phase-Frequency-Detector
(PFD) input, without consuming proportionate chip area. The
loop parameters are designed keeping in mind typical SERDES
jitter requirements, while also providing the flexibility of a wide
range of input and output frequencies. The DPLL implemented
in 65nm CMOS technology, handles input frequency in the
range 0.7MHz to 50MHz, and provides an output frequency up
to 1.8GHz, with a phase noise of -87dBC/Hz at 1MHz offset.
The rest of the paper is organized as follows. Section II
discusses the typical requirements from a SERDES DPLL, and
proposes generic design choices based on them. Section III
extends the DPLL architecture to optimize power, area and
performance. Temperature compensation of the DCO and
passive filtering from [1] are briefly revisited, and a re-
circulating T2D architecture is presented. Implementation and
circuit details, with simulation and silicon results are described
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in section IV. Comparisons with the state of the art are
described in section V. Conclusions are presented in section VI.
II. DPLL FOR SERDES
As discussed in the previous section, in a SERDES
application only jitter at frequencies higher than the CDR
bandwidth is important. The phase noise curves of the RX and
TX DPLLs are both multiplied by the CDR HPF, before
integrating to calculate the contribution to the jitter budget. At
the same time, SERDES systems especially those built for
mobile phone applications need to support a range of input
frequencies, while providing a fine resolution on the output
frequency.
Fig.2. shows the block diagram of a typical DPLL. The
phase error detected by the Phase-Frequency Detector (PFD) is
converted into a digital code by the Time to Digital Converter
(T2D). The T2D output is processed by the Digital Loop Filter
(DLF). The output of the DLF is multiplied by a variable gain
KG before being used as the input code of the Digitally
Controlled Oscillator (DCO). KG is used for normalizing the
loop gain. The Feedback Divider (1/M) divides the DCO output
clock before feeding it back to the PFD. The additional dividers,
in the forward path (1/L), and the input path (1/N), help achieve
larger output and input frequency range. ΣΔ dithering is used on
the DCO to improve its frequency accuracy, and on the
Feedback Divider (1/M) to allow fine frequency steps at the
DPLL output. Passive Filtering (not shown in Fig. 2. but shown
later in Fig. 3.) removes the high frequency jitter caused by ΣΔ
action in the DCO. Further, for SERDES applications, we have
the following observations:
1. Ring Oscillator DCO: Since close-in noise is not critical
(filtered out by the CDR HPF), Ring Oscillator DCO can be
used and the complexity and cost of an LC tank can be avoided.
2. Low Reference Frequency and Loop Bandwidth: Since
close-in phase noise is not important, the DPLL bandwidth can
be kept very low (sub 100kHz). The input clock can be divided
down to low frequencies to be able to obtain the required
Frequency resolution at the output, if possible avoiding ΣΔ
dithering on the Loop divider. Even if ΣΔ dithering is used, the
low loop bandwidth can be used to knock off the reference
frequency spurs thus introduced. Unlike in analog PLLs, low
bandwidth in DPLLs does not cost a lot of extra area.
3. Passive filter after the ΣΔ in the DCO can be as low as a
few MHz reducing jitter caused by ΣΔ action. The DPLL loop
bandwidth being low, stability is not impacted.
4. Simple PFD+T2D: The low loop bandwidth filters out
most of the quantization noise introduced by the PFD+T2D.
Hence, a simple T2D, with the resolution of an inverter delay is
sufficient. That is schemes to obtain very low T2D resolution
are not required. However, the DPLL clock can have
considerable low frequency noise, and the T2D range needs to
be large (in several nanoseconds). On the other hand, the
higher jitter randomizes the quantization noise, so that it appears
white, and no spurs are produced. Direct TDC conversion (not
requiring PFD) for fractional division [3], and the associated
complexity, is not worth it since fractional division can be easily
obtained by ΣΔ action on the Feedback Divider, the latter being
almost jitter free, because of the low DPLL loop bandwidth.
Fig.2. DPLL Architecture
In short, the presence of the CDR loop in the SERDES link
can be exploited to simplify DPLL design.
III. DCO and T2D ARCHITECTURE
A. DCO and Temperature Compensation
The block diagram of the DCO is shown in Fig. 3. It
consists of a partitioned current mode DAC followed by a
current controlled ring oscillator (ICO). The Coarse DAC,
during a calibration at power-up, gets the DCO frequency close
to the required value, while the Fine (ΣΔ) DAC is used to
provide range while the DPLL is in lock. The Temperature
Compensation (TC) DAC applies occasional corrections for the
temperature variation in the ICO, allowing for a small Fine
DAC range. The Very Low Pass Filter (VLPF) ensures that the
TC DAC code changes do not translate to a large frequency
error at the DPLL output: the current output at the VLPF
changes very slowly so that the DPLL loop is able to track and
correct most of the resulting ICO frequency change. ΣΔ
dithering is used on the Fine DAC to obtain frequency accuracy.
The ΣΔ modulator runs off a divided down version of the DCO
output clock. A small Fine DAC range enables series passive
filtering after the Fine DAC that helps knock off most of the
high frequency noise caused by ΣΔ action. An improvement
over previous work is that the Coarse Code also controls the
current steps in the ΣΔ and TC DACs, keeping these a fixed
proportion of the Coarse DAC current. As the frequency in a
ring oscillator is roughly proportional to the controlling current,
this, more or less, keeps the ΣΔ and TC DAC frequency steps,
ranges, and associated frequency errors proportional to the
operating frequency of the DCO.
Fig.3.DCO block diagram

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B. PFD+T2D mirroring error. The transistor M1 acts like a level shifter and
The use of ring oscillators coupled with low DPLL is used for biasing convenience.
bandwidth, results in a high pk-pk jitter at the DPLL output and
hence at the PFD inputs. The PFD/T2D dynamic range
therefore needs to be large. An inverter chain with a large
number of elements is not area or implementation efficient. An
alternative is to use a re-circulating delay line as shown in Fig.
4. It consists of an n stage delay chain followed by a K-bit
counter. The delay chain consists of n-1 inverters followed by a
buffer. In the beginning alternate inverters are reset to ‘0’. An
OR pulse and an AND pulse are generated by the logic OR and
the logic AND of the UP and DOWN pulses output by the PFD.
On the rising edge of the OR pulse, the delay chain starts
toggling, causing the output OUTN to toggle once every N×Tr,
where Tr is the delay of one inverter. A counter counts the
Fig.5. Regulated Cascode and Bias Filter
number of times OUTN toggles. On the rising edge of the AND
pulse, the state of the delay chain and the state of the counter are R-C filtering is used on the biasing arm to filter out noise
latched. Together, they give out the digital code equivalent to from an on-chip bias current reference, as well as from the
the magnitude of the phase error. This PFD-T2D architecture biasing arm itself, with the R and C obtained by PMOS
can be built to handle very large phase errors without a transistors as shown in Fig.5. The bias filter pole is placed at
proportionate increase in area. 30kHz. The PBIAS_FILT and CASC_BIAS nodes are shared
The UP/DN Sensor circuit detects whether REFCLK or the between the Coarse and Fine DACs, whereas the TC DAC has
FBCLK came first, and thus gives the 'sign' of the phase error. its own, similar, regulated cascode.
Reducing the number of elements in the delay chain and The Fine (ΣΔ) DAC consists of 8 elements with
increasing the number of bits in the counter would result in a differential switches used to improve switching linearity.
smaller area for a given total delay, and a more linear A standard 2nd order ΣΔ modulator with an 8-level
conversion. However, this would imply a higher operating quantizer, operating at a frequency around 250MHz is used to
frequency for the counter. The number of elements in the delay control the ΣΔ DAC. A first order series R-C Filter (R=1.5k,
chain is determined by this trade-off. C=40pF) is put in series with the ΣΔ arm of the DAC with a
bandwidth varying between 2MHz-4MHz across process and
temperature. This ensures an over-sampling ratio of at least
60, providing significant attenuation to the ΣΔ noise. The
voltage drop across the filter does not exceed 100mV.
The Coarse DAC code also controls the Fine DAC range,
keeping the latter a constant fraction of the DCO output
frequency. The Fine DAC range is around +/-90MHz when
the DCO is operating at 1.8GHz.
Fig.4. PFD and T2D architecture The ICO is a simple three stage single ended ring (see
Fig.6.). This is the minimum number of devices that can be
IV. IMPLEMENTATION
used in the ring, and allows for low phase noise at reasonable
The architecture described in section III was implemented current consumption.
in a 65nm CMOS technology to provide a maximum of
1.8GHz output clock. The DPLL supports an input frequency
range of 0.7MHz to 50MHz; an internal reference divider is
used to divide the frequency internally to a suitable frequency
in the range of 0.7MHz to 2.1MHz.
Calibration and Normalization is used to ensure that the
DPLL bandwidth is between 20kHz to 60kHz across process,
temperature and reference frequencies.
The coarse DAC is built as a 9 bit current DAC (4
Thermometric MSBs and 5 Binary LSBs). The DAC operates
from a 1.8V supply with regulated cascoding used to improve
supply noise rejection, as shown in Fig. 5. Note that the Fig. 6. ICO architecture
voltage CASC_BIAS1 is also generated from a similar
regulated cascode not shown in figure, to reduce systematic The Temperature Compensation Circuit uses a current

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DAC and a TC VLPF implemented by MOS resistors and a
20pF PMOS capacitor [1]. The bandwidth of the VLPF is at
worst (highest) equal to 200Hz across process, temperature
and TC code. The Temperature Compensation DAC range,
again controlled by the Coarse Code, is set at +/-400MHz for a
1.8GHz operation, and sufficiently covers the temperature
variation of the DCO output frequency. Each code of the 6-bit
TC DAC corresponds to worst-case frequency step of
12.5MHz. As explained in [1], the frequency error introduced
by Temperature Compensation is roughly given by FTCstep×
(BWVLPF/BWDPLL), where FTCstep is the equivalent
Temperature Compensation DAC frequency step, BWVLPF is
the bandwidth of the VLPF, and BWDPLL is the DPLL
bandwidth,. Since the DPLL bandwidth is at least 20kHz, the
frequency error caused by every TC operation works out to
125kHz, which is less than 100ppm of the output frequency.
Fig. 7. DPLL phase noise measured on silicon
The TC DAC range is more than 4 times the Fine DAC range.
If the TC DAC were not present, the Fine DAC would have to
be increased 5 times, which would have implied much higher
jitter due to ΣΔ operation.
The T2D has 16 elements in the ring, each with 30ps
delay, and a 6-bit counter, resulting in a range greater than
60ns. The delay elements are implemented as NAND gates.
The PLL consumes 3.5mA out of a 1.8V supply. It
occupies a die area of 0.23 sq mm, out of which about 0.11 sq
mm is the core area, and the rest is taken up by digital DFT,
two internal 1.8V-to-1.2V linear regulators, and a bias current
reference. The PLL does not require external components.
Fig. 7. shows the phase noise of the DPLL as measured on
silicon, on a post-divided 100MHz clock. The input clock to
the DPLL was 21MHz, which was pre-divided by 30 to get a
PLL reference frequency of 0.7MHz. The phase noise for
1.8GHz operation is –87dBc/Hz at 1MHz offset. The highest
spur is lower than -95dBC with the other spurs being at least
6dB lower. The integrated jitter after considering the HDMI Fig. 8. Effective DPLL phase noise after considering CDR HPF
CDR HPF (4MHz corner, 20dB/decade roll off) is 3.8ps rms,
and eSATA HPF (1.1MHz, 40dB/decade roll off) is 4.4ps rms.
This is suitable for operation up to 3Gbps for both these
standards. Fig.8. shows the effective phase noise contribution
from the DPLL, as seen by the system, after considering the
effect of the CDR HPF. The DPLL was verified to remain in
lock over a temperature range of –40°C to 125°C, once locked
at either extreme.
In Fig.7. the spur at 5MHz, is thought to be due to supply
coupling on output dividers that are provided a noisy digital
supply. Changing the PLL bandwidth or the passive filtering Fig.9. Histogram of Phase Error Codes recorded on silicon
after the ΣΔ in the DCO did not alter the spur magnitude, ruling
out spurs due to T2D or due to ΣΔ operation. The chip micrograph of the DPLL, as a part of a test chip
Fig.9. shows a histogram of T2D codes, recorded on silicon. is shown in Fig.10.
The maximum code is 270, which, for a T2D resolution of 30ps,
implies a maximum input jitter of 8.1ns, which is comfortably
within the T2D range designed for.

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Fig. 10.Chip micrograph of DPLL as part of a test chip
V. COMPARSION WITH EXISTING WORK
Table 1 shows a comparison with recently published work
on DPLLs suitable for SERDES applications. Ref. [4][5][6]
use an LC DCO (high area) coupled with high bandwidth to
achieve a phase noise better than what may be required in a
SERDES application. Ref. [7] uses a ring oscillator DCO and
achieves a phase noise performance comparable to this work
and much lower power and area. However, the maximum
frequency achieved is only 800MHz, the phase noise reported
is with a 26MHz reference (not the lowest allowed 2MHz),
and there are multiple spurs as high as -45dBC. Most
importantly [7] appears to have a low lock range and might
require recalibration with temperature change. None of the
DPLLs [3]-[7] use the passive filtering after ΣΔ dithering in
the DCO, as used in this work. This work therefore compares
favourably with state of the art in having a ring oscillator
DCO, greater than 1.5GHz output frequency, low area and
power, low spurs, and a high, post locking, temperature range.
circulating T2D concept, Subhash Pai and Shivaprakash
Halagur for digital design, Ananth Kamath for physical
design, and Ravishanker Pasupuleti for board design and test.
REFERENCES
[1] Anant S Kamath, Biman Chattopdhyay and Gopalkrishna Nayak, “A
65nm CMOS, Ring-Oscillator based, High Accuracy Digital Phase
Lock Loop for USB2.0”, IEEE Custom Integrated Circuits Conference,
September 2009.
[2] A.M.Fahim, “A Compact, Low-Power Low-Jitter Digital DPLL”,
Proceedings of the 29th European Solid State Circuits Conference, pages
101-104, September 2003.
[3] Enrico Temporiti et al., “Insights into Wideband Fractional All-Digital
PLLs for RF Applications”, IEEE Custom Integrated Circuits
Conference, September 2009.
[4] Liangge Xu et al, “A 2.4-GHz Low-Power All-Digital Phase-Locked
Loop”, IEEE Custom Integrated Circuits Conference, September 2009.
[5] Marco Zanuso et al, “A 3MHz-BW 3.6GHz Digital Fractional-N PLL with
Sub-Gate Delay TDC, Phase-Interpolation Divider, and Digital Mismatch
Cancellation”, ISSCC, February 2010.
[6] Takashi Tokairin et al, “A 2.1-to-2.8GHz All-Digital Frequency
Synthesizer with a Time-Windowed TDC”, ISSCC, February 2010.
[7] Mike Shuo-Wei Chen et al, “A Calibration-Free 800MHz Fractional-N
Digital PLL with Embedded TDC”, ISSCC, February 2010.

Table 1. Comparison with state of the art

Work [4] [5] [6] [7] This Work
Max Freq. (Hz) 2.9G 3.6G 2.8 800M 1.8G
LC/Ring LC LC LC ring ring
Fref range (Hz) 12.3M 40M 40M 2-40M 0.7-50M
Phase Noise dBC/Hz* -130 -110 -110 -80 -87
Max spur (dBC)** -57 -90 -95 -45 -95
Area (mm2) 0.24 0.4 0.37 0.027 0.11
Power(mW) 12 80 9.7 3 6.3
Temp. range after lock ? ? ? ? -40 to 125
* At 1MHz offset, scaled to 1.8GHz **scaled to 1.8GHz

VI. CONCLUSIONS
A 1.8GHz ring-oscillator based high accuracy DPLL
suitable for SERDES applications was presented. It was
shown that SERDES requirements make certain beneficial
architectural choices possible: especially, ring oscillator DCO
can be used, and the complexities and costs of an LC tank can
be avoided. Temperature Compensation, Passive Filtering of
SD noise, and a re-circulating T2D, resulted in an optimized
design. Silicon results from a 65nm implementation were
presented. The design methods and results shown were found
to compare favourably with previously published solutions.
ACKNOWLEDGMENT
The authors thank Nagaraj Krishnaswamy for the re-

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