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Designing for Low Power in SoC Projects

10th International Forum on Embedded


MPSoC and Multicore June 28 - July 2
2010, Gifu, Japan

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Outline

•Motivation – why low power consumption is important?


•Definition – power and energy in digital circuits
•Dynamic Voltage and Frequency Scaling
•Power estimation
•Designing for low power – minimising dynamic power
•Designing for low power – minimising static power
•Conclusions

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Motivation

•Below motivation for low power design


•Extended battery life
•Better user experience
•Reduced packaging costs
•Better reliability

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An example of SoC - U8500

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Definitions

•Time (s), performance metric


•Energy (Joule), efficiency metric
•Power (Watt), energy consumed per unit time
•Example: typical a use case (like MP3 playback) can be splitted into
multiple tasks based on their power consumption. Intention is to
minimize the total energy consumption of the use case (i.e. cumulative
area of the blocks).

Power

T
a
s Task 3
k
Task 1
2 Task 5

Task 4 Task 6
Time

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Definitions

•Static (leakage) power:


•Unfortunately transistors are not ideal switches
•Reduced gate lengths and supply and thresold voltages turn
to increased leakage if no attention is paid
•Contribution of static power is increasing
•Dynamic power:
•Consumed when (dis)charging the capacitors
•Short-circuit current contributes also
•Dynamic power can be formulated as
Power  energy per transition  transition rate
  CloadVDD f ,
2

where α is activity factor, VDD is voltage, Cload capacitive load,


and f is frequency

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Designing for Low Power – DVFS

Power Power Power


(avg) (avg) (avg)

Processing
f=f1 v=v1
f=0.5*f1 v=v1
f=f1 Baseline v=v1 DFS DVFS
f=0.5*f1 v=v1 f=0.5*f1 v=0.85* v1
f=0.5*f1 v=0.85* v1
Leakage v=v1 v=v1
v=0.85* v1

t1 2*t1 time t1 2*t1 time t1 2*t1 time

E1  Pprocessin g  Pbaseline  Pleakage E 2  Pprocessin g  0.5Pbaseline  Pleakage E3  0.72Pprocessin g  0.36Pbaseline  0.61Pleakage

•Example:
Pprocessig  30mW
Pbaseline  15mW
Pleakage  10mW
t  1s
E1  (30 *1)  (15 * 2)  (10 * 2)  80mJ
E 2  (0.5 * 30 * 2)  (0.5 *15 * 2)  (10 * 2)  65mJ ~20% savings with DFS alone
E 3  (0.72 * 0.5 * 30 * 2)  (0.72 * 0.5 *15 * 2)  (0.61*10 * 2)  45mJ ~45% savings with DVFS!

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Power Estimation

•In order to understand the power efficiency of the design, power


estimation is needed
•Static estimation is error-prone
•Dynamic estimation is preferred
•Obtaining reliable activity factors is the basis for accurate power
estimation
•Activity factor represents the probability for the transistor for changing its
state
•Activity factors are obtained by simulation (i.e. mimicking the real use
case)
•Gives early feedback for the designer

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Reducing Dynamic Power – Clock Gatings

•Static clock gating:


•Typically IPs have SW controllable register for enabling or disabling the
functionality (clocks)
•HW engineers typically overestimate SW capability to handle different low
power settings
•Overall, it takes time to get SW optimized for power consumption
•Dynamic clock gating:
•HW should be made as autonomous as possible in low power settings
•Clock gating is determined based on the state of the IP
•Examples: DMA engine, memory controller, serial IFs

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Reducing Dynamic Power – Clock Tree

Clock tree may consume even 50% of dynamic power!


•Relying on automatic clock gate insertion is not enough!

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Reducing Dynamic Power - IPs

•In case of IPs, most of the dynamic power consumed may come from other
source than its data path.
•Bus IF and its logic may contribute a lot due to high frequencies used!
•Special care must be addressed to optimize bus IF power consumption:

Response Not Idle


Request
FSM
Clock
Clk
gate
Clk Write EN
Control
Bus IF Regs

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Reducing Dynamic Power – Memories

•Memories need special attention as selected and clocked RAM


representes significant dynamic power consumption
•Selection and clocking should to be controlled external to RAM
Access
Enable Address
Address specific Select
decoding

RAM

Clock
Clock Clock
Gate

Select

RAM

Clock
Gate Clock

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Reducing Static Power – Power Gating

•Switch off the unused logic for minimizing static power


•Design partitioning for multiple power domains and multiple supply
voltages
•Selection of optimal operating points for each partition
•Centralized control for managing power domains

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Conclusions

•Power is one of the main design parameters


•Power optimization to be addressed from the first design stages
•Power optimization to be done at all design stages
•Dynamic power estimation is needed for reliable analysis and
feedback
•Careful clock tree design and clock gatings are needed
•Design partitioning and dedicated operating point selection for
minimising static power

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