Beruflich Dokumente
Kultur Dokumente
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Outline
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Motivation
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An example of SoC - U8500
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Definitions
Power
T
a
s Task 3
k
Task 1
2 Task 5
Task 4 Task 6
Time
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Definitions
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Designing for Low Power – DVFS
Processing
f=f1 v=v1
f=0.5*f1 v=v1
f=f1 Baseline v=v1 DFS DVFS
f=0.5*f1 v=v1 f=0.5*f1 v=0.85* v1
f=0.5*f1 v=0.85* v1
Leakage v=v1 v=v1
v=0.85* v1
•Example:
Pprocessig 30mW
Pbaseline 15mW
Pleakage 10mW
t 1s
E1 (30 *1) (15 * 2) (10 * 2) 80mJ
E 2 (0.5 * 30 * 2) (0.5 *15 * 2) (10 * 2) 65mJ ~20% savings with DFS alone
E 3 (0.72 * 0.5 * 30 * 2) (0.72 * 0.5 *15 * 2) (0.61*10 * 2) 45mJ ~45% savings with DVFS!
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Power Estimation
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Reducing Dynamic Power – Clock Gatings
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Reducing Dynamic Power – Clock Tree
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Reducing Dynamic Power - IPs
•In case of IPs, most of the dynamic power consumed may come from other
source than its data path.
•Bus IF and its logic may contribute a lot due to high frequencies used!
•Special care must be addressed to optimize bus IF power consumption:
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Reducing Dynamic Power – Memories
RAM
Clock
Clock Clock
Gate
Select
RAM
Clock
Gate Clock
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Reducing Static Power – Power Gating
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Conclusions
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