CNS11XX STR91XX DS V1.4

CNS11XX
STR91XX
Broadband Home Gateway Processor
Data Sheet
CNS11XX/STR91XX
April, 2008
Dissemination or disclosure of this proprietary and confidential

information is NOT permitted without the written consent of
Cavium Networks.
Contents of this document are subject to change without notice.
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Cavium Networks Proprietary and Confidential DO NOT COPY
Orion: STR91XX
CNS11XX
Data Sheet
Part Number Mapping Table
The following table describes the high level product and part number mapping of the Star Semiconductor
products to the Cavium Networks product numbering system. The last one or two characters (denoted XX) will
be the same in the Star and Cavium Networks numbering systems. Please contact your local sales
representative for any required assistance with part number conversions.

Star Semiconductor to Cavium Network Part Number Mapping
Family Star Part Numbers Cavium Part Numbers
Orion STR91XX CNS11XX
Orion with Content Processor STR92XX CNS12XX
Equuleus with 10/100 Phy STR813X CNS213X

Equuleus STR818X CNS218X
Orion Evaluation Board STR91XX-EVB CNS11XX-EVB

Equuleus Evaluation Board STR813X-EVB CNS213X-EVB
REV. E1.4 April,2008

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Orion: STR91XX
CNS11XX
Data Sheet
PUBLISHED BY
Cavium Networks
Phone: 650-623-7000
Fax: 650-625-9751
© 2004-2008 by Cavium Networks
All rights reserved. No part of this manual may be reproduced in any form, or transmitted by any means, without
the written permission of Cavium Networks.
Cavium Networks makes no warranty about the use of its products, and reserves the right to change this
document at any time, without notice. Whereas great care has been taken in the preparation in the preparation of
this manual, Cavium Networks, the publisher, and the authors assume no responsibility for errors or omissions.
Please contact Cavium Networks sales department to check that you have the latest version of this document
before finalizing a design.
All trademarks or service marks referred to in this manual are the property of their respective owners.

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CNS11XX
STR91XX
Data Sheet
CNS11XX/STR91XX FEATURES
z 32-bit RISC Core
9 Higher performance ARM922-compatible RISC
(with 16kB I-cache, 16kB D-cache, 8kB z External Memory Interface
I-scratchpad, 8kB D-scratchpad) memory and 9 Static Memory: support 8/16-bit programmable
memory management unit(MMU) for high-level external bus width with address range up to 16
RTOS, with programmable CPU core clocks up Mbytes, for ROM/Flash/SRAM
to 250MHz 9 DDR SDRAM: 16/32-bit data path widths with
9 Proprietary advanced system bus architecture address range up to 256Mbytes, supporting
achieving superior performance programmable burst lengths of 4/8, and CAS
9 Supports TRACE32 and/or Multi-ICE JTAG latency of 2.0/2.5
debugging interfaces
9 Built-in intelligent power management for normal z External Peripheral Interface
and power-saving mode of operations 9 Up to two RGMII/MII interfaces (MAC or PHY
9 Support IRQ/FIQ interrupt modes mode) for external transceivers or single-chip
9 Support little-endian ordering switch
9 Embedded USB2.0-compliant host PHY and
z Network Processing Engines EHCI/OHCI controller supporting two external
9 Embedded 2-port 10Base-T/100Base-TX/ USB devices simultaneously for low-/full-/
1000Base-T MAC’s with 4-port L2 gigabit switch high-speed operations (for printer, digital
engine for wire-speed broadband switch camera and storage, etc.)
application, compliant with 802.3-2002 9 High-speed 16C550-compliant UART serial
9 Hardware-based network address translation channel supporting configurable baud-rates up
(HNAT) accelerator supporting L3/L4 fast-path to 1.5Mbps for monitor console or data
routing to off-load CPU transport interface with hardware CTS/RTS
9 DMA engines with burst mode support for flow control (for Bluetooth radio module, etc.)
efficient data transfer among CPU and 9 8/16-bit external I/O interface supporting
WAN/LAN ports PCMCIA interface or generic DSP/CPU host
9 1K entries address lookup table interfaces (for commercial-off-the-shelf VoIP
9 Support IPv4 packet filtering and TCP/UDP/IP DSP co-processor, etc.)
checksum off-load for incoming and outgoing 9 Up to 21 individually programmable GPIO’s
packets
Cavium Networks
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Orion: STR91XX
CNS11XX
Data Sheet
(shared with other function pins)
9 PCI v.2.2-compliant host bridge between 32-bit
PCI bus (running up to 66MHz) and on-chip
system bus, supports up to three(3) external
PCI-based devices (for 802.11 WLAN modules,
media co-processors, etc.)
z Other Function Blocks

z Targeted Applications
9 Two 32-bit programmable timers, one
9 FE/GbE 11n SOHO Router
watch-dog timer and one real-time clock (RTC)
9 11n GbE AP
9 Programmable interrupt controller with FIQ/IRQ
9 VDSL Broadband Router/Gateway
priority configurable
9 Home Media/Entertainment Gateway
9 Integrated PLL clock synthesizer generates all
9 Printer Server
the required clocks from 25MHz reference
9 Wire/Wireless IP CAM
9 Optimized on-chip voltage regulator provides
9 Network Attachment Storage (NAS)
2.5/1.8V supplies with low-cost external PNP
9 P2P Download Station
pass transistors
9 UWB Hub
z Electrical Characteristics
z Software Supports
9 Package:
9 Nucleus and Linux BSP supports
BGA-304 (for CNS1102/1105-STR9102/9105)
9 Technical documents
LFBGA-257 (for CNS1104/STR9104)
PQFP-208 (for
CNS1101/CNS1109-STR9101/9109)
9 0.18um low-power design with intelligent power
management
9 Single 3.3V supply:
3.3V for general I/O’s, 2.5V for DDR I/O’s, and
1.8V for core logic and embedded analog PLL’s
9 Power Consumption: within 2 watts

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CNS11XX
STR91XX
Data Sheet
Multi-ICE ICE
Debugger ARM922-compatible RISC Core
MMU
SRAM I-cache D-cache I-scratch D-scratch

(16kB) (16kB) pad(8kB) pad(8kB) 802.11a/b/g
32-bit/
66MHz Module
Static PCI Host PCI
Memory Bus and Bridge
FLASH
Controller Control
Memory VPN
Logic
Interrupt Co-processor
Controller
DDR
16/32-bit Hardware
SDRAM WDT
DDR NAT
Controller MPEG-1/-2/-4
SDRAM
Real-time Co-processor
Counter
USB2.0/1.1
Host CTL Gigabit Switch
Printer/DSC (4-port) Timers
HD & PHY PNP
Regulator BJT Drivers
UART
Controller Gigabit Gigabit PCMCIA CLKGen &
MAC-1 MAC-0 Controller GPIO Power Mng’t
Bluetooth
Module
RGMII/MII
5P
10/100/(1000)M
10/100/(1000M) VoIP
PHY
Switch DSP
CODEC/
SLIC
Figure 1. CNS11XX/STR91XX System Block Diagram
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Phone: 650-623-7000
Fax: 650-625-9751
Orion: STR91XX
CNS11XX
Data Sheet
Table 1. Cross Reference Matrix of Part Number versus Applicable User Interfaces
P/N
CNS1101/ CNS1102/ CNS1104/ CNS1105/ CNS1109/
STR9101 STR9102 STR9104 STR9105 STR9109
Interfaces
Network
Storage,
Wired/Wireless FE 11n Router, 11n
Typical Applications Wireless IP CAM P2P Download
11n GbE Router VDSL Router co-processor
Station, UWB
Hub
Package Type PQFP-208 BGA-304 LFBGA-257 BGA-304 PQFP-208
Form Factor 28mmX28mm 27mmX27mm 14mmX14mm 27mmX27mm 28mmX28mm
Parallel Flash 8/16-bit 8/16-bit 8/16-bit 8/16-bit 8/16-bit
DDR SDRAM 16-bit 16/32-bit 16-bit 16/32-bit 16-bit
Ethernet MAC 1x 10/100 2x 10/100/1000 2x 10/100 2x 10/100 1x 10/100/1000
Embedded Switch Y Y Y Y Y
Hardware NAT/NAPT Y Y Y Y Y
USB2.0 Host - Up to 2 Up to 2 Up to 2 -
PCI 2.2 Host(66/33MH

Up to 2 Up to 3 - Up to 3 Up to 2
z)
PCMCIA - Y Y Y -
GPIO (shared pins) Y (11) Y (21) Y(21) Y (21) Y (11)
UART Y Y Y Y Y
16-bit local bus Y Y Y Y Y
JTAG-ICE ARM-like ARM/ARM-like ARM/ARM-like ARM/ARM-like ARM-like

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Orion: STR91XX
CNS11XX
Data Sheet
Revision History
Revision Date Summary of Changes
1.4 August 1, 2008 First Cavium Networks Release
1.4 April 21, 2008 1.Update 1.8V and 2.5V Regulator Control Register
ECN-TD-08-04005 2.Add 9101/9104/9109 package thermal resistanceθJA to Table 4-3.
1.3 February 04, 2008 1.Add AD version Part Order Number (STR9101-AD00g,STR9101-AD00gu,
ECN-TD-08-02001 STR9104-AD00g,STR9104-AD10g,STR9105-AD11g,STR9109-AD00g
STR9109-AD00gu,STR9109-AD10gu) in Table 6-1
Del AD version Part Order Number(STR9104-AD01g) in Table 6-1
2.Add Specific P/N’s in Part Order Numbering(STR9101-AD00Mgu,
STR9109-AD00Mgu,STR9102-AD00Mgu,STR9202-AD00Bg,
STR9202-AD00Bgu,STR9203-AD00Bg) in Table 6-2
th
1.2 September 12 , 2007 1. Merge CNS11XX/STR91XX series data sheet into a one.
ECN-TD-07-09001 2. Add a cross reference matrix of part number versus applicable user
interfaces
3. Add GPIO pins description (Table1-7)
4. Add SMC and PCMCIA address bus description
5. Add part order numbering and package marking
rd
1.1 June 3 , 2006 1. The shared pin name of GPIO[15] in Table 1-7 should be RESET.
2. Bit[8:9] of Table 1-8 shall be corrected to:
- Bit[8]: AHB-to-PCI Bridge Status
- Bit[9]: Reserved
3. Add column on Triggering Scheme for each interrupt source in Table 1-8
4. Bit[8:9] of Interrupt Source Register (section 3.3.12) shall be corrected to
- Bit[8]: AHB-to-PCI Bridge Status
- Bit[9]: Reserved.
5. Update I/O pads driving strength
6. Flash/SRAM timing update
7. typo: page 28
2’b01: IPV4H5NF & UDP (can do IP/UDP checksum)
8. Change PCI pins to 3.3/5V tolerant
9. Change MII pins driving strength from 14mA to 7mA
10. Update Flash/SRAM timing diagram

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Orion: STR91XX
CNS11XX
Data Sheet
11. Add PCMCIA Common Memory, Attribute Memory, and I/O functions
description.
12. Update PCMCIA timing diagram
13. Add supplement of byte ordering of each Ethernet Frame field, and update
MAC[47:0] byte ordering of ARL Table Access Control 1 and 2 registers
14. Bit 9, CPU_hold, of Interrupt Status Register (0x88) of Switch is obsolete.
15. Supplement of GPIO register description
16. Update Interrupt Mask Register default value from 0x0000-0000 to
0xFFFF-FFFF.
17. Update switch register 0x088 description
18. Update bit 28 (dis_uc_pause) description of switch register 0x008, 0x00C
19. Section 4.2 ESD Machine Mode is changed from 200V to 150V.
th
1.0 December 24 , 2004 Formal release

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Orion: STR91XX
CNS11XX
Data Sheet
Table of Contents
1.0 Functional Descriptions.................................................................................................................................... 14

1.1 32-bit RISC Core................................................................................................................................................. 14
1.2 System Bus Architecture................................................................................................................................... 14
1.3 Double Data Rate SDRAM Controller (DDRC) ......................................................................................... 15
1.4 Static Memory Controller (SMC).................................................................................................................... 16
1.5 Generic DMA Engine (GDMA) ...................................................................................................................... 17
1.6 Embedded 4-port Gigabit Switch Engine..................................................................................................... 17
1.6.1 Packet Format ...................................................................................................................................................... 17
1.6.2 VLAN .................................................................................................................................................................... 18
1.6.3 Address Resolution Logic ................................................................................................................................ 18
1.6.3.1 Address Table Format ....................................................................................................................................... 18
1.6.3.2 Forwarding Flow Chart..................................................................................................................................... 20
1.6.3.3 NIC Mode............................................................................................................................................................. 27
1.6.4 Flow Control........................................................................................................................................................ 28
1.6.5 Quality of Service (QoS)................................................................................................................................... 28
1.6.6 Broadcast Storm Prevention and Egress Rate Limit ................................................................................... 29
1.6.7 DMA Scheme ...................................................................................................................................................... 29
1.7 Hardware NAT (HNAT) Engine ..................................................................................................................... 32
1.7.1 General introduction ......................................................................................................................................... 32
1.8 Reserved ............................................................................................................................................................... 33
1.9 USB 2.0/1.1 Host Controller with Integrated Transceivers ....................................................................... 33
1.9.1 AHB Interface and DMA.................................................................................................................................. 34
1.9.2 List Processor....................................................................................................................................................... 35
1.9.3 Host Parallel Interface Engine (HPIE) or Host Serial Interface Engine (HSIE) ................................... 35
1.9.4 Port Router ........................................................................................................................................................... 35
1.10 PCI Host Bridge .................................................................................................................................................. 36
1.10.1 PCI Configuration Cycle .................................................................................................................................. 37
1.11 PCMCIA (16-bit) Interface ............................................................................................................................... 38
1.11.1 Memory Function ............................................................................................................................................... 39
1.11.2 I/O Function......................................................................................................................................................... 40
1.12 High-speed UART Controller ......................................................................................................................... 40
1.13 General Purpose Inputs/Outputs (GPIO’s) .................................................................................................. 40
1.14 Timer ..................................................................................................................................................................... 42
1.15 Watch-Dog Timer (WDT) ................................................................................................................................. 42
1.16 Real-time Clock (RTC) ...................................................................................................................................... 42
1.17 Interrupt Controller (INTC)............................................................................................................................. 42
1.18 Clock Generator and Power Management ................................................................................................... 43
1.19 Linear Regulators ............................................................................................................................................... 45
2.0 Pin Assignment and Descriptions.................................................................................................................. 46
2.1 Package Pin-out .................................................................................................................................................. 55
2.1.1 CNS1101/CNS1109/STR9101/STR9109 (PQFP-208) Package Pin-out...................................................... 55
2.1.2 CNS1102/CNS1105/STR9102/STR9105 (BGA-304) Package Pin-out....................................................... 56
2.1.3 CNS1104/STR9104 (LFBGA-257) Package Pin-out...................................................................................... 57
2.2 Package Pin-Number vs. Pin-Name ............................................................................................................... 58
2.2.1 CNS1101/CNS1109/STR9101/STR9109 (PQFP-208) Package Pin-Number vs. Pin-Name .................. 58

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Data Sheet
2.2.2 CNS1102/CNS1105/STR9102/STR9105 (BGA-304) Package Pin-Number vs. Pin-Name.................... 59
2.2.3 CNS1104/STR9104 (LFBGA-257) Package Pin-Number vs. Pin-Name .................................................. 61
3.0 System Address Map and Register Descriptions........................................................................................ 63
3.1 Memory Mapping .............................................................................................................................................. 63
3.2 Register Definitions .......................................................................................................................................... 65
3.3 Detailed Register Descriptions (In terms of functional blocks).............................................................. 71
3.3.1 Static Memory Control...................................................................................................................................... 71
3.3.2 DDR SDRAM Control ...................................................................................................................................... 76
3.3.3 Generic DMA (GDMA) Controller ................................................................................................................ 80
3.3.4 Embedded Switch Controller (including HNAT and MAC) ................................................................... 87
3.3.5 MISC Control Registers.................................................................................................................................. 107
3.3.6 Clock/Power Management .............................................................................................................................108
3.3.7 High-speed UART Control ............................................................................................................................114
3.3.8 Timer ................................................................................................................................................................... 120
3.3.9 Watch Dog Timer ............................................................................................................................................. 123
3.3.10 Real Time Clock ...............................................................................................................................................124
3.3.11 GPIO ................................................................................................................................................................... 126
3.3.12 Interrupt Controller ......................................................................................................................................... 129
3.3.13 PCMCIA Host Controller ...............................................................................................................................130
3.3.14 PCI Bridge Configuration Data Register .................................................................................................... 132
3.3.15 PCI Bridge Configuration Address Register..............................................................................................132
3.3.16 USB1.1 Configuration Registers ................................................................................................................... 133
3.3.17 USB1.1 Operation Register ............................................................................................................................134
3.3.17.1 Control and Status Partition ..........................................................................................................................134
3.3.17.2 Memory Pointer Partition...............................................................................................................................140
3.3.17.3 Frame Counter Partition ................................................................................................................................. 141
3.3.17.4 Root Hub Partition........................................................................................................................................... 143
3.3.18 USB2.0 Configuration Registers ................................................................................................................... 150
3.3.19 USB2.0 Operational Registers .......................................................................................................................151
4.0 Electrical Characteristics................................................................................................................................. 157
4.1 DC Electrical Characteristics .........................................................................................................................157
4.2 Absolute Maximum Ratings..........................................................................................................................159
4.3 Recommended Operation Conditions......................................................................................................... 159
4.4 Power Consumption ........................................................................................................................................160
4.5 AC Timing Specifications ..............................................................................................................................160
4.6 Interface Timing Waveforms.........................................................................................................................166
5.0 Mechanical Specifications..............................................................................................................................174
5.1 PQFP-208 Package Outline and Dimensions .............................................................................................174
5.2 BGA-304 Package Outline and Dimensions ..............................................................................................175
5.3 LFBGA-257 Package Outline and Dimensions..........................................................................................176
6.0 Part Order Numbering and Package Marking...........................................................................................177

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Orion: STR91XX
CNS11XX
Data Sheet
List of Figures
Figure 1. STR91XX System Block Diagram .................................................................................................6
Figure 1-1. ARM-922 Compatible Processor. ................................................................................................14
Figure 1-2. DDR Controller............................................................................................................................16
Figure 1-3. SMC Controller............................................................................................................................17
Figure 1-4. Major Flow of Packet Forwarding................................................................................................20
Figure 1-5. Flow of Port State Filtering ..........................................................................................................21
Figure 1-6. Flow of SA Security Filtering .......................................................................................................22
Figure 1-7. Flow of DA Filtering (1 of 3).........................................................................................................23
Figure 1-10. Flow of VLAN Egress Check .......................................................................................................26
Figure 1-11. Flow of Re-direct .........................................................................................................................27
Figure 1-12. Fast- and Slow-paths of Embedded Switch with Hardware NAT .................................................33
Figure 1-13. USB2.0/1.1 PHY/Controller Block Diagram.................................................................................34
Figure 1-14. Port Router Block Diagram..........................................................................................................36
Figure 1-15. PCI Host Bridge ..........................................................................................................................37
Figure 1-16. Type 0 Translation.......................................................................................................................38
Figure 1-17. Type 1 Translation.......................................................................................................................38
Figure 1-18. PCMCIA_HBA Block Diagram.....................................................................................................39
Figure 1-19. Overall Clock Domains................................................................................................................44
Figure 1-20. Typical Application Circuits for Regulator ....................................................................................45
Figure 2-1. STR9101/9109 PQFP-208 Package Pin-out ...............................................................................55
Figure 2-2. STR9102/9105 BGA-304 Package Pin-out .................................................................................56
Figure 2-3. STR9104 LFBGA-257 Package Pin-out ......................................................................................57
Figure 4-1. RGMII Interface Timing .............................................................................................................166
Figure 4-2. MII Interface Timing...................................................................................................................167
Figure 4-3. Reverse MII Interface Timing ....................................................................................................167
Figure 4-4. Flash/SRAM Interface Write Timing ..........................................................................................168
Figure 4-5. Flash/SRAM Interface Read Timing ..........................................................................................168
Figure 4-6. DDR SDRAM Interface Timing 0 ...............................................................................................169
Figure 4-7. DDR SDRAM Interface Timing 1 ...............................................................................................169
Figure 4-8. PCMCIA Interface Memory Write Timing ...................................................................................170
Figure 4-9. PCMCIA Interface Memory Read Timing...................................................................................170
Figure 4-10. PCMCIA Interface I/O Write Timing ...........................................................................................171
Figure 4-11. PCMCIA Interface I/O Read Timing...........................................................................................172
Figure 4-12. PCI Interface Timing..................................................................................................................172
Figure 4-13. UART Interface Timing ..............................................................................................................172
Figure 4-14. ARM-Like ICE Interface Timing .................................................................................................173
Figure 4-15. Multi-ICE Interface Timing .........................................................................................................173
Figure 5-1. STR9101/9109 Package Outline and Dimensions— 208-pins 28mm*28mm PQFP..................174
Figure 5-2. STR9102/9105 Package Outline and Dimensions— 304-pins 27mm*27mm BGA....................175
Figure 5-3. STR9104 Package Outline and Dimensions— 257-pins 14mm*14mm LFBGA.........................176
Figure 6-1. Sample Part Order Number.......................................................................................................177
Figure 6-2. Package Marking and Pin 1 Location ........................................................................................178

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Orion: STR91XX
CNS11XX
Data Sheet
List of Tables
Table 1. Cross Reference Matrix of Part Number versus Applicable User Interfaces..................................7
Table 1-1. Common Memory Read Function ...............................................................................................39
Table 1-2. Common Memory Write Function................................................................................................39
Table 1-3. Attribute Memory Read Function.................................................................................................40
Table 1-4. Attribute Memory Write Function .................................................................................................40
Table 1-5. I/O Read Function .......................................................................................................................40
Table 1-6. I/O Write Function .......................................................................................................................40
Table 1-7. GPIO Pin Assignment and Shared Pins ......................................................................................41
Table 1-8. Peripheral Interrupt Mapping.......................................................................................................42
Table 2-1. Pin Type Notations ......................................................................................................................46
Table 2-2. Pin Assignment and Description..................................................................................................46
Table 2-3. Reset-Latch Configuration Pins...................................................................................................54
Table 2-3. STR9101/9109 Package Pin-Number vs. Pin-Name (In Order of Pin Number)...........................58
Table 2-4. STR9102/9105 Package Pin-Number vs. Pin-Name (In Order of Ball Number) ..........................59
Table 2-5. STR9104 Package Pin-Number vs. Pin-Name (In Order of Ball Number) ...................................61
Table 3-1. Memory Map ...............................................................................................................................63
Table 3-2. Register Definitions .....................................................................................................................65
Table 3-3. Access Type Notations................................................................................................................71
Table 3-4. UART Interrupt Identification .....................................................................................................120
Table 4-1. DC Electrical Characteristics.....................................................................................................157
Table 4-2. Absolute Maximum Ratings.......................................................................................................159
Table 4-3. Recommended Operation Conditions .......................................................................................159
Table 4-4. Power Consumption..................................................................................................................160
Table 4-5. AC Timing Specifications...........................................................................................................160
Table 6-1. STR91XX AD version Part Order Number List ..........................................................................177
Table 6-2. STR91XX AD version Part Order Number List with Specific Customer Code............................177

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Orion: STR91XX
CNS11XX
Data Sheet
1.0 Functional Descriptions
1.1 32-bit RISC Core
ARM-922 compatible RISC core, based on ARM V4 architecture and compliant to V4 instruction sets and register
sets, is with Harvard architecture with SIX(6) pipelined stages—Fetch, Decode, Shift, Execution, Memory and
Write. To enhance performance, the CPU core also contains a Branch Target Buffer(BTB) to reduce branch
penalties. There are totally SEVEN(7) operation modes supported: Supervisor, System, FIQ, IRQ, Abort, User
and Undefined Modes. The functional block of the CPU core is illustrated in Figure 1-1 and relevant detailed
descriptions are addressed below.
Figure 1-1. ARM-922 Compatible Processor.
z The Branch Target Buffer(BTB) implements an accurate branch prediction mechanism to improve
processor performance to resolve control dependency and reduce branch penalty.
z Memory Management Unit(MMU) for high-level RTOS support, with configurable 2-way or 4-way set
associate TLB to improve overall CPU performance
z Two-way associated I-cache and D-cache memory of 16k bytes each are embedded
z I-scratchpad and D-scratchpad of 8k bytes each are embedded as fast on-chip SRAM for
performance-critical program/data pre-fetch at full CPU speed
z CPU core clock can be programmable down from 21.87MHz and up to 250MHz, and 200MHz is
guaranteed.
z Support FIQ and IRQ interrupts
z Support little-endian ordering
z Support two ICE debugger interfaces—a simplified ARM JTAG interface and fully-compliant ARM
Multi-ICE debug interfaces, compatible to AXDTM or RealViewTM commercial available debuggers
z Support power saving modes- SLEEP and IDLE mode
z Support ARM AMBA bus specification v2.0
1.2 System Bus Architecture
This chip builds in a multi layer high performance system bus compliant to AMBA bus spec. v2.0. The AHB bus

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Orion: STR91XX
CNS11XX
Data Sheet
clock is programmable and can be up to 100MHz for high performance peripherals requirement. The APB bus
clock speed is set at half of AHB clock and is employed for lower bandwidth peripherals.
1.3 Double Data Rate SDRAM Controller (DDRC)
The DDRC supports data path width of 16 or 32 bits, with addressing range up to 256Mbytes. The CAS latency
supported are 2.0 or 2.5 cycles. Data mask for byte, half-word or word is supported for WRITE operation. The
block diagram of DDR memory controller is shown in Figure1-2.
The DDRC_reg interface handles the programming of relevant registers of DDRC, and settings of DDR SDRAM
parameters. All data transfers to and from the registers of DDRC must be 32-bit wide.
Each AHB Slave connect a AHB Master for it to access external DDR SDRAM, It supports pre-read and
post-write features and built in two cache-size buffers to enhance memory bandwidth and reduce transaction
latency.
The Command Queue provides arbitration among all the AHB Slave interfaces and it guarantees data integrity
among these channels’ accessing. Each AHB interface is assigned with same priority.
The Memory Control block includes a state machine for DRAM access control, and can provide two delay
controls for DQS Input, and DQ/DQM Output. The state machine is featured with proprietary access scheme with
maximized memory bandwidth and minimized transaction latency. Refresh control logic with programmable
auto-refresh times in average periodic refresh interval reduces the pre-charge command. DQS Input delay control
is used to adjust sample clock phase to latch correct DQ bus input data. DQ/DQM output delay control is used to
adjust related timing between DQ/DQM and DQS.

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Orion: STR91XX
CNS11XX
Data Sheet
DDRC
DDRC reg
AHB Slave 0
AHB Slave 1
AHB Slave 2
AHB Slave 3 Memory Control DDR

AHB
Command SDRAM
Interface
Queue Interface
AHB Slave 4
AHB Slave 5
DQS Input
Delay Control
AHB Slave 6
DQ/DQM
Output Delay
Control
AHB Slave 7
Figure 1-2. DDR Controller
1.4 Static Memory Controller (SMC)
The SMC supports 8/16-bit programmable external bus-width with address range up to 16M bytes for
ROM/Flash/async-SRAM. Totally TWO(2) banks of external static memory can be accessed. The WRITE
accessing is featured with zero wait-state.
The block diagram of SMC is shown in Figure1.3, where the Static Memory Control Core generates all the R/W
access cycles for external static memories. The SMC control registers can be accessed through the AHB Slave
(Reg) and it must be a 32-bit wide transaction. The external static memory accessing is through AHB Slave
(Mem), and it can be 8-bit or 16-bit wide.

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Data Sheet
SMC
AHB Slave (Reg)

AHB Static ROM/Flash/
Interface Memory async-SRAM
Control
Core
AHB Slave (Mem)
Figure 1-3. SMC Controller.
1.5 Generic DMA Engine (GDMA)
A FOUR(4) channel DMA controller is built in for memory to memory, memory to peripheral, and peripheral to
memory transfers with a shared buffer. The DMA engine supports four priority levels and group round robin
arbitration scheme and 8, 16, and 32 bit data width transactions. It also supports a hardware handshake with
UART to reduce the processor interrupt interactions and enhance system performance.
1.6 Embedded 4-port Gigabit Switch Engine
This chip integrates a 4-port Gigabit Switch Engine with two 10/100/1000 Mbps RGMII/MII ports, one internal
CPU port and one hardware NAT hook up port. It is designed with a share-memory switching fabric with 4
gigabit-ports non-blocking capability. Packets are relayed by a reliable store-and-forward scheme. It is a VLAN
aware L2 switch with the ability to identify L3 and L4 packets and with L3/L4 check-sum off-load at CPU port.
1.6.1 Packet Format

The Gigabit Switch Engine can support Ethernet/802.3 format packet with packet length up to 9K bytes. The
acceptable packet length is controllable through bit [5:4] of “Switch Configuration Register” (Offset 0x04). And
the MAC ports can do auto-payload padding when the transmitting packet length is less than 64 bytes. Each
packet transmitted from the MAC ports always meet the 64 bytes minimum packet length requirement. And for
VLAN tagged transmission packet, 68 bytes are the minimum packet length.
The Switch Engine also supports proprietary Inter-Switch-Tagging (IST) to share necessary information
between CNS11XX/STR91XX and external switch controller. This feature can support spanning tree protocol
and force-routeing to any port of external switch controller. The register “Inter Switch Tag Control Register”
(Offset 0x90) controls this function’s ON/OFF at each port. When turn on IST at a port, the MAC treat each
received packet as VLAN tagged, no matter what is the value at TPID field. At normal case, the TPID field is
with the value of 0x8100 to identify this packet is VLAN tagged. But at IST mode, user can replace this field
with user-defined value and route the packet to CPU by proper setting a static MAC address at ARL table.
The Switch Engine supports PPP-over-Ethernet (PPPoE, RFC2516) Header insertion and removal. PPPoE
provides the ability to connect a network of hosts (LAN) over a simple bridging access device (Home Gateway)
to a remote Access Concentrator (WAN). It provides access control and billing functionality in a manner similar

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Data Sheet
to dial-up services using PPP. For packets from LAN to WAN, the WAN port MAC can insert PPPoE header
into the transmitting packets according to CPU’s (slow path) or HNAT’s (fast path) instruction. On the contrary,
for packets from WAN to LAN, the LAN port MAC can remove PPPoE header from the transmitting packets
according to CPU’s or HNAT’s instruction.
1.6.2 VLAN
The Switch Engine supports port-based and 802.1q tag-based VLAN. And it can support up to 8 VLANs, and
these VLAN IDs can be any of the 4K VLAN space. User can set necessary 12-bits VIDs at registers
0x060~0x06C. Internally, Switch Engine uses VLAN Group ID (GID) 0~7 to represent these VLAN IDs. When
received packet is VLAN tagged, use tagged ID as VLAN ID, and compare it with those VID registers to get a
GID (0~7). Otherwise, use ingress port GID (register 0x05C) as the packet’s GID.
These Switch Ports support VLAN ingress check (bit 24 of register 0x008~0x010). If ingress check enable, and
the ingress port is not a member of the tagged VLAN group (register 0x070), then the packet will be dropped.
Egress check is performed through VLAN Port Map Register (0x070). When the egress port is not a member of
the VLAN group, the packet will be dropped. Each egress packets can be tagged or un-tagged. The setting is
based on per VLAN per port (0x074). If tagging/un-tagging will modify the transmit packet, CRC will be
re-generated (crc_stripping, bit21 of register 0x004, must be set to high). If the egress port is VLAN tagged, the
VLAN ID (12-bits), related to the GID (0~7), will be inserted to the VLAN tag.
1.6.3 Address Resolution Logic

The Address Resolution Logic (ARL) supports 1024 entries with 2-way hash. And it supports 3 kinds of hash
algorithms (Direct, XOR48, and XOR32 mode, bit 7~6 of register 0x004). It supports Shared-VLAN-Learning
(SVL) and Independent-VLAN-Learning (IVL), and is configured by bit 22 of register 0x004. At SVL mode, only
MAC address is used to hash the table. Therefore, only a unique MAC address is allowed in the address table.
And at IVL, both MAC address and VLAN ID are used to hash the table. Therefore, the same MAC address
with different VLAN ID is allowed in the address table.
These ARL entries are software touchable through register 0x050~0x058. It provides a friendly valid entry
search command. The search scheme can sequentially response valid entries content to these access
registers (0x054, 0x058). It also provides a look-up command. Software just issue a look-up command with
MAC address and VLAN ID (if IVL), the look-up result will be showed at the access registers (0x054, 0x058). Of
course, it also provides a write command to insert static entry into the address table.
1.6.3.1 Address Table Format
SA Filter My_MAC VLAN AGE Port_Map MAC Address

(1) (1) (3) (3) (3) (48)
The relevant sub-fields are specified as below:

MAC Address field: 48 bits MAC address field.
Port_Map field: Bit 0 is for MAC port 0, bit 1 is for MAC port 1, and bit 2 is for CPU port.
Age field: Aging of the dynamic entries.

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Data Sheet
The aging time is configurable through bit 3~0 of register 0x004. And per port has an aging enable
control bit (bit 22 of reg. 0x004, 0x008) to control if each MAC address entry belonging to the port to
be aged out or not. Unicast and Multicast addresses share the same table. Multicast addresses
entries will not be aged out. The definition is showed below.
3’b000: invalid
3’b001: valid and new entry.
3’b010~3’b110: valid and age-old entry.
3’b111: static entry.
VLAN field: The VLAN field has 3 bits representing GID 0~7.
My_MAC field: The My_MAC bit indicates that the MAC address is the gateway’s MAC address.
SA Filter field: When set, and SA hit the entry, the packet will be dropped.

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Data Sheet
1.6.3.2 Forwarding Flow Chart
The major forwarding flow chart of a packet received from a MAC port is illustrated in Figure 1-4. And
several detailed flow charts are also illustrated below.
Receive a Packet from a M A C Port
Port State Filtering
SA Security Filtering
D A Filtering
V L A N Egress Check
Re-direct
Forward the Packet to Destination Ports
Figure 1-4. Major Flow of Packet Forwarding

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Data Sheet
Start
Ingress Port in Blocking

State? no A
(bit 20 of 0x008 or 0x00C)
yes
Forward to
BPDU Packet? yes
CPU
no
Only BPDU allow? Forward to

(bit 21 of 0x008 or 0x00C) no
CPU
yes
Drop
Figure 1-5. Flow of Port State Filtering

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Data Sheet
SA look up
SA learning disable and in SA

SA match Ingress
security mode? yes yes
Port?
(bit 19, 23 of 0x008 or 0x00C)
no
no
drop
yes SA filtering bit is

set?
no
drop B
Figure 1-6. Flow of SA Security Filtering

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Data Sheet
Unknown VLAN? yes
Drop
no
Ingress check enable and

ingress port not in the yes
VLAN?
(bit 24 of 0x008, 0x00C)
Drop
no
My-MAC and
IPv4H5NF yes
Packet?
HNAT ensable?
(bit 23 of 0x004) no
no yes
Send to Send to
HNAT CPU
My-MAC and
not IPv4H5NF yes
Packet?
Send to
no CPU
Figure 1-7. Flow of DA Filtering (1 of 3)

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Data Sheet
Forward BC packet to
DA is BC? yes CPU disable? yes
(bit 27 of 0x008, 0x00C)
Flood to
no
other
MACs*
no
Flood to CPU
and other E
MACs*
DA is reserved MC and
Reserved MC Filtering yes
enable?
(bit 18 of 0x004)
no Drop
Forward MC packet to
DA is MC? yes CPU disable? yes
(bit 26 of 0x008, 0x00C)
Follow look
Hit a ARL entry? yes up result*
no
no
Flood to other
E
MACs*
no
yes Follow look

Hit a ARL entry?
up result*
no
Flood to CPU
D and other E
MACs*

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Data Sheet
Forward unknown packet Flood to other

Hit a ARL entry? no to CPU disable? yes
MACs*
(bit 25 of 0x008, 0x00C)
no
Flood to CPU
yes and other E
MACs*
Destination Port is
yes Drop
Source Port?
no
Follow look
up result*

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Data Sheet
M ask by
VLAN
group
Empty TX Port
M ap?
yes drop
no
Figure 1-10. Flow of VLAN Egress Check

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Fire_wall mode and

HNA T enable and yes
IPv4H5NF packet?
(bit 24 of 0x004)
no Send to
HNA T
Fire_wall mode? yes
Send to
CPU
no
Skip_L 2_L ook_Up? yes

(bit 29, 28 of 0x004)
Send to
CPU
no
Send to
Destination
Ports
Figure 1-11. Flow of Re-direct
1.6.3.3 NIC Mode

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Data Sheet
In general, the CRC and VLAN tag will be stripped off for each received packet. But when NIC mode is set (bit
30 of 0x004), these two MAC ports behave as purely two NICs and all received packets will not be modified.
Therefore, CPU can receive original packets when they are being forwarded to CPU. Note that, at this mode,
Software should set necessary static entries into the ARL table and above forwarding rules still apply. In
general, NIC has a miscellaneous mode, which all of incoming packets will be received to CPU. The switch
engine also has a scheme to emulate the miscellaneous behaviour. Per port has a control bit
“Skip_L2_Look_Up” (bit 29, 28 of reg. 0x004) to enable or disable this function.
1.6.4 Flow Control

These two 10/100/1000 MAC ports fully support IEEE 802.3x flow control at full-duplex mode. The 802.3x flow
control function ON/OFF is dependent on auto-negotiation’s result or dependent on force mode if
auto-negotiation function is off. And at half-duplex mode, back-pressure flow control is provided. The
back-pressure flow control has 3 kinds of operation modes and is configured by bit [17:16] of register 0x004.
The 1st is called “smart back pressure”. When consecutive JAM packet number reach the jam_no threshold (bit
[15:12] of reg. 0x004), the following incoming packet will be received, not be back-pressured. The 2nd is called
“force collision mode”. At this mode, all of incoming packets will be jammed until back-pressure condition
released. The 3rd is called “force carrier mode”. At this mode, the jammed port always transmits jam packets to
occupy the channel. Per port back pressure flow control can be ON/OFF by bit[17] of register 0x008 and
0x00C.
Per port flow control assert or release is controlled by 3 factors. They are input queue threshold, output queue
threshold, and global buffer threshold. These thresholds can be set through “Flow Control Global Threshold
Register (0x044)” and “Flow Control Port Threshold Register (0x048)”. Only the above 3 thresholds all reached,
the port’s flow control assert, and then 802.3x flow control packet is sent at full-duplex mode or back-pressure
at half-duplex mode. In order to smoothing packet flow through put, there is a hysteresis scheme at global
threshold. When occupied pages of packet buffer reach “Flow Control Assert Threshold (bit [6:0] of reg. 0x044)”,
global threshold flag assert. And only when occupied pages of packet buffer less than “Flow Control Release
Threshold (bit [14:8] of reg. 0x044)”, the global threshold flag de-assert. There are different global buffer
threshold for unicast packets and multicast/broadcast packets.
The flow control scheme supports “Head of Line Blocking Prevention” through input queue threshold and output
queue threshold. And there are 4 priorities output queue per port to support high resolution QoS. Each output
queue has a dedicate output queue threshold to provide more favours to high priority packets. There is no
independent register setting for input queue threshold. The input queue threshold is the total sum of 4 output
queue thresholds.
1.6.5 Quality of Service (QoS)

As indicated above, there are 4 priority output queues per port to support high resolution QoS. And each
packet’s priority can be set by received port, priority field of VLAN tag, TOS of IP, and UDP port number. Each
port has a corresponding port priority setting at bit [20:18], [17:15], and [14:12] of reg. 0x014 for CPU port, MAC
port 1, and MAC port 0 respectively. For each received packet, it has a receive port priority from the above port
priority settings. For each VLAN tagged packet, it has a tagged priority. For each IP packet, each TOS number
of 0~63 has a corresponding priority setting at registers 0x01C~0x038. For each UDP packet, if the source port
number or destination port number of UDP header matches the register setting “udp_defined_port” (bit [15:0] of
reg. 0x018), then the “udp_pri” (bit [23:21] of reg. 0x014) will be the UDP priority of the received packet. The
final packet priority is the highest one of the above 4 individual packet priorities. When the packet is being
forwarded to an output port and with VLAN tag, the tagged priority can be the final priority or the original VLAN
tagged priority, and the option is controlled by bit [2] of reg. 0x014.

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Data Sheet
There are 3 kinds of output scheduling for the 4 priority queues: Weighted-Round-Robin (WRR) mode, Strict
Priority Mode, and Mix Mode. The operation mode can be selected by bit [1:0] of reg. 0x03C. At WRR mode,
there are 5 weightings (1, 2, 4, 8, 16) for each priority queue, which can be set through bit [18:4] of reg. 0x03C.
If there are packets waiting for transmission among these queues, these queues’ through put will obey the
weighting ratio. At Strict Priority Mode, only when higher priority queue is empty, lower priority queue is allowed
to transmit queued packets. And at Mix Mode, only when the highest priority queue (Q3) is empty, other queues
(Q2, Q1, Q0) have the opportunity to transmit packets, and obey Q2, Q1, and Q0’s weightings.
1.6.6 Broadcast Storm Prevention and Egress Rate Limit

These 2 MAC ports support “Broadcast Storm Prevention”. Broadcast packets, Multicast packets and unknown
packets can be configured individually to be included into Broadcast-Storm-Rate control (bit [31:29] of reg.
0x008, 0x00C). The Broadcast-Storm-Rate is limited by “BCS_rate” (bit [27:24] of reg. 0x040). The lowest
configurable rate is 64kbps. When BC packets incoming rate exceeds the setting, extra packets will be
dropped.
These MAC ports also support egress rate limit. The egress rate control scheme is Leak-Bucket and the
maximum Bucket size is configurable by bit [1:0] of reg. 0x040. The available bucket sizes are 1.5K bytes, 3K
bytes, 9K bytes, and 12K bytes. Per port has an egress rate setting (bit [22:2] of reg. 0x040). And configurable
egress rate is from 64Kbps to 1Gbps.
1.6.7 DMA Scheme

The DMA controller, within the embedded switch engine, forwards packets between host memory and switch’s
packet memory. It implements a sophisticated descriptor ring architecture, and support multiple segments for a
TX/RX packet to fit modern zero-copy socket. It also supports Read Alignment and Write Alignment for both
transmit path (To Switch) and receive path (From Switch). The Read Alignment feature enhances the DMA
performance in cache line oriented systems. Read a segment starting from a non-cache line aligned address
may cause low performance. To resolve this performance anomaly, the DMA controller attempts to terminate
transmit DMA cycles on a cache line boundary and start the next transaction on a cache line aligned address.
The Write Alignment feature allows a packet to be stored at offset 2 bytes from a cache line boundary at host
memory. This feature meets protocol stack’s 2-byte offset requirement for high-level RTOS or Linux, and
achieves zero-copy from Switch driver to TCP/IP protocol-stack.
It also supports TCP/UDP/IP checksum offload for incoming and outgoing packets. The detailed TX/RX
descriptor formats are illustrated below.
TX Descriptor Format:

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Data Sheet
Segment D ata Pointer[31:0]
C
E I I U T
O F L F PRI F PM A P Segment D ata L ength
O N C C C
W S S P [ 2:0] R [ 2:0] [15:0]
R T O O O
N
I I
N SI D N V ID
Rserved [23:0]
S [ 2:0] S [ 2:0]
S V
Reserved [31:0]
*The highlighted (shaded) fields are per Descriptor sensitive; the other fields are per Packet sensitive
(meaningful only at the descriptor with FS=1)
Offset# Bit# Symbol Descriptions

0 31:0 SDP Segment data pointer: point to the starting address of this transmitted data segment.
The pointer is allowed to be only byte alignment.
4 31 COWN CPU Ownership: This bit, when set, indicates that the descriptor owned by CPU.
When cleared, it indicates that the descriptor own by the DMA. The DMA sets this bit
when the relative segment data is transmitted and return it to the CPU.
4 30 EOR End of descriptor ring: This bit, when set, indicates that this is the last descriptor in
the descriptor ring. When DMA’s internal transmit pointer reaches here, the pointer
will return to the first descriptor (TX_DES_BASE, reg. 0x110) of the descriptor ring
4 29 FS First Segment descriptor: This bit, when set, indicates that this is the first descriptor
of a TX packet, and that this descriptor is pointing to the first segment of the packet.
4 28 LS Last Segment descriptor: This bit, when set, indicates that this is the last descriptor
of a TX packet, and that this descriptor is pointing to the last segment of the packet
4 27 INT Interrupt: When set, DMA will generate an interrupt (txtc_int) after sending out this
packet (not this segment only).
4 26 FP Force Priority: Force the Ethernet switch to treat this packet as priority indicated in
PRI field. This also forces the switch to insert a VLAN Tag (if INSV=1) with a priority
field equals to the PRI[2:0].
4 25:23 PRI The Forced Priority: 7 is the highest priority; 0 is the lowest priority
4 22 FR Force Route: Force the Ethernet switch to forward the packet to port(s) indicated by
PMAP[2:0]
4 21:19 PMAP The forced port map: PMAP[2] is the CPU port; PMAP[1] is the MAC port 1;
PMAP[0] is the MAC port 0.
4 18 ICO Enable IP checksum generation offload
4 17 UCO Enable UDP checksum generation offload
4 16 TCO Enable TCP checksum generation offload
4 15:0 SDL Segment Data length: indicate the length of this transmitted segment in bytes
8 31:8 Reserved

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8 7 INSS Insert PPPoE header with the session ID indexed by SID[2:0]
8 6:4 SID PPPoE Session index. There are 8 user-predefined PPPoE session IDs in the
Ethernet switch (Session ID 0~7 Register).
8 3 INSV Insert VLAN Tag with the VLAN ID indexed by GID[2:0]
8 2:0 GID VLAN Group ID 0~7. There are 8 user-predefined VLAN IDs in the Ethernet switch
(VLAN Group ID 0~7 Register).
12 31:0 Reserved
RX Descriptor Format:
Segment D ata Pointer[31:0]
C
E I L Segment D ata L ength (when FS=0)/
O F L SP HR Prot
O P 4 W hole Packet L ength (when FS=1)
W S S [ 1:0] [ 5:0] [ 1:0]
R F F [15:0]
N
Reserved [31:0]
Reserved [31:0]
*The highlighted (shaded) fields are per Descriptor sensitive; the other fields are per Packet sensitive (meaningful
only at the descriptor with FS=1)

0 31:0 SDP Segment data pointer: point to the starting address of this received data segment.
The pointer must be 4-word cache line alignment or offset 2 bytes from the cache line
boundary.
4 31 COWN CPU Ownership: This bit, when set, indicates that the descriptor owned by the CPU.
When cleared, it indicates that the descriptor own by the DMA. The DMA sets this bit
when the relative segment data is received.
4 30 EOR End of descriptor ring: This bit, when set, indicates that this is the last descriptor in the
descriptor ring. When DMA’s internal receive pointer reaches here, the pointer will
return to the first descriptor (RX_Des_BASE, reg. 0x114) of the descriptor ring
4 29 FS First Segment descriptor: This bit, when set, indicates that this is the first descriptor of
a RX packet, and that this descriptor is pointing to the first segment of the packet.
CPU should reset this bit when it allocates this descriptor.
4 28 LS Last Segment descriptor: This bit, when set, indicates that this is the last descriptor of
a RX packet, and that this descriptor is pointing to the last segment of the packet
CPU should reset this bit when it allocates this descriptor
4 27:26 SP The source port of the received packet. SP=0 is the MAC port 0; SP=1 is the MAC port
1; SP=2 is the CPU port itself.

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4 25:20 HR HNAT reason: Any non-zero values represent a distinct reason to tell CPU why the
packet is forwarded to CPU by HNAT. (Please refer to the HNAT Functional description
for details)
4 19:18 Prot Protocol:
2’b00: IPV4H5 & not TCP & not UDP (can do IP checksum)
2’b01: IPV4H5NF & UDP (can do IP/UDP checksum)
2’b10: IPV4H5NF & TCP (can do IP/TCP checksum)
2’b11: Others (no any checksum offload is done)
4 17 IPF IP checksum check fail. This bit is meaningful only when Prot != 2’b11
4 16 L4F Layer-4 checksum fail (TCP or UDP over IP). This bit is meaningful only when
Prot=2’b01(UDP) or 2’b10(TCP)
4 15:0 SDL/WPL Segment Data Length/Whole Packet Length: indicates the length of this received
segment in bytes when FS=0, or the length of this received packet when FS=1.
CPU should set SDL to the allocated segment buffer length (in bytes) when it allocates
the descriptor. DMA will modify this field to the actual data length it fills for the non-first
segment (FS=0) or the whole packet length for the first segment (FS=1).
8 31:0 Reserved
12 31:0 Reserved
1.7 Hardware NAT (HNAT) Engine
z Support wire-speed (1000Mbps x 2) NAT or NAPT

z Support TCP SYN-flooding attack avoidance
z Support 1K/2K/4K(selectable) ARP cache entries using 2-way hash
z Support 1K/2K/4K(selectable) NAPT entries using 2-way hash
z Hardware can build dynamic NAPT and ARP entries automatically
z Support Packet Filtering (ACL) by matching packets against selected header fields(IP, L4 DP/SP,
Protocol, physical source port, TCP flags, ICMP type/code) defined in the rule table
z Support 128 complex rules or 192 simple rules
z Support NAT/Virtual server by setting actions in the rule table
z Support Policy based routing by setting actions in the rule table
z Support IP/UDP/TCP checksum recalculation
z Replace MAC DA/SA and decrease IP TTL automatically
z Support 256 public IP addresses
z Support 4 next hop MAC addresses for policy based routing
z Support 4K private IP addresses
z Support one PPPoE session for each public IP
z Add/Remove PPPoE header in hardware
z Support user-defined “rule reason” attached in packet descriptor when packet is forced to CPU port
cause of rule matched
z Support packet redirection to a port without modification
z Support H/W based aging for NAPT/ARP entries
1.7.1 General introduction

HNAT is a special hardware function that is hooked into an internal port of the embedded switch. The
relationship among the embedded switch engine, HNAT and CPU is shown in Figure 1-12. In general,
the embedded switch will forward packets to the HNAT virtual port when the following conditions are
met at the same time:

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1. The packet’s destination MAC address matches the MAC address of the VLAN it belongs to.
2. The packet is in the form of IPV4H5NF (IP version 4, header length == 5, no fragment). The IP
packet defined here could be the form of IPoE (type = 0x0800) or PPPoE (type = 0x8864,
protocol=0x0021)
3. The packet is a good packet (correct L2 CRC)
With companion software package “SmartHNAT” for Linux BSP, users can seamlessly enable HNAT
and experience Giga wire speed throughput of NAT/NAPT function for SOHO Router. Please contact
Star sales for detail information.
CPU DRAM
Slow Path
Embedded
Switch
HNAT SRAM
DMA
Switching Fabric
MAC_TX MAC_RX
Layer 2
Fast Path
Switch Path
Figure 1-12. Fast- and Slow-paths of Embedded Switch with Hardware NAT
1.8 Reserved
1.9 USB 2.0/1.1 Host Controller with Integrated Transceivers
The embedded USB host controller consists of an USB1.1 Host Controller (OHCI), an USB2.0 Host Controller
(EHCI), and TWO USB1.1/2.0 PHYs. The block diagram is showed in the Figure 1-13. The USB1.1 Host
Controller supports all of full speed (12Mbps) and low speed (1.5Mbps) devices, which are compliance with USB
Specification, Version 1.1. It embeds a 64-bytes FIFO and supports Control Transfer, Bulk Transfer, Interrupt
Transfer, and Isochronous Transfer and can connect up to 127 devices at the same time. The USB2.0 Host

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Controller supports high speed (480Mbps) devices, which are compliance with USB Specification, Version 2.0. It
embeds TWO 1K-bytes FIFOs, one for TX and one for RX, and supports Control Transfer, Bulk Transfer, Interrupt
Transfer, and Isochronous Transfer and can connect up to 127 devices at the same time.
AHB (DRAM)
AHB (CPU)
Interrupt
EXP
AHB Master/Slave AHB Master/Slave
Interface Interface
EHCI OHCI
DMA DMA
List List
Processor Processor
Host Host Serial CSR

CSR
Parallel Interface
Interface Engine
Engine (HSIE)
(HPIE) The grayed
sections will be
Root Hub Root Hub
powered down on
standby
Port Router
Power Down Logic
PowerDown
From PMU
RemoteWake
USB 2.0 PHY To PMU
USB 2.0 PHY

ClockUSB 2.0 Transceiver Macrocell Interface (UTMI)
Generator
Digital Block (common block)
This section and PHY will
Analog Front End PLL always be powered
HS XCVR FS/LS XCVR
BIAS
Data+ Data- Data+ Data-

Expansion Port 0 Expansion Port 1
Figure 1-13. USB2.0/1.1 PHY/Controller Block Diagram
1.9.1 AHB Interface and DMA

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There are a dedicated AHB Master Interface and AHB Slave Interface for each EHCI controller and OHCI
controller. An AHB Master Interface and related DMA controller co-work to do DMA of frame data and frame
descriptor between external DRAM and the USB Host Controller. And AHB Slave Interface is for the processor to
configure the USB Host Controller
1.9.2 List Processor
The List Processor manages the data structures from the Host Controller Driver and coordinates all activities in
the Host Controller. The List Processor has three main control sections that operate hierarchically:
List Control -- highest level of the control hierarchy:

It schedules which type of list (Isochronous, Interrupt, Bulk, Control) is to be processed.
Endpoint Descriptor (Queue Head Descriptor) Control -- middle level of the control hierarchy:
Once the List Control has detected a valid list to process, this controls the loading, processing of the
Transfer Descriptor, and write-back of the Endpoint Descriptor for the current list.
Transfer Descriptor (Queue Head Transfer Descriptor, iTD Descriptor, SiTD Descriptor) Control -- lowest
level of the control hierarchy.
Once the Endpoint Descriptor (QH) Control has loaded a valid ED (QH), this controls the loading,
processing of the data transfer, and write-back of the Transfer Descriptor (qTD, …) for the current ED (QH).
1.9.3 Host Parallel Interface Engine (HPIE) or Host Serial Interface Engine (HSIE)
The embedded USB host controller contains engines of HPIE and HSIE for USB2.0 and 1.1 respectively.
The HPIE (HSIE) is responsible for managing all transactions to the USB. It controls the bus protocol, packet
generation/extraction, data parallel-to-serial conversion, CRC coding, bit stuffing, and NRZI encoding.
All the transactions on the USB are requested by the List Processor and Frame Manager(not shown in the block
diagram). After the List Processor retrieves all information necessary to initiate communication to a USB device, it
generates a request to the HPIE(HSIE) accompanied by endpoint specific control information required to
generate proper protocol and packet formats to establish the desired communication pipe. The data buffer
provides a data path for the data packets and controls the number of bytes transferred.
1.9.4 Port Router
The USB Host controller comprises one high-speed host controller, which implements the EHCI programming
interface and one OHCI host controller. This configuration is used to deliver the required full USB 2.0-defined port
capability; e.g. Low-, Full-, and High-speed capability for every port. Figure 1-14 shown below illustrates a simple
block diagram of the port routing logic and its relationship to the EHCI and OHCI host controllers.
There exists one transceiver per physical port and each host controller module has its own port status and control
registers. The EHCI controller and OHCI controller have individual port status and control registers for every port.
Either EHCI or OHCI host controller can control each physical transceiver. Routing logic lies between the
transceiver and the port status and control registers. The port routing logic is controlled from signals originating in
the EHCI host controller. The EHCI host controller has a global routing policy control field and per-port ownership
control fields. The Configured Flag (CF) bit (defined in OP register of EHCI) is the global routing policy control. At
power-on or reset, the default routing policy is to the OHCI controllers. In general, when the EHCI owns the ports,
the OHCI host controller’s port registers do not see a connect indication from the transceiver. Similarly, when the
OHCI host controller owns a port, the EHCI controller's port registers do not see a connect indication from the

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Data Sheet
transceiver.
Figure 1-14. Port Router Block Diagram
1.10 PCI Host Bridge
The PCI Host Bridge supports PCI Specification v2.1 and 2.2 protocols. The PCI bus can be run at clock
frequency up to 66MHz and supports up to 3 external PCI devices simultaneously. The host bridge is designed
for interfacing the Host CPU with PCI bus and forward data access from both the upstream and downstream
directions. The host bridge consists of three function units: AHB bus slave, AHB bus master, and PCI interface.
The AHB bus and the PCI bus can operate at two different clock domains. Any bus mastering devices on the AHB
bus can also access the host bridge. The core has multiple data buffers to achieve high-speed data posting,
prevent bus deadlock, and allow clock domain crossing for the data.
The host bridge core allows the CPU to initialize the entire system during power-up reset using standard PCI
protocol. Both type-zero and type-one transactions are supported. The CPU requests configuration access on the
PCI bus by writing to or reading from the CONFIG_ADDR (0xA400_0000) and CONFIG_DATA (0xA000_0000)
registers. User can view the section 1.10.1 for detail.
The host bridge initiates memory or IO read and write cycles on the PCI bus upon AHB bus requests. It contains
4 write buffers, two in the AHB bus clock domain and two in the PCI clock domain, to post-write data. Data can be
written from the AHB bus, at the same time, write operation is running on the PCI bus.
Reading by the AHB bus is handled as delayed-read. The AHB slave retries the CPU, while it is reading data from
the PCI bus. Instead of inserting wait state while waiting for return data, the AHB slave uses AHB bus “retry” to
free up the AHB bus for other accesses. Once read data is ready from the PCI bus, data return to the CPU with
zero wait state in subsequent read. The primary benefit of the delayed-read method is to prevent deadlock
between the PCI and AHB buses.
When accessed by an external PCI bus master, the host bridge functions as a PCI target. The PCI target
contains two write-buffers and a read-buffer to handle write posting and transferring data across the two clock
domains. The read/write request received from the PCI bus is forwarded upstream to the AHB bus through the
built-in AHB bus master.

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Data Sheet
Figure 1-15. PCI Host Bridge
1.10.1 PCI Configuration Cycle
The PCI Host Bridge provides an access window (CONFIG_ADDR and CONFIG_DATA registers) for CPU to
configure external PCI devices and the bridge itself. The configuration mechanism implemented by the host
bridge is the PC-compatible standard mechanism, defined by the PCI specification as Configuration Mechanism
#1. Both Type 0 and Type 1 configuration cycles are supported.
Type 0 and Type 1 configuration cycle implies that the host bridge is capable of configure PCI agents in the same
bus segment as well as PCI agents in the other side of a PCI-to-PCI bridge. In other words, the host bridge
supports multiple segments PCI bus.
To initiate a PCI configuration access, the CPU is first required to write the address into the CONFIG_ADDR
register. The bridge will translate the CONFIG_ADDR information into a configuration register address based on
whether it is a Type 0 or Type 1 configuration access. The format of the CONFIG_ADDR register and the
translation scheme of type 0 and type 1 are showed at the following Figure 1-16 and Figure1-17.
The CPU then read or write to the CONFIG_DATA register to initiate a configuration read or write access. The
read/write access to the CONFIG_DATA triggers the host bridge to initiate PCI configuration access to the PCI
bus. If it is a read, configuration data read from PCI bus is deposited to the CONFIG_DATA register and returned
to the AHB bus. If it is a write access, data written into the CONFIG_DATA register is written to the PCI bus as
configuration write data.

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Data Sheet
31 30 24 23 16 15 11 10 8 7 2 1 0
D evice Function Register
Enable Reserved Bus number 00
number number number
Function Register
Only one bit here is ¡ §
on¡¨ 00
number number
31 11 10 8 7 2 1 0
Figure 1-16. Type 0 Translation
31 30 24 23 16 15 11 10 8 7 2 1 0
Device Function Register
Enable Reserved Bus number 00
Device Function Register

Reserved Bus number 00
31 24 23 16 15 11 10 8 7 2 1 0
Figure 1-17. Type 1 Translation
1.11 PCMCIA (16-bit) Interface
The PCMCIA host bridge can support one PCMCIA socket direct connection, which is complaint to PCMCIA v2.1
specifications, for 8-bit or 16-bit card interface. It can allow 16-bit data and 20-bit address accessing. The block
diagram of PCMCIA controller is shown in Figure 1-18.

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Data Sheet
PCMCIA_HBA
AHB_Slave_Mem
AHB_Slave_Att
PCMCIA
AHB Protocol PCMCIA
Interface Controller Interface
AHB_Slave_IO
AHB_Slave_Reg
Figure 1-18. PCMCIA_HBA Block Diagram
The PCMCIA Host Bridge consists of 4 AHB slaves and a PCMCIA protocol controller. The AHB_Slave_Mem,
AHB_Slave_Att, and AHB_Slave_IO are the interfaces for an AHB Master (for example CPU) to access external
PCMCIA device’s common Memory, Attribute memory, and I/O space, respectively. The transaction can be 8-bit
or 16-bit wide. The AHB_Slave_Reg is the interface for CPU to configure and control internal registers of
PCMCIA Protocol Controller, and the transaction must be 32-bit wide.
1.11.1 Memory Function

The following tables show Common Memory Read/Write functions and Attribute Memory Read/Write functions.
Table 1-1. Common Memory Read Function

Function Mode REG_n CE2_n CE1_n PA0 POE_n PWE_n PD[15:8] PD[7:0]
Standby Mode X H H X X X High-Z High-Z
Even Byte Access H H L L L H High-Z Even-Byte
Odd Byte Access H L H H L H Odd-Byte High-Z
Word Access (16 bits) H L L L L H Odd-Byte Even-Byte
Table 1-2. Common Memory Write Function

Even Byte Access H H L L H L High-Z Even-Byte
Odd Byte Access H L H H H L Odd-Byte High-Z
Word Access (16 bits) H L L L H L Odd-Byte Even-Byte

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Table 1-3. Attribute Memory Read Function

Even Byte Access L H L L L H High-Z Even-Byte
Odd Byte Access L L H H L H Odd-Byte High-Z
Word Access (16 bits) L L L L L H Odd-Byte Even-Byte
Table 1-4. Attribute Memory Write Function

Even Byte Access L H L L H L High-Z Even-Byte
Odd Byte Access L L H H H L Odd-Byte High-Z
Word Access (16 bits) L L L L H L Odd-Byte Even-Byte
1.11.2 I/O Function

The PCMCIA I/O mode supports 8-bit and 16-bit access. The access width is configured by setting the register bit
“IOIS16” (bit 2 of Card Detect and Global Control Register). The following tables show I/O Read/Write functions.
Table 1-5. I/O Read Function

Function Mode REG_n CE2_n CE1_n PA0 IORD_n IOWR_n PD[15:8] PD[7:0]
Byte Access L H L X L H High-Z Even-Byte
(IOIS16=0) Odd-Byte
Word Access L L L L L H Odd-Byte Even-Byte
(IOIS16=1)
Table 1-6. I/O Write Function

Function Mode REG_n CE2_n CE1_n PA0 IORD_n IOWR_n PD[15:8] PD[7:0]
Byte Access L H L X H L High-Z Even-Byte
(IOIS16=0) Odd-Byte
Word Access L L L L H L Odd-Byte Even-Byte
(IOIS16=1)
1.12 High-speed UART Controller
The embedded high speed UART controller is compliant to 16C550 UART, and supports hardware CTS/RTS flow
control. It has two 8-bitwide FIFOs with depth of 16 for TX and RX, and supports a hardware handshake with
Generic DMA to reduce the processor interrupt interactions and enhance system performance. Its baud rate is
programmable and can be up to 1.5Mbps.
1.13 General Purpose Inputs/Outputs (GPIO’s)
There are totally 21 programmable I/O pins and each pin can be independently configured to input or output
direction, and can be configured as external interrupt input. The triggering can be rising-, falling-, both-edges, or

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Data Sheet
high-/low-level. It should be noted that these GPIO pins are shared with pins of other functional groups as
illustrated in Table 1-7.
Table 1-7. GPIO Pin Assignment and Shared Pins

GPIO Pin No. Pin No. Pin No. Shared Pin Name Remark
Index CNS1101 CNS1102 CNS1104/ [Function Group] (Enable GPIO function)
CNS1109/ CNS1105/ STR9104
STR9101 STR9102
STR9109 STR9105
PQFP-208 BGA-304 LFBGA-257
GPIO [0] 175 A12 B9 ICK/TCK [Multi-ICE] Configurable by SA[4]
(SA[4] not pull-up)
GPIO [1] 176 C11 C9 IMS/TMS [Multi-ICE] Configurable by SA[4]
(SA[4] not pull-up)
GPIO [2] 177 B11 A8 IDIO/TDO [Multi-ICE] Configurable by SA[4]
(SA[4] not pull-up)
GPIO [3] 178 A11 A7 EXTGOICE/DBGRO [Multi-ICE] Configurable by SA[4]
(SA[4] not pull-up)
GPIO [4] 164 B16 B16 UR_TXD [UART] Configurable by SA[9]
(SA[9] not pull-up)
GPIO [5] 165 B15 B15 UR_RXD [UART] Configurable by SA[9]
(SA[9] not pull-up)
GPIO [6] 166 C14 C14 UR_CTS [UART] Configurable by SA[9]
(SA[9] not pull-up)
GPIO [7] 167 A15 B12 UR_RTS [UART] Configurable by SA[9]
(SA[9] not pull-up)
GPIO [8] 49 P3 R4 P0_CRS [MII0] Configurable by SA[14]
(SA[14] external pull-up)
GPIO [9] 48 N3 R3 P0_COL [MII0] Configurable by SA[14]
GPIO[10] -- V4 R14 P1_CRS [MII1] Configurable by SA[15]
GPIO[11] -- V3 R13 P1_COL [MII1] Configurable by SA[15]
GPIO[12] -- H1 R2 CE1_n [PCMCIA] Configurable by SA[16]
GPIO[13] 24 * H2 P3 CE2_n [PCMCIA] Configurable by SA[16]
GPIO[14] -- J2 M3 IREQ_n [PCMCIA] Configurable by SA[16]
GPIO[15] -- G3 K1 RESET [PCMCIA] Configurable by SA[16]
GPIO[16] -- J3 U2 WAIT_n [PCMCIA] Configurable by SA[16]
GPIO[17] -- J1 N2 INPACK_n [PCMCIA] Configurable by SA[16]
GPIO[18] -- C13 C10 nTRST [Multi-ICE] Configurable by SA[5]
(SA[5] not pull-up)

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Data Sheet
GPIO Pin No. Pin No. Pin No. Shared Pin Name Remark
Index CNS1101 CNS1102 CNS1104/ [Function Group] (Enable GPIO function)
CNS1109/ CNS1105/ STR9104
STR9101 STR9102
STR9109 STR9105
PQFP-208 BGA-304 LFBGA-257
GPIO[19] -- C12 C12 TDI [Multi-ICE] Configurable by SA[5]
(SA[5] not pull-up)
GPIO[20] -- B12 C13 DBGACK [Multi-ICE] Configurable by SA[5]
(SA[5] not pull-up)
Note *: At CNS1101/CNS1109-STR9101/9109, GPIO[13] only has input function and interrupt function. Its output
function is disabled.
1.14 Timer
Two 32 bit general timers are implemented. They can count up or down, and be clocking at 1kHz or fine APB bus
clock (which can be programmable at 50MHz, 47.5MHz, etc. dependent on AHB clock frequency) if
high-resolution timer is needed.
1.15 Watch-Dog Timer (WDT)
A 32 bit down counter, clocking at 10Hz, is employed for WDT. The output signals at time out can be one or
combinations of system reset, and system interrupt.
1.16 Real-time Clock (RTC)
The clock frequency of RTC is 1Hz. RTC provides separate second, minute, hour, and day counters to off load
firmware complexity and reduce power consumption. It supports per second, per minute, and per hour auto alarm
and, of course, any real time alarm.
1.17 Interrupt Controller (INTC)
The RISC CPU supports Fast Interrupt Request (FIQ) and Standard Interrupt Request (IRQ), and the FIQ always
has higher priority than IRQ to be served. The Interrupt Controller has 23 interrupt inputs (showed in Table 1-8),
and each of these interrupts can be programmed as FIQ or IRQ and can be programmed as rising/falling edge or
high/low level trigger. The peripheral interrupt mapping is shown in the following table.
Table 1-8. Peripheral Interrupt Mapping

Interrupt
Interrupt Sources Triggering Scheme
Register(0x00)
Bit[0] Timer#1 Rising-edge Trigger
Bit[1] Timer#2 Rising-edge Trigger
Bit[2] Clock and Power Management Falling-edge Trigger
Bit[3] Watch Dog Timer Rising-edge Trigger
Bit[4] GPIO Pins Programmable Trigger
Bit[5] PCI External Interrupt 0 Low-level Trigger

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Bit[8] AHB-to-PCI Bridge Status High-level Trigger
Bit[9] Reserved High-level Trigger
Bit[10] UART High-level Trigger
Bit[11] Generic DMA Terminal Counter High-level Trigger
Bit[12] Generic DMA Error High-level Trigger
Bit[13] PCMCIA High-level Trigger
Bit[14] RTC High-level Trigger
Bit[15] External Interrupt Pin (EXT_INT) Low-level Trigger
Bit[16] Reserved Rising-edge Trigger
Bit[17] Reserved Rising-edge Trigger
Bit[18] Switch Controller Error High-level Trigger
Bit[19] Switch DMA TSTC (To-Switch-Tx-Complete) Rising-edge Trigger
Bit[20] Switch DMA FSRC (Fm-Switch-Rx-Complete) Rising-edge Trigger
Bit[21] Switch DMA TSQE (To-Switch-Queue-Empty) Rising-edge Trigger
Bit[22] Switch DMA FSQE (Fm-Switch-Queue-Empty) Rising-edge Trigger
Bit[23] USB 1.1 host controller Low-level Trigger
Bit[24] USB 2.0 host controller Low-level Trigger
Bit[25:31] Reserved -
1.18 Clock Generator and Power Management
A sophisticated Clock Generator is designed with clock domains as showed in Figure 1-19. Only a single external
25MHz +/- 50ppm reference input is required to generate all of clocks of individual functional blocks, such as
RISC CPU, AHB peripherals, APB peripherals, embedded Gigabit Switch, PCI Bridge, UART, USB, … etc. An
intelligent Power Management is also implemented. Major embedded functional blocks can be powered down by
programmable gated-clock, including Static Memory Controller, Gigabit Switch, USB Host Controller, PCI Bridge,
UART, etc. Moreover, it supports programmable operation clock frequency for CPU, AHB bus, APB bus, and PCI
bus to optimize Power/Performance ratio.

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Data Sheet
24M
DIV 2 UART Clock
DIV 3.25
14.769M
USB Host
Xtal 1.1 & 2.0 DIV 10 DIV 4
Pad 48M 12M
12M
PLL_USB DIV 4 DIV 4
DIV 25 480M 120M 30M
(Optional) 12M
66M
APB Clock 33M
22M
16.5M
DIV 1, 2, 3, 4
DIV 10 PLL_PCI DIV 5 PCI Clock
300M
30M 330M 66M
PLL_300
Xtal 125M
Pad 25M
25M 125M 2.5M
PLL_MAC DIV 1, 5, 50
MAC Clock
250M
225M
200M
175M CPU Clock
PLL_SYS DIV 1, 2, 3, 4
AHB Clock
DIV 1, 2, 3, 4
APB Clock
DIV 2
Timer Clock WD Clock RT Clock

DIV 1000 DIV 25 DIV 100 DIV 10
1KHz 10Hz 1Hz
Figure 1-19. Overall Clock Domains

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Data Sheet
1.19 Linear Regulators
Two on-chip voltage regulator controllers with two off-chip low-cost PNP BJT’s with output current rating up to 3A
are included to reduce system BOM—one for 3.3-to-1.8V translation and the other for 3.3-to-2.5V translation.
Figure 1-20, below, shows the typical application circuit for the Regulators. It should be noted that the regulated
1.8V and 2.5V can supply on-chip peripherals as well as off-chip key components in system(for example, gigabit
Ethernet PHY or external switch controller).
3.3V supply
PVDD AVDD_U33 AVDD_R33 2SB1132
V18_CTL Q1
Regulated
1.8V O/P
CVDD
AVDD_SP
AVDD_U External 1.8V
AVDD_UP Components
STR91XX
2SB1132
V25_CTL Q2
Regulated
2.5V O/P
PVDD_DDR
External 2.5V
PVDD_SW0
Components
PVDD_SW1
Note: When in MII mode, the related PVDD_SW0 or PVDD_SW1 should be supplied by 3.3V,
instead of 2.5V power.
Figure 1-20. Typical Application Circuits for Regulator

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Data Sheet
2.0 Pin Assignment and Descriptions

Some signals are assigned with dual purposes, so they may appear in more than one signal group.
The symbols in I/O Type column are described at Table 2-1.
Table 2-1. Pin Type Notations

I/O Type Function
I Digital Input Pin
O Digital Output Pin

I/O Digital Bi-directional Pin
PU Pin with Pull Up Resistor
Pin with Pull Down

PD
Resistor
A Analog Pin
AO Analog Output Pin
AI Analog Input Pin
P Power Supply
G Power Ground
Table 2-2. Pin Assignment and Description

Pin CNS1101 CNS1102 CNS1104/ I/O Pin Alternative
Name CNS1109/ CNS1105/ STR9104 Type Descriptions Pins
STR9101 STR9102 Pin Number
STR9109 STR9105
Pin Number Pin Number
PCI Interfaces
54, 55, 56, 57, V5, U5, U6, V6,
60, 61, 62, 63, U7, W6, V7, Y6
66, 67, 68, 69, Y7, V8, W8, Y8

70, 71, 72, 73, V9, W9, Y9, U10
AD[31:0] - I/O PCI Address and Data bus
87, 88, 89, 90, U12, Y13, W13, V13
91, 92, 93, 94, U13, W14, Y15, V14
96, 97, 98, 99, U14, Y16, V15, W16

101, 102, 103, 104 Y17, U15, V16, W17
C_BE_n[3:0] 65, 74, 86, 95 W7, V10, V12, W15 - I/O Bus command and Byte Enables, low active.
PAR 82 W12 - I/O Even parity across AD[31:0] and C_BE_n[3:0]

Cycle Frame is driven by the current master
FRAME_n 75 W10 - I/O to indicate the beginning and duration of the
access; low active.
Initiator Ready indicates the initiating agent's
IRDY_n 76 Y10 - I/O ability to complete the current data phase of
the transaction; low active.
Target Ready indicates the target agent's
TRDY_n 77 Y11 - I/O
ability to complete the current data phase of

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Data Sheet
the transaction; low active.
Stop indicates the current target is requesting

STOP_n 79 V11 - I/O the master to stop the current transaction; low
active.
Device Select, when actively driven, indicates
DEVSEL_n 78 W11 - I/O the driving device has decoded its address as
the target of the current access; low active.
Parity Error is only for the report of data parity
PERR_n 80 U11 - I/O errors during all PCI transactions except a
Special Cycle; low active.
System Error is for reporting address errors,
data parity errors on the Special Cycle
SERR_n 81 Y12 - I/O, PU
command, or any other system error where
the result will be catastrophic; low active.
Request indicates to the arbiter that agent 0
REQ0_n 28 K2 - I, PU
desires use of the bus; low active.
REQ1_n 31 L2 - I, PU
REQ2_n - M1 - I, PU
Grant indicates to agent 0 that access to the
GNT0_n 27 K3 - O
bus has been granted, low active.
GNT1_n 30 L1 - O
bus has been granted; low active.
GNT2_n - L4 - O
bus has been granted; low active.
PCI Interrupt 0, for a PCI agent to request an
INT0_n 26 K4 - I, PU
interrupt to the host; low active.
INT1_n 29 K1 - I, PU
INT2_n - L3 - I, PU
PCI_RST_n 32 M2 - O PCI Reset, low active.
PCI_CLK 53 U4 - O PCI Clock
DDR Memory Interface

CK, 115, P20 M15 DDR Clock Output. CK and CK_n are
O
CK_n 114 P19 N15 differential clock output.
CKE 113 N17 P15 O DDR Clock Enable
DCS_n 111 R20 R15 O Chip Select, low active.

Row Address Select, one of command
RAS_n 141 G18 J17 O
signals.
Column Address Select, one of command
CAS_n 142 F19 H16 O
signals.
DWE_n 143 E20 H17 O Write Enable, one of command signals.
DDR Data Mask
For
DM[3:0] 116, 117 N18, N19, N20, M18 K15, L15 O
CNS1101/CNS1109/CNS1104/STR9101/9109
/9104, only DM[1:0] is available.
BA[1:0] 139, 140 G19, F20 H15, G15 O DDR Bank Address
144, F18, G16,
145, 146, 147, 148, E19, D20, F17,E18, G17, F17, F15, F16,
DA[12:0] O DDR Row or Column Address Bus
151, 152, 153, 154, D19, C20, D18, E17, E17, E16, D17, E15,
155, 156, 157, 158 C19, B20, D17, C17 D15, D16, C17, C16

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Data Sheet
Y18, U16, V17, W18
U17, Y19, W19, V18
U16, T16, T17, R16,
118, 119, 120, 121, Y20, V19, W20, U19
R17, M16, N16,
122, 123, 124, 125, T18, U20, T19, R18 DDR Data Bus
P16,
DDQ[31:0] I/O For STR9101/9109/9104, only 16-bit data bus
129, 130, 131, 132, M19, M20, L18, L19 DDQ[15:0] is available.
L16, P17, N17, K16,
133, 134, 137, 138 L20, K19, K18, K17
M17, L17, K17, J16
J19, J18, H20, J17
H19, H18, G20, H17
DDR I/O Reference Voltage (1.25V)
For
VREF[1:0] 126 U18, J20 J15 AI
CNS1101/CNS1109/CNS1104/STR9101/910
9/9104, only VREF[0] is available.
DDR Data Strobe, input for read data, output
for write data.
DQS[3:0] 109, 110 P17, T20, R19, P18 U15, T15 I/O For
CNS1101/CNS1109/CNS1104/STR9101/910
9/9104, only DQS[1:0] is available.
Static Memory Interface
External interrupt. It can be programmed as
EXT_INT 23 H3 T2 I rising or falling or high-level or low-level
triggered interrupt source.
Static Memory Chip Enable of Bank 0, low
SCE0_n 21 G2 N1 O
active
Static Memory Chip Enable of Bank 1, low
SCE1_n 22 G1 P1 O
active
Static Memory Write Enable, low active
Shared with
SWE_n 17 F1 J1 O This pin is also shared with PCMCIA’s write
PWE_n
enable “PWE_n”.
Static Memory Output Enable, low_active
Shared with
SOE_n 18 H4 L1 O This pin is also shared with PCMCIA’s output
POE_n
enable “POE_n”.
Shared with
Static Memory Address Bus [22:17] REG_n,
198, 199, B5, C5, G1, F3,
SA[22:17] O These pins are also shared with PCMCIA’s IORD_n,
200, 202, 203, 204 B4, A3, A2, B3 E3, G2, C5, E2
{REG_n, IORD_n, IOWR_n, PA[19:17]}. IOWR_n,
PA[19:17]
Static Memory Address Bus [16:0].
In Power-On-Reset period, SA[16:0] are
inputs pins with internal 35k Ohm pull down
resistor. These signals will be also latched as
205, C4, B3,
configuration signals. If configuring to high is
206, 207, 3, 4, D4, C3, B2, A1, C4, C3, D3, C2,
needed, an external resistor around 5k Ohm Shared with
SA[16:0] 5, 6, 7, 8, E4, D3, C2, B1, D2, G3, F2, K3, I/O,PD
is needed to pull it up. “Refer to Table 2-2 PA[16:0]
9, 10, 11, 12, C1, D2, E3, F4, K2, J2, L2, L3,
Configuration Pins”.
13, 14, 15, 16 E2, F3, E1, F2 H2, J3, H1, H3
Note: when SMC work at 16-bit mode,
SA[22:0] is byte address; when SMC work at
8-bit mode, SA[22:0] is half-word (16-bit)
address.
179, 180, 184, 185, A10, C10, B10, A9 B8, A6, A5, B7,
Static Memory Data Bus
186, 187, 188, 189, B9, C9, A8, B8, C8, A3, A2, B6, Shared with
SDQ[15:0] I/O, PD These pins are also shared with PCMCIA’s
190, 191, 192, 193, C8, A7, B7, A6, B1, C7, B5, C1, PD[15:0]
data bus “PD[15:0]”.
194, 195, 196, 197 C7, B6, A5, C6 B4, B2, D1, F1
PCMCIA Interface
Card Enable. The CE1_n enables even
numbered address byte and CE2_n enables Shared with
CE1_n, H1, R2,
- I/O, PU odd numbered address byte, low active. GPIO[12],
CE2_n H2 P3
When PCMCIA interface is disabled by GPIO[13]
configuring SA[16], these 2 pins are treated

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Data Sheet
as GPIO[12] and [13]
Shared with
PWE_n - F1 J1 O PCMCIA Write Enable, low active
SWE_n
Shared with
POE_n - H4 L1 O PCMCIA Output Enable, low active
SOE_n
Interrupt Request, low active
When PCMCIA interface is disabled by Shared with
IREQ_n - J2 M3 I/O, PU
configuring SA[16], this pin is treated as GPIO[14]
GPIO[14]
When the REG_n signal is asserted, access
is limited to Attribute Memory (POE_n or Shared with
REG_n - B5 G1 O
PWE_n active) and to the I/O space (IORD_n SA[22]
or IOWR_n active).
Shared with
IORD_n - C5 F3 O I/O space Read Enable, low active
SA[21]
Shared with
IOWR_n - B4 E3 O I/O space Write Enable, low active
SA[20]
PCMCIA Card Reset, high active.
RESET - G3 K1 I/O, PU
GPIO[15]
Extend bus cycle, low active
WAIT_n - J3 U2 I/O, PU
GPIO[16]
Input Port Acknowledge (another interrupt
signal), low active
Shared with
INPACK_n - J1 N2 I/O, PU When PCMCIA interface is disabled by
GPIO[17]
configuring SA[16], this pin is treated as a
GPIO[17]
Shared with
PA[19:17] - A3, A2, B3 G2, C5, E2 O PCMCIA Address bus.
SA[19:17]
C4, B3,
D4, C3, B2, A1 C4, C3, D3, C2,
PCMCIA Address bus. Shared with
PA[16:0] - E4, D3, C2, B1, D2, G3, F2, K3, I/O, PD
Note: PA[19:0] is byte address. SA[16:0]
C1, D2, E3, F4, K2, J2, L2, L3,
E2, F3, E1, F2 H2, J3, H1, H3
A10, C10, B10, A9 B8, A6, A5, B7,
B9, C9, A8, B8, C8, A3, A2, B6, Shared with
PD[15:0] - I/O, PD PCMCIA Data bus.
C8, A7, B7, A6, B1, C7, B5, C1, SDQ[15:0]
C7, B6, A5, C6 B4, B2, D1, F1
Ethernet MAC Interfaces MAC Mode and PHY Mode
Port 0 Transmit Clock.
MII: transmit clock, 25/2.5 MHz, input
Reverse MII: receive clock, 25/2.5 MHz,
output
P0_TXCLK 41 R2 T5 I/O
RGMII: transmit clock, 125/25/2.5 MHz,
output
Reverse RGMII: receive clock, 125/25/2.5
MHz, output
Port 0 Transmit Data.
MII: transmit data, output
Reverse MII: receive data, output
RGMII: transmit data [3:0] at TXCLK rising
P0_TXD[3:0] 37, 36, 35, 34 P2, P1, N2, N1 U4, T3, T4, U5 O edge and [7:4] at TXCLK falling edge,
output
Reverse RGMII: receive data [3:0] at
RXCLK rising edge and [7:4] at RXCLK
falling edge, output.
Port 0 Transmit Enable
P0_TXEN 33 M3 U3 O
MII: TXEN, output

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Orion: STR91XX
CNS11XX
Data Sheet
Reverse MII: RXDV, output
RGMII: TX_CTL, output
Reverse RGMII: RX_CTL, output
Port 0 Receive Clock.
MII: receive clock, 25/2.5 MHz, input
Reverse MII: transmit clock, 25/2.5 MHz,
output
P0_RXCLK 42 R1 T7 I/O
RGMII: receive clock, 125/25/2.5 MHz,
input
Reverse RGMII: transmit clock, 125/25/2.5
MHz, input
Port 0 Receive Data.
MII: receive data, input
Reverse MII: transmit data, input
RGMII: receive data [3:0] at RXCLK rising
P0_RXD[3:0] 46, 45, 44, 43 U2, V1, U1, T1 T6, U7, U8, T8 I edge and [7:4] at RXCLK falling edge,
input
Reverse RGMII: transmit data [3:0] at
TXCLK rising edge and [7:4] at TXCLK
falling edge, input.
Port 0 Receive Data Valid
MII: RXDV, input
P0_RXDV 47 T2 U6 I Reverse MII: TXEN, input
RGMII: RX_CTL, input
Reverse RGMII: TX_CTL, input
Port 0 Carrier Sense
MII: Carrier Sense, input
Reverse MII: Carrier Sense, output
Shared w/
P0_CRS 49 P3 R4 I/O, PD RGMII: by configuring SA[14] to treat this
GPIO[8]
pin as GPIO[8]
Reverse RGMII: by configuring SA[14] to
treat this pin as GPIO[8]
Port 0 Collision
MII: Collision, input
Reverse MII: Collision, output
Shared w/
P0_COL 48 N3 R3 I/O, PD RGMII: by configuring SA[14] to treat this
GPIO[9]
pin as GPIO[9]
Port 1 Transmit Clock.
MII: transmit clock, 25/2.5 MHz, input
Reverse MII: receive clock, 25/2.5 MHz,
output
P1_TXCLK - W3 T10 I/O
RGMII: transmit clock, 125/25/2.5 MHz,
output
Reverse RGMII: receive clock, 125/25/2.5
MHz, output
Port 1 Transmit Data.
MII: transmit data, output
Reverse MII: receive data, output
RGMII: transmit data [3:0] at TXCLK rising
P1_TXD[3:0] - Y2, W2, Y1, W1 U9, T9, U10, T11 O edge and [7:4] at TXCLK falling edge,
output
Reverse RGMII: receive data [3:0] at
RXCLK rising edge and [7:4] at RXCLK
falling edge, output.
Port 1 Transmit Enable
MII: TXEN, output
P1_TXEN - V2 U11 O Reverse MII: RXDV, output
RGMII: TX_CTL, output
Reverse RGMII: RX_CTL, output
Port 1 Receive Clock.
P1_RXCLK - Y3 U12 I/O
MII: receive clock, 25/2.5 MHz, input

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Orion: STR91XX
CNS11XX
Data Sheet
Reverse MII: transmit clock, 25/2.5 MHz,
output
RGMII: receive clock, 125/25/2.5 MHz,
input
Reverse RGMII: transmit clock, 125/25/2.5
MHz, input
Port 1 Receive Data.
MII: receive data, input
Reverse MII: transmit data, input
RGMII: receive data [3:0] at RXCLK rising
P1_RXD[3:0] - Y5, W5, Y4, W4 U14, T13, U13, T12 I, PD edge and [7:4] at RXCLK falling edge,
input
Reverse RGMII: transmit data [3:0] at
TXCLK rising edge and [7:4] at TXCLK
falling edge, input.
Port 1 Receive Data Valid
MII: RXDV, input
P1_RXDV - U3 T14 I, PD Reverse MII: TXEN, input
RGMII: RX_CTL, input
Reverse RGMII: TX_CTL, input
Port 1 Carrier Sense
MII: Carrier Sense, input
Reverse MII: Carrier Sense, output
Shared w/
P1_CRS - V4 R14 I/O, PD RGMII: by configuring SA[15] to treat this
GPIO[10]
pin as GPIO[10]
Port 1 Collision
MII: Collision, input
Reverse MII: Collision, output
Shared w/
P1_COL - V3 R13 I/O, PD RGMII: by configuring SA[15] to treat this
GPIO[11]
pin as GPIO[11]
Management Data Clock. Only support MII &
MDC 50 R3 R5 O
RGMII
Management Data Input/Output. Only
MDIO 51 T3 N3 I/O, PU
support MII & RGMII.
USB Interfaces
P0_DP, B18 A16
- A USB 1.1/2.0 PHY Port 0 Differential Signals
P0_DM B19 A15
P1_DP, A16 A11
- A USB 1.1/2.0 PHY Port 1 Differential Signals
P1_DM A17 A12
REXT - C16 B14 A External reference resistance for signal swing
Crystal In for USB reference clock
UXIN - A18 A13 AI (12MHz)---reserved for test purpose, not used
in normal application
Crystal Out for USB reference
UXOUT - A19 A14 AO clock.—reserved for test purpose, not used in
normal application
JTAG(ICE) Interfaces
JTAG Test Clock
When JTAG (ICE) interface is disabled by Shared with
ICK/TCK 175 A12 B9 I/O, PD
configuring SA[4], this pin is treated as a GPIO[0],
GPIO[0]
JTAG Test Mode Select
When JTAG (ICE) interface is disabled by Shared with
IMS/TMS 176 C11 C9 I/O, PD
configuring SA[4], this pin is treated as a GPIO[1]
GPIO[1]

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Orion: STR91XX
CNS11XX
Data Sheet
ARM-like ICE Data In/Out or JTAG Test
Data Out
Shared with
IDIO/TDO 177 B11 A8 I/O, PD When JTAG (ICE) interface is disabled by
GPIO[2]
GPIO[2]
ARM-like ICE control signal or Multi-ICE
Debug Request
EXTGOICE/DB Shared with
178 A11 A7 I/O, PD When JTAG (ICE) interface is disabled by
GRQ GPIO[3]
GPIO[3]
JTAG Reset (Multi-ICE only)
When JTAG interface is disabled by
Shared with
nTRST - C13 C10 I/O, PD configuring SA[4] or Multi-ICE interface is
GPIO[18]
disabled by configured SA[5], this pin is
treated as a GPIO[18]
JTAG Test Data In (Multi-ICE only)
Shared with
TDI - C12 C12 I/O, PD configuring SA[4] or Multi-ICE interface is
GPIO[19]
Multi-ICE Debug ACK
Shared with
DBGACK - B12 C13 I/O, PD configuring SA[4] or Multi-ICE interface is
GPIO[20]
UART Interfaces
UART TX Data
When UART interface is disabled by Shared with
UR_TXD 164 B16 B16 I/O, PU
GPIO[4]
UART RX Data
UR_RXD 165 B15 B15 I/O, PU
GPIO[5]
UART CTS
UR_CTS 166 C14 C14 I/O, PU
GPIO[6]
UART RTS
UR_RTS 167 A15 B12 I/O, PU
GPIO[7]
Miscellaneous Interfaces
RESET_n 174 B13 B10 I System Reset, low active.
Crystal In for system reference clock
SXIN 172 A13 A10 AI
(25MHz).
SXOUT 173 A14 A9 AO Crystal Out for system reference clock.
3.3V-to-2.5V Regulator control pin for external
V25_CTL 160 C18 B17 AO
PNP BJT
3.3V-to-1.8V Regulator control pin for external
V18_CTL 161 B17 C15 AO
PNP BJT
CLK12_OUT - C15 B13 O 12MHz Clock Output (Continuous Clock)
Test Mode Select Pin, for test purpose only;
TEST_MODE2 169 B14 C11 I, PD
keep it in low.
GPIO Interfaces
GPIO[20:18]
GPIO[20:18] - B12, C12, C13 C13, C12, C10 I/O, PD
They are shared with {DBGACK, TDI, nTRST}

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Orion: STR91XX
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Data Sheet
GPIO[20:18] are enabled if SA[5] is not pulled
up.
GPIO[17:12]
They are shared with {INPACK_n, WAIT_n,
RESET, IREQ_n, CE2_n, CE1_n}
GPIO[17:12] are enabled if SA[16] is pulled
up.
J1, J3, N2, U2, For CNS1101/CNS1109/STR9101/9109, only
GPIO[17:12] 24 I/O, PU
G3, J2, H2, H1 K1, M3, P3, R2 GPIO[13] is available, and only input function
and interrupt function are enabled. Its output
function is disabled.
For other part numbers, GPIO[17:12] are
available, and GPIO full functions are
enabled.
GPIO[11:10]
They are shared with {P1_COL, P1_CRS}
GPIO[11:10] - V3, V4 R13, R14 I/O, PD
GPIO[11:10] are enabled if SA[15] is pulled
up.
GPIO[9:8]
GPIO[9:8] 48, 49 N3, P3 R3, R4 I/O, PD They are shared with {P0_COL, P0_CRS}
GPIO[9:8] are enabled if SA[14] is pulled up.
GPIO[7:4]
They are shared with {UR_RTS, UR_CTS,
A15, C14, B15, B12, C14, B15,
GPIO[7:4] 167, 166, 165, 164 I/O, PU UR_RXD, RU_TXD}
B16 B16,
up.
GPIO[3:0]
They are shared with {EXTGOICE/DBGRQ,
GPIO[3:0] 178, 177, 176, 175 A11, B11, C11, A12 A7, A8, C9, B9 I/O, PD IDIO/TDO, IMS/TMS, ICK/TCK}
up.
Power and Ground
A4, A20, D1, G4,
G17, H8, H9, H10,
H11, H12, H13,
J8, J9, J10, J11, A1, A4, A17, E1,
J12, J13 F6~F12, G6~G12,
20, 52, 85, 112, K8, K9, K10, K11, H6~H12, J6~J12,
136, 183, 208, 2, K12, K13, K20 K4, K6~K12,
GND 39, 58, 84, 106, L8, L9, L10, L11, L6~L12, M1,
G Core Ground / Pad Ground
127, 149, 168, 182 L12, L13 M6~M12, P4, P5,
M8, M9, M10, M11, P6, P12, P13, P14,
M12, M13 U1, U17
N4, N8, N9, N10,
N11, N12, N13
P4, R17, V20, Y14
D7, D4, D5, G4,
19, 40, 64,
CVDD D8, L17, M17, R4, H4, H14, J14, M4, P Core Power Supply (1.8V)
100, 108, 135, 201
R5, T4, T5, T6 N4, P9, P10, P11
1, 25, D5, D6, E5, C6, D6,
PVDD P Pad Power Supply (3.3V)
59, 83, 105, 181 E6, F5, U8, U9 E4, F4, P7, P8
PVDD_DDR 107, 128, 150 R16, T15, T16, T17 K14, L14, M14, N14 P DDR I/O Pad Power Supply (2.5V)
Switch Port 0 MII/RGMII Power Supply (3.3V
PVDD_SW0 38 J4 J4 P
or 2.5V)
Switch port 1 MII/RGMII Power Supply (3.3V
PVDD_SW1 - M4 L4 P
or 2.5V)
AGND_SP 171 D9 D7 G System PLL Ground
AVDD_SP 170 D10 D8 P System PLL Power Supply (1.8V)

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Orion: STR91XX
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Data Sheet
AGND_U - D15, E15 D14, E14 G USB2.0 PHY Analog Ground
AVDD_U - D13, D14 D11, D12 P USB2.0 PHY Analog Power Supply (1.8V)
AVDD_U33 - E16 D13 P USB1.1 PHY Analog Power Supply (3.3V)
AGND_UP - D11 D9 G USB PHY PLL Ground

USB PHY PLL Power Supply (1.8V)
For CNS1101/CNS1109/STR9101/9109, the
AVDD_UP 163 D12 D10 P
power must be supplied to generate UART
clock source.
Analog Ground of Regulator 3.3V-to-2.5V and
AGND_R 162 D16 F14 G
3.3V-to-1.8V
Analog Power (3.3V) of Regulator
AVDD_R33 159 F16 G14 P
3.3V-to-2.5V and 3.3V-to-1.8V
Table 2-3. Reset-Latch Configuration Pins

Configuration Pin Pin Settings
Name Number (EPU=External Pull-Up, IPD=Internal Pull-Down)
Reserved SA[3:0] E2, F3, E1, F2 They are for test purpose. Don’t pull them up externally.
EPU: JTAG Interface Enable
JTAG Function Selection SA[4] F4
IPD: JTAG function is disabled and these Pins are used as GPIO Pins
EPU: ARM Multi-ICE
IPD: ARM-like ICE. When ARM-like ICE is selected, these
Multi-ICE Selection SA[5] E3
only-for-Mulit-ICE Pins (nTRST, TDI, DBGACK) are used as GPIO
Pins.
SA[7:6] configuration:
SA[7:6]={IPD, IPD}: 175MHz,
CPU Clock Speed Selection SA[7:6] C1, D2 SA[7:6]={IPD, EPU}: 200MHz,
SA[7:6]={EPU, IPD}: Reserved(225MHz),
SA[7:6]={EPU, EPU}: Reserved(250MHz)
EPU: 8-bit
Flash Data Bus Width Selection SA[8] B1
IPD: 16-bit
EPU: UART Interface Enable
UART Function Selection SA[9] C2
IPD: UART function is disabled and these pins are used as GPIO pins
Reserved SA[10] D3 It is for test purpose. Don’t pull it up externally.
EPU: CPU clock frequency is reduced by 2 times further from SA[7:6]’s
Low CPU Clock Operation SA[11] E4 configuration.
IPD: keep SA[7:6]’s configuration
Reserved SA[12] A1 It is for test purpose. Don’t pull it up externally.
USB PHY Reference Clock Source IPD: Use internal clock source
SA[13] B2
Selection EPU: Use external clock source (reserved for test purpose)
IPD: MAC Port-0 CRS and COL enable,
SA[14] C3 EPU: Port-0 CRS and COL are disabled and used as GPIO pins
CRS/COL Function Selection
IPD: MAC Port-1 CRS and COL enable,
SA[15] D4 EPU: MAC Port-1 CRS and COL are disabled and used as GPIO pins
IPD: PCMCIA interface enable,
PCMCIA Function Selection SA[16] C4 EPU: PCMCIA function is disabled and these pins are used as GPIO
pins

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Orion: STR91XX
CNS11XX
Data Sheet
2.1 Package Pin-out
2.1.1 CNS1101/CNS1109/STR9101/STR9109 (PQFP-208) Package Pin-out
EXTGOICE/GPIO[3]
UR_RXD/GPIO[5]
UR_RTS/GPIO[7]
UR_CTS/GPIO[6]
UR_TXD/GPIO[4]
TEST_MODE2
IDIO/GPIO[2]
IMS/GPIO[1]
ICK/GPIO[0]
AVDD_R33
AGND_SP
AVDD_UP
AVDD_SP
RESET_n
V18_CTL
V25_CTL
AGND_R
SDQ[10]
SDQ[11]
SDQ[12]
SDQ[13]
SDQ[14]
SDQ[15]
SXOUT
SDQ[0]
SDQ[1]
SDQ[2]
SDQ[3]
SDQ[4]
SDQ[5]
SDQ[6]
SDQ[7]
SDQ[8]
SDQ[9]
SA[14]
SA[15]
SA[16]
SA[17]
SA[18]
SA[19]
SA[20]
SA[21]
SA[22]
CGND
CGND
PGND
PGND
CVDD
PVDD
AD[0]
AD[1]
SXIN
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
169
168
167
166
165
164
163
162
161
160
159
158
157
188
187
170
PVDD 1 156 DA[2]
PGND 2 155 DA[3]
SA[13] 3 154 DA[4]
SA[12] 4 153 DA[5]
SA[11] 5 152 DA[6]
SA[10] 6 151 DA[7]
SA[9] 7 150 PVDD_DDR
SA[8] 8 149 PGND
SA[7] 9 148 DA[8]
SA[6] 10 147 DA[9]
SA[5] 11 146 DA[10]
SA[4] 12 145 DA[11]
SA[3] 13 144 DA[12]
SA[2] 14 143 DWE_n
SA[1] 15 142 CAS_n
SA[0] 16 141 RAS_n
SWE_n 17 140 BA[0]
SOE_n 18 139 BA[1]
CVDD 19 138 DDQ[0]
CGND 20 137 DDQ[1]
SCE0_n 21 STR9101/9109 136 CGND
SCE1_n 22 135 CVDD
EXT_INT 23 134 DDQ[2]
GPIO[13] 24 133 DDQ[3]
PVDD 25
PQFP-208 132 DDQ[4]
INT0_n 26 131 DDQ[5]
GNT0_n 27 130 DDQ[6]
REQ0_n 28 (Top View) 129 DDQ[7]
INT1_n 29 128 PVDD_DDR
GNT1_n 30 127 PGND
REQ1_n 31 126 VREF
PCI_RST_n 32 125 DDQ[8]
TXEN 33 124 DDQ[9]
TXD[0] 34 123 DDQ[10]
TXD[1] 35 122 DDQ[11]
TXD[2] 36 121 DDQ[12]
TXD[3] 37 120 DDQ[13]
PVDD_SW0 38 119 DDQ[14]
PGND 39 118 DDQ[15]
CVDD 40 117 DM[0]
TXCLK 41 116 DM[1]
RXCLK 42 115 CK
RXD[0] 43 114 CK_n
RXD[1] 44 113 CKE
RXD[2] 45 112 CGND
RXD[3] 46 111 DCS_n
RXDV 47 110 DQS[0]
COL/GPIO[9] 48 109 DQS[1]
CRS/GPIO[8] 49 108 CVDD
MDC 50 107 PVDD_DDR
MDIO 51 106 PGND
CGND 52 105 PVDD
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
IRDY_n
TRDY_n
DEVSEL_n
STOP_n
PERR_n
SERR_n
PCI_CLK
PGND
PVDD
CVDD
FRAME_n
PAR
PVDD
PGND
CGND
CVDD
AD[31]
AD[30]
AD[29]
AD[28]
AD[27]
AD[26]
AD[25]
AD[24]
C_BE_n[3]
AD[23]
AD[22]
AD[21]
AD[20]
AD[19]
AD[18]
AD[17]
AD[16]
C_BE_n[2]
C_BE_n[1]
AD[15]
AD[14]
AD[13]
AD[12]
AD[11]
AD[10]
AD[9]
AD[8]
C_BE_n[0]
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
AD[2]
AD[1]
AD[0]
Figure 2-1. CNS1101/CNS1109/STR9101/STR9109 PQFP-208 Package Pin-out

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Orion: STR91XX
CNS11XX
Data Sheet
2.1.2 CNS1102/CNS1105/STR9102/STR9105 (BGA-304) Package Pin-out
BGA-304 Ball Assignment

pin1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PD[12]/ PD[15]/ EXTGO

PA[12]/ PA[18]/ PA[19]/ PD[1]/S PD[4]/S PD[6]/S PD[9]/S ICK/TC UR_RT
A GND SDQ[12 SDQ[15 ICE/DB SXIN SXOUT P1_DP P1_DM UXIN UXOUT GND
SA[12] SA[18] SA[19] DQ[1] DQ[4] DQ[6] DQ[9] K S
] ] GRQ
IOWR_ PD[11]/ PD[13]/
PA[8]/S PA[13]/ PA[17]/ REG_n/ PD[2]/S PD[5]/S PD[8]/S IDIO/TD DBGAC RESET TEST_ UR_RX UR_TX V18_CT
B n/SA[20 SDQ[11 SDQ[13 P0_DP P0_DM DA[2]
A[8] SA[13] SA[17] SA[22] DQ[2] DQ[5] DQ[8] O K _n MODE2 D D L
] ] ]
PD[10]/ PD[14]/
PA[7]/S PA[9]/S PA[14]/ PA[16]/ IORD_n PD[0]/S PD[3]/S PD[7]/S IMS/TM UR_CT CLK12_ V25_CT
C SDQ[10 SDQ[14 TDI NTRST REXT DA[0] DA[3] DA[6]
A[7] A[9] SA[14] SA[16] /SA[21] DQ[0] DQ[3] DQ[7] S S OUT L
] ]
PA[6]/S PA[10]/ PA[15]/ AGND_ AVDD_ AGND_ AVDD_ AVDD_ AVDD_ AGND_ AGND_
D GND PVDD PVDD CVDD CVDD DA[1] DA[5] DA[7] DA[10]
A[6] SA[10] SA[15] SP SP UP UP U U U R
PA[1]/S PA[3]/S PA[5]/S PA[11]/ AGND_ AVDD_

E PVDD PVDD DA[4] DA[8] DA[11] DWE_n
A[1] A[3] A[5] SA[11] U U33
PWE_n/ PA[0]/S PA[2]/S PA[4]/S AVDD_

F PVDD DA[9] DA[12] CAS_n BA[0]
SWE_n A[0] A[2] A[4] R33
G SCE1_n SCE0_n RESET GND GND RAS_n BA[1] DDQ[1]
CE1_n/ CE2_n/
EXT_IN POE_n/
H GPIO[1 GPIO[1 GND GND GND GND GND GND DDQ[0] DDQ[2] DDQ[3] DDQ[5]
T SOE_n
2] 3]
INPACK PVDD_ VREF[0
J IREQ_n WAIT_n GND GND GND GND GND GND DDQ[4] DDQ[6] DDQ[7]
_n SW0 ]
REQ0_ GNT0_ DDQ[10

K INT1_n INT0_n GND GND GND GND GND GND DDQ[8] DDQ[9] GND
n n ]
GNT1_ REQ1_ GNT2_ DDQ[13 DDQ[12 DDQ[11

L INT2_n GND GND GND GND GND GND CVDD
n n n ] ] ]
REQ2_ PCI_RS P0_TXE PVDD_ DDQ[15 DDQ[14

M GND GND GND GND GND GND CVDD DM[0]
n T_n N SW1 ] ]
P0_TX P0_TX P0_CO

N GND GND GND GND GND GND GND CKE DM[3] DM[2] DM[1]
D[0] D[1] L
P0_TX P0_TX P0_CR

P GND DQS[3] DQS[0] CK_n CK
D[2] D[3] S
P0_RX P0_TX PVDD_ DDQ[16

R MDC CVDD CVDD GND DQS[1] DCS_n
CLK CLK DDR ]
P0_RX P0_RX PVDD_ PVDD_ PVDD_ DDQ[19 DDQ[17

T MDIO CVDD CVDD CVDD DQS[2]
D[0] DV DDR DDR DDR ] ]
P0_RX P0_RX P1_RX PCI_CL PERR_ DDQ[30 DDQ[27 VREF[1 DDQ[20 DDQ[18
U AD[30] AD[29] AD[27] PVDD PVDD AD[16] AD[15] AD[11] AD[7] AD[2]
D[1] D[3] DV K n ] ] ] ] ]
P0_RX P1_TXE P1_CO P1_CR C_BE_n STOP_ C_BE_n DDQ[29 DDQ[24 DDQ[22
V AD[31] AD[28] AD[25] AD[22] AD[19] AD[12] AD[8] AD[5] AD[1] GND
D[2] N L S [2] n [1] ] ] ]
P1_TX P1_TX P1_TX P1_RX P1_RX C_BE_n FRAME DEVSE C_BE_n DDQ[28 DDQ[25 DDQ[21
W AD[26] AD[21] AD[18] PAR AD[13] AD[10] AD[4] AD[0]
D[0] D[2] CLK D[0] D[2] [3] _n L_n [0] ] ] ]
P1_TX P1_TX P1_RX P1_RX P1_RX I_RDY_ T_RDY SERR_ DDQ[31 DDQ[26 DDQ[23
Y AD[24] AD[23] AD[20] AD[17] AD[14] GND AD[9] AD[6] AD[3]
D[1] D[3] CLK D[1] D[3] n _n n ] ] ]
Figure 2-2. CNS1102/CNS1105/STR9102/CNS9105 BGA-304 Package Pin-out

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Orion: STR91XX
CNS11XX
Data Sheet
2.1.3 CNS1104/STR9104 (LFBGA-257) Package Pin-out
LFBGA-257-14*14 Ball Assignment

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
EXTGOI
PD[9]/S PD[10]/S PD[13]/S PD[14]/S IDIO/TD
A GND GND CE/DBG SXOUT SXIN P1_DP P1_DM UXIN UXOUT P0_DM P0_DP GND
DQ[9] DQ[10] DQ[13] DQ[14] O
RQ
PD[7]/S PD[2]/S PA[16]/S PD[3]/S PD[5]/S PD[8]/S PD[12]/S PD[15]/S RESET_ CLK12_ V25_CT
B ICK/TCK NC UR_RTS REXT UR_RXD UR_TXD
DQ[7] DQ[2] A[16] DQ[3] DQ[5] DQ[8] DQ[12] DQ[15] n OUT L
PD[4]/S PA[12]/S PA[14]/S PA[15]/S PA[18]/S PD[6]/S PD[11]/S IMS/TM TEST_M DBGAC V18_CT
C PVDD nTRST TDI UR_CTS DA[0] DA[1]
DQ[4] A[12] A[14] A[15] A[18] DQ[6] DQ[11] S ODE2 K L
PD[1]/S PA[11]/S PA[13]/S AGND_S AVDD_S AGND_ AVDD_U AVDD_U AGND_

D CVDD CVDD PVDD AVDD_U AVDD_U DA[3] DA[2] DA[5]
DQ[1] A[11] A[13] P P UP P 33 U
PA[17]/S IOWR_n/ AGND_

E GND PVDD DA[4] DA[6] DA[7]
A[17] SA[20] U
PD[0]/S PA[9]/SA IORD_n/ AGND_

F PVDD GND GND GND GND GND GND GND DA[9] DA[8] DA[10]
DQ[0] [9] SA[21] R
REG_n/ PA[19]/S PA[10]/S AVDD_R

G CVDD GND GND GND GND GND GND GND BA[0] DA[12] DA[11]
SA[22] A[19] A[10] 33
PA[1]/SA PA[3]/SA PA[0]/SA

H CVDD GND GND GND GND GND GND GND CVDD BA[1] CAS_n DWE_n
[1] [3] [0]
PWE_n/ PA[6]/SA PA[2]/SA PVDD_S

J GND GND GND GND GND GND GND CVDD VREF DDQ[0] RAS_n
SWE_n [6] [2] W0
PA[7]/SA PA[8]/SA PVDD_D

K RESET GND GND GND GND GND GND GND GND DM[1] DDQ[4] DDQ[1]
[7] [8] DR
POE_n/S PA[5]/SA PA[4]/SA PVDD_S PVDD_D

L GND GND GND GND GND GND GND DM[0] DDQ[7] DDQ[2]
OE_n [5] [4] W1 DR
PVDD_D
M GND NC IREQ_n CVDD GND GND GND GND GND GND GND CK DDQ[10] DDQ[3]
DR
INPACK PVDD_D
N SCE0_n MDIO CVDD CK_n DDQ[9] DDQ[5]
_n DR
CE2_n/G
P SCE1_n NC GND GND GND PVDD PVDD CVDD CVDD CVDD GND GND GND CKE DDQ[8] DDQ[6]
PIO[13]
CE1_n/G
R NC P0_COL P0_CRS MDC NC NC NC NC NC NC NC P1_COL P1_CRS DCS_n DDQ[12] DDQ[11]
PIO[12]
P0_TXD[ P0_TXD[ P0_TXC P0_RXD[ P0_RXC P0_RXD[ P1_TXD[ P1_TXC P1_TXD[ P1_RXD[ P1_RXD[ P1_RXD
T NC EXT_INT DQS[0] DDQ[14] DDQ[13]
2] 1] LK 3] LK 0] 2] LK 0] 0] 2] V
P0_TXE P0_TXD[ P0_TXD[ P0_RXD[ P0_RXD[ P1_TXD[ P1_TXD[ P1_TXE P1_RXC P1_RXD[ P1_RXD[
U GND WAIT_n P0_RXDV DQS[1] DDQ[15] GND
N 3] 0] 2] 1] 3] 1] N LK 1] 3]
Figure 2-3. CNS1104/STR9104 LFBGA-257 Package Pin-out

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Orion: STR91XX
CNS11XX
Data Sheet
2.2 Package Pin-Number vs. Pin-Name
2.2.1 CNS1101/CNS1109/STR9101/STR9109 (PQFP-208) Package Pin-Number vs. Pin-Name
Table 2-3. STR9101/9109 Package Pin-Number vs. Pin-Name (In Order of Pin Number)
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1 PVDD 53 PCI_CLK 105 PVDD 157 DA[1]
2 PGND 54 AD[31] 106 PGND 158 DA[0]
3 SA[13] 55 AD[30] 107 PVDD_DDR 159 AVDD_R33
4 SA[12] 56 AD[29] 108 CVDD 160 V25_CTL
5 SA[11] 57 AD[28] 109 DQS[1] 161 V18_CTL
6 SA[10] 58 PGND 110 DQS[0] 162 AGND_R
7 SA[9] 59 PVDD 111 DCS_n 163 AVDD_UP
8 SA[8] 60 AD[27] 112 CGND 164 UR_TXD/GPIO[4]
9 SA[7] 61 AD[26] 113 CKE 165 UR_RXD/GPIO[5]
10 SA[6] 62 AD[25] 114 CK_n 166 UR_CTS/GPIO[6]
11 SA[5] 63 AD[24] 115 CK 167 UR_RTS/GPIO[7]
12 SA[4] 64 CVDD 116 DM[1] 168 PGND
13 SA[3] 65 C_BE_n[3] 117 DM[0] 169 TEST_MODE2
14 SA[2] 66 AD[23] 118 DDQ[15] 170 AVDD_SP
15 SA[1] 67 AD[22] 119 DDQ[14] 171 AGND_SP
16 SA[0] 68 AD[21] 120 DDQ[13] 172 SXIN
17 SWE_n 69 AD[20] 121 DDQ[12] 173 SXOUT
18 SOE_n 70 AD[19] 122 DDQ[11] 174 RESET_n
19 CVDD 71 AD[18] 123 DDQ[10] 175 ICK/GPIO[0]
20 CGND 72 AD[17] 124 DDQ[9] 176 IMS/GPIO[1]
21 SCE0_n 73 AD[16] 125 DDQ[8] 177 IDIO/GPIO[2]
22 SCE1_n 74 C_BE_n[2] 126 VREF 178 EXTGOICE/GPIO[3]
23 EXT_INT 75 FRAME_n 127 PGND 179 SDQ[15]
24 GPIO[13] 76 IRDY_n 128 PVDD_DDR 180 SDQ[14]
25 PVDD 77 TRDY_n 129 DDQ[7] 181 PVDD
26 INT0_n 78 DEVSEL_n 130 DDQ[6] 182 PGND
27 GNT0_n 79 STOP_n 131 DDQ[5] 183 CGND
28 REQ0_n 80 PERR_n 132 DDQ[4] 184 SDQ[13]
29 INT1_n 81 SERR_n 133 DDQ[3] 185 SDQ[12]
30 GNT1_n 82 PAR 134 DDQ[2] 186 SDQ[11]
31 REQ1_n 83 PVDD 135 CVDD 187 SDQ[10]
32 PCI_RST_n 84 PGND 136 CGND 188 SDQ[9]
33 TXEN 85 CGND 137 DDQ[1] 189 SDQ[8]
34 TXD[0] 86 C_BE_n[1] 138 DDQ[0] 190 SDQ[7]
35 TXD[1] 87 AD[15] 139 BA[1] 191 SDQ[6]
36 TXD[2] 88 AD[14] 140 BA[0] 192 SDQ[5]
37 TXD[3] 89 AD[13] 141 RAS_n 193 SDQ[4]
38 PVDD_SW0 90 AD[12] 142 CAS_n 194 SDQ[3]
39 PGND 91 AD[11] 143 DWE_n 195 SDQ[2]
40 CVDD 92 AD[10] 144 DA[12] 196 SDQ[1]
41 TXCLK 93 AD[9] 145 DA[11] 197 SDQ[0]
42 RXCLK 94 AD[8] 146 DA[10] 198 SA[22]
43 RXD[0] 95 C_BE_n[0] 147 DA[9] 199 SA[21]
44 RXD[1] 96 AD[7] 148 DA[8] 200 SA[20]
45 RXD[2] 97 AD[6] 149 PGND 201 CVDD
46 RXD[3] 98 AD[5] 150 PVDD_DDR 202 SA[19]
47 RXDV 99 AD[4] 151 DA[7] 203 SA[18]
48 COL/GPIO[9] 100 CVDD 152 DA[6] 204 SA[17]
49 CRS/GPIO[8] 101 AD[3] 153 DA[5] 205 SA[16]
50 MDC 102 AD[2] 154 DA[4] 206 SA[15]
51 MDIO 103 AD[1] 155 DA[3] 207 SA[14]
52 CGND 104 AD[0] 156 DA[2] 208 CGND

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Orion: STR91XX
CNS11XX
Data Sheet
2.2.2 CNS1102/CNS1105/STR9102/STR9105 (BGA-304) Package Pin-Number vs. Pin-Name
Table 2-4. CNS1102/CNS1105/STR9102/STR9105 Package Pin-Number vs. Pin-Name (In Order of Ball
Number)
Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name
A1 PA[12]/SA[12] B1 PA[8]/SA[8] C1 PA[7]/SA[7] D1 GND
A2 PA[18]/SA[18] B2 PA[13]/SA[13] C2 PA[9]/SA[9] D2 PA[6]/SA[6]
A3 PA[19]/SA[19] B3 PA[17]/SA[17] C3 PA[14]/SA[14] D3 PA[10]/SA[10]
A4 GND B4 IOWR_n/SA[20] C4 PA[16]/SA[16] D4 PA[15]/SA[15]
A5 PD[1]/SDQ[1] B5 REG_n/SA[22] C5 IORD_n/SA[21] D5 PVDD
A6 PD[4]/SDQ[4] B6 PD[2]/SDQ[2] C6 PD[0]/SDQ[0] D6 PVDD
A7 PD[6]/SDQ[6] B7 PD[5]/SDQ[5] C7 PD[3]/SDQ[3] D7 CVDD
A8 PD[9]/SDQ[9] B8 PD[8]/SDQ[8] C8 PD[7]/SDQ[7] D8 CVDD
A9 PD[12]/SDQ[12] B9 PD[11]/SDQ[11] C9 PD[10]/SDQ[10] D9 AGND_SP
A10 PD[15]/SDQ[15] B10 PD[13]/SDQ[13] C10 PD[14]/SDQ[14] D10 AVDD_SP
A11 EXTGOICE/DBGRQ(GPI B11 IDIO/TDO(GPIO[2]) C11 IMS/TMS(GPIO[1]) D11 AGND_UP
O[3])
A12 ICK/TCK(GPIO[0]) B12 DBGACK(GPIO[20]) C12 TDI(GPIO[19]) D12 AVDD_UP
A13 SXIN B13 RESET_n C13 nTRST(GPIO[18]) D13 AVDD_U
A14 SXOUT B14 TEST_MODE2 C14 UR_CTS(GPIO[6]) D14 AVDD_U
A15 UR_RTS(GPIO[7]) B15 UR_RXD(GPIO[5]) C15 CLK12_OUT D15 AGND_U
A16 P1_DP B16 UR_TXD(GPIO[4]) C16 REXT D16 AGND_R
A17 P1_DM B17 V18_CTL C17 DA[0] D17 DA[1]
A18 UXIN B18 P0_DP C18 V25_CTL D18 DA[5]
A19 UXOUT B19 P0_DM C19 DA[3] D19 DA[7]
A20 GND B20 DA[2] C20 DA[6] D20 DA[10]
E1 PA[1]/SA[1] F1 PWE_n/SWE_n G1 SCE1_n H1 CE1_n/GPIO[12]
E2 PA[3]/SA[3] F2 PA[0]/SA[0] G2 SCE0_n H2 CE2_n/GPIO[13]
E3 PA[5]/SA[5] F3 PA[2]/SA[2] G3 RESET(GPIO[15]) H3 EXT_INT
E4 PA[11]/SA[11] F4 PA[4]/SA[4] G4 GND H4 POE_n/SOE_n
E5 PVDD F5 PVDD G5 - H5 -
E6 PVDD F6 - G6 - H6 -
E7 - F7 - G7 - H7 -
E8 - F8 - G8 - H8 GND
E9 - F9 - G9 - H9 GND
E10 - F10 - G10 - H10 GND
E11 - F11 - G11 - H11 GND
E12 - F12 - G12 - H12 GND
E13 - F13 - G13 - H13 GND
E14 - F14 - G14 - H14 -
E15 AGND_U F15 - G15 - H15 -
E16 AVDD_U33 F16 AVDD_R33 G16 - H16 -
E17 DA[4] F17 DA[9] G17 GND H17 DDQ[0]
E18 DA[8] F18 DA[12] G18 RAS_n H18 DDQ[2]
E19 DA[11] F19 CAS_n G19 BA[1] H19 DDQ[3]
E20 DWE_n F20 BA[0] G20 DDQ[1] H20 DDQ[5]
J1 INPACK_n(GPIO[17]) K1 INT1_n L1 GNT1_n M1 REQ2_n
J2 IREQ_n(GPIO[14]) K2 REQ0_n L2 REQ1_n M2 PCI_RST_n
J3 WAIT_n(GPIO[16]) K3 GNT0_n L3 INT2_n M3 P0_TXEN
J4 PVDD_SW0 K4 INT0_n L4 GNT2_n M4 PVDD_SW1
J5 - K5 - L5 - M5 -
J6 - K6 - L6 - M6 -
J7 - K7 - L7 - M7 -

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Orion: STR91XX
CNS11XX
Data Sheet
J8 GND K8 GND L8 GND M8 GND
J14 - K14 - L14 - M14 -
J15 - K15 - L15 - M15 -
J16 - K16 - L16 - M16 -
J17 DDQ[4] K17 DDQ[8] L17 CVDD M17 CVDD
J18 DDQ[6] K18 DDQ[9] L18 DDQ[13] M18 DM[0]
J19 DDQ[7] K19 DDQ[10] L19 DDQ[12] M19 DDQ[15]
J20 VREF[0] K20 GND L20 DDQ[11] M20 DDQ[14]
N1 P0_TXD[0] P1 P0_TXD[2] R1 P0_RXCLK T1 P0_RXD[0]
N2 P0_TXD[1] P2 P0_TXD[3] R2 P0_TXCLK T2 P0_RXDV
N3 P0_COL(GPIO[9]) P3 P0_CRS(GPIO[8]) R3 MDC T3 MDIO
N4 GND P4 GND R4 CVDD T4 CVDD
N5 - P5 - R5 CVDD T5 CVDD
N6 - P6 - R6 - T6 CVDD
N7 - P7 - R7 - T7 -
N8 GND P8 - R8 - T8 -
N9 GND P9 - R9 - T9 -
N10 GND P10 - R10 - T10 -
N11 GND P11 - R11 - T11 -
N12 GND P12 - R12 - T12 -
N13 GND P13 - R13 - T13 -
N14 - P14 - R14 - T14 -
N15 - P15 - R15 - T15 PVDD_DDR
N16 - P16 - R16 PVDD_DDR T16 PVDD_DDR
N17 CKE P17 DQS[3] R17 GND T17 PVDD_DDR
N18 DM[3] P18 DQS[0] R18 DDQ[16] T18 DDQ[19]
N19 DM[2] P19 CK_n R19 DQS[1] T19 DDQ[17]
N20 DM[1] P20 CK R20 DCS_n T20 DQS[2]
U1 P0_RXD[1] V1 P0_RXD[2] W1 P1_TXD[0] Y1 P1_TXD[1]
U2 P0_RXD[3] V2 P1_TXEN W2 P1_TXD[2] Y2 P1_TXD[3]
U3 P1_RXDV V3 P1_COL(GPIO[11]) W3 P1_TXCLK Y3 P1_RXCLK
U4 PCI_CLK V4 P1_CRS(GPIO[10] W4 P1_RXD[0] Y4 P1_RXD[1]
U5 AD[30] V5 AD[31] W5 P1_RXD[2] Y5 P1_RXD[3]
U6 AD[29] V6 AD[28] W6 AD[26] Y6 AD[24]
U7 AD[27] V7 AD[25] W7 C_BE_n[3] Y7 AD[23]
U8 PVDD V8 AD[22] W8 AD[21] Y8 AD[20]
U9 PVDD V9 AD[19] W9 AD[18] Y9 AD[17]
U10 AD[16] V10 C_BE_n[2] W10 FRAME_n Y10 I_RDY_n
U11 PERR_n V11 STOP_n W11 DEVSEL_n Y11 T_RDY_n
U12 AD[15] V12 C_BE_n[1] W12 PAR Y12 SERR_n
U13 AD[11] V13 AD[12] W13 AD[13] Y13 AD[14]
U14 AD[7] V14 AD[8] W14 AD[10] Y14 GND
U15 AD[2] V15 AD[5] W15 C_BE_n[0] Y15 AD[9]
U16 DDQ[30] V16 AD[1] W16 AD[4] Y16 AD[6]
U17 DDQ[27] V17 DDQ[29] W17 AD[0] Y17 AD[3]
U18 VREF[1] V18 DDQ[24] W18 DDQ[28] Y18 DDQ[31]
U19 DDQ[20] V19 DDQ[22] W19 DDQ[25] Y19 DDQ[26]
U20 DDQ[18] V20 GND W20 DDQ[21] Y20 DDQ[23]

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Orion: STR91XX
CNS11XX
Data Sheet
2.2.3 CNS1104/STR9104 (LFBGA-257) Package Pin-Number vs. Pin-Name
Table 2-5. CNS1104/STR9104 Package Pin-Number vs. Pin-Name (In Order of Ball Number)
Ball No. Pin Name Ball No. Pin Name Ball No. Pin Name Ball No. Pin Name
A1 GND B1 PD[7]/SDQ[7] C1 PD[4]/SDQ[4] D1 PD[1]/SDQ[1]
A2 PD[9]/SDQ[9] B2 PD[2]/SDQ[2] C2 PA[12]/SA[12] D2 PA[11]/SA[11]
A3 PD[10]/SDQ[10] B3 PA[16]/SA[16] C3 PA[14]/SA[14] D3 PA[13]/SA[13]
A4 GND B4 PD[3]/SDQ[3] C4 PA[15]/SA[15] D4 CVDD
A5 PD[13]/SDQ[13] B5 PD[5]/SDQ[5] C5 PA[18]/SA[18] D5 CVDD
A6 PD[14]/SDQ[14] B6 PD[8]/SDQ[8] C6 PVDD D6 PVDD
A7 EXTGOICE/DBGRQ B7 PD[12]/SDQ[12] C7 PD[6]/SDQ[6] D7 AGND_SP
(GPIO[3])
A8 IDIO/TDO (GPIO[2]) B8 PD[15]/SDQ[15] C8 PD[11]/SDQ[11] D8 AVDD_SP
A9 SXOUT B9 ICK/TCK(GPIO[0]) C9 IMS/TMS D9 AGND_UP
(GPIO[1])
A10 SXIN B10 RESET_n C10 nTRST/GPIO[18] D10 AVDD_UP
A11 P1_DP B11 NC C11 TEST_MODE2 D11 AVDD_U
A12 P1_DM B12 UR_RTS(GPIO[7]) C12 TDI/GPIO[19] D12 AVDD_U
A13 UXIN B13 CLK12_OUT C13 DBGACK/GPIO[20] D13 AVDD_U33
A14 UXOUT B14 REXT C14 UR_CTS/GPIO[6] D14 AGND_U
A15 P0_DM B15 UR_RXD/GPIO[5] C15 V18_CTL D15 DA[3]
A16 P0_DP B16 UR_TXD/GPIO[4] C16 DA[0] D16 DA[2]
A17 GND B17 V25_CTL C17 DA[1] D17 DA[5]
E1 GND F1 PD[0]/SDQ[0] G1 REG_n/SA[22] H1 PA[1]/SA[1]
E2 PA[17]/SA[17] F2 PA[9]/SA[9] G2 PA[19]/SA[19] H2 PA[3]/SA[3]
E3 IOWR_n/SA[20] F3 IORD_n/SA[21] G3 PA[10]/SA[10] H3 PA[0]/SA[0]
E4 PVDD F4 PVDD G4 CVDD H4 CVDD
E5 F5 G5 H5
E6 F6 GND G6 GND H6 GND
E13 F13 G13 H13
E14 AGND_U F14 AGND_R G14 AVDD_R33 H14 CVDD
E15 DA[4] F15 DA[9] G15 BA[0] H15 BA[1]
E16 DA[6] F16 DA[8] G16 DA[12] H16 CAS_n
E17 DA[7] F17 DA[10] G17 DA[11] H17 DWE_n
J1 PWE_n/SWE_n K1 RESET/GPIO[15] L1 POE_n/SOE_n M1 GND
J2 PA[6]/SA[6] K2 PA[7]/SA[7] L2 PA[5]/SA[5] M2 NC
J3 PA[2]/SA[2] K3 PA[8]/SA[8] L3 PA[4]/SA[4] M3 IREQ_n/GPIO[1
4]
J4 PVDD_SW0 K4 GND L4 PVDD_SW1 M4 CVDD
J5 K5 L5 M5
J13 K13 L13 M13
J14 CVDD K14 PVDD_DDR L14 PVDD_DDR M14 PVDD_DDR

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Orion: STR91XX
CNS11XX
Data Sheet
J15 VREF K15 DM[1] L15 DM[0] M15 CK
J16 DDQ[0] K16 DDQ[4] L16 DDQ[7] M16 DDQ[10]
J17 RAS_n K17 DDQ[1] L17 DDQ[2] M17 DDQ[3]
N1 SCE0_n P1 SCE1_n R1 NC T1 NC
N2 INPACK_n/GPIO[17] P2 NC R2 CE1_n/GPIO[12] T2 EXT_INT
N3 MDIO P3 CE2_n/GPIO[13] R3 P0_COL/GPIO[9] T3 P0_TXD[2]
N4 CVDD P4 GND R4 P0_CRS/GPIO[8] T4 P0_TXD[1]
N5 P5 GND R5 MDC T5 P0_TXCLK
N6 P6 GND R6 NC T6 P0_RXD[3]
N7 P7 PVDD R7 NC T7 P0_RXCLK
N8 P8 PVDD R8 NC T8 P0_RXD[0]
N9 P9 CVDD R9 NC T9 P1_TXD[2]
N10 P10 CVDD R10 NC T10 P1_TXCLK
N11 P11 CVDD R11 NC T11 P1_TXD[0]
N12 P12 GND R12 NC T12 P1_RXD[0]
N13 P13 GND R13 P1_COL/GPIO[11] T13 P1_RXD[2]
N14 PVDD_DDR P14 GND R14 P1_CRS/GPIO[10] T14 P1_RXDV
N15 CK_n P15 CKE R15 DCS_n T15 DQS[0]
N16 DDQ[9] P16 DDQ[8] R16 DDQ[12] T16 DDQ[14]
N17 DDQ[5] P17 DDQ[6] R17 DDQ[11] T17 DDQ[13]
U1 GND V1 W1 Y1
U2 WAIT_n/GPIO[16] V2 W2 Y2
U3 P0_TXEN V3 W3 Y3
U4 P0_TXD[3] V4 W4 Y4
U5 P0_TXD[0] V5 W5 Y5
U6 P0_RXDV V6 W6 Y6
U7 P0_RXD[2] V7 W7 Y7
U8 P0_RXD[1] V8 W8 Y8
U9 P1_TXD[3] V9 W9 Y9
U10 P1_TXD[1] V10 W10 Y10
U11 P1_TXEN V11 W11 Y11
U12 P1_RXCLK V12 W12 Y12
U13 P1_RXD[1] V13 W13 Y13
U14 P1_RXD[3] V14 W14 Y14
U15 DQS[1] V15 W15 Y15
U16 DDQ[15] V16 W16 Y16
U17 GND V17 W17 Y17

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Orion: STR91XX
CNS11XX
Data Sheet
3.0 System Address Map and Register Descriptions
3.1 Memory Mapping
The following Table 3-1 shows 32-bit address memory map of all function blocks, external memory, and external
devices.
Table 3-1. Memory Map
Function Base Size of Descriptions
Address Region
Alias Memory 0x0000_0000 256MB Alias Memory Region.
Memory map has two states, one is Reset State; the other is Re-map State. After power on
reset, Memory map is at the Reset State, and the Flash/SRAM Memory Region is mapped
to the region, and system can be cold boot from external Flash Memory. After the
“Remap_Enable” bit (bit 0 of Memory Re-map Register of MISC Register Region) is set to
1, Memory map is changed to Re-map State, and the DDR SDRAM Memory Region is
mapped to the region.
Flash/SRAM Memory 0x1000_0000 256MB Flash/SRAM Memory Region.
External Flash or SRAM memory can be accessed through this region.
DDR SDRAM Memory 0x2000_0000 256MB DDR SDRAM Memory Region
External DDR SDRAM memory can be accessed through this region.
Static Memory Control 0x3000_0000 256MB Static Memory Control Register Region
Register The registers of Static Memory Controller (SMC) can be accessed through this region. SMC
supports two banks of Flash/SRAM memory. Bank 0 should be started from the Base
Address of Flash/SRAM Memory Region. And the starting address of Bank 1 can be
programmed through “Memory Bank 1 Configuration Register”.
DDR SDRAM Control 0x4000_0000 256MB DDR SDRAM Control Register Region.
Register The registers of DDR SDRAM Controller can be accessed through this region.
Reserved 0x5000_0000 256MB
Generic DMA Register 0x6000_0000 256MB Generic DMA (GDMA) Register Region
The registers of GDMA can be accessed through this region.
Switch and HNAT 0x7000_0000 16MB Switch and HNAT Register Region
Register The registers of Switch and HNAT can be accessed through this region.
Reserved 0x7100_0000 80MB
MISC Register 0x7600_0000 16MB MISC Register Region
Memory re-map control register, and PCI Bridge capability registers, and AHB bus control
register are collected at this region.
Power Management 0x7700_0000 16MB Power Management Register Region
Register The registers of Clock and Power Management can be accessed through this region.
UART Register 0x7800_0000 16MB UART Register Region
The registers of UART can be accessed through this region.
Timer Register 0x7900_0000 16MB Timer Register Region
The registers of Timer can be accessed through this region.
Watch Dog Timer 0x7A00_0000 16MB Watch Dog Timer (WDT) Register Region
Register The registers of WDT can be accessed through this region.
Real Time Clock 0x7B00_0000 16MB Real Time Clock (RTC) Register Region
Register The registers of RTC can be accessed through this region.
GPIO Register 0x7C00_0000 16MB GPIO Register Region
The registers of GPIO can be accessed through this region.
Interrupt Control 0x7D00_0000 16MB Interrupt Control Register Region
Register The registers of Interrupt Controller can be accessed through this region.
Reserved 0x7E00_0000 32MB
PCMCIA Control 0x8000_0000 256MB PCMCIA Control Register Region
Register The registers of PCMCIA Controller can be accessed through this region.
PCMCIA Attribute 0x9000_0000 64MB PCMCIA Attribute Memory Region
Memory A PCMCIA device’s Attribute Memory can be accessed through this region.
PCMCIA Common 0x9400_0000 64MB PCMCIA Common Memory Region
Memory A PCMCIA device’s Common Memory can be accessed through this region.
PCMCIA I/O Space 0x9800_0000 64MB PCMCIA I/O Space Region
A PCMCIA device’s I/O Space can be accessed through this region.
Reserved 0x9C00_0000 64MB

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Data Sheet
PCI Configuration Data 0xA000_0000 64MB PCI Configuration Data Register Region
Register The embedded PCI Bridge provides a configuration window (CONFIG_DATA and
CONFIG_ADDR registers) for Host CPU to configure all of attached PCI devices and the
PCI Bridge itself. CONFIG_DATA is the one and only one register at this region.
PCI Configuration 0xA400_0000 64MB PCI Configuration Address Register Region
Address Register The embedded PCI Bridge provides a configuration window (CONFIG_DATA and
CONFIG_ADDR registers) for Host CPU to configure all of attached PCI devices and the
PCI Bridge itself. CONFIG_ADDR is the one and only one register at this region.
PCI I/O Space 0xA800_0000 128MB PCI I/O Space Region
All of AHB bus transaction at this region will be translated to PCI bus I/O space transaction.
PCI Memory Space 0xB000_0000 256MB PCI Memory Space Region
All of AHB bus transaction at this region will be translated to PCI bus Memory space
transaction.
USB1.1 Configuration 0xC000_0000 64MB USB1.1 Configuration Register Region
Register USB1.1 Configuration registers can be accessed through this region.
USB1.1 Operation 0xC400_0000 64MB USB1.1 Operation Register Region
Register USB1.1 Operation registers can be accessed through this region.
USB2.0 Configuration 0xC800_0000 64MB USB2.0 Configuration Register Region
Register USB2.0 Configuration registers can be accessed through this region.
USB2.0 Operation 0xCC00_0000 64MB USB2.0 Operation Register Region
Register USB2.0 Operation registers can be accessed through this region.
Reserved 0xD000_0000 768MB

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Orion: STR91XX
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Data Sheet
3.2 Register Definitions
Table 3-2. Register Definitions

Offset Type Description Default
Static Memory Control Base Address: 0x3000_0000
0x00 RW Memory Bank 0(Flash) Configuration 0x1000_0801
0x04 RW Memory Bank 0(Flash) Timing Parameter 0x000f_F3FF
0x08 RW Memory Bank 1(SRAM) Configuration 0x0000_0800
0x0c RW Memory Bank 1(SRAM) Timing Parameter 0x000f_F3FF
SDRAM Control Base Address: 0x4000_0000
0x00 RW DDRC Timing Parameter 0 0x009e_EA88
0x04 RW DDRC Timing Parameter 1 0x0000_83C5
0x08 RW DDRC Configuration 0x0000_0000
0x0C RW External Bank Configuration 0x0000_01A0
0x10 RW Pad Power Down Control 0x0000_0000
0x14 RW DDQ Output Delay 0x0004_4444
0x18 RW DQS Input Delay 0x4444_4444
0x1C RW Pre-Read Enable 0x0000_0000
0x20 RW GDMA Pre-Read Time Out 0x0000_001F
0x24 RW Gigabit Switch (GSW) Pre-Read Time Out 0x0000_001F
0x28 RW USB2.0 Pre-Read Time Out 0x0000_001F
0x2C (Reserved)
Generic DMA (GDMA) Control Base Address: 0x6000_0000
0x00 RO Interrupt Status 0x0000_0000
0x04 RO Terminal Count Interrupt Status 0x0000_0000
0x08 WO Clear Terminal Count Interrupt
0x0C RO Error Interrupt Status 0x0000_0000
0x10 WO Clear Error Interrupt
0x14 RO Terminal Count Status 0x0000_0000
0x18 RO Error Status 0x0000_0000
0x1C RO Channel Enable Status 0x0000_0000
0x20 RO Channel Busy Status 0x0000_0000
0x24 RW Main Configuration 0x0000_0000
0x28 RW Synchronization Control 0x0000_0000
0x100 RW Channel 0 Control 0x0000_1200
0x104 RW Channel 0 Configuration 0x0000_0007
0x108 RW Channel 0 Source Address Undefined
0x10C RW Channel 0 Destination Address Undefined
0x114 RW Channel 0 Transfer Size Undefined

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Data Sheet
Switch Control Base Address: 0x7000_0000
0x000 PHY Control Register
0x004 Switch Configuration Register
0x008 MAC Port 0 Configuration Register
0x00C MAC Port 1 Configuration Register
0x010 CPU port configuration register
0x014 Priority Control Register
0x018 UDP Define Port Register
0x01C IP TOS 0~7 Priority Register
0x020 IP TOS 8~15 Priority Register
0x02C IP TOS 32~39 Priority Register
0x03C Scheduling Control Register
0x040 Rate Limit Control Register
0x044 Flow Control Global Threshold Register
0x048 Flow Control Port Threshold Register
0x04C Smart Flow Control Register
0x050 ARL Table Access Control 0 Register
0x05C Port VID Register
0x060 VLAN Group ID 0~1 Register
0x06C VLAN Group ID 6~7 Register
0x070 VLAN Port Map Register
0x074 VLAN Tag Port Map Register
0x078 Session ID 0~1 Register
0x07C Session ID 2~3 Register
0x088 Interrupt Status Register
0x08C Interrupt Mask Register
0x090 Auto-Polling PHY Address

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Data Sheet
0x094 Test 0 Register (Clock Skew Setting)
0x098 Test 1 Register (Queue Status and PHY Address)
0x09C Inter Switch Tag Control Register
0x100 TS_DMA Control Register
0x104 FS_DMA Control Register
0x108 TS Descriptor Pointer
0x10C FS Descriptor Pointer
0x110 TS Descriptor Base Address Register
0x114 FS Descriptor Base Address Register
0x118 Delayed Interrupt Configuration Register
(Reserved)
MISC Base Address: 0x7600_0000
0x00 RW Memory Re-map Register 0x0000_0000
(Reserved)
0x18 RW PCI 66MHz Capability Configuration Register 0x0000_0101
0x1C RW PCI Control Register 0x0000_011F
(Reserved)
0x34 RW AHB Arbiter Early Termination control 0x0000_000F
Power Management Base Address: 0x7700_0000
0x00 RW Clock Mask Control for AHB and APB devices 0x0001_00FE
0x04 RW Software Reset Control 0x0000_0001
0x08 RW System Clock Control 0x0000_0050
0x0C RW CPU Initialization Setting 0x1402_F9C0
0x10 RW PLL Power Down Control 0x0000_001E
0x14 RO Reset Latch Configuration Undefined
0x18 RW Regulator Control Register 0x0000_20F0
0x1C RW Pad Drive Strength Control Register 0x0000_0001
UART Base Address: 0x7800_0000
0x00 R Receive Data Port 0x0000_0000
W Transmit Data Port 0x0000_0000
DLAB=1 Baud Rate Divisor Latch Least Significant Byte 0x0000_0001
0x04 R/W Interrupt Enable 0x0000_0000
DLAB=1 Baud Rate Divisor Latch Most Significant Byte 0x0000_0000
0x08 R Interrupt Indication 0x0000_0001
W FIFO Control 0x0000_0000
DLAB=1 UART Clock Pre-scalar 0x0000_0000
0x0C RW Line Control 0x0000_0000
0x10 RW UART Control 0x0000_0000
0x14 R Line Status 0x0000_0060
W Test Control 0x0000_0000
0x18 RO UART Status 0x0000_0000
0x1C RW Scratch Pad Register. 0x0000_0000
Timer Base Address: 0x7900_0000
0x00 RW Timer 1 Counter 0x0000_0000
0x04 RW Timer 1 Auto Reload Value 0x0000_0000
0x08 RW Timer 1 Match Value 1 0x0000_0000

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Data Sheet
0x0C RW Timer 1 Match Value 2 0x0000_0000
0x10 RW Timer 2 Counter 0x0000_0000
0x14 RW Timer 2 Auto Reload Value 0x0000_0000
0x18 RW Timer 2 Match Value 1 0x0000_0000
0x1C RW Timer 2 Match Value 2 0x0000_0000
0x30 RW Timer 1 and 2 Control 0x0000_0000
0x34 RW Interrupt Status 0x0000_0000
0x38 RW Interrupt Mask 0x0000_0000
Watch Dog Timer Base Address: 0x7A00_0000
0x00 RO Watch Dog Timer Counter 0x03EF_1480
0x04 RW Watch Dog Timer Counter Auto Reload 0x03EF_1480
0x08 WO Watch Dog Timer Counter Restart 0x0000_0000
0x0C RW Watch Dog Timer Control 0x0000_0000
0x10 RO Watch Dog Timer Status 0x0000_0000
0x14 WO Watch Dog Timer Clear 0x0000_0000
0x18 RW Watch Dog Timer Interrupt Length 0x0000_00FF
Real Time Clock Base Address: 0x7B00_0000
0x00 RO RTC Second 0x0000_0000
0x04 RO RTC Minute 0x0000_0000
0x08 RO RTC Hour 0x0000_0000
0x0C RO RTC Day Count 0x0000_0000
0x10 RW RTC Second Alarm 0x0000_003F
0x14 RW RTC Minute Alarm 0x0000_003F
0x18 RW RTC Hour Alarm 0x0000_001F
0x1C RW RTC Record 0x0000_0000
0x20 RW RTC Control 0x0000_0000
0x34 RW RTC Interrupt 0x0000_0000
GPIO Base Address: 0x7C00_0000
0x00 RW GPIO Data Output 0x0000_0000
0x04 RO GPIO Data Input 0x0000_0000
0x08 RW GPIO Direction 0x0000_0000
0x0C (Reserved) 0x0000_0000
0x10 WO GPIO Data Bit Set 0x0000_0000
0x14 WO GPIO Data Bit Clear 0x0000_0000
0x20 RW GPIO Interrupt Enable 0x0000_0000
0x24 RO GPIO Interrupt Raw Status 0x0000_0000
0x28 RO GPIO Interrupt Masked Status 0x0000_0000
0x2C RW GPIO Interrupt Mask 0x0000_0000
0x30 WO GPIO Interrupt Clear 0x0000_0000
0x34 RW GPIO Interrupt Trigger Method 0x0000_0000
0x38 RW GPIO Interrupt Trigger by Both Edges 0x0000_0000
0x3C RW GPIO Interrupt Trigger by Rising/Falling Edge or High/Low Level. 0x0000_0000
0x40 RW Bounce Enable 0x0000_0000
0x44 RW Bounce Clock Pre-scale 0x0000_07D0
Interrupt Control Base Address: 0x7D00_0000
0x00 RO Interrupt Source 0x0000_0000

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Data Sheet
0x04 RW Interrupt Mask 0xFFFF_FFFF
0x08 WO Interrupt Clear 0x0000_0000
0x0C RW Interrupt Trigger Mode 0x0000_0000
0x10 RW Interrupt Trigger Level 0x0000_0000
0x14 RO Interrupt Status 0x0000_0000
0x18 RW FIQ Mode Select 0x0000_0000
PCMCIA Control Base Address: 0x8000_0000
0x00 RO Interface Status Register By card info.
0x04 RW Card Status Change Register 0x0000_0000
0x08 (Reserved) 0x0000_0000
0x0C RW Card Detect and Global Control Register 0x0000_0000
0x10 RW Interrupt Configuration Register 0x0000_0000
0x14 RW Memory Access Timing Control Register 0 0x0000_0000
0x18 RW Memory Access Timing Control Register 1 0x0000_0000
0x1C RW IO Access Timing Control Register 0 0x0000_0000
0x20 RW IO Access Timing Control Register 1 0x0000_0000
PCI Bridge Configuration-Data Base Address: 0xA000_0000
0x00 RW CONFIG_DATA
PCI Bridge Configuration-Address Base Address: 0xA400_0000
0x00 RW CONFIG_ADDR
USB1.1 Controller Configuration Base Address: 0xC000_0000

0x04-05 RW Command Register 0x0000
(Recommend to configuring this register as 0x0006)
0x44 RW Operational Mode Enable Register 0x22
USB1.1 OHCI Operation Register Base Address: 0xC400_0000
0x0 RO HcRevision 0x0000_0110
0x4 RW HcControl 0x0000_0000
0x8 RW HcCommandStatus 0x0000_0000
0xC RW HcInterruptStatus 0x0000_0000
0x10 RW HcInterruptEnable 0x0000_0000
0x14 RW HcInterruptDisable 0x0000_0000
0x18 RW HcHCCA 0x0000_0000
0x1C RW HcPeriodCurrentED 0x0000_0000
0x20 RW HcControlHeadED 0x0000_0000
0x24 RW HcControlCurrentED 0x0000_0000
0x28 RW HcBulkHeadED 0x0000_0000
0x2C RW HcBulkCurrentED 0x0000_0000
0x30 RW HcDoneHead 0x0000_0000
0x34 RW HcFmInterval 0x0000_2EDF
0x38 RO HcFmRemaining 0x0000_0000
0x3C RO HcFmNumber 0x0000_0000
0x40 RW HcPeriodicStart 0x0000_0000
0x44 RW HcLSThreshold 0x0000_0628
0x48 RW HcRhDescriptorA 0x0100_0002
0x4C RW HcRhDescriptorB 0x0000_0000

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Data Sheet
00x50 RW HcRhStatus 0x0000_0000
00x54 RW HcRhPortStatus[1] 0x0000_0000
00x58 RW HcRhPortStatus[2] 0x0000_0000
USB2.0 (EHCI) Controller Configuration Register Base Address: 0xC800_0000
0x04-05 RW Command Register 0x0000
0x40-43 RW Operational Mode Enable Register 0x0000_0080
USB2.0 (EHCI) Controller Operational Register Base Address: 0xCC00_0000
0x00 RO CAPLENGTH 0x20
Capability Register Length
0x01 - (Reserved) -
0x02-03 RO HCIVERSION 0x0100
Interface Version Number
0x04-07 RO HCSPARAMS 0x0010_1202
Structural Parameters
0x08-0B RO HCCPARAMS 0x0000_7070
Capability Parameters
0x0C-1F - (Reserved) -
0x20-23 RW USB2CMD 0x0008_0000
USB2.0 Command
0x24-27 RW USB2STS 0x0000_1000
USB2.0 Status
0x28-2B RW USB2INTR 0x0000_0000
USB2.0 Interrupt Enable
0x2C-2F RW FRINDEX 0x0000_0000
USB2.0 Frame Index
0x30-33 - (Reserved) -
0x34-37 RW PERIODICLISTBASE Undefined
Frame List Base Address
0x38-3B RW ASYNCLISTADDR Undefined
Next Asynchronous List Address
0x3C-3F - (Reserved) -
0x60-63 RW CONFIGFLAG 0x0000_0000
Configured Flag Register
0x64-67 RW PORTSC0 0x0000_3000
Port Status/Control
0x68-6B RW PORTSC1 0x0000_3000
Port Status/Control

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Orion: STR91XX
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Data Sheet
3.3 Detailed Register Descriptions (In terms of functional blocks)
In the Table 3-1, register access type notations are described for reference.
Table 3-3. Access Type Notations

Type Description
RO Read Only.
If a register is read only, writes have no effect.
WO Write Only.
If a register is write only, reads return un-predictable value.
RW Read/Write.
A register with this type can be read and written.
R/WC Read/Write Clear.
A register with this type can be read and written. However, a write of a 1 clears the corresponding
bit and a write of a 0 has no effect.
3.3.1 Static Memory Control
0x00 – Memory Bank 0 Configuration Register

Bits Type Name Description Default
31:29 Reserved 3’b0
28 RW BNK_EN Bank Enables 1’b1
1: Enable
0: Disable
27:15 RW BNK_BASE Bank Base Address. 13’b0
The value of this register configures the base address
from bit 27 to bit 15 of this bank. Since CPU boot from
address 0x0000_0000, the base address of Bank 0 (Flash
Memory) should be set to 0x0000.
11 RW BNK_WPROT Bank Write Protected. 1’b1
If BNK_WPROT is set to 1, the memory bank can’t be
written. Any write to protected bank will cause ERROR
response on AHB. If BNK_WPROT is 0, the
corresponding bank can be read or written.
10:8 RW These bits are for test purpose. Please keep them as default. 3’b0
7:4 RW BNK_SIZE Bank Size. 4’b0
The following encoding shows the size of bank. Bank
size other than the following values may cause
unexpected error.
1011: 32KB.
1100: 64KB.
1101: 128KB.
1110: 256KB.
1111: 512KB.
0000: 1MB.

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Data Sheet
0001: 2MB.
0010: 4MB.
0011: 8MB.
0100: 16MB.
0101: 32MB.
3:1 Reserved 3’b0
0 RW BNK_MBW Memory Bus Width. Set by inverse of
This register indicates the bus width of external memory external
bus. configuration
0: Memory data width is 8. pin SA[8].
1: Memory data width is 16.
0x04 – Memory Bank 0 Timing Parameter Register

31:28 WO ETRNA Extended Turn-around Time. 4’hF
Please view the TRNA below for detail.
Note: It is write-only registers, its value is un-visible,
and its default value after reset is 4’hF.
27:24 WO EAT1 Extended Access Time 1. 4’hF
Please view the AT1 below for detail.
23:20 Reserved 4’h1
19:18 RW AST Address Setup Time. 2’b11
This register specifies the latency, in turns of system
clock cycle, needed to assert read-enable or write-enable
after address assertion.
2’b00: 1 cycle
2’b01: 2 cycles
2’b10: 3 cycles
2’b11: 4 cycles
17:16 RW WTC Write-enable to Chip-enable Delay. 2’b11
clock cycle, needed to assert chip-enable after
write-enable or read-enable assertion.
2’b00: 0 cycle
2’b01: 2 cycles
2’b10: 3 cycles
2’b11: 4 cycles
15:12 RW AT1 Access Time 1. 4’hF
The combined {EAT1, AT1} specifies the low pulse
width of chip-enable “SCE0_n” for accessing external
SRAM device in turns of system clock cycle.
{EAT1, AT1}:
8’h00: 1 cycles
8’h01: 2 cycles
…

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Data Sheet
8’hFF: 256 cycles
7:6 RW CTW Chip-disable to Write-disable Delay. 2’b11
clock cycle, needed to de-assert write-enable or
read-enable after chip-enable de-assertion.
Latency of chip-disable to write-disable:
2’b00: 0 cycle
2’b01: 2 cycles
2’b10: 3 cycles
2’b11: 4 cycles
Latency of chip-disable to read-disable:

2’b00: -1 cycle
2’b01: 1 cycles
2’b10: 2 cycles
2’b11: 3 cycles
5:4 RW AHT Address Hold Time. 2’b11
clock cycle, needed to de-assert address after
write-enable/read-enable de-assertion.
2’b00: 1 cycle
2’b01: 2 cycles
2’b10: 3 cycles
2’b11: 4 cycles
3:0 RW TRNA Turn-around Time. 4’hF
The combined {ETRNA, TRNA} specifies the latency
needed to re-drive data bus in turns of system clock
cycle.
{ETRNA, TRNA}:
8’h00: 1 cycles
8’h01: 2 cycles
…
8’hFF: 256 cycles
0x08 – Memory Bank 1 Configuration Register

28 RW BNK_EN Bank Enable 1’b0
1: Enabled
0: Disabled
27:15 RW BNK_BASE Bank Base Address. 13’b0
The value of this register configures the base address
from bit 27 to bit 15 of this bank.
11 RW BNK_WPROT Bank Write Protected. 1’b1
If BNK_WPROT is set to 1, the memory bank can’t be

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Data Sheet
written. Any write to protected bank will cause ERROR
response on AHB. If BNK_WPROT is 0, the
corresponding bank can be read or written.
10:8 RW Reserved These bits are for test purpose. Please keep them as 3’b0
default.
7:4 RW BNK_SIZE Bank Size. 4’b0000
The following encoding shows the size of bank. Bank
size other than the following values may cause
unexpected error.
1011: 32KB.
1100: 64KB.
1101: 128KB.
1110: 256KB.
1111: 512KB.
0000: 1MB.
0001: 2MB.
0010: 4MB.
0011: 8MB.
0100: 16MB.
0101: 32MB.
3:1 Reserved 3’b0
0 RW BNK_MBW Memory Bus Width. 1’b0
This register indicates the bus width of external memory
bus.
0: Memory data width is 8
1: Memory data width is 16
0x0C – Memory Bank 1 Timing Parameter Register

31:28 WO ETRNA Extended Turn-around Time. 4’hF
Please view the TRNA below for detail.
27:24 WO EAT1 Extended Access Time 1. 4’hF
Please view the AT1 below for detail.
19:18 RW AST Address Setup Time. 2’b11
clock cycle, needed to assert read-enable or write-enable
after address assertion.
2’b00: 1 cycle
2’b01: 2 cycles
2’b10: 3 cycles
2’b11: 4 cycles
17:16 RW WTC Write-enable to Chip-enable Delay. 2’b11

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Data Sheet
clock cycle, needed to assert chip-enable after
write-enable or read-enable assertion.
2’b00: 0 cycle
2’b01: 2 cycles
2’b10: 3 cycles
2’b11: 4 cycles
15:12 RW AT1 Access Time 1. 4’hF
The combined {EAT1, AT1} specifies the low pulse
width of chip-enable “SCE1_n” for accessing external
SRAM device in turns of system clock cycle.
{EAT1, AT1}:
8’h00: 1 cycles
8’h01: 2 cycles
…
8’hFF: 256 cycles
7:6 RW CTW Chip-disable to Write-disable Delay. 2’b11
clock cycle, needed to de-assert write-enable or
read-enable after chip-enable de-assertion.
Latency of chip-disable to write-disable:
2’b00: 0 cycle
2’b01: 2 cycles
2’b10: 3 cycles
2’b11: 4 cycles
Latency of chip-disable to read-disable:

2’b00: -1 cycle
2’b01: 1 cycles
2’b10: 2 cycles
2’b11: 3 cycles
5:4 RW AHT Address Hold Time. 2’b11
clock cycle, needed to de-assert address after
write-enable/read-enable de-assertion.
2’b00: 1 cycle
2’b01: 2 cycles
2’b10: 3 cycles
2’b11: 4 cycles
3:0 RW TRNA Turn-around Time. 4’hF
The combined {ETRNA, TRNA} specifies the latency
needed to re-drive data bus in turns of system clock
cycle.
{ETRNA, TRNA}:
8’h00: 1 cycles
8’h01: 2 cycles

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Data Sheet
…
8’hFF: 256 cycles
3.3.2 DDR SDRAM Control
0x00 – DDRC Timing Parameter 0 Register

31:25 R Reserved. 7’b0

24:22 RW CASL Set DDR Device CAS Latency. 3’b010
010: CASL = 2.
110: CASL = 2.5.
Others: reserved
21 RW DLL_Disable Set DDR Device DLL Enable/Disable. 1’b0
The DLL must be enabled for normal operation. When
the part is running without the DLL enable, device
functionality may be altered.
0: DLL Enabled.
1: DLL Disabled.
20:19 RW Reserved 2’b11
18:17 RW tMRD Minimum cycle time of LOAD MODE REGISTER 2’h3
command.
16:14 RW tRAS Minimum cycle time of ACTIVE to PRECHARGE 3’h3
command.
13:10 RW tRFC Minimum cycle time of AUTO-REFRESH command 4’hA
period.
9:8 RW tRCD Minimum cycle time of ACTIVE to READ or WRITE 2’h2
command.
7:6 RW tRP Minimum cycle time of PRECHARGE command period. 2’h2
5:4 Reserved 2’h0
3:2 RW tWR Write Recovery cycle time 2’h2
1:0 R Reserved 2’h0
Note: the above default settings are subject to 256Mb DDR running at 125MHz.
0x04 –DDRC Timing Parameter 1 Register


15:12 RW TARF Number of AUTO-REFRESH commands in a burst. 4’h8
Note the JEDEC specification allows a maximum of
“eight” AUTO REFRESH commands can be posted to
any given DDR SDRAM to improve efficiency in
scheduling and switching between tasks. The TRAF
should be limited to be not larger than 8.
11:0 RW tREFI AUTO-REFRESH command average Interval. 12’h3C5
This value is constrained by DDR SDRAM component

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Data Sheet
used. The average auto refresh period (tREFI) of
different size DDR SDRAM is showed below:
64Mb, 128Mb: 15.6 μs.
256Mb, 512Mb: 7.8 μs.
For example, a 256Mb DRAM running at 125MHz,
the tREFI should be set as 7.8us or a little bit less than
7.8ns. (7.8us/8ns cycle = 12’h3CF)
Note: the above default settings are subject to 256Mb DDR running at 125MHz.
0x08 – DDRC Configuration Register

1 R ICMP Initial Complete Flag. 1’b0
When Initial procedures are finished, ICMP will be set
to 1.
0 W ISTRT Initial Sequence Start. 1’b0
If ISTRT is set to 1, DDR device initialization sequence
will be progressed again.
0x0C – Bank Configuration Register

31: 9 Reserved 23’b0
8 RW BNK_EN Bank Enable 1’b0
1: Enable.
0: Disabled
7:6 RW BNK_DDW DDR SDRAM Data Width. 2’b10
This register indicates the data width of individual
SDRAM module.
00: x4 device.
01: x8 device.
10: x16 device.
11: reserved.
5:4 RW BNK_DSZ DDR SDRAM Size. 2’b10
This register indicates the size of individual DDR
SDRAM module.
00: 64Mb.
01: 128Mb.
10: 256Mb.
11: 512Mb.
3:1 Reserved 3’b0
0 RW BNK_MBW Memory Bus Width. 1’b0
This register indicates the bus width of external memory
bus.
0x10 – Pad Power Down Control Registers

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Orion: STR91XX
CNS11XX
Data Sheet
1 RW HW_Pad_PD Power Down Higher Half-Word Pad Receiver. 1’b0
0: pad receiver of DDQ[31:16] and DQS[3:2] in active
1: pad receiver of DDQ[31:16] and DQS[3:2] power
down
0 RW LW_Pad_PD Power Down Lower Half-Word Pad Receivers. 1’b0
0: pad receiver of DDQ[15:0] and DQS[1:0] in active
1: pad receiver of DDQ[15:0] and DQS[1:0] power
down
0x14 – DDQ Output Delay

19:16 RW hclk_dly HCLK Sync. Delay Control 4’h4
This is to adjust system clock to synchronize data from
DDR receive path. Typically, each step is with 0.4ns
variance.
Suggest re-configuring the delay control to 4’h7.
15 Reserved 1’b0
14:12 RW DDQ_Out_Dly3 Byte Lane 3 DDQ[31:24] Output Delay Control 3’h4
This is to adjust delay of Byte –Lane 3 transmitting data
to meet DDR write timing spec. Typically, each step is
with 0.4ns variance.
11 Reserved 1’b0
10:8 RW DDQ_Out_Dly2 Byte –Lane 2 DDQ[23:16] output delay control 3’h4
7 Reserved 1’b0
3 Reserved 1’b0
0x18 – DQS Input Delay

31 Reserved 1’b0
30:28 RW Dqs_ In_Dly3_n Byte Lane 3 DQS[3] input falling edge sample delay 3’h4
This is to adjust delay of DQS[3] input falling edge to
sample DDQ[31:24]. Typically, each step is with 0.4ns
variance.

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Orion: STR91XX
CNS11XX
Data Sheet
27 Reserved 1’b0
variance.
23 Reserved 1’b0
variance.
19 Reserved 1’b0
variance.
15 Reserved 1’b0
14:12 RW Dqs_In_Dly3 Byte Lane 3 DQS[3] input rising edge sample delay 3’h4
This is to adjust delay of DQS[3] input rising edge to
variance.
11 Reserved 1’b0
variance.
7 Reserved 1’b0
variance.
3 Reserved 1’b0
variance.
0x1C – Pre-Read Enable

7:0 RW Pre_Read_Enable AHB Channel Pre-Read Enable. (HIGH active) 8’h00
Pre-Read is an enhanced ability to read external
DRAM’s data, suitable for bulk data transfer. These
register bits can enable the following function blocks’
pre-read function.
Pre_Read_Enable[0]: CPU
Pre_Read_Enable[1]: Generic DMA
Pre_Read_Enable[2]: Switch Rx_DMA

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Orion: STR91XX
CNS11XX
Data Sheet
Pre_Read_Enable[3]: PCI
Pre_Read_Enable[4]: USB2.0
Pre_Read_Enable[5]: USB1.1
Pre_Read_Enable[6]: Reserved
Pre_Read_Enable[7]: Switch Tx_DMA
0x20 – GDMA Pre-Read Time Out

5:0 RW Pre_Read_Time_Out0 GDMA Pre-Read time out. 6’h1F
This is to set the cycle time of pre-read data time out.
After time out, the pre-read data at GDMA channel is
invalidated.
0x24 – Gigabit Switch(GSW) Pre-Read Time Out

5:0 RW Pre_Read_Time_Out1 GSW Pre-Read time out 6’h1F
After time out, the pre-read data at GSW channel is
invalidated.
0x28 – USB2.0 Pre-Read Time Out

5:0 RW Pre_Read_Time_Out2 USB2.0 Pre-Read time out 6’h1F
After time out, the pre-read data at USB2.0 channel is
invalidated.
0x2C – Reserved
3.3.3 Generic DMA (GDMA) Controller
0x00 – Interrupt Status Register (INT)

3 RO INT[3] Status of GDMA Interrupts after Masking 1’b0
(Channel-3).
0: no pending interrupt at channel-3.
1: with pending interrupt at channel-3.
(Channel-2).

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Orion: STR91XX
CNS11XX
Data Sheet
(Channel-1).
(Channel-0).
0x04 – Terminal Count Interrupt Status Register (INT_TC)

3 RO INT_TC[3] Status of GDMA Terminal Count Interrupts After 1’b0
Masking (Channel-3)
Masking (Channel-2)
Masking (Channel-1)
Masking (Channel-0)
0x08 – Terminal Count Interrupt Status Clear Register(INT_TC_CLR)

31:4 Reserved
3 WO INT_TC_CLR[3] Write 1 to clear the INT_TC[3] and TC[3] status
0x0C – Error Interrupt Status Register (INT_ERR)

3 RO INT_ERR[3] Status of GDMA Error Interrupts After Masking 1’b0
(Channel-3)
0: No pending interrupt.
1: With pending interrupt.
(Channel-2).

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Orion: STR91XX
CNS11XX
Data Sheet
(Channel-1).
(Channel-0).
0x10 – Error Interrupt Status Clear Register (INT_ERR_CLR)

31:4 Reserved
3 WO INT_ERR_CLR[3] Write 1 to clear the INT_ERR[3] and ERR[3] status
0x14 – Terminal Count Status Register (TC)

3 RO TC[3] Status of GDMA Terminal Count (Channel-3). 1’b0
0: No terminal count status.
1: With terminal count status.
0x18 – Error Status Register (ERR)

3 RO ERR[3] Status of GDMA Error (Channel-3). 1’b0
0: No error status.
1: With error status.
2 RO ERR[2] Status of GDMA Error (Channel-2). 1’b0
0: No error status.
1 RO ERR[1] Status of GDMA error (Channel-1). 1’b0
0: No error status.
0 RO ERR[0] Status of GDMA error (Channel-0). 1’b0
0: No error status.

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Orion: STR91XX
CNS11XX
Data Sheet
0x1C – Channel enable Status Register (CH_EN_FLAG)

3 RO CH3_EN_FLAG Status of Channel 3 CH_EN on the C3_CSR register. 1’b0
0: CH_EN = 0.
1: CH_EN = 1.
0: CH_EN = 0.
1: CH_EN = 1.
0: CH_EN = 0.
1: CH_EN = 1.
0: CH_EN = 0.
1: CH_EN = 1.
0x20 – Channel Busy Status Register (CH_BUSY_FLAG)

3 RO CH3_BUSY_FLAG Status of Channel 3 BUSY on the C3_CFG Register. 1’b0
0: BUSY = 0.
1: BUSY = 1.
2 RO CH2_BUSY_FLAG Status of the channel 2 BUSY on the C2_CFG Register. 1’b0
0: BUSY = 0.
1: BUSY = 1.
0: BUSY = 0.
1: BUSY = 1.
0: BUSY = 0.
1: BUSY = 1.
0x24 –Main Configuration Status Register (CSR)

2 RW M1ENDIAN Master 1 Endian Configuration. 1’b0
0: Little-endian mode.
1: Reserved
1 RW M0ENDIAN Master 0 Endian Configuration. 1’b0
0: Little-endian mode.
1: Reserved
0 RW DMACEN GDMA Controller Enable. 1’b0
0: Disable.
1: Enable.

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Orion: STR91XX
CNS11XX
Data Sheet
0x28 – Synchronous Register (SYNC)

3 RW Hardware DMA Request Synchronization Logic 1’b0
Enable for Channel 3
0: Disable.
1: Enable.
0: Disable.
1: Enable.
0: Disable.
1: Enable.
0: Disable.
1: Enable.
0x100 – Channel 0 Control Register (C0_CSR)

23:22 RW CHPRI Channel Priority Level. 2’b00
11: highest priority.
10: 2nd high priority.
01: 3rd high priority.
00: lowest priority (default).
21 RW PROT3 HPROT[3]: Protection Information for Cacheable. 1’b0
0: Not cacheable (default).
1: Cacheable.
20 RW PROT2 HPROT[2]: Protection Information for Bufferable. 1’b0
0: Not bufferable (default).
1: Bufferable.
19 RW PROT1 HPROT[1]: Protection information for the mode 1’b0
0: User mode (default).
1: Privileged mode.
18:16 RW SRC_SIZE Source Burst Size Selection. 3’b000
000: burst size = 1(default).
001: burst size = 4.

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Orion: STR91XX
CNS11XX
Data Sheet
Note: Source burst size is not relative to the HBRUST (AHB
signals), it just means how many transfers before the DMA
re-arbitrate among active channels.
15 WO ABT Transaction Abort. 1’b0
Write 1 to this bit will cause the DMA to stop its current
transfer, set the ERR bit and assert interrupt.
14 Reserved. 1’b0
13:11 RW SRC_WIDTH Source Transfer Width. 3’b010
The hardware automatically packs and unpacks the data
as required.
000: Transfer width is 8 bits.
010: Transfer width is 32 bits (default).
Others: Reserved.
Notice:
If source transfer width < destination transfer width, DMA
will pack input data. For example: source transfer width =
8bit, destination transfer width = 32bit, then DMA will pack
four 8bit source data and transfer one 32bit data.
Limitation: Don’t’ set SRCAD_CTL = 01(decrement source
address) when pack function works, DMA will have a wrong
action.
If source transfer width > destination transfer width, DMA
will unpack input data. For example: source transfer width =
32bit, destination transfer width = 8bit, then DMA will
unpack one 32bit source data and transfer four 8bit data to
destination.
10:8 RW DST_WIDTH Destination Transfer Width. 3’b010
The hardware automatically packs and unpacks the data
as required.
010: Transfer width is 32 bits (default).
Others: Reserved.
7 RW MODE Mode of Operation. 1’b0
0: Normal Mode (default).
1: Hardware Handshake Mode.
Note:
Hardware Handshake Mode is only effective in channel
2(0x140) with UART_TX as the destination, and in channel
3(0x160) with UART_RX as the source.
6:5 RW SRCAD_CTL Source Address Control. 2’b00

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Orion: STR91XX
CNS11XX
Data Sheet
00: Increment source address (default)
01: Decrement source address
10: Fixed source address.
11: Reserved.
Notice: Don’t’ set SRCAD_CTL = 01(decrement source
address) when pack function works, DMA will have a wrong
action.
4:3 RW DSTAD_CTL Destination Address Control. 2’b00
00: Increment destination address (default).
01: Decrement destination address.
10: Fixed destination address.
11: Reserved
2 RW SRC_SEL Selection of AHB Master as Source. 1’b0
0: AHB Master 0 is the source (default).
1: AHB Master 1 is the source.
1 RW DST_SEL Selection of AHB Master as Destination. 1’b0
0: AHB Master 0 is the destination (default).
1: AHB Master 1 is the destination.
0 RW CH_EN Channel Enabled 1’b0
0: Disable (default).
1: Enable.
0x104 – Channel 0 Configuration Register (C0_CFG)

31:9 RO Reserved. 23’b0
8 RO BUSY The DMA channel is BUSY. 1’b0
2 RW INT_ABT_MSK Channel Abort Interrupt Mask. 1’b1
0: interrupt enabled.
1: Mask interrupt (default).
1 RW INT_ERR_MSK Channel Error Interrupt Mask. 1’b1
0 RW INT_TC_MASK Channel Terminal Count Interrupt Mask. 1’b1
0x108 –Channel 0 Source Address Register (C0_SrcAddr)


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Orion: STR91XX
CNS11XX
Data Sheet
31:0 RW SrcAddr Source Address Undefined
0x10C –Channel 0 Destination Address Register (C0_DstAddr)

31:0 RW DstAddr Destination Address Undefined
0x114 –Channel 0 Transfer Size Register (C0_SIZE)

31:12 Reserved.
11:0 RW TOT_SIZE Total Transfer Size. Undefined
NOTE: The transfer unit depends on the source width.
For example:
SRC_WIDTH=000, unit: 8bit.
3.3.4 Embedded Switch Controller (including HNAT and MAC)
0x000- PHY Control Register

31:16 RW rw_data Read/Write Data. 16’b0
For write command, the write data should be ready
here before issuing write command.
For read command, when rw_ok is asserted, the
register data is ready here.
15 RW rw_ok Read/Write Command Has Completed, write 1 to 1’b0
clear
14 RW rd_cmd Read Command, self clear 1’b0
13 RW wt_cmd Write Command, self clear 1’b0
12:8 RW phy_register PHY Register Address. 5’h00
7:1 Reserved
0 RW phy_addr[0] PHY Address. 1’b0
Note that this bit is to be concatenated with
bit [19:16] of 0x098 register to form the PHY address
for PHY commands.
0x004- Switch Configuration Register

30 RW NIC_mode Network Ports Are Treated as NICs. 1’b0

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Orion: STR91XX
CNS11XX
Data Sheet
All rx packets are not modified and note that the
switch is auto-configured as port-based VLAN in NIC
mode.
29:28 RW Skip_L2_lookup Skip_L2_lookup is used to emulate NIC’s 2’b00
miscellaneous mode. At this mode, all of incoming
packets will be received to CPU. (High active)
bit 29: skip L2 lookup from port 1
bit 28: skip L2 lookup from port 0
27:25 Reserved
24 RW Firewall_mode Firewall Mode. 1’b0
Send IPV4H5NF (no need to match my_mac) packets
to HNAT for firewall application.
23 RW HNAT_en Hardware NAT Accelerator Enable. 1’b0
0: Disable
1: Enable
22 RW IVL Independent VLAN Learning Enable. 1’b1
0: Share VLAN Learning (SVL).
1: IVL.
21 RW crc_stripping CRC Stripping. 1’b1
0: Keep original CRC when transmitting.
1: Strip CRC when RX, and regenerate it when TX.
20:19 RW col_mode Collision Mode. 2’b11
00: Never drop (except late collision)
01: Collision limit = 1
10: Collision limit = 2
11: Collision limit = 16 (standard)
18 RW rev_mc_flt Reserved Multicast Address Filtering. 1’b0
0: Forward.
1: Filter.
Note: Reserved MC = 01-80-C2-00-00-00 (BPDU) and
01-80-C2-00-00-02 ~0F
17:16 RW bp_mode Back Pressure Mode. 2’b10
00: Disable back-pressure.
01: Smart back-pressure, the jam number is set by
“jam_no”.
10: Jam all incoming packets until back-pressure
condition released.
11: Force carrier HIGH to do back-pressure.
15:12 RW jam_no Back Pressure Consecutive Jam Number. 4’hA
In back-pressure mode, when the consecutive jam
number is reached, this port will receive one packet
without jamming.
11 Reserved
10:8 RW bkoff_mode Collision Back Off Timer Setting. 3’b111
000: Re-transmit immediately after collision.
001~110: Back off range 0~2^(N-1).
111: Follow standard.

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Orion: STR91XX
CNS11XX
Data Sheet
7:6 RW hash_alg MAC Address Hashing Algorithm. 2’b00
00: Direct mode, using last 10-bit as hashing
address.
01: XOR48 mode.
10: XOR32 mode.
11: reserved.
5:4 RW max_len Maximum Packet Length. 2’b01
00: 1518 bytes.
01: 1522 bytes.
10: 1536 bytes
11: 9K bytes (Jumbo frame).
Note: When set maximum packet length to 9K bytes, all
ports (include CPU) support 9K bytes jumbo frames.
3:0 RW age_time Aging Time Setting. 4’h1
0000: Disable aging.
0001~0111: 2^(N-1) * 300sec.
1xxx: Fast aging (around 60sec).
0x008 - MAC Port 0 Configuration Register

0x00C- MAC Port 1 Configuration Register
31 RW BCS_bc_pkt_en Enable the inclusion of broadcast packets into 1’b0
Broadcast Storm Rate Control.
0: Disable
1: Enable
30 RW BCS_mc_pkt_en Enable the inclusion of multicast packets into 1’b0
0: Disable
1: Enable
29 RW BCS_un_pkt_en Enable the inclusion of unknown packets into 1’b0
0: Disable
1: Enable
28 RW dis_uc_pause Disable the treating of unicast pause frames as 802.3x 1’b0
pause frames.
0: Enable unicast pause frame
1: Disable unicast pause frame
Note that the following conditions must be met to treat
a packet as a unicast pause frame
1. DA is unicast and with destination to CPU
2. TYPE and OP-code fields match pause frame
format
When disable unicast pause frame, the received unicast
pause frame will be forwarded to CPU and not be
treated as a pause frame. When enable unicast pause
frame, the received unicast pause frame will be treated
as a pause frame and dropped.

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Orion: STR91XX
CNS11XX
Data Sheet
27 RW bc_pkt_dis Disable Forwarding broadcast packets to CPU 1’b0
0: Forward broadcast packets to CPU.
1: Don’t forward broadcast packets to CPU.
26 RW mc_pkt_dis Disable Forwarding Multicast Packets to CPU. 1’b0
0: Forward multicast packets to CPU.
1: Don’t forward multicast packets to CPU
25 RW un_pkt_dis Disable Forwarding Unknown Packets to CPU. 1’b0
0: Forward unknown packets to CPU.
1: Don’t forward unknown packets to CPU.
24 RW ingress_check Ingress Check Enable. 1’b0
When ingress_check is enabled, if the receiving
packet has a VLAN ID tagged which the receiving
port is not belonged to, the receiving packet will be
dropped.
23 RW SA_secured SA Secured Mode. 1’b0
0: Forward packets without caring if SA matched.
1: Only forward packets with SA matched and
port number matched.
Note: SA secured function works only when SA learning
disable.
22 RW age_en Aging Enable. 1’b1
0: MAC address belonging to the port doesn’t be
aged out.
1: Aging enable.
21 RW block_mode Block Mode. 1’b0
0: Forward all packets to CPU in blocking state
1: Only forward control packets (BPDU) to CPU
in blocking state.
20 RW blocking _state Blocking State. 1’b0
In blocking state, no learning, and no transmitting, but
only forward qualified packets to CPU.
19 RW learn_dis SA Learning Disable. 1’b0
18 RW port_dis Port Disable. 1’b0
17 RW bp_en Back Pressure Enable. 1’b1
Need to qualify bp_mode.
16 RW Reserved 1’b0
15 RW rgmii_phy RGMII_PHY used. 1’b0
Setting rgmii_phy will enable the MAC to use RGMII
interface and operate at 10/100/1000 triple speeds.
Otherwise, MAC will use MII (or reverse-MII, if
rev_MII_RGMII is set) interface and can only operate
at 10/100 mode of operation.
1: RGMII interface is used
0: MII or reverse-MII interface is used
14 RW rev_MII_RGMII Reversed RGMII/MII Mode Enable. 1’b0
0: Normal RGMII/MII mode (MAC side)
1: Reversed RGMI/MII mode (PHY side)

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Orion: STR91XX
CNS11XX
Data Sheet
Note: when in reversed RGMII/MII mode, the interface
must be configured by force mode.
Inter-connection in reversed MII mode:
(CNS11XX/
STR91XX side) (External MAC side)
RXC Æ TXC
TXC Æ RXC
TXD Æ RXD
TXEN Æ RXDV
RXD Å TXD
RXDV Å TXEN
COL Æ COL
CRS Æ CRS
Inter-connection in reversed RGMII mode:
(CNS11XX/
STR91XX side) (External MAC side)
RXC Å TXC
TXC Æ RXC
TXD Æ RXD
TX_CTL Æ RX_CTL
RXD Å TXD
RX_CTL Å TX_CTL
13 RW txc_check_en TX Clock Period Checking Enable. 1’b1
If more than 400ns, disable the MAC port.
12 RW force_fc_tx Force TX flow control when MI disabled (only for 1’b1
1000Mbps mode)
0: TX flow control OFF.
1: TX flow control ON.
11 RW force_fc_rx Force Rx Flow Control when MI disabled. 1’b1
10/100Mbps mode:
0: Flow Control OFF
1: Flow Control ON
1000Mbps mode:
0: RX Flow Control OFF
1: RX Flow Control ON
10 RW force_duplex Force Duplex when MI disabled. 1’b1
0: Half-duplex.
1: Full-duplex.
9:8 RW force_speed Force Speed when MI disabled. 2’b01
00: 10Mbps.
01: 100Mbps.
10: 1000Mbps.
11: reserved.
7 RW AN_en Auto-Negotiation Enable. 1’b1
Setting this bit will enable PHY auto-negotiation and
use the polling results from PHY as the operation
modes.
Clearing this bit will disable PHY auto-negotiation and

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Orion: STR91XX
CNS11XX
Data Sheet
use forced operation modes (forced_spd,
forced_dpx…). Also, the forced operation modes will
be written to PHY to make the PHY and MAC
operations consistent.
6 RO fc_tx_st TX Flow Control Status (only for 1000Mbps mode).
0: TX Flow Control OFF
1: TX Flow Control ON
5 RO fc_rx_st RX Flow Control Status.
10/100Mbps mode:
0: Flow Control OFF
1: Flow Control ON
1000Mbps mode:
0: RX Flow Control OFF
1: RX Flow Control ON.
4 RO duplex_st Duplex Status.
0: Half-duplex.
1: Full-duplex.
3:2 RO speed_st Speed Status.
00: 10Mbps.
01: 100Mbps.
10: 1000Mbps.
11: reserved.
1 RO txc_st TX Clock Status.
0: Normal.
1: No TXC, or clock period too long.
0 RO link_st PHY Link Status.
0: Link down.
1: Link up.
0x010- CPU Port Configuration Register

31 RW Offset_2bytes Word Alignment Offset Enabled To CPU Port. 1’b0
The valid memory address pointed in the field

seg_data_ptr of RX DMA descriptor shall be either
4*N+2 or 4*N-aligned:
0: de-align to (4*N+2) address offset.
1: align to word-aligned (4*N) address offset.
24 RW ingress_check Ingress Check Enable. 1’b0
23 RW SA_secured SA Secured Mode. 1’b0
0: Forward packets without checking if SA
matched
1: Only forward packets with SA matched and
port-number matched.
Note: SA secured function works only when SA learning
disable.
22 RW age_en Aging Enable. 1’b1

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Orion: STR91XX
CNS11XX
Data Sheet
0: MAC address belonging to the port doesn’t be
aged out.
1: Aging enable
19 RW learn_dis SA Learning Disable. 1’b1
18 RW port_dis Port Disable. 1’b1
0x014- Priority Control Register

23:21 RW upd_pri Priority of UDP packet received from all ports. 3’b0
20:18 RW port_pri_CPU Priority of all packets received from CPU port. 3’b0
17:15 RW port_pri_1 Priority of all packets received from Port 1. 3’b0
14:12 RW port_pri_0 Priority of all packets received from Port 0. 3’b0
11:9 RW tos_pri_en IP TOS Priority Check Enable. 3’b0
bit 9: Port 0.
bit 10: Port 1.
bit 11: CPU Port.
8:6 RW udp_pri_en Per port UDP Packet Priority Check Enable. 3’b0
bit 6: Port 0.
bit 7: Port 1.
bit 8: CPU port.
5:3 RW vlan_pri_en Per port VLAN Priority Check Enable. 3’b0
bit 3: Port 0.
bit 4: Port 1.
bit 5: CPU port.
2 RW regen_user_pri Regenerate User Priority in TX Priority Tag. 1’b0
0: Keep original priority tag of the received packet
when forwarding if the received packet has
priority tag.
1: Regenerate user priority by switch priority
setting when forwarding.
1:0 traffic_class Number of Traffic Class: 2’b0
00: 1 traffic class.
11: reserved.
Warning: Do not change traffic_class setting if
there are packets in switch. Must disable switch and
wait for all packets released before changing
traffic_class.
Available traffic
classes
1 2 4
User 0(dft) 0 0 1
priority 1 0 0 0
2 0 0 0
3 0 0 1
4 0 1 2

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Orion: STR91XX
CNS11XX
Data Sheet
5 0 1 2
6 0 1 3
7 0 1 3
0x018- UDP Priority Register

15:0 RW udp_defined_port If RX packet is a UDP packet, its source port and 16’d0
destination port will be compared to this defined port
#. If either one matches, this packet will use upd_pri
as its priority.
Note: The first received/transmitted byte of port number
from network is deposited at high byte
(udp_defined_port[15:8]). For example, web port = 0x0080,
then udp_defined_port[15:0] = 0x0080.
0x01C- IP TOS 0~7 Priority Register

23:21 RW TOS7_pri Priority of IP packets with TOS = 7 3’b0
0x020- IP TOS 8~15 Priority Register



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Orion: STR91XX
CNS11XX
Data Sheet

0x02C- IP TOS 32~39 Priority Register


0x034-- IP TOS 48~55 Priority Register

0x038-- IP TOS 56~63 Priority Register


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Orion: STR91XX
CNS11XX
Data Sheet
0x03C—Scheduling Control Register

18:16 RW Q3_weight Queue 3 Weight. 3’d3
0: weight = 1
1: weight = 2
2: weight = 4
3: weight = 8
4: weight = 16
5~7: reserved
1:0 RW sch_mode Scheduling Mode. 2’b01
00: WRR(Q3, Q2, Q1, Q0).
01: Strict priority, Q3 > Q2 > Q1 > Q0.
10: Mix mode, Q3 > WRR(Q2, Q1, Q0).
11: Reserved.
0x040-- Rate Limit Control Register

27:24 RW BCS_rate Broadcast Storm Rate = 64kbps * 2^N, N=0~10. 4’d0
22:16 RW p1tx_bw Port 1 TX Bandwidth. 7’d0
14:8 RW p0tx_bw Port 0 TX Bandwidth. 7’d0
0: Disable rate limit control
1~127: Bandwidth = N*base_rate
5:4 RW p1_base_rate Port 1 Base Rate. 2’b10
00: 64Kbps.
01: 1Mbps.
10: 10Mbps.
11: reserved.
3:2 RW p0_base_rate Port 0 Base Rate. 2’b10
00: 64Kbps.
01: 1Mbps.
10: 10Mbps.
11: reserved.
1:0 RW egress_bkt_size Max Bucket Size for Egress Rate Limit. 2’b11
00: 1.5K bytes.
01: 3K bytes.

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Orion: STR91XX
CNS11XX
Data Sheet
10: 9K bytes.
11: 12K bytes.
Note that the setting will impact the precision of
applied algorithm. The user is recommended to use the
largest value of 2'b11.
0x044-- Flow Control Global Threshold Register

23:20 RW mc_fc_rls MC Flow Control Release Threshold (for 4’d2
4-traffic-class mode). Unit: packet
19:16 RW mc_fc_set MC Flow Control Assert Threshold (for 4-traffic-class 4’d4
mode). Unit: packet
14:8 RW fc_rls Flow Control Release Threshold. Unit: page 7’d68
6:0 RW fc_set Flow Control Assert Threshold. Unit: page 7’d57
0x048—Flow Control Port Threshold Register

30:24 RW port_pri3_th MAC and CPU Port Buffer Threshold (for priority 3 7’d8
packets). Unit: page
0x04C—Smart Flow Control Register

9:8 RW smart_spd_HNAT HNAT Speed Used for Smart Flow Control. 2’b01
00: rate-limited to 10Mbps level.
11: reserved.
7:6 RW smart_spd_CPU CPU Port Speed Used for Smart Flow Control. 2’b01
11: reserved
5:4 RW smart_spd1 Port 1 Speed Used for Smart Flow Control. 2’b11
11: follow network speed
00: rate-limited to 10Mbps level
3:2 RW smart_spd0 Port 0 Speed Used for Smart Flow Control. 2’b11
11: follow network speed

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1 RW smart_fc_2 Smart Flow Control Order 2 Enable. 1’b0
When enabled, and flow control threshold reached,
and the speed of source port is TWO-order higher than
destination port, then this packet will be dropped
instead of flow control.
0 RW smart_fc_1 Smart Flow Control Order 1 Enable. 1’b0
When enabled, and flow control threshold reached,
and the speed of source port is ONE-order higher than
destination port, then this packet will be dropped
instead of flow control.
0x050—ARL Table Access Control 0 Register

3 RW wt_cmd ARL Table Write Command. 1’b0
Write this MAC address entry prepared in ARL Table
Access Control 1 and 2 registers into ARL table.
It is self-cleared.
2 RW lkup_cmd ARL Table Look-up Command. 1’b0
Read the entry of the ARL table belonging to the MAC
address and VLAN ID (if IVL) in ARL Table Access
Control 1 and 2 registers. Before issuing this command,
MAC address and VLAN ID (if IVL) must be ready. It
is self-cleared.
1 RW srch_again_cmd Search for the next valid address. It is self-cleared. 1’b0
0 RW srch_start_cmd Searching for the valid entries from the start of address 1’b0
table. It is self-cleared.
0x054-- ARL Table Access Control 1 Register

31:24 RW MAC[39:32] MAC address [39:32] of the address entry, which is 8’b0
read from or will be written to an entry of the ARL
table or for address table look up.
Note: The first received/transmitted byte of MAC address
from network is deposited at higher byte (MAC[47:40]). For
example, Pause Frame MAC = 0x01-80-C2-00-00-01,
MAC[47:40] = 0x01, MAC[39:32} = 0x80, MAC[31:24] =
0xC2, … and MAC[7:0] = 0x01. Please note that, through
the data sheet, all Ethernet Frame fields, defined in registers
or tables, for example, the above UDP port number of UDP
Priority Register, are higher byte ordering, that is
transmit/receive higher byte first.
table or for address table look up.
13:11 RW port_map Port map of the address entry, which is read from or 3’b0
will be written to an entry of the ARL table.

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10:8 RW age_field Age field of the address entry, which is read from or 3’b0
7:5 RW vlan_id VLAN group ID of the address entry, which is read 3’b0
from, or will be written to an entry of the ARL table, or
for IVL address table look up.
4 RW vlan_mac “vlan_mac” bit of the address entry, which is read 1’b0
from or will be written to an entry of the ARL table.
3 RW filter Filter bit of the address entry, which is read from or 1’b0
2 RO lkup_srch_match There is an entry in the address table, which matches
the look up MAC address and VLAN ID (if IVL) or
searching up one valid entry. The exact action depends
on what the command is executed.
1 RO table_end Search to the end of the address table
0 RO cmd_complete The ARL table access command has completed.
0x058-- ARL Table Access Control 2 Register

31:24 RW MAC[7:0] MAC address [7:0] of the address entry, which is read 8’b0
from or will be written to an entry of the ARL table, or
for address table look up.
23:16 RW MAC[15:8] MAC address [15:8] of the address entry, which is read 8’b0
from or will be written to an entry of the ARL table, or
for address table look up.
table, or for address table look up.
table, or for address table look up.
0x05C-- Port VID Register

10:8 RW pvidCPU PVID of CPU Port. 3’d0
6:4 RW pvid1 PVID of Port 1. 3’d0
2:0 RW pvid0 PVID of Port 0. 3’d0
0x060-- VLAN Group ID 0~1 Register

23:12 RW gid1 Physical VLAN ID of Virtual Group ID 1. 12’h002
0x064-- VLAN Group ID 2~3 Register


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Data Sheet
0x068--VLAN Group ID 4~5 Register

0x06C-- VLAN Group ID 6~7 Register

0x070--VLAN Port Map Register

23:21 RW vlan_group7 Port map of virtual group ID 7 3’b000
2:0 RW vlan_group0 Port map of virtual group ID 0. 3’b111
bit 0: Port 0.
bit 1: Port 1.
bit 2: CPU port
0x074-- VLAN Tag Port Map Register

23:21 RW vlan7_tagging Tag Port Map of Virtual Group ID 7. 3’b000
2:0 RW vlan0_tagging Tag port map of Virtual Group ID 0. 3’b111
bit 0: Port 0.
bit 1: Port 1.
bit 2: CPU Port.
0x078-- Session ID 0~1 Register

31:16 RW session1 Physical Session ID of Virtual Session ID 1. 16’b0
0x07C-- Session ID 2~3 Register


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Data Sheet


0x088-- Interrupt Status Register

(Note: All of the register’s bits are “write 1 clear”)
31 RW Port1_ingress_drop Drop by Ingress Check. 1’b0
30 RW Port1_local_drop Drop by Local Traffic. 1’b0
29 RW Port1_RMC_drop This bit is asserted and the received packet will be 1’b0
Port1_RMC_Pause_drop dropped when the following conditions occurred
1. When reserved multicast packet is received
and rev_mc_flt (bit 18 of register 0x004) is set.
2. When unicast pause frame is received and
dis_uc_pause (bit24 of register 0x00C) is 0.
3. When normal pause frame is received (DA =
0x0180C2000001, and TYPE and OP-code
fields match pause frame format).
28 RW Port1_no_destination_drop Drop by Queue Full. 1’b0
This flag is asserted when a packet is received but no
where to forward. It could be caused by
1. RX port flow control off and drop threshold
(same as flow control threshold) reached.
2. Ingress check fail
3. Unknown VLAN
4. reserved multicast filtering
5. destination port in block state
6. local packet
27 RW Port1_jammed_drop Drop by Backpressure. 1’b0
When the bit is asserted, means the port has ever
jammed receiving packet at half-duplex mode due to
flow control threshold reached.
26 RW Port1_rx_error_drop Drop by RX Packet Error. 1’b0
This flag indicates one of the following situations
occurred.
1. CRC error
2. Runt Frame and CRC error
3. Oversize Frame and CRC error
4. SFD Fail

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5. Dribble bit error
6. Runt Frame and CRC OK
7. Oversize Frame and CRC OK
25 RW Port1_BCS_drop Drop by Broadcast Storm. 1’b0
Drop receiving broadcast/multicast/unknown unicast
packet due to Broadcast Storm Prevention threshold
reached.
24 RW Port1_no_link_drop Drop by No Free Links. 1’b0
Drop receiving packet due to no more packet buffer
available for the packet.
23 RW Port0_ingress_drop Drop by Ingress Check. 1’b0
22 RW Port0_local_drop Drop by Local Traffic. 1’b0
21 RW Port0_RMC_drop This bit is asserted and the received packet will be 1’b0
Port0_RMC_Pause_drop dropped when the following conditions occurred
1. When reserved multicast packet is received
and rev_mc_flt (bit 18 of register 0x004) is set.
2. When unicast pause frame is received and
dis_uc_pause (bit24 of register 0x008) is 0.
3. When normal pause frame is received (DA =
0x0180C2000001, and TYPE and OP-code
fields match pause frame format).
20 RW Port0_no_destination_drop Drop by Queue Full. 1’b0
This flag is asserted when a packet is received but no
where to forward. It could be caused by
1. RX port flow control off and drop threshold
(same as flow control threshold) reached.
2. Ingress check fail
3. Unknown VLAN
4. reserved multicast filtering
5. destination port in block state
6. local packet
19 RW Port0_jammed_drop Drop by Backpressure. 1’b0
When the bit is asserted, means the port has ever
jammed receiving packet at half-duplex mode due to
flow control threshold reached.
18 RW Port0_rx_error_drop Drop by RX Packet Error. 1’b0
This flag indicates one of the following situations
occurred.
1. CRC error
2. Runt Frame and CRC error
3. Oversize Frame and CRC error
4. SFD Fail
5. Dribble bit error
6. Runt Frame and CRC OK
7. Oversize Frame and CRC OK
17 RW Port0_BCS_drop Drop by Broadcast Storm. 1’b0
Drop receiving broadcast/multicast/unknown unicast

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packet due to Broadcast Storm Prevention threshold
reached.
16 RW Port0_no_link_drop Drop by No Free Links. 1’b0
Drop receiving packet due to no more packet buffer
available for the packet.
15:13 Reserved
12 RW CPU_unknown_vlan Port CPU Received Packets with Unknown VLAN 1’b0
11 RW Port1_unknown_vlan Port 1 Received Packets with Unknown VLAN 1’b0
10 RW Port0_unknown_vlan Port 0 Received Packets with Unknown VLAN 1’b0
9 RW CPU_hold Obsolete 1’b0
8 RW Intruder1 Port 1 Received Intruder Packets. 1’b0
This flag will be asserted when port 1 is in SA secured
mode and disable SA learning, and a received packet’s
SA lookup mismatches. The packet will be dropped.
7 RW Intruder0 Port 0 Received Intruder Packets. 1’b0
This flag will be asserted when port 0 is in SA secured
mode and disable SA learning, and a received packet’s
SA lookup mismatches. The packet will be dropped.
6 RW port_status_chg Assert When Any Port Change Link State. 1’b0
(link up ÅÆ link down).
5 RW buffer_full All Pages of Packet Buffer are Used. 1’b0
4 RW Global_Q_full Assert When Global Threshold Reached. 1’b0
3 RW HNAT_Q_full Assert When Global Threshold Reached and HNAT 1’b0
port Queue threshold reached.
2 RW CPU_Q_full Assert When Global Threshold Reached and CPU port 1’b0
Queue Threshold Reached.
1 RW port1_Q_full Assert When Global Threshold Reached and Port 1 1’b0
Queue threshold reached.
0 RW port0_Q_full Assert When Global threshold reached and Port 0 1’b0
Queue threshold reached.
0x08C-- Interrupt Mask Register

31:0 RW int_mask Interrupt Mask of Interrupt Status Register bit 31~0. 32’hFFFFFFFF
0x090-- Auto-Polling PHY Address

10:8 RW phy_add1[3:1] The PHY address of Port 1 used for auto-polling. 3’b0
Note that bit 6 and 10:8 of 0x090 and bit 26 of 0x098
are concatenated to form the PHY address of
Port 1 for auto-polling.
6 RW phy_add1[0] The PHY address of Port 1 used for auto-polling. 1’b1
Note that bit 6 and 10:8 of 0x090 and bit 26 of 0x098 are
concatenated to form the PHY address of Port 1 for
auto-polling.
Note that bit 1:0 and 5:4 of 0x090 and bit 25 of

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0x098 are concatenated to form the PHY
address of Port 0 for auto-polling.
Note that bit 1:0 and 5:4 of 0x090 and bit 25 of 0x098
are concatenated to form the PHY address of Port 0 for
auto-polling.
0x094-- Test 0 Register (Clock Skew Setting)

31:30 RW port1_tx_skew The skew adjustment between Port-1 RGMII Tx clock 2’b01
and Tx data/enable. To meet RGMII 2.0 timing spec,
please set this as 2’b10. That is, the default value must
be overwritten.
00: 0 ns.
01: 1.5 ns.
10: 2.0 ns.
11: 2.5 ns.
29:28 RW port1_rx_skew The skew adjustment between Port-1 RGMII Rx clock 2’b00
and Rx data/enable.
00: 0 ns.
01: 1.5 ns.
10: 2.0 ns.
11: 2.5 ns.
27:26 RW port0_tx_skew The skew adjustment between Port-0 RGMII Tx clock 2’b01
and Tx data/enable. To meet RGMII 2.0 timing spec,
please set this as 2’b10. That is, the default value must
be overwritten.
00: 0 ns.
01: 1.5 ns.
10: 2.0 ns.
11: 2.5 ns.
25:24 RW port0_rx_skew The skew adjustment between Port-0 RGMII Rx clock 2’b00
and Rx data/enable.
00: 0 ns.
01: 1.5 ns.
10: 2.0 ns.
11: 2.5 ns.
20:0 Reserved Reserved
0x098-- Test 1 Register (Queue Status and PHY Address)

Note that bit 6 and 10:8 of 0x090 and bit 26 of 0x098 are
concatenated to form the PHY address of Port 1 for
auto-polling.
Note that bit [1:0] and [5:4] of 0x090 and bit 25 of

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0x098 are concatenated to form the PHY address of
Port 0 for auto-polling.
24 RW sim_mode Simulation Mode to Accelerate Timers. 1’b0
It is a test mode, user must not to set it to 1.
22:21 RO Tx_bw_cntl_on Port Map of TX Bandwidth Control On Flag
Each bit is asserted when related port TX bandwidth
threshold reached. At asserted stage, no packet is
transmitted from the port.
bit 21: Port 0.
bit 22: Port 1.
20 RO HNAT_Q_full HNAT Queue Instant Status.
Assert When Global Threshold Reached and HNAT
port Queue threshold reached.
19:16 RW phy_addr[4:1] The PHY address used to read/write PHY commands. 4’d0
Note that bit [19:16] of 0x098 and bit 0 of 0x000 are
concatenated to form the PHY address for PHY
commands.
15:12 RO Port1_Q_full Port 1 Priority Queues Instant Status.
Asserted when Global Threshold Reached and port 1
related priority queue threshold reached.
bit 12: Priority 0 queue status.
11:8 RO Port0_Q_full Port 0 Priority Queues Instant Status.
Asserted when Global Threshold Reached and port 0
related priority queue threshold reached.
7:0 RO free_link_cnt Free Pages Count of Packet Buffer.
The packet buffer total has 192 pages and is linked at
Free-Page-Linker. When ports request some pages to
store RX packet, the free page count will decrease. And
when packets are transmitted, these pages will be
released to the Free-Page-Linker, and the free page
count will increase. The register field shows current
free pages count for reference.
0x09C—Inter Switch Tag Control Register

2:0 RW reserve_ist Handle all the Rx packets as VLAN tagged packets and 3’b000
not remove VLAN tag from the packet. It is dedicated
for inter-switch tag application.
bit 0: Port 0.
bit 1: Port 1.

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bit 2: CPU port
0x0A0~0x0FF Reserved
0x100, TS_DMA Control Register

0 RW TS_EN z Writing 1 will start the TS_DMA to transmit the 1’b0
packet if there are packets stored in DRAM
chained by TS_Descriptor.
z Writing 0 will stop TS_DMA operation after the
current ongoing whole packet is transmitted.
z TS_DMA will clear this bit, if it reads a descriptor
with C=1, or any bus error occurs.
0x104-- FS_DMA Control Register

0 RW FS_EN z Writing 1 will start FS_DMA to receive the 1’b0
incoming packets from Switch. If FS_DMA is
already in the running mode (not in IDLE state,
but including WAIT_FS_DATA state), writing 1
to this bit will take no effect.
z Writing 0 will stop FS_DMA after FS_DMA
completes the current whole packet moving and
return to IDLE state. If FS_DMA is already in the
IDLE state, writing 0 will take no effect.
z This bit will be cleared by HW, if FS_DMA reads
a descriptor with C=1, or any bus error occurs
0x108-- TS Descriptor Pointer

31:2 RW TSSD TS_Descriptor Starting Address. 30’b0
This field indicates the starting address of the
TS_Descriptor chain.
TS_DMA reads the descriptor from this location when
it is enabled. The address is 32-bit alignment.
0x10C-- FS Descriptor Pointer

31:2 RW FSSD FS_Descriptor Starting Address. 30’b0
This field indicates the starting address of the
FS_Descriptor chain.
FS_DMA reads the descriptor from this location when
it is enabled. The address is 32-bit alignment.
0x110-- TS Descriptor Base Address Register

31:2 RW TS_BASE Base Address of TS_Descriptor Ring. 30’b0
The address is with 32-bit alignment.

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0x114-- FS Descriptor Base Address Register

31:2 RW FS_BASE Base Address of FS_Descriptor Ring. 30’b0
The address is with 32-bit alignment.
0x118—Delayed Interrupt Configuration Register

31:17 Reserved
16 RW DLEAY_INT_EN 1: Enable delayed interrupt mechanism. 1’b0
0: Disable delayed interrupt mechanism.
15:8 RW MAX_PEND_INT_CNT Specified Max # of pended FSRC_INT. 8’b0
When the # of pended FSRC_INT equal or grater than
the value specified here or interrupt pending time
reach the limit(See bellow), an Final FSRC_INT is
generated.
7:0 RW MAX_PEND_TIME Specified Max pending time for the internal FSRC_INT. 8’b0
When the pending time equal or grater
MAX_PEND_TIME x 20us or , the # of pended
FSRC_INT equal or grater than
MAX_PEND_INT_CNT (see above), an Final
FSRC_INT is generated
0x11C~0x1FF --Reserved
0x200~0x298 --Reserved
3.3.5 MISC Control Registers
0x00 – Memory Re-map Register

31:1 RO Reserved. 31’h00000000
0 RW RemapEn Remap Enable. 1’b0
After set, it can only be cleared by reset.
0: alias 0x10000000 as 0x00000000
1: alias 0x20000000 as 0x00000000
0x04, 0x08, 0x0C, 0x10, 0x14 – Reserved
0x18– PCI 66MHz Capability Configuration Register

31:1 RW Reserved 31’h80
0 RW run_66MHz 66 MHz Capability 1’b1
This bit can indicate to PCI devices whether or not this
PCI bridge is capable of running at 66MHz.
0: running at only 33MHz
1: can support 66MHz operation

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0x1C – PCI Control Register

8 RW hs_fast This bit can be set to 1 to improve the performance of 1’b1
AHB-to-PCI write accesses. Set it to 1 improves the
latency of PCI master write accesses.
This input should be set to 1 if the AHB clock runs faster
than the PCI clock. It should be set to 0 if the CPU clock
does not run faster than the PCI clock. If clock speeds
are undetermined, hs_fast should be set to 0.
7:0 RW Reserved 8’h1F
0x20, 0x24, 0x28, 0x2C, 0x30 – Reserved
0x34 –Early Termination Control Register for AHB controller

5:0 RW TransCtl 0: The burst transfer is not always terminated, except 6’h0F
when receiving an error / split / retry response.
>0: The burst transfer is always terminated, after one
data has been transferred ok.
3.3.6 Clock/Power Management
0x00 – Clock mask control for AHB and APB devices.

16 RW PCLK_UART_MEN PCLK of UART Mask Enable. 1’b1
0: Enable clock.
1: Disable clock.
15:7 RO Reserved 9’b0
5 RW USB_MEN HCLK of USB Mask Enable. 1’b1
0: Enable clock.
1: Disable clock.
The following steps must be followed to enable USB

function:
1. Select a USB clock source (pin SA[13] pull-down
(default), select internal 12MHz clock as the clock
source; SA[13] pull-up, select XTAL12 as clock
source, and the configuration result is showed at bit 13
of Reg. 0x14 (USB_CLK_SEL)).
2. Enable relative clock source (clear PLL300_PWD of
Reg. 0x10 if USB_CLK_SEL = 0, clear
USBXTAL_PWD and PLLUSB_PWD of Reg. 0x10 if
USB_CLK_SEL = 1)

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3. De-assert mask of HCLK of USB (clear USB_MEN)
4. De-assert USB software reset bit (set USB_SWRn of
Reg. 0x04)
4 RW SWITCH_MEN HCLK and PCLK of Switch Mask Enable. 1’b1
0: Enable clock.
1: Disable clock.
The following steps must be followed to enable switch

function:
1. Enable PLL125 (clear PLL125_PWD of Reg. 0x10)
2. De-assert mask of HCLK and PCLK of switch (clear
SWITCH_MEN)
3. De-assert switch software reset bit (set Switch_SWRn
of Reg. 0x04)
3 RW HCLK_DMA_MEN HCLK of Generic DMA Mask Enable. 1’b1
0: Enable clock.
1: Disable clock.
The following steps must be followed to enable DMA

function:
1. De-assert mask of HCLK of DMA (clear
HCLK_DMA_MEN)
2. De-assert switch software reset bit (set DMA_SWRn
of Reg. 0x04)
2 RW PCI_MEN HCLK of PCI Bridge Mask Enable. 1’b1
0: Enable clock.
1: Disable clock.
The following step must be followed to enable PCI Bridge
function:
1. If exact 33M or 66MHz PCI clock is needed, enable
PLL330 (clear PLL330_PWD of Reg. 0x10)
2. Select a PCI clock source (PCI_Source_Sel of Reg.
0x08)
3. Set PCI_DIV to get required frequency
4. De-assert mask of PCI clock and HCLK of PCI Bridge
(clear PCI_MEN)
5. De-assert PCI Bridge software reset bit (set
PCI_SWRn of Reg. 0x04)
1 RW HCLK_PCMCIA_MEN HCLK of PCMCIA Mask Enable. 1’b1
0: enable clock.
1: disable clock.
The following step must be followed to enable PCMCIA

function:
1. De-assert mask of HCLK of PCMCIA (clear
HCLK_PCMCIA_MEN)
2. De-assert PCMCIA software reset (set
PCMCIA_SWRn of Reg. 0x04)

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0 RW HCLK_SMC_MEN HCLK of Static Memory Control Mask Enable. 1’b0
0: Enable clock.
1: Disable clock.
0x04 – Software reset control

6 RW UART_SWRn UART Software Reset. (LOW active) 1’b0
It is needed to program it low, then high to generate a
reset low pulse.
5 RW USB_SWRn USB Software Reset. ( LOW active) 1’b0
reset low pulse.
4 RW Switch_SWRn Switch Software Reset. (LOW active) 1’b0
reset low pulse.
Note: The Switch Software Reset only reset Switch core
and HNAT core and HNAT register to initial state. It
does not reset Switch’s register to default value.
3 RW DMA_SWRn Generic DMA Software Reset. (LOW active) 1’b0
reset low pulse.
2 RW PCI_SWRn PCI Bridge Software Reset. (LOW active) 1’b0
reset low pulse.
1 RW PCMCIA_SWRn PCMCIA Software Reset. (LOW active) 1’b0
reset low pulse.
0 RW Global_SWRn Global Software Reset. (LOW active) 1’b1
When the bit is programmed to low, the whole system is
reset. It will be auto cleared to high after 2 APB clocks.
0x08 – System clock control register

31:12 RO Reserved 20’ b0
11:10 RW PCI_DIV PCI Clock Divider. 2’b00
00: divided by 1.
01: divided by 2.
10: divided by 3.
11: divided by 4.
8 RW PCI_Source_Sel PCI Clock Source Select. 1’b0
0: from CLK66.
1: from APB clock.
5:4 RW HCLK_DIV HCLK Clock Divider. Dividend: FCLK. 2’b01

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00: divided by 1.
01: divided by 2.
10: divided by 3.
11: divided by 4.
3:2 RW FCLK_DIV CPU Clock Divider. 2’b00
Dividend: PLL output clock.
00: divided by 1.
01: divided by 2.
10: divided by 3.
11: divided by 4.
1:0 RW PLL_Sel PLL Frequency Select. Set by external
00: 175MHz. configuration
01: 200MHz. pins SA[7:6]
10: Reserved.
11: Reserved.
0x0C – CPU Initialization Register

31:22 Reserved
21:16 RW PAT PLL Acquisition Time. 6’b000010
This field defines the time the PLL need to be stable
when power on or leaving power down mode. The PLL
stable time is defined as wake_up_time = (PAT + 1) *
1024 / OSCIN, where OSCIN = 25MHz.
15:0 RW Reserved
0x10 – PLL Power Down Control Register

5 RW SYSTEM_XTAL_PWD Enable System XTAL (25MHz) Power Down Function 1’b0
0: Never power down
1: Power down when CPU enters sleep mode
4 RW USBXTAL_PWD Power Down XTAL Pad in USB PHY. 1’b1
1: Power down
3 RW PLLUSB_PWD Power Down PLL in USB PHY. 1’b1
1: Power down
2 RW PLL330_PWD Power Down PLL-330 (for PCI Bridge). 1’b0
1: Power down
1 RW PLL300_PWD Power Down PLL-300 (for USB). 1’b0
1: Power down
0 RW PLL125_PWD Power Down PLL-125 (for Switch MAC). 1’b0
1: Power down
0x14 – Reset Latch Configuration Register

31:17 RO Reserved

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16 RO PCMCIA_Disable PCMCIA Interface Disable. Set by external
0: PCMCIA Interface Enable configuration pin
1: Disable PCMCIA interfaces and treat these SA[16].
pins (CE1_n, CE2_n, IREQ_n, RESET,
WAIT_n, INPACK_n) as GPIOs.
15 RO P1_CRSCOL_as_GPIO Treat MAC port 1 CRS and COL as GPIO if high. Set by external
configuration pin
SA[15].
14 RO P0_CRSCOL_as_GPIO Treat MAC port 0 CRS and COL as GPIO if high. Set by external
configuration pin
SA[14].
13 RO USB_CLK_SEL USB 12MHz Clock Source Select. Set by external
0: Internal 12MHz clock source. configuration pin
1: External 12MHz XTAL. SA[13].
12 RO Reserved Set by external
configuration pin
SA[12].
11 RO Low_CPUClkSel Low CPU Clock Operation Set by external
0: CPU clock is as the following “CPUClkSel” configuration pin
described. SA[11].
1: CPU clock frequency is reduced by 2 times
further from CPUClkSel’s description.
10 RO Reserved Set by external
configuration pin
SA[10].
9 RO UART_Enable UART Interface Enable. Set by external
0: Disable UART interfaces and use these pins configuration pin
as GPIO pins. SA[9].
1: UART Interface Enable.
8 RO FlashDW_8 Flash Memory Data Bus Width. Set by external
0: 16 bits. configuration pin
1: 8 bits. SA[8].
7:6 RO CPUClkSel CPU Initial Clock Frequency Select. Set by external
00: 175MHz. configuration pin
01: 200MHz. SA[7:6].
10: Reserved.
11: Reserved.
5 RO ICESEL ICE Select. Set by external
0: ARM-like ICE. configuration pin
1: ARM Multi-ICE. SA[5].
4 RO JTAG_Enable ICE Interface Enable. Set by external
0: Disable ICE interfaces and use these pins as configuration pin
GPIO pins. SA[4].
1: ICE interface enable.
3 RO endian Endian. Set by external
0: Little Endian. configuration pin

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Data Sheet
1: Reserved SA[3].
2:1 RO TEST_MODE[1:0] It is for test purpose. Set by external
configuration pin
SA[2:1].
0 RO BYPASS It is for test purpose. Set by external
configuration pin
SA[0].
0x18 – Regulator Control Register

13:11 RW vdd_18_sel Control 1.8V Regulator Regulated vdd Output. 3’b100
000: vdd=1.477V.
001: vdd=1.532V.
010: vdd=1.592V.
011: vdd=1.655V.
100: vdd=1.724V.
101: vdd=1.799V.
110: vdd=1.881V.
111: vdd=1.977V.
10:9 RW gm2_18 Adjust 1.8V Regulator Loop Stability. 2’b00
00: I=60μA.
01: I=90μA.
10: I=120μA.
11: I=150μA.
8:6 RW vdd_25_sel Control 2.5V Regulator Regulated vdd Output. 3’b011
000: vdd=2.079V.
001: vdd=2.189V.
010: vdd=2.310V.
011: vdd=2.445V.
100: vdd=2.598V.
101: vdd=2.772V.
110: vdd=2.969V.
111: vdd=3.193V.
5:4 RW gm2_25 Adjust 2.5V Regulator Loop Stability. 2’b11
00: I=60μA.
01: I=90μA.
10: I=120μA.
11: I=150μA.
3:2 RW bg_sel Adjust Bandgap Voltage. 2’b00
00: 1.236V.
01: 1.253V.
10: 1.270V.
11: 1.287V.
1 RW pd_18 Power Down 1.8V Regulator (active HIGH). 1’b0
0 RW pd_25 Power Down 2.5V Regulator (active HIGH). 1’b0

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Data Sheet
0x1C – Pad Drive Strength Control Register
3 RW P1_Low_Speed MAC Port 1 I/O Pad Drive Strength Select. 1’b0
0: Gigabit mode.
1: 10/100 mode.
2 RW P0_Low_Speed MAC Port 0 I/O Pad Drive Strength Select. 1’b0
0: Giga mode.
1: 10/100 mode.
1:0 RW PCI_Drive_Sel PCI I/O Pad Drive Strength Select 2’b01
00: PCMCIA/CARDBUS mode.
01: PCI mode
1x: Reserved
0x20, 0x24 – Reserved
3.3.7 High-speed UART Control
0x00 – Receive Buffer Register/ Transmitter Holding Register/ Baud-Rate Divisor Latch
DLAB = 0 for read (RBR)
7:0 RO RBR Receive Data Port. 8’b0
DLAB = 0 for write (THR)
7:0 WO THR Transmit Data Port 8’b0
DLAB = 1 (DLL)
7:0 RW DLL Baud Rate Divisor Latch Least Significant Byte. 8’h01
The Divisor Latch is a 16-bit register, whose most
significant byte is hold in the following DLM, and its
least significant byte is hold in DLL. The Baud Rate can
be controlled by DLL, and DLM with the clock
generated from Pre-scaler. Division factor from 1 to
65535 can be programmed. When {DLM, DLL} = 0,
UART Baud Rate = 0.
0x04 –Interrupt Enable Register / Baud-Rate Divisor Latch

DLAB = 0 (IER)
3 RW UART Status This bit enables the UART Status Interrupt when set to 1’b0
logic 1
2 RW Receiver Line Status This bit enables the Receiver Line Status Interrupt when 1’b0

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set to logic 1
1 RW THR Empty This bit enables the Transmitter Holding Register Empty 1’b0
Interrupt when set to logic 1
0 RW Receiver Data Available This bit enables the Received Data Available Interrupt 1’b0
(and character reception timeout interrupts in the FIFO
mode) when set to logic 1
DLAB = 1 (DLM)
7:0 RW DLM Baud Rate Divisor Latch Most Significant Byte 8’h00
0x08 –Interrupt Identification Register / Pre-scalar Register

DLAB = 0 for read (IIR)
7:6 RO FIFO Mode Enable These two bits are set when FCR[0] is set as 1. 2’b00
5 RO Reserved 1’b0
4 RO Tx FIFO full This bit is set as 1 when Tx FIFO is full. 1’b0
3:0 RO Interrupt Identification These bits identify the highest priority interrupt that is 4’b0001
Code pending. Please view the following Table 3-3 for detail.
DLAB = 0 for write (FCR)
31:8 WO Reserved. 24’b0
7:6 WO RXFIFO_TRGL Use to set the trigger level for the Rx FIFO interrupt. 2’b00
00: 1 character
01: 4 characters
10: 8 characters
11: 14 characters
5:3 WO Reserved 3’b0
2 WO Tx FIFO Reset Set this bit to logic 1 clears all bytes in the Tx FIFO and 1’b0
resets its counter logic to 0. The shift register is not
cleared, so any reception active will continue.
The bit will automatically return to zero.
1 WO Rx FIFO Reset Set this bit to logic 1 clears all bytes in the Rx FIFO and 1’b0
resets its counter logic to 0. The shift register is not
cleared, so any reception active will continue.
The bit will automatically return to zero.
0 WO FIFO Enable Set this bit to logic 1 enables both the transmitter and 1’b0
receiver FIFO. Changing this bit automatically resets
both FIFO.
DLAB = 1 (PSR)
1:0 RW PSR Set Pre-scalar Value of UART Baud Rate Generator. 2’b00
The Pre-scalar will generate clock for Baud Rate Divisor
with 48MHz input clock source:
00: Disable clock.

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Data Sheet
01: 24MHz (Divided by 2).
10: 14.769231MHz (Divided by 3.25).
10: 14.769231MHz (Divided by 3.25).
0x0C –Line Control Register (LCR)

7 RW DLAB Divisor Latch Access Bit (DLAB). 1’b0
This bit must be set in order to access the DLL, DLM
and PSR registers which program the division constants
for the baud rate divider and the pre-scalar.
6 RW Set Break Break Control 1’b0
This bit causes a break condition to be transmitted to the
receiving UART.
When it is set to HIGH, the serial output (UR_TXD) is
forced to the Spacing (logic 0) state.
When it is set to LOW, the break is disabled.
The Break Control bit acts only on UR_TXD and has no
effect on the transmitter logic, so if several characters are
stored in the transmitter’s FIFO, they will be removed
from this FIFO and passed sequentially to the
Transmitter Shift Register, which serializes them. This
can be useful to establish the break time making use of
the THR Empty and Transmitter Empty flags of the LSR.
5 RW Stick Parity Enable of Stick Parity 1’b0
When bits 3, 4 and 5 are logic 1, the Parity bit is
transmitted and checked as logic 0.
If bits 3 and 5 are HIGH and bit 4 is LOW, then the
Parity bit is transmitted and checked as logic 1.
If bit 5 is LOW, Stick Parity is disabled.
4 RW Even Parity Even Parity Select. 1’b0
When bit 3 is HIGH and bit 4 is LOW, an odd number of
logic 1’s is transmitted or checked in the data word bits
and Parity bit.
3 RW Parity Enable Parity Enable. 1’b0
When this bit is HIGH, a Parity bit is generated
(transmit data) or checked (receive data) between the
last data word bit and Stop bit of the serial data. When
bit 3 is HIGH and bit 4 is LOW, an even number of logic
1s is transmitted or checked.
2 RW Stop Bits Select Number of Stop Bits 1’b0
This bit selects the number of stop bits to be transmitted.
If cleared, only one stop bit will be transmitted.
If set, two stop bits (1.5 with 5-bit data) will be
transmitted before the start bit of the next character. The
receiver always checks only one stop bit.
1 RW WL1 This bit along with WL0 defines the word length of the 1’b0

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data being transmitted and received.
0 RW WL0 This bit along with WL1 defines the word length of the 1’b0
data being transmitted and received.
Word Length and Stop Bits Setting Table

LCR code Character
Number of
Bit 2 Bit 1 Bit 0 Length
Stop bits
Stop bits WL1 WL0 (bits)
0 0 5
0 1 6
0 1
1 0 7
1 1 8
0 0 5 1.5
0 1 6
1
1 0 7 2
1 1 8
0x10 –UART Control Register (UCR)

5 RW DMA Mode In the FIFO mode (FCR[0] = 1), and this bit is set, DMA 1’b0
mode is enabled.
4 RW Loop Loop-back Mode. 1’b0
This is the loop back mode control bit. Loop back mode
is intended for the UART communication testing.
1 RW RTS Request To Send. 1’b0
This bit controls the “request to send” active low output
(UR_RTS).
0x14 –UART Line Status /Test Control Register

For Read (LSR)
7 RO FIFO Data Error FIFO Data Error Flag. 1’b0
If the FIFO is disabled (16450 mode), this bit is always
zero.
If the FIFO is active, this bit will be set as soon as any
data character in the receiver’s FIFO has parity or
framing error or the break indication active.
Note that this bit is cleared when the CPU reads the LSR
and the rest of the data in the receiver’s FIFO do not
have any of these three associated flags on.
6 RO Transmitter Empty Transmitter Empty Flag. 1’b0

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It is “1” when both the THR (or Tx FIFO) and the TSR
(Transmitter Shift Register) are empty. Reading this bit
as “1” means that no transmission is currently taking
place in the UR_TXD output pin, the transmission line is
idle.
Note that as soon as new data is written in the THR, this
bit will be cleared.
5 RO THR Empty THR Empty Flag. 1’b0
It indicates that the UART is ready to accept a new
character for transmission. In addition, this bit causes
the UART to issue an interrupt to the CPU when the
Transmit Holding Register Empty Interrupt enable bit
(IER[1]) is set high.
In non-FIFO mode, this bit is set whenever the 1-byte
THR is empty. If the THR holds data to be transmitted,
this bit is immediately set when this data is passed to
the TSR.
In FIFO mode, this bit is set when the transmitter’s FIFO
is completely empty, being 0 if there is at least one byte
in the FIFO waiting to be passed to the TSR for
transmission.
4 RO Break Interrupt It is set to “1” if the receiver’s line input UR_RXD was 1’b0
held at zero for a complete character time. It is to say the
positions corresponding to the start bit, the data, the
parity bit (if any) and the (first) stop bit were all
detected as zeroes. Note that a FramingError flag always
accompanies this flag. This bit is queued in the
receiver’s FIFO in the same way as the Parity Error bit.
When break occurs, only one zero character is loaded
into the FIFO. The next character transfer is enabled
after UR_RXD goes to the marking state and receives the
next valid start bit.
Note that this bit is cleared as soon as the LSR is read.
3 RO Framing Error Frame Error Flag. 1’b0
It indicates that the received character did not have a
valid stop bit (i.e., a 0 was detected in the (first) stop bit
position instead of a 1). This bit is queued in the
receiver’s FIFO in the same way as the Parity Error bit.
When a frame error is detected, the receiver tries to
resynchronize: if the next sample is again a zero it will
be taken as the beginning of a possible new start bit.
2 RO Parity Error Parity Error Flag. 1’b0
When it is set, it indicates that the parity of the received
characters wrong according to the current setting in
LCR. This bit is queued in the receiver’s FIFO, so it is
associated to the particular character that had the error.

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Therefore, LSR must be read before RBR: each time a
character is read from RBR, the next character passes to
the top of the FIFO and LSR is loaded with the queued
error flags corresponding to this top-of-the-FIFO
character.
1 RO Overrun Error Overrun Error Flag. 1’b0
When it is set, a character has been completely
assembled in the Receiver Shift Register without having
free space to put it in the receiver’s FIFO or holding
register. When an overrun condition appears, the result
is different depending on whether the 16-byte FIFO is
active or not: If the FIFO is not active, so that only a
1-character Receiver Holing Register is available, the
unread data in this RBR will not be overwritten with the
new character just received.
If the FIFO is active, the character just received in the
Receiver Shift Register will be overwritten, but the data
already present in the FIFO is not changed. The Overrun
Error flag is set as soon as the overrun condition
appears. It is not queued in the FIFO if this is active.
0 RO Data Ready Data Ready Flag. 1’b0
It is set if one or more characters have been received and
are waiting in the receiver’s FIFO for the user to read
them. It is cleared to logic 0 by reading all of the data in
the Receiver Buffer Register or the FIFO.
For Write: Reserved
0x18 –UART Status Register (USR)

4 RO CTS Clear To Send (CTS) is the complement of the UR_CTS 1’b0
input.
0 RO Delta CTS If set, it means that the UR_CTS input has changed since 1’b0
the last time the microprocessor read this register.
0x1C –Scratch Pad Register (SPR)

7:0 RW User Data This 8-bit read/write register has no effect on the 8’h00
operation of the Serial Port. It is intended as a
scratchpad register to be used by the programmer to
hold data temporarily.

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Data Sheet
Table 3-4. UART Interrupt Identification
Interrupt Identification
Interrupt Set and Reset Functions
Code
Bits3 Bits2 Bits1 Bits0 Priority Level Interrupt Interrupt Source Description Interrupt Reset Method
Type
0 0 0 1 ---- None There is no interrupt pending. None
0 1 1 0 Highest Receiver Line There is an overrun error, parity error, framing error Read the Line Status
Status or break interrupt indication corresponding to the Register (LSR)
received data on top of the receive FIFO. Note that
the FIFO error flag in LSR does not influence this
interrupt, which is related only to the data on top of
the Rx FIFO. This is directly related to the presence
of a 1 in any of the LSR bits 1 to 4.
0 1 0 0 Second Received Data In non-FIFO mode, there is received data available Read the Receiver Buffer
Ready in the RHR register. In FIFO mode, the number of Register (RBR)
characters in the receive FIFO is equal to or greater
than the trigger level programmed in FCR. The
interrupt signal will stay active while the number of
words in the FIFO stays higher than that value and
will be cleared when the microprocessor reads the
necessary words to make the number of words in
the FIFO less than the trigger level. Note that this is
not directly related to LSR bit 0, which always
indicates that there is at least one word ready.
1 1 0 0 Second Character There is at least one character in the receive FIFO Read the Receiver Buffer
Reception and during a time corresponding to four characters Register (RBR)
Timeout at the selected baud rate, no new character has
been received. A FIFO timeout interrupt will occur, if
the following conditions exist:
1. At least one character is in the FIFO.
2. The most recent serial character received were
longer than 4 continuous character times ago (if 2
stop bits are programmed, the second one is
included in this time delay).
0 0 1 0 Third Transmitter In non-FIFO mode, the 1-byte THR is empty. In FIFO Write the Transmitter
Holding mode, the complete 16-byte transmit FIFO is empty, Holding Register (THR).
Register so 1 to 16 characters can be written to THR. That is Alternatively, reading the
Empty to say, THR Empty bit in LSR is one. Interrupt Identification
Register (IIR) will also clear
the interrupt if this is the
interrupt type being currently
indicated (this will not clear
the flag in the LSR).
0 0 0 0 Fourth Modem Status A change has been detected in the Clear To Send Read the Modem Status
(CTS), Data Set Ready (DSR) or Carrier Detect (CD) Register (MSR)
input lines or a trailing edge in the Ring Indicator (RI)
input line. That is to say, at least one of MSR bits 0
to 3 is one.
3.3.8 Timer
0x00 – Timer1 Counter Register

31:0 RW Tm1Counter Timer1 Counter. 32’b0
If the timer is disabled, Tm1Counter will hold current
value. And if the counter up/down counts to 0, an
overflow event occurs.

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0x04 –Timer 1 Auto Reload Value Register

31:0 RW Tm1Load Timer1 Auto Reload Value. 32’b0
If Timer1 overflow occurs, the value of Tm1Load is
loaded into Tm1Counter.
0x08 –Timer1 Match Value 1 Register

31:0 RW Tm1Match1 Timer1 Match Value1. 32’b0
When Tm1Counter’s value is equal to Tm1Match1 and
Timer1 is enabled, the Tm1Match1 interrupt is asserted.
0x0C –Timer1 Match Value 2 Register

0x10 – Timer2 Counter Register

31:0 RW Tm2Counter Timer2 Counter. 32’b0
If the timer is disabled, Tm2Counter will hold current
value. And if the counter up/down counts to 0, an
overflow event occurs.
0x14 –Timer 2 Auto Reload Value Register

31:0 RW Tm2Load Timer2 Auto Reload Value. 32’b0
If Timer2 overflow occurs, the value of Tm2Load is
loaded into Tm2Counter.
0x18 –Timer2 Match Value 1 Register

0x1C –Timer2 Match Value 2 Register

0x30 –Timer 1 and 2 Control Register


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10 RW TmCR[10] Timer2 Up/Down Counter Control. 1’b0
0: Up.
1: Down.
9 RW TmCR[9] Timer1 Up/Down Counter Control. 1’b0
0: Up.
1: Down.
5 RW Tm2OFEnable Timer2 Overflow Interrupt Enable. 1’b0
0: Disable.
1: Enable.
4 RW Tm2Clock Timer2 Clock Source Select. 1’b0
0: PCLK.
1: 1KHz Clock
3 RW Tm2Enable Timer2 Enable. 1’b0
0: Disable.
1: Enable.
2 RW Tm1OFEnable Timer1 Overflow Interrupt Enable. 1’b0
0: Disable.
1: Enable.
1 RW Tm1Clock Timer1 Clock Source Select. 1’b0
0: PCLK.
1: 1KHz Clock
0 RW Tm1Enable Timer1 Enable. 1’b0
0: Disable.
1: Enable.
0x34 –Interrupt Status Register

5 RW Tm2overflow Timer2 Overflow Interrupt. 1’b0
4 RW Tm2Match2 Timer2 Match Value2 Interrupt. 1’b0
3 RW Tm2Match1 Timer2 Match Value1 Interrupt 1’b0
2 RW Tm1overflow Timer1 Overflow Interrupt 1’b0
0x38 –Interrupt Mask Register

5 RW Tm2overflow mask Timer2 Overflow Interrupt Mask. 1’b0
0: non-mask
1: mask
4 RW Tm2Match2 mask Timer2 Match Value2 Interrupt Mask. 1’b0
0: non-mask
1: mask

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0: non-mask
1: mask
2 RW Tm1overflow mask Timer1 Overflow Interrupt Mask. 1’b0
0: non-mask.
1: mask.
0: non-mask
1: mask
0: non-mask
1: mask
3.3.9 Watch Dog Timer
0x00 –Watch Dog Timer Counter Register

31:0 RO WdCounter Watch Dog Timer Counter Register. 32’h03EF_1480
WdCounter is a down counter and contains the
counter’s current value.
0x04–Watch Dog Timer Counter Auto-reload Register

31:0 RW WdLoad Watch Dog Timer Counter Auto Reload Register. 32’h03EF_1480
When reset or restart, the value of WdLoad will be
loaded into WdCounter.
0x08 –Watch Dog Timer Counter Restart Register

15:0 WO WdRestart Watch Dog Timer Counter Restart Register. 16’b0
Writing 0x5AB9 to this register, Watch Dog Timer will
automatically reload WdLoad to WDcounter and restart
to counting.
0x0C –Watch Dog Timer Control Register

4 RW WdClock Watch Dog Timer Clock Source Select. 1’b0
0: PCLK
1: 10Hz Clock
2 RW WdIntr Watch Dog Timer System Interrupt Enable. 1’b0
0: Disable
1: Enable
1 RW WdRst Watch Dog Timer System Reset Enable. 1’b0
0: Disable.

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1: Enable.
0 RW WdEnable Watch Dog Timer Enable. 1’b0
0: Disable.
1: Enable.
0x10 –Watch Dog Timer Status Register

0 RO WdStatus Watch Dog Timer Status. 1’b0
This bit is set when the counter reaches zero.
0: Does not reach zero.
1: Watch Dog reaches zero.
0x14 –Watch Dog Timer Clear Register

0 WO WdClear Watch Dog Timer Clear. 1’b0
Writing HIGH to this register will clear WdStatus.
0x18 –Watch Dog Timer Interrupt Length Register

7:0 RW WdIntrlen Watch Dog Timer Interrupt Length. 8’hFF
This register controls the length of reset and
interrupt.
3.3.10 Real Time Clock
0x00 –RTC Second Register

5:0 RO RtcSecond RTC Second Counter Register. 6’b0
Its range is 0~59.
0x04 –RTC Minute Register

5:0 RO RtcMinute RTC Minute Counter Register. 6’b0
Its range is 0~59.
0x08 –RTC Hour Register

4:0 RO RtcHour RTC Hour Counter Register. 5’h00
Its range is 0~23.
0x0C –RTC Day Register

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Data Sheet
15:0 RO RtcDays RTC Day Counter Register. 16’b0
0x10 –RTC Second Alarm Register

5:0 RW AlarmSecond RTC Second Alarm Register. 6’h3F
For example, if user want to set alarm at 12:10:10, the
AlarmSecond needs to be set 0xA.
0x14 –RTC Minute Alarm Register

5:0 RW AlarmMinute RTC Minute Alarm Register. 6’h3F
AlarmMinute needs to be set 0xA.
0x18 –RTC Hour Alarm Register

4:0 RW AlarmHour RTC Hour Alarm Register. 5’h1F
AlarmHour needs to be set 0xC.
0x1C –RTC Record Register

31:0 RW RtcRecord RTC Record Register. 32’b0
It is used to adjust the difference of current time and
RTC counter time. The following expression can
determine the value of RtcRecord.
RtcDays*86400 + RtcHour*3600 + RtcMinute*60 +
RtcSecond + RtcRecord = seconds of (Current time – Base
time)
“Base time” is defined by programmer. For example, it can be
defined at 2000/01/01/00:00:00. And “Current time” is input
by user when system initialization.
0x20 –RTC control Register

5 RW RTC match alarm RTC Match Alarm Interrupt Enable. 1’b0
interrupt When enabled, the RTC rtc_alarm interrupt occurrs
every match alarm.
0: Disable.
1: Enable.
4 RW RTC interrupt every day RTC Auto Alarm Every Day Enable. 1’b0

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When enabled, the RTC rtc_day interrupt
occurrsevery day
0: Disable.
1: Enable.
3 RW RTC interrupt every RTC Auto Alarm Every Hour Enable. 1’b0
hour When enabled, the RTC rtc_hour interrupt occurrs
every hour
0: Disable.
1: Enable.
2 RW RTC interrupt every RTC Auto Alarm Every Minute Enable. 1’b0
minute When enabled, the RTC rtc_min interrupt occurrs
every minute
0: Disable.
1: Enable.
1 RW RTC interrupt every RTC Auto Alarm Every Second Enable. 1’b0
second When enabled, the RTC rtc_sec interrupt occurrs
every second.
0: Disable.
1: Enable.
0 RW RTC enable RTC Interrupt Enable. 1’b0
0: Disable.
1: Enable.

4 RW Rtc_alarm Indicate the rtc_alarm interrupt occurs 1’b0
3 RW Rtc_day Indicate the rtc_day interrupt occurs 1’b0
2 RW Rtc_hour Indicate the rtc_hour interrupt occurs 1’b0
1 RW Rtc_min Indicate the rtc_min interrupt occurs 1’b0
0 RW Rtc_sec Indicate the rtc_sec interrupt occurs 1’b0
3.3.11 GPIO
0x00 –GPIO Data Output Register

20:0 RW GpioDataOut GPIO Data Output Register. 21’b0
It is Double Word operation logic as usual, comparing to
the following GPIO Data Bit Set Register and GPIO
Data Bit Clear Register. Writing to the register will
affect every register bits.
0x04 –GPIO Data Input Register

20:0 R GpioDataIn GPIO Data Input Register. 21’b0

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0x08 –GPIO Direction Register
20:0 RW PinDir GPIO Direction Register. 21’b0
0: Pin input.
1: Pin output.
0x0C –Reserved
0x10 –GPIO Data Bit Set Register

20:0 W GpioDataSet GPIO Data Bit Set Register. 21’b0
It is bit operation logic. When write to this register and if
some bits of GpioDataSet are 1, the corresponding bits
in GpioDataOut register will be set to 1, and the others
will not be changed.
0x14 –GPIO Data Bit Clear Register

20:0 W GpioDataClear GPIO Data Bit Clear Register. 21’b0
It is bit operation logic. When write to this register and if
some bits of GpioDataClear are 1, the corresponding bits
in GpioDataOut register will be cleard, and the others
will not be changed.
0x18, 0x1C Reserved
0x20 –GPIO Interrupt Enable Register

20:0 RW IntrEnable GPIO Interrupt Enable Register. 21’b0
0: Pin interrupt is disabled
1: Pin interrupt is enabled
0x24 –GPIO Interrupt Raw Status Register

20:0 R IntrRawState GPIO Interrupt Raw Status Register. 21’b0
0: Interrupt is not detected.
1: Interrupt is detected.
0x28 –GPIO Interrupt Masked Status Register

20:0 R IntrMaskedState GPIO Interrupt Masked Status Register. 21’b0
0: Interrupt is not detected or masked.
1: Interrupt is detected and not masked.
0x2C –GPIO Interrupt Mask Register

20:0 RW IntrMask GPIO Interrupt Mask Register. 21’b0

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Data Sheet
0: Mask is disabled.
1: Mask is enabled.
0x30 –GPIO Interrupt Clear Register

20:0 WO IntrClear GPIO Interrupt Clear. 21’b0
Write 0: No effect
Write 1: Clear interrupt
0x34 –GPIO Interrupt Trigger Method Register

20:0 RW IntrTrigger GPIO Interrupt Trigger Method Register. 21’b0
0: Edge trigger.
1: Level trigger.
0x38 –GPIO Interrupt Trigger by Both Edges Register

20:0 RW IntrBoth GPIO Interrupt Edge Trigger by Both. 21’b0
0: Single edge.
1: Both edges.
0x3C –GPIO Interrupt Trigger by Rising-/Falling-Edge or High/Low level Register

20:0 RW IntrRiseNeg GPIO Interrupt Triggered by Rising or Failing Edge. 21’b0
0: Rising-edge.
1: Falling-edge.
GPIO Interrupt Triggered by High or Low Level.
0: High-level.
1: Low-level.
0x40 –GPIO Bounce Enable Register

20:0 RW BounceEnable GPIO Pre-scale Clock Enable. 21’b0
When enable, the interrupt pin is sampled by extended
clock of PCLK, instead of PCLK..
0: Disable.
1: Enable.
0x44 –GPIO Bounce clock pre-scale Register

31:24 RO Reserved 8’h00
23:0 RW BouncePreScale GPIO Pre-scale. 24’h0007D0
It is used to adjust interrupt sampling clock period as
the following expression:
Extended Clock Frequency = PCLK/( BouncePreScale+1)
The allowed range is 0x0001 ~ 0xFFFF.

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3.3.12 Interrupt Controller
0x00 – Interrupt Source Register

31:0 RO Irqsrcreg Interrupt Bit Definition. 32’b0
Bit[0]: Timer#1
Bit[1]: Timer#2
Bit[2]: Clock and Power Management
Bit[3]: Watch Dog Timer
Bit[4]: GPIO
Bit[5]: PCI External Interrupt 0
Bit[8]: AHB-to-PCI Bridge Status
Bit[9]: Reserved
Bit[10]: UART
Bit[11]: Generic DMA Terminal Counter
Bit[12]: Generic DMA Error
Bit[13]: PCMCIA
Bit[14]: RTC
Bit[15]: External Interrupt
Bit[16]: Reserved
Bit[17]: Reserved
Bit[18]: Switch Controller
Bit[19]: Switch DMA TSTC (To-Switch-Tx-Complete)
Bit[20]: Switch DMA FSRC (Fm-Switch-Rx-Complete)
Bit[21]: Switch DMA TSQE(To-Switch-Queue-Empty)
Bit[22]: Switch DMA FSQE (Fm-Switch-Queue-Empty)
Bit[23]: USB 1.1 host controller
Bit[24]: USB 2.0 host controller
Bit[25:31]: Reserved
Interrupt Inputs.
0: Interrupt is non-active.
1: Interrupt is active.
0x04 – Interrupt Mask Register

31:0 RW irqmaskreg Interrupt MASK Register. 0xFFFF-FFFF
1: Mask the corresponding bit interrupt source.
0: UnMask the corresponding bit interrupt source.
0x08 – Interrupt Clear Register

31:0 WO Irqclear Clear Interrupt. 32’b0
Write 0: no action
Write 1: clear relative interrupt source status
This clear bit will only take action on edge triggered

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interrupt sources and will reset to 0 automatically after
clearing the interrupt status.
0xC – Interrupt Trigger Mode Register

31:0 RW irqtrigmode Interrupt Trigger Mode 32’b0
0: Level-trigger
1: Edge-trigger
0x10 – Interrupt Trigger Level Register

31:0 RW irqtriglevel Interrupt Trigger Level 32’b0
0: High level trigger or rising edge trigger
1: Low level trigger or falling edge trigger

31:0 RO irqstatus Interrupt Status After Mask. 32’b0
0: No interrupt
1: Interrupt active
0x18 – FIQ mode select Register

31:0 RW FiqSelReg FIQ Mode Select 32’b0
0: Set to IRQ interrupt.
1: Set to FIQ interrupt.
3.3.13 PCMCIA Host Controller
0x00 - Interface Status Register

31:7 Reserved.
6 RO INPACK_n This bit indicates the value of the INPACK_n pin of I/O
and Memory Card.
5 RO RDY/IREQ_n This bit indicates the value of the READY pin of
Memory Only Card or the IREQ_n pin of I/O and
Memory Card.
0x04 - Card Status Change Register

31:8 Reserved Reserved 24’b0
7 RW SoftCardDetect_Change Software Card Detect Change 1’b0
0: A transition on the SoftCardDetect bit of the
following Card Detect and Global Control Register has
not occurred since it is last read or last
“write-1-clear”.

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1: A transition on the SoftCardDetect bit has occurred.
6 Reserved 1’b0
5 RW IREQ_n_Change IREQ_n Change 1’b0
0: A transition on the IREQ_n pin has not occurred
since it is last read or last “write-1-clear”.
1: A transition on the IREQ_n pin has occurred.
3 RW INPACK_n_Change Input Port Acknowledge Change. 1’b0
0: A transition on the INPACK_n pin has not
occurred since it is last read or last “write-1-clear”.
1: A transition on the INPACK_n pin has occurred.
0x08 - Reserved
0x0C - Card Detect and Global Control Register

5 RW RESET Setting this bit to 1 activates the RESET signal to the 1’b0
PCMCIA card. The RESET signal is active until this bit is
set to 0
4 RW SoftCardDetect Software Card Detect Interrupt. 1’b0
If the CardDetectEn bit of the Interrupt Configuration
Register is set to 1, then change this bit from 0 to 1 will
cause a software card detect change interrupt.
2 RW IOIS16 I/O Card Data Bus Width is 16. 1’b0
0: I/O Card Data Bus Width = 8
1: I/O Card Data Bus Width = 16
1 RW InterrupClearMode Interrupt Clear Mode. 1’b0
0: The interrupt status bits of the Card Status
Change Register are read cleared
1: Each of the interrupt status bits of the Card
Status Change Register is write-1-cleared.
0x10 - Interrupt Configuration Register

6 RW CardDetectEn Card Detect Enable. 1’b0
0: Masked.
1: Enabled.
5-4 RW IREQ_n_En IREQ_n Enable. 2’b0
00: IREQ_n interrupt is masked
01: An interrupt is issued when Level 0 is detected at
IREQ_n pin.
10: An interrupt is issued when a falling-edge from

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IREQ_n pin is detected.
11: An interrupt is issued when a rising-edge from
IREQ_n pin is detected.
3 RW INPACK_n_En Input Port Acknowledge Change Enable. 1’b0
0: Masked.
1: Enabled.
0x14 - Memory Access Timing Control Register 0

7:0 RW tAP0 Assert Duration Cycle Time of POE_n/ PWE_n 8’h00
The reference clock is AHB bus clock. And this value
should be larger than zero.
0x18 - Memory Access Timing Control Register 1

7:4 RW tAS0 Access Setup Cycle Time of POE_n/PWE_n 4’h0
The reference clock is AHB bus clock.
3:0 RW tAH0 Access Hold Cycle Time of POE_n/PWE_n 4’h0
0x1C - IO Access Timing Control Register 0

7:0 RW tAP1 Assert Duration Cycle Time of IORD_n/ IOWR_n 8’h00
The reference clock is AHB bus clock. And this value
should be larger than zero.
0x20 - IO Access Timing Control Register 1

7:4 RW tAS1 Access Setup Cycle Time of IORD_n/IOWR_n 4’h0
3:0 RW tAH1 Access Hold Cycle Time of IORD_n/IOWR_n 4’h0
3.3.14 PCI Bridge Configuration Data Register
0xA000_0000 - CONFIG_DATA
31:0 RW CONFIG_DATA PCI configuration data access window.
3.3.15 PCI Bridge Configuration Address Register

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0xA400_0000 - CONFIG_ADDR
31 RW Enable Configuration Access Enable 1’b0
0: disable
1: enable
23:16 RW Bus number PCI Bus Number 8’b0
It is used to select 1 of 256 buses in a system. If the Bus
Number is zero, Type 0 configuration translation is
used. If the Bus Number is non-zero, Type 1
configuration translation is used.
15:11 RW Device number PCI Device Number 5’b0
It is used to select 1 of 21 PCI devices on a given bus.
Device 0’s IDSEL is connected to AD[11], and Device 1’s
IDSEL is connected to AD[12], and so on.
10:8 RW Function number Function Number 3’b0
It is used to select 1 of 8 possible functions on a
multifunction device.
7:2 RW Register number Register Number 6’b0
It is used to select a 32-bit data in the Configuration
Space of the intended target.
3.3.16 USB1.1 Configuration Registers
0x04-05-- Command Register

Bits Type Description Default
15:3 RW Reserved.
13’b0
These bits are always 0.
2 RW Master Enable. 1’b0
If set to 1, Host Controller(HC) is enabled to run master cycles. (Recom. to 1’b1)
1 RW Operation Register Access Enable. 1’b0
If set to 1, USB1.1 Operation Registers can be accessed. (Recom. to 1’b1)
0x44--Operational Mode Enable Register (Default: 0x22h)

7 RW Reserved. 1’b0
6 RW BuferUnderOrphan. 1’b0
The buffer point will reset while data under-run occurs. (Recom. to 1’b1)
5 RW NoResp3HS. (LOW Active)
1’b1
When clear, the Error interrupt is reported after three consecutive USB bus
(Recom. to 1’b0)
transfer error.

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4 RW HcControl bit 9 and bit10 Function Enable.
When this bit is set, the function of RemoteWakeupConnected and
1’b0
RemoteWakeupEnable in OHCI will be enabled.
Otherwise, these two bits are always cleared.
3 RW Reserved. 1’b0
2 RW BUFUNDEREOF.
1’b0
Setting this bit will stop the Data Buffer Module function until next access.
1 RW S3_WAKEUP.
HC will accept wait-state write command after leaving suspend mode if 1’b1
there are no device attached.
0 RW Data Buffer Region16.
When set, the size of the region for the data buffer is 16 bytes. 1’b0
Otherwise, the size is 32 bytes.
0x45, 0x46, 0x48, 0x49-- Reserved
3.3.17 USB1.1 Operation Register
3.3.17.1 Control and Status Partition
0x00-- HcRevision Register

31:9 Reserved
8 RO Legacy.
This read-only field is 1 to indicate that the legacy support registers are 1’b1
present in this HC.
7:0 RO Revision.
This read-only field contains the BCD representation of the version of the
HCI specification that is implemented by this HC. For example, a value of 8’h10
11h corresponds to version 1.1. All of the HC implementations that are
compliant with current OpenHCI 1.0 specification will have a value of 10h.
0x04-- HcControl Register

10 RO RemoteWakeupEnable.
This bit is used by HCD to enable or disable the remote wakeup feature
upon the detection of upstream resume signaling. When this bit is set and
1’b0
the Resume Detected bit in HC Interrupt Status is set, a remote wakeup is
signaled to the host system. Setting this bit has no impact on the
generation of hardware interrupt.

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9 RO Remote Wakeup Connected.
This bit indicates whether HC supports remote wakeup signaling or not. If
remote wakeup is supported and used by the system, it is the responsibility 1’b0
of system firmware to set this bit during POST. HC clears the bit upon a
hardware reset but does not alter it upon software reset.
8 RW Interrupt Routing.
This bit determines the routing of interrupts generated by events registered
in HC Interrupt Status. If clear, all interrupts are routed to the normal host
bus interrupt mechanism. If set, interrupts are routed to the System 1’b0
Management Interrupt. HCD clears this bit upon hardware reset, but it
does not alter this bit upon a software reset. HCD uses this bit as a tag to
indicate the ownership of HC.
7:6 RW HostControllerFunctionalState for USB.
00b: UsbReset.
01b: UsbResume.
10b: UsbOperational.
11b: UsbSuspend.
A transition to UsbOperational from another state causes SOF generation
to begin 1 ms later. HCD may determine whether HC has begun sending 2’b0
SOFs by reading the StartofFrame field of HcInterruptStatus.
This field may be changed by HC only in the UsbSuspend state. HC may
move from the UsbSuspend state to the UsbResume state after detecting the
resume signal from a downstream port.
HC enters UsbSuspend after a software reset, whereas it enters UsbReset
after a hardware reset. The latter also resets the Root Hub and asserts
subsequent reset signal to downstream ports.
5 RW BulkListEnable.
This bit is set to enable the processing of the Bulk list in the next Frame. If
cleared by HCD, processing of the Bulk list does not occur after the next
SOF. HC checks this bit whenever it determines to process the list. 1’b0
When disabled, HCD may modify the list. If HcBulkCurrentED is pointing
to a ED to be removed, HCD must advance the pointer by updating
HcBulkCurrentED before re-enabling the processing of the list.
4 RW ControlListEnable.
This bit is set to enable the processing of the Control list in the next Frame. If
cleared by HCD, the processing of the Control list does not occur after the
next SOF. HC must check this bit whenever it determines to process the 1’b0
list. When disabled, HCD may modify the list. If HcControlCurrentED
is pointing to a ED to be removed, HCD must advance the pointer by
updating HcControlCurrentED before re-enabling the processing of the list.
3 RW IsochronousEnable.
This bit is used by HCD to enable/disable the processing of isochronous 1’b0
EDs. While processing the periodic list in a Frame, HC checks the status of

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this bit when it finds an Isochronous ED (F=1). If set (enabled), HC
continues processing the EDs. If cleared (disabled), HC halts processing of
the periodic list (which now contains only isochronous EDs) and begins
processing the Bulk/Control lists. Setting this bit is guaranteed to take
effect in the next Frame (not the current Frame).
2 RW PeriodicListEnable.
This bit is set to enable the processing of the periodic list in the next Frame.
1’b0
If cleared by HCD, the processing of the periodic list does not occur after the
next SOF. HC must check this bit before it starts processing the list.
1:0 RW ControlBulkServiceRatio.
This specifies the service ratio between Control and Bulk EDs. Before
processing any of the non-periodic lists, HC must compare the ratio
specified with its internal count on how many non-empty Control EDs have
been processed, in determining whether to continue serving another Control
ED or switching to Bulk EDs. The internal count will be retained when
crossing the frame boundary. In case of reset, HCD is responsible for
2’b0
restoring this value.
CBSR No. of Control EDs Over Bulk EDs Served
0 1:1
1 2:1
2 3:1
3 4:1
0x08--HcCommandStatus Register
31:18 Reserved
14’b0
17:16 RO SchedulingOverrunCount.
These bits are incremented on each scheduling overrun error. It is
initialized to 00b and wraps around at 11b. This will be incremented when a
scheduling overrun is detected even if Scheduling Overrun in Hc Interrupt 2’b0
Status has already been set. This is used by HCD to monitor any persistent
scheduling problems.
15:4 Reserved
3 RW OwnershipChangeRequest.
This bit is set by an OS HCD to request a change of control of the HC.
When set HC will set the Ownership Change field in HcInterrupt Status. 1’b0
After the changeover, this bit is cleared and remains so until the next request
from OS HCD.
2 RW BulkListFilled.
This bit is used to indicate whether there are any TDs on the Bulk list. It is
set by HCD whenever it adds a TD to an ED in the Bulk list. 1’b0
When HC begins to process the head of the Bulk list, it checks BF. As long

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as BulkListFilled is 0, HC will not start processing the Bulk list. If
BulkListFilled is 1, HC will start processing the Bulk list and will set BF to 0.
If HC finds a TD on the list, then HC will set BulkListFilled to 1 causing the
Bulk list processing to continue. If no TD is found on the Bulk list, and if
HCD does not set BulkListFilled, then BulkListFilled will still be 0 when HC
completes processing the Bulk list and Bulk list processing will stop.
1 RW ControlListFilled.
This bit is used to indicate whether there are any TDs on the Control list. It
is set by HCD whenever it adds a TD to an ED in the Control list.
When HC begins to process the head of the Control list, it checks CLF. As
long as ControlListFilled is 0, HC will not start processing the Control list.
If CF is 1, HC will start processing the Control list and will set 1’b0
ControlListFilled to 0. If HC finds a TD on the list, then HC will set
ControlListFilled to 1 causing the Control list processing to continue. If no
TD is found on the Control list, and if the HCD does not set
ControlListFilled, then ControlListFilled will still be 0 when HC completes
processing the Control list and Control list processing will stop
0 RW HostControllerReset.
This bit is set by HCD to initiate a software reset of HC. Regardless of the
functional state of HC, it moves to the UsbSuspend state in which most of the
operational registers are reset except those stated otherwise; e.g., the
InterruptRouting field of HcControl, and no Host bus accesses are allowed. 1’b0
This bit is cleared by HC upon the completion of the reset operation. The
reset operation must be completed within 10 μs. This bit, when set, should
not cause a reset to the Root Hub and no subsequent reset signal should be
asserted to its downstream ports.
0x0C--HcInterruptStatus Register
31 Reserved 1’b0
30 RW Ownership Change Status.
This bit is set by HC when HCD sets the Ownership Change Request field in
1’b0
HcCommandStatus. This event, when unmasked, will always generate an
System Management Interrupt (SMI#) immediately.
6 RW RootHubStatusChange Status.
This bit is set when the content of HcRhStatus or the content of any of 1’b0
HcRhPortStatus[NumberofDownstreamPort] has changed.
5 RW FrameNumberOverflow Status.
This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 1’b0
to 1 or from 1 to 0, and after HccaFrameNumber has been updated.
4 RO UnrecoverableError Status.
1’b0
This bit is set when HC detects a system error not related to USB. HC

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Data Sheet
should not proceed with any processing nor signaling before the system
error has been corrected. HCD clears this bit after HC has been reset.
This event is not implemented and is hard-coded to '0'.
3 RW ResumeDetected Status.
This bit is set when HC detects that a device on the USB is asserting resume
signaling. It is the transition from no resume signaling to resume signaling 1’b0
causing this bit to be set. This bit is not set when HCD sets the UsbResume
state.
2 RW StartofFrame Status.
This bit is set by HC at each start of a frame and after the update of 1’b0
HccaFrameNumber. HC also generates a SOF token at the same time.
1 RW WritebackDoneHead Status.
This bit is set immediately after HC has written HcDoneHead to
HccaDoneHead. Further updates of the HccaDoneHead will not occur 1’b0
until this bit has been cleared. HCD should only clear this bit after it has
saved the content of HccaDoneHead.
0 RW SchedulingOverrun Status.
This bit is set when the USB schedule for the current Frame overruns and
after the update of HccaFrameNumber. A scheduling overrun will also 1’b0
cause the SchedulingOverrunCount of HcCommandStatus to be
incremented.
0x10--HcInterruptEnable Register
31 RW MasterInterrupt Enable.
A '0' written to this field is ignored by HC.
A '1' written to this field enables interrupt generation due to events specified 1’b0
in the other bits of this register.
This is used by HCD as a Master Interrupt Enable.
30 RW OwnershipChange Enable.
0 : Ignore. 1’b0
1 : Enable interrupt generation due to Ownership Change.
6 RW RootHubStatusChange Enable.
0 : Ignore. 1’b0
1 : Enable interrupt generation due to Root Hub Status Change.
5 RW FrameNumberOverflow Enable.
0 : Ignore. 1’b0
1 : Enable interrupt generation due to Frame Number Overflow.
4 RW UnrecoverableError Enable.
1’b0
This event is not implemented. All writes to this bit will be ignored.

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3 RW ResumeDetected Enable.
0 : Ignore 1’b0
1 : Enable interrupt generation due to Resume Detect.
2 RW StartofFrame Enable.
0 : Ignore 1’b0
1 : Enable interrupt generation due to Start of Frame.
1 RW WritebackDoneHead Enable.
0 : Ignore 1’b0
1 : Enable interrupt generation due to HcDoneHead Writeback
0 RW SchedulingOverrun Enable.
0 : Ignore 1’b0
1 : Enable interrupt generation due to Scheduling Overrun.
0x14--HcInterruptDisable Register
31 RW MasterInterrupt Disable.
A '0' written to this field is ignored by HC.
A '1' written to this field disables interrupt generation due to events 1’b0
specified in the other bits of this register.
Note that this field is set after a hardware or software reset.
30 RW OwnershipChange Disable.
0 : Ignore. 1’b0
1 : Disable interrupt generation due to Ownership Change.
6 RW RootHubStatusChange Disable.
0 : Ignore. 1’b0
1 : Disable interrupt generation due to Root Hub Status Change.
5 RW FrameNumberOverflow Disable.
0 : Ignore. 1’b0
1 : Disable interrupt generation due to Frame Number Overflow.
4 RW UnrecoverableError Disable.
1’b0
This event is not implemented. All writes to this bit will be ignored.
3 RW ResumeDetected Disable.
0 : Ignore 1’b0
1 : Disable interrupt generation due to Resume Detect.
2 RW StartofFrame Disable.
0 : Ignore. 1’b0
1 : Disable interrupt generation due to Start of Frame.

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1 RW WritebackDoneHead Disable.
0 : Ignore. 1’b0
1 : Disable interrupt generation due to HcDoneHead Writeback.
0 RW Scheduling Overrun Disable
0 : Ignore. 1’b0
1 : Disable interrupt generation due to Scheduling Overrun.
3.3.17.2 Memory Pointer Partition
0x18--HcHCCA Register
31:8 RW This is the base address of the Host Controller Communication Area. 24’b0
7:0 Reserved. 8’b0
0x1Ch--HcPeriodCurrentED Register
31:4 RW PeriodCurrentED.
This is used by HC to point to the head of one of the Periodic lists that will
be processed in the current Frame. The content of this register is updated 28’b0
by HC after a periodic ED has been processed. HCD may read the content
in determining which ED is currently being processed at the time of reading.
3:0 Reserved 4’b0
0x20h-- HcControlHeadED Register

31:4 RW ControlHeadED.
HC traverses the Control list starting with the HcControlHeadED pointer. 28’b0
The content is loaded from HCCA during the initialization of HC.
0x24--HcControlCurrentED Register
31:4 RW ControlCurrentED.
This pointer is advanced to the next ED after serving the present one. HC
will continue processing the list from where it left off in the last Frame.
When it reaches the end of the Control list, HC checks the
ControlListFilled in HcCommandStatus. 28’b0
If set, it copies the content of HcControlHeadED to
HcControlCurrentED and clears the bit.
If not set, it does nothing. HCD is allowed to modify this register only when
the ControlListEnable of HcControl is cleared. When set, HCD only

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reads the instantaneous value of this register. Initially, this is set to zero to
indicate the end of the Control list.
0x28--HcBulkHeadED Register
31:4 RW BulkHeadED.
HC traverses the Bulk list starting with the HcBulkHeadED pointer. The 28’b0
content is loaded from HCCA during the initialization of HC.
3:0 Reserved.
0x2C--HcBulkCurrentED Register
31:4 RW BulkCurrentED.
This is advanced to the next ED after the HC has served the present one.
HC continues processing the list from where it left off in the last Frame.
When it reaches the end of the Bulk list, HC checks the
ControlListFilled of HcControl. If set, it copies the content of
28’b0
HcBulkHeadED to HcBulkCurrentED and clears the bit. If it is not set, it
does nothing. HCD is only allowed to modify this register when the
BulkListEnable of HcControl is cleared. When set, the HCD only
reads the instantaneous value of this register. This is initially set to zero to
indicate the end of the Bulk list.
0x30--HcDoneHead Register
31:4 RW DoneHead.
When a TD is completed, HC writes the content of HcDoneHead to the
NextTD field of the TD. HC then overwrites the content of HcDoneHead
with the address of this TD. 28’b0
This is set to zero whenever HC writes the content of this register to HCCA.
It also sets the WritebackDoneHead of HcInterruptStatus.
3:0 Reserved 4’b0
3.3.17.3 Frame Counter Partition
0x34--HcFmInterval Register
31 RW FrameIntervalToggle.
1’b0
HCD toggles this bit whenever it loads a new value to FrameInterval.
30:16 RW FSLargestDataPacket. 15’b0

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This field specifies a value that is loaded into the Largest Data Packet
Counter at the beginning of each frame. The counter value represents the
largest amount of data in bits which can be sent or received by the HC in a
single transaction at any given time without causing scheduling overrun.
The field value is calculated by the HCD.
13:0 RW FrameInterval.
This specifies the interval between two consecutive SOFs in bit times. The
nominal value is set to be 11,999.
HCD should store the current value of this field before resetting HC. By 14’h2EDF
setting the HostControllerReset field of HcCommandStatus as this will
cause the HC to reset this field to its nominal value. HCD may choose to
restore the stored value upon the completion of the Reset sequence.
0x38--HcFmRemaining Register
31 RO FrameRemainingToggle.
This bit is loaded from the FrameIntervalToggle field of HcFmInterval
1’b0
whenever FrameRemaining reaches 0. This bit is used by HCD for the
synchronization between FrameInterval and FrameRemaining.
13:0 RO FrameRemaining.
This counter is decremented at each bit time.
When it reaches zero, it is reset by loading the FrameIntervalvalue
specified in HcFmInterval at the next bit time boundary. 14’h0628
When entering the UsbOperational state, HC re-loads the content with the
FrameInterval of HcFmInterval and uses the updated value from the
next SOF.
0x3C--HcFmNumber Register
15:0 RO FrameNumber.
This is incremented when HcFmRemaining is re-loaded. It will be rolled
over to 0h after FFFFh. When entering the UsbOperational state, this will
be incremented automatically. The content will be written to HCCA after 16’b0
HC has incremented the FrameNumber at each frame boundary and sent a
SOF but before HC reads the first ED in that Frame. After writing to HCCA,
HC will set the StartofFrame in HcInterruptStatus.
0x40--HcPeriodicStart Register

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13:0 RW PeriodicStart.
After a hardware reset, this field is cleared. This is then set by HCD during
the HC initialization. The value is calculated roughly as 10% off from
HcFmInterval. A typical value will be 3E67h.
14’b0
When HcFmRemaining reaches the value specified, processing of the periodic
lists will have priority over Control/Bulk processing. HC will therefore start
processing the Interrupt list after completing the current Control or Bulk
transaction that is in progress.
0x44--HcLSThreshold Register
11:0 RW LSThreshold.
This field contains a value that is compared to the FrameRemaining field
prior to initiating a Low Speed transaction. The transaction is started only 12’b0
if FrameRemaining ≥ this field. The value is calculated by HCD with the
consideration of transmission and set-up overhead.
3.3.17.4 Root Hub Partition
0x48--HcRhDescriptorA Register(Default: 0x0100_0002)

31:24 RW PowerOnToPowerGoodTime.
This byte specifies the duration HCD has to wait before accessing a
powered-on port of the Root Hub. It is implementation-specific. The unit 8’h01
of time is 2 ms.
The duration is calculated as POTPGT * 2 ms.
23: 13 Reserved 11’b0
12 RW NoOverCurrentProtection.
This bit describes how the overcurrent status for the Root Hub ports is
reported. When this bit is cleared, the OverCurrentProtectionMode
field specifies global or per-port reporting. 1’b0
0: Over-current status is reported collectively for all downstream
ports.
1: No over-current protection supported.
11 RW OverCurrentProtectionMode.
This bit describes how the overcurrent status for the Root Hub ports is
reported. At reset, this field should reflect the same mode as 1’b0
PowerSwitchingMode. This field is valid only if the
NoOverCurrentProtection field is cleared.

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0 : Over-current status is reported collectively for all downstream ports.
1 : Over-current status is reported on a per-port basis.
10 RO DeviceType.
This bit specifies that the Root Hub is not a compound device. The Root Hub
1’b0
is not permitted to be a compound device. This field should always
read/write 0.
9 RW NoPowerSwitching.
These bits are used to specify whether power switching is supported or
ports are always powered. USB HC supports global power switching mode.
When this bit is cleared, the PowerSwitchingMode specifies global or 1’b0
per-port switching.
0 : Ports are power switched.
1 : Ports are always powered on when the HC is powered on.
8 RW PowerSwitchingMode.
This bit is used to specify how the power switching of the Root Hub ports is
controlled. USB HC supports global power switching mode. This field is
only valid if the NoPowerSwitching field is cleared.
0: all ports are powered at the same time.
1: Each port is powered individually.
1’b0
This mode allows port power to be controlled by either the global switch or
per-port switching.
If the PortPowerControlMask bit is set, the port responds only to port
power commands (Set/ClearPortPower).
If the port mask is cleared, then the port is controlled only by the global
power switch (Set/ Clear Global Power).
7:0 RO NumberDownstreamPorts.
These bits specify the number of downstream ports supported by the Root
Hub.
Both of the HC support three downstream ports.
In A version it can be programmed to 02h or 01h, HC0 is controlled by SB

CFG 6C bit 0,1 and HC1 is controlled by SB CFG 6C bit 2,3. The setting is 8’h02
tabulated below
NDP’s value SB CFG 6C bit0 or SB CFG 6C bit1 or
bit2 bit3
01h 1 X
02h 0 1
03h 0 0
0x4C--HcRhDescriptorB Register

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31:16 RW PortPowerControlMask.
Each bit indicates if a port is affected by a global power control command
when PowerSwitchingMode is set.
z When set, the port's power state is only affected by per-port power
control (Set/ClearPortPower).
z When cleared, the port is controlled by the global power switch
(Set/ClearGlobalPower). If the device is configured to global 16’b0
switching mode (PowerSwitchingMode=0), this field is not valid.
USB HC implements global power switching.
bit 0: Reserved
bit 1: Ganged-power mask on Port #1
bit 2: Ganged-power mask on Port #2
bit 3-15: reserved
15:0 RW DeviceRemovable.
Each bit is dedicated to a port of the Root Hub. When cleared, the attached
device is removable. When set, the attached device is not removable.
bit 0: Reserved 16’b0
bit 1: Device attached to Port #1
bit 2: Device attached to Port #2
bit 3-15: reserved
0x50--HcRhStatus Register
31 WO ClearRemoteWakeupEnable(Write)
Writing a '1' clears DeviceRemoveWakeupEnable. 1’b0
Writing a '0' has no effect.
17 RW OverCurrentIndicatorChange.
This bit is set by hardware when a change has occurred to the OCI field of
this register. 1’b0
The HCD clears this bit by writing a '1'.
Writing a ‘0’ has no effect.
16 RW LocalPowerStatusChange(Read).
The Root Hub does not support the local power status feature; thus, this bit
is always read as '0'.
SetGlobalPower(Write).
1’b0
In global power mode (PowerSwitchingMode=0), this bit is written to '1'
to turn on power to all ports (clear PortPowerStatus). In per-port
power mode, it sets PortPowerStatus only on ports whose
PortPowerControlMask bit is not set. Writing a ‘0’ has no effect.

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15 RW DeviceRemoteWakeupEnable(Read).
This bit enables a ConnectStatusChange bit as a resume event, causing a
UsbSuspend to UsbResume state transition and setting the
ResumeDetected interrupt.
0 : ConnectStatusChange is not a remote wakeup event. 1’b0
1 : ConnectStatusChange is a remote wakeup event.
SetRemoteWakeupEnable(Write).
Writing a '1' sets DeviceRemoveWakeupEnable.
14:2 Reserved
1 RO OverCurrentIndicator.
This bit reports overcurrent conditions when the global reporting is
implemented. When set, an over-current condition exists. When cleared, 1’b0
all power operations are normal. If per-port over-current protection is
implemented this bit is always ‘0’
0 RW LocalPowerStatus(Read).
The Root Hub does not support the local power status feature; thus, this bit
is always read as '0'.
ClearGlobalPower(Write).
In global power mode (PowerSwitchingMode=0), This bit is written to '1' 1’b0
to turn off power to all ports (clear PortPowerStatus). In per-port
power mode, it clears PortPowerStatus only on ports whose
PortPowerControlMask bit is not set.
Writing a ‘0’ has no effect.
0x54--HcRhPortStatus [1] Register (USB Port 0)

0x58--HcRhPortStatus [2] Register (USB Port 1)
20 RW PortResetStatusChange.
This bit is set at the end of the 10-ms port reset signal.
The HCD writes a '1' to clear this bit.
1’b0
0: port reset is not complete.
1: port reset is complete.
19 RW PortOverCurrentIndicatorChange.
This bit is valid only if over-current conditions are reported on a per-port
basis. This bit is set when Root Hub changes the
PortOverCurrentIndicator bit. 1’b0
The HCD writes a '1' to clear this bit.

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0 : no change in PortOverCurrentIndicator.
1 : PortOverCurrentIndicator has changed.
18 RW PortSuspendStatusChange.
This bit is set when the full resume sequence has been completed. This
sequence includes the 20-s resume pulse, LS EOP, and 3-ms
resynchronization delay. The HCD writes a '1' to clear this bit. Writing a
'0' has no effect. This bit is also cleared when ResetStatusChange is 1’b0
set.
0 : resume is not completed.
1 : resume completed.
17 RW PortEnableStatusChange.
This bit is set when hardware events cause the PortEnableStatus bit to
be cleared.
Changes from HCD writes do not set this bit. The HCD writes a '1' to clear 1’b0
this bit. Writing a '0' has no effect.
0 : no change in PortEnableStatus.
1 : change in PortEnableStatus.
16 RW ConnectStatusChange.
This bit is set whenever a connect or disconnect event occurs. The HCD
writes a '1' to clear this bit. Writing a '0' has no effect. If
CurrentConnectStatus is cleared when a SetPortReset,
SetPortEnable, or SetPortSuspend write occurs, this bit is set to force
the driver to re-evaluate the connection status since these writes should not 1’b0
occur if the port is disconnected.
0 : no change in CurrentConnectStatus.
1 : change in CurrentConnectStatus.
Note: If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub
reset to inform the system that the device is attached.
9 RW LowSpeedDeviceAttached(Read).
This bit indicates the speed of the device attached to this port. When set, a
Low Speed device is attached to this port. When clear, a Full Speed device
is attached to this port. This field is valid only when the 1’b0
CurrentConnectStatus is set.
0 : full speed device attached.
1 : low speed device attached.
8 RW Port Power Status(Read).
This bit reflects the port’s power status, regardless of the type of power
switching implemented. This bit is cleared if an overcurrent condition is
1’b0
detected. HCD sets this bit by writing Set Port Power or Set Global Power.
HCD clears this bit by writing Clear Port Power or Clear Global Power.
Which power control switches will be enabled is determined by Power

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Switching Mode and Port Power Control Mask[NDP]. In global switching
mode (Power Switching Mode=0), only Set/ClearGlobalPower controls this
bit. In per-port power switching (Power Switching Mode=1), if the Port
Power Control Mask[NDP] bit for the port is set, only Set/ClearPortPower
commands are enabled. If the mask is not set, only Set/ Clear Global
Power commands are enabled. When port power is disabled, Current
Connect Status, Port Enable Status, Port Suspend Status, and Port Reset
Status should be reset.
0 : port power is OFF.
1 : port power is ON.
SetPortPower(Write).
The HCD writes a '1' to set the PortPowerStatus bit.
Note: This bit is always reads ‘1b’ if power switching is not supported.
7:5 Reserved 3’b0
4 RW PortResetStatus(Read).
When this bit is set by a write to SetPortReset, port reset signaling is
asserted. When reset is completed, this bit is cleared when
PortResetStatusChange is set. This bit cannot be set if
CurrentConnectStatus is cleared.
0 : port reset signal is not active.
1 : port reset signal is active. 1’b0
SetPortReset(Write).
The HCD sets the port reset signaling by writing a '1' to this bit. Writing a
'0' has no effect.
If CurrentConnectStatus is cleared, this write does not set
PortResetStatus, but instead sets ConnectStatusChange.
This informs the driver that it attempted to reset a disconnected port.
3 RW PortOverCurrentIndicator(Read).
This bit is only valid when the Root Hub is configured in such a way that
over-current conditions are reported on a per-port basis. If per-port
over-current reporting is not supported, this bit is set to 0. If cleared, all
power operations are normal for this port. If set, an over-current condition
exists on this port. This bit always reflects the over-current input signal
0 : no over-current condition. 1’b0
1 : over-current condition detected.
ClearSuspendStatus(Write).
The HCD writes a '1' to initiate a resume.
Writing a '0' has no effect. A resume is initiated only if
PortSuspendStatus is set.
2 RW PortSuspendStatus(Read).
1’b0
This bit indicates the port is suspended or in the resume sequence. It is set

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Data Sheet
by a SetSuspendState write and cleared when
PortSuspendStatusChange is set at the end of the resume interval.
This bit cannot be set if CurrentConnectStatus is cleared. This bit is
also cleared when PortResetStatusChange is set at the end of the port
reset or when the HC is placed in the UsbResume state. If an upstream
resume is in progress, it should propagate to the HC.
0 : port is not suspended.
1 : port is suspended.
SetPortSuspend(Write).
The HCD sets the PortSuspendStatus bit by writing a '1' to this bit.
If CurrentConnectStatus is cleared, this write does not set
PortSuspendStatus; instead it sets ConnectStatusChange. This
informs the driver that it attempted to suspend a disconnected port.
1 RW PortEnableStatus(Read).
This bit indicates whether the port is enabled or disabled. The Root Hub
may clear this bit when an over-current condition, disconnect event,
switched-off power, or operational bus error such as babble is detected.
This change also causes PortEnabledStatusChange to be set. HCD
sets this bit by writing SetPortEnable and clears it by writing
ClearPortEnable. This bit cannot be set when
CurrentConnectStatus is cleared. This bit is also set, if not already, at
the completion of a port reset when ResetStatusChange is set or port
1’b0
suspend when SuspendStatusChange is set.
0 : port is disabled.
1 : port is enabled.
SetPortEnable(Write).
The HCD sets PortEnableStatus by writing a '1'.Writing a '0' has no
effect. If CurrentConnectStatus is cleared, this write does not set
PortEnableStatus, but instead sets ConnectStatusChange. This
informs the driver that it attempted to enable a disconnected port.
0 RW CurrentConnectStatus(Read).
This bit reflects the current state of the downstream port.
0 : no device connected.
1 : device connected.
ClearPortEnable(Write). 1’b0
The HCD writes a '1' to this bit to clear the PortEnableStatus bit.
Writing a '0' has no effect. The CurrentConnectStatus is not affected
by any write.
Note: This bit is always read ‘1b’ when the attached device is nonremovable
(DeviceRemoveable[NDP]).

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Data Sheet
3.3.18 USB2.0 Configuration Registers
0x04-05--Command Register(Default value: 0x0000)

Bit Type Description Default
15:3 RW Reserved .
13’b0
These bits are always 0.
2 RW Master Enable. 1’b0
If set to 1, EHC is enabled to run master cycles. (Recom. to 1’b1)
1 RW Operation Register Access Enable. 1’b0
If set to 1, USB2.0 Operation Registers can be accessed. (Recom. to 1’b1)
0 RO Reserved 1’b0
0x40-43--Operational Mode Enable Register (Default: 0x0000_0080)

31:8 RW Reserved
These bits are only used for test-mode. Changes to these bits will cause 24’b0
undefined behavior.
7:5 RW FIFO Threshold Control,
These bits are used to control the FIFO threshold level. When FIFO
threshold is reached, OUT cycle will be driven by EHC.
000: FIFO threshold is set to 128 bytes
010: FIFO threshold is set to 384 bytes 3’b100
4:3 RW Reserved
These bits are only used for test-mode.
Changes to these bits will cause undefined behavior.
2 RW Debug Port Enable.
This register enables the debug port for EHC.
1’b0
1: Debug port is enabled
0: Debug port is disabled
1:0 RW Write Special Registers Protect.
These registers protect write-special registers.
2’b0
10: Registers can be written
Others: Register cannot be written

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3.3.19 USB2.0 Operational Registers
0x00--CAPLENGTH – Capability Registers Length

7:0 RO Capability Register Length.
8’h20
This register indicates to the length of the host controller capability registers.
0x02-03--HCIVERSION – Host Controller Interface Version Number

15:0 RO Host Controller Interface Version Number.
16’h0100
This register indicates the EHC support the EHCI Spec Revision 1.0.
0x04-07--HCSPARAMS – Structure Parameters (Default : 0x0010_1202)

31:24 RO Reserved
8’b0
These registers are always 0.
23:20 RO Debug Port Number.
4’h1
This register identifies the first port as the debug port.
19:16 RO Reserved
4’h0
15:12 RO Number of Companion Controller (N_CC).
This field indicates the number of companion controllers associated with 4’h1
this USB2.0 host controller.
11:8 RO Number of Ports per Companion Controller (N_PCC).
This field indicates the number of ports supported per companion host 4’h2
controller.
7:4 RO Reserved
4’h0
3:0 RO Number of Ports (N_PORTS).
4’h2
This field indicates the number of ports supported on this host controller.
0x08-0B--HCCPARAMS – Capability Parameters (Default: 0x0000_7070)

31:16 RO Reserved
16’b0
15:8 RO EHCI Extend Capabilities Pointer (EECP).
8’h70
This field indicates the existence of a capability list.
7:4 RW Isochronous Scheduling Threshold.
This field indicates, relative to the current position of the executing host 4’h7
controller, where software can reliable update the isochronous schedule.

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3 RO Reserved
1’b0
This register is always 0.
2 RW Asynchronous Schedule Park Capability.
If this bit is set to a one, then the host controller supports the park feature for 1’b0
high-speed queue heads in the Asynchronous Schedule.
1:0 RO Reserved
2’b00
0x20-23--USB2CMD – USB2.0 Command Register (Default: 0x0008_0000)

31:24 RO Reserved
8’b0
23:16 RW Interrupt Threshold Control.
This field is used by system software to select the maximum rate at which 8’h08
the host controller will issue interrupt.
15:12 RO Reserved
4’b0
11 RW Asynchronous Schedule Park Mode Enable.
If the Asynchronous Park Capability bit in the HCCPARAMS register is a
1’b0
one, then this bit defaults to a 1h and is R/W. Software uses this bit to
enable or disable Park mode.
10 RO Reserved
1’b0
This register is always 0.
9:8 RW Asynchronous Schedule Park Mode Count.
If the Asynchronous Park Capability bit in the HCCPARAMS register is a
one, then this bit defaults to a 3h and is R/W. This field contains a count to
2’b0
the number of successive transactions the host controller is allowed to
execute from a high-speed queue head on the asynchronous schedule before
continuing traversal of the asynchronous schedule.
7 RW Light Host Controller Reset.
It allows the driver to reset the EHCI controller without affecting the state of 1’b0
the ports or the relationship to the companion host controllers.
6 RW Interrupt on Async Advance Doorbell.
This bit is used as a doorbell by software to tell the host controller to issue 1’b0
an interrupt the next time it advances asynchronous schedule.
5 RW Asynchronous Schedule Enable
This bit controls whether the host controller skips processing the 1’b0
Asynchronous Schedule.
4 RW Periodic Schedule Enable
This bit controls whether the host controller skips processing the Periodic 1’b0
Schedule.

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3:2 RO Reserved
2’b0
1 RW Host Controller Reset (HCRESET)
1’b0
This control bit is used by software to reset the host controller.
0 RW Run/Stop (RS)
1’b0
When set to a 1, the host controller proceeds with execution of the schedule.
0x24-27--USB2STS – USB2.0 Status Register (Default: 0x0000_1000)

31:16 RO Reserved
16’b0
15 RO Asynchronous Schedule Status.
This bit reports the current real status of the Asynchronous Schedule. If this 1’b0
bit is a zero then the status of the Asynchronous Schedule is disable.
14 RO Periodic Schedule Status.
This bit reports the current real status of the Periodic Schedule. If this bit is a 1’b0
zero then the status of the Periodic Schedule is disable.
13 RO Reclamation.
1’b0
This bit is used to detect an empty asynchronous schedule.
12 RO Host Controller Halted (HCHalted).
This bit is a zero whenever the Run/Stop bit is a one. The Host Controller
1’b1
sets this bit to one after it has stopped executing as a result of the Run/Stop
bit being set to 0, either by software or by the Host Controller hardware.
11:6 RO Reserved
6’b0
5 R/W Interrupt on Async Advance.
C System software can force the host controller to issue an interrupt the next
time the host controller advances the asynchronous schedule by writing a 1’b0
one to the Interrupt on Async Advance Doorbell bit in the USB2CMD
register.
4 R/W Host System Error.
C The Host Controller sets this bit to 1 when a serious error occurs during a 1’b0
host system access involving the Host Controller module.
3 R/W Frame List Rollover.
C The Host Controller sets this bit to a one when the Frame List Index rolls 1’b0
over from its maximum value to zero.
2 R/W Port Change Detect.
C The Host Controller sets this bit to a one when any port for which the Port
Owner bit is set to zero has a change bit transition from a zero to a one or a 1’b0
Force Port Resume bit transition from a zero to a one as a result of a J-K
transaction detected on a suspended port. This bit will also be set as a result

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Data Sheet
of the Connect Status Change being set to a one after system software has
relinquished ownership of a connected port by writing a one to a port’s Port
Owner bit.
1 R/W USB Error Interrupt (USBERRINT).
C The Host Controller sets this bit to 1 when completion of a USB transaction 1’b0
results in an error condition.
0 R/W USB Interrupt (USBINT).
C The Host Controller sets this bit to 1 one the completion of a USB
1’b0
transaction, which result in the retirement of a Transfer Descriptor that had
its IOC bit set.
0x28-2C--USB2INTR – USB2.0 Interrupt Enable Register (Default: 0x0000_0000)

31:6 RO Reserved
26’b0
5 RW Interrupt on Async Advance Enable. 1’b0
4 RW Host System Error Enable. 1’b0
3 RW Frame List Rollover Enable. 1’b0
2 RW Port Change Detect Enable. 1’b0
1 RW USB Error Interrupt Enable. 1’b0
0 RW USB Interrupt Enable. 1’b0
0x2C-2F--FRINDEX – Frame Index Register

31:14 RO Reserved
18’b0
13:0 RW Frame Index.
14’b0
The value in this register increment at the end of each time frame.
0x34-37--PERIODICLISTBASE – Periodic Frame List Base Address Register (Default: undefined)

31:12 RW Base Address.
These bits correspond to memory address [31:12].
11:0 RO Reserved
12’b0
0x38-3B--ASYNCLISTBASE – Current Asynchronous List Address Register (Default: undefined)

31:5 RW Link Pointer.

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These bits correspond to memory address [31:5].
4:0 RO Reserved
5’b0
0x60-63--CONFIGFLAG – Configure Flag Register

31:1 RO Reserved
31’b0
0 RW Configure Flag (CF).
Host software sets this bit as the last action in its process of configuring the
1’b0
Host Controller. Writing a one to this register will route all port to this host
controller.
0x64-67--PORTSC0 – Port 0 Status and Control Register

0x68-6B--PORTSC1 – Port 1 Status and Control Register (Default: 0x0000_3000)
31:23 RO Reserved
9’b0
22 RW Wake on Over-current Enable (WKOC_E).
Writing this bit to a one enables the port to be sensitive to over-current 1’b0
conditions as wake-up events.
21 RW Wake on Disconnect Enable (WKDSCNNT_E).
Writing this bit to a one enables the port to be sensitive to device disconnects 1’b0
as wake-up events.
20 RW Wake on Connect Enable (WKCNNT_E).
Writing this bit to a one enables the port to be sensitive to device connects as 1’b0
wake-up events.
19:16 RW Port Test Control.
4’b0
When this field is zero, the port is NOT operation in a test mode.
15:14 RO Reserved
2’b0
13 RW Port Owner.
This bit unconditionally goes to a 0b when the Configured bit in the
CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally 1’b1
goes to 1b whenever the Configured bit is zero. Software writes a one to this
bit when the attached device is not a high-speed device.
12 RO Port Power (PP).
The Host Controller does not have port power control switches. Each port is 1’b1
hard-wired to power.
11:10 RO Line Status.
2’b0
These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10)

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Data Sheet
signal lines.
9 RO Reserved
1’b0
This bit is always 0.
8 RW Port Reset.
When software writes a one to this bit, the bus reset sequence as defined in
1’b0
the USB Spec Revision 2.0 is started. Software writes a zero to this bit to
terminate the bus reset sequence.
7 RW Suspend.
Software writes a one to this bit to suspend the downstream port. A write of
zero to this bit is ignored by the host controller. The host controller will 1’b0
unconditionally set this bit to a zero when software sets the Force Port
Resume from 1 to 0 or sets the Port Reset bit to 1.
6 RW Force Port Resume.
Software sets this bit to a 1 to driver resume signaling. The Host Controller
sets this bit to a 1 if a J-to-K transition is detected while the port is in the
1’b0
Suspend state. A write of zero to this bit will force the downstream port
follows the resume sequence follows the defined sequence documented in
the USB Spec Revision 2.0.
5 R/W Over-current Change.
C 1’b0
This bit gets set to a one when there is a change to Over-current Active.
4 RO Over-current Active.
0: This port does not have an over-current condition. 1’b0
1: This port has an over-current condition.
3 R/W Port Enable/Disable Change.
C For the root hub, this bit gets set to a one only when a port is disabled due to 1’b0
the appropriate conditions existing at the EOF2 pointer.
2 RW Port Enable/Disabled.
Ports can only be enabled by the host controller as a part of the reset and
1’b0
enable. Software cannot enable a port by writing a one to this field. Ports can
be disabled by either a fault condition or by host software.
1 R/W Connect Status Change.
C 1: Change in Current Connect Status. 1’b0
0: No change.
0 RW Current Connect Status.
1’b0
This value reflects the current connect status of the port.

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4.0 Electrical Characteristics
4.1 DC Electrical Characteristics
DC electrical characteristics are listed in Table 4-1.
Table 4-1. DC Electrical Characteristics

RGMII Interface (VDDIO= 2.5V+-10%)
Symbol Parameter Condition Min Typ. Max Unit
Vih Input High Voltage 1.7 VDDIO+0.3 V
Vil Input Low Voltage -0.3 0.7 V
Iih Input High Current Vin=VDDIO(max) -10 10 uA
Iil Input Low Current Vin=GND -10 10 uA
Voh Output High Voltage Ioh=-14mA 2.0 V
Vol Output Low Voltage Iol=14mA 0.4 V
Cin Input Capacitance 5 12 pF
MII Interface (VDDIO= 3.3V+-10%)

1
Voh1 Output High Voltage Ioh=-4mA, * 2.4 V
Vol1 Output Low Voltage Iol=4mA, *1 0.4 V
Voh2 Output High Voltage Ioh=-7mA, *2 2.4 V
2
Vol2 Output Low Voltage Iol=7mA, * 0.4 V
Note 1. For pin P0_CRS, P0_COL, P1_CRS, and P1_COL
2. For pins except Note1' mentioned
Flash/SRAM/PCMCIA/Misc Interface (VDDIO=3.3V+-10%)

3
Voh1 Output High Voltage Ioh=-4mA, * 2.4 V
Vol1 Output Low Voltage Iol=4mA, *3 0.4 V

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Voh2 Output High Voltage Ioh=-8mA, *4 2.4 V

4
Vol2 Output Low Voltage Iol=8mA, * 0.4 V
Note 3. For pin SCE0_n and SCE1_n
4. For pins except Note3' mentioned
DDR SDRAM Interface (SSTL-2 Class-I) (VDD=2.5V+-10%)

Vref Reference Voltage 1.13 1.25 1.38 V
Vih Input High Voltage Vref+0.15 VDD+0.3 V
Vil Input Low Voltage -0.3 Vref-0.15 V
Iih Input High Current Vin=VDD(max) -10 10 uA
Voh Output High Voltage Ioh=-8.1mA 1.74 V
Vol Output Low Voltage Iol=8.1mA 0.76 V
Cin Input Capacitance pF
PCI/Cardbus Interface ( VCC=3.3V+-10% )

Vih Input High Voltage 0.5VCC 5.5 V
Vil Input Low Voltage -0.5 0.3VCC V
Iih Input High Current Vin=VCC(max) -10 10 uA
Voh Output High Voltage Ioh=-500uA 0.9VCC V
Vol Output Low Voltage Iol=1500uA 0.1VCC V
Cin Input Pin Capacitance 10 16 pF
Cclk Clock Pin Capacitance 5 12 pF
USB1.1/2.0 Interface (D+/D-)

VDIHS HS Differential Input Sensitivity |(D+)-(D-)| 150 mV
VCMHS HS Common Mode Range -50 500 mV
VHSOH HS Output Voltage High 360 440 mV
VHSOL HS Output Voltage Low -10 10 mV
VDIFS FS Differential Input Sensitivity |(D+)-(D-)| 200 mV
VCMFS FS Common Mode Range 0.8 2.5 V

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Data Sheet
VFSOH FS Output Voltage High 2.8 3.6 V

VFSOL FS Output Voltage Low 0.3 V
ZDRV Drive Output Impedance for HS & FS 40.5 45 49.5 Ohm
ILO Hi-Z State Data Line Leakage -10 10 uA
4.2 Absolute Maximum Ratings
Table 4-2. Absolute Maximum Ratings

Parameter Symbol Min Max Unit
PVDD, PVDD_SW0,
PVDD_SW1,
I/O Supply Voltage PVDD_DDR -0.5 4.6 V
Core Supply Voltage CVDD -0.5 2.5 V
Input Voltage -0.5 6.0 V
Output Voltage -0.5 6.0 V
Storage Temperature -65 150
ESD Protection(Human Body Mode) HBM 2000 V
ESD Protection(Machine Mode) MM 150 V
4.3 Recommended Operation Conditions
Table 4-3. Recommended Operation Conditions

Parameter Symbol Min. Max. Unit
I/O Supply Voltage PVDD 3.0 3.6 V
PVDD_SW0,
I/O Supply Voltage (for MII/Reverse MII) PVDD_SW1 3.0 3.6 V
PVDD_SW0,
I/O Supply Voltage (for RGMII) PVDD_SW1 2.25 2.75 V
I/O Supply Voltage (for DDR) PVDD_DDR 2.25 2.75 V
Core Supply Voltage CVDD 1.62 1.98 V
Operation Temperature 0 70
Junction Temperature 0 125
Low-level Input Voltage -0.3 0.8 V
High-level Input Voltage 2.0 5.5 V
BGA-304
(CNS1102/CNS1109/STR9102/STR9105)
package thermal resistance from junction to
ambient – No air flow@2W θJA(0/sec) 27.3 /W

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Orion: STR91XX
CNS11XX
Data Sheet
Parameter Symbol Min. Max. Unit
BGA-304
(CNS1102/CNS1109/STR9102/STR9105)
package thermal resistance from junction to
ambient – air flow 2m/sec@2W θJA(2/sec) 23.4 /W
LFBGA-257 (STR9104) package thermal
resistance from junction to ambient – No air
flow@2W θJA(0/sec) 26.7 /W
LFBGA-257 (STR9104) package thermal
resistance from junction to ambient – air flow
2m/sec@2W θJA(2/sec) 21.8 /W
PQFP-208 (STR9101/9109) package thermal
resistance from junction to ambient – No air
flow@2W θJA(0/sec) 40.9 /W
PQFP-208 (STR9101/9109) package thermal
resistance from junction to ambient – air flow
2m/sec@2W θJA(2/sec) 35.1 /W
4.4 Power Consumption
Table 4-4. Power Consumption

Supply Voltage Symbol Typical Maximum
PVDD (3.3V) 18mA
PVDD_SW0 (3.3V) 14mA
PVDD_SW1 (2.5V) 9mA
CVDD (1.8V) 280mA
PVDD_DDR (2.5V) 90mA
AVDD_U (1.8V) 72mA
AVDD_UP (1.8V) 10mA
AVDD_SP (1.8V) 1mA
AVDD_R33 (3.3V) 2mA
AVDD_U33 (3.3V) 4mA
Total Power Consumption Typical Maximum
1026mW
Note: Test conditions--CPU run at 200MHz, two USB ports are enabled, switch control run at
10/100/1000M mode.
4.5 AC Timing Specifications
Table 4-5. AC Timing Specifications

Parameter Symbol Min Typical Max Units Notes

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Data Sheet
RGMII Interface
Data to Clock output Setup (at
tSETUP_T 1.2 2.0 - ns 1
Transmitter-integrated delay)
Clock to Data output Hold (at
tHOLD_T 1.2 2.0 - ns 1
Transmitter-integrated delay)
Data to Clock input Setup (at
tSETUP_R 1.0 2.0 - ns 2
Receiver-integrated delay)
Clock to Data input Hold (at
tHOLD_R 1.0 2.0 - ns 2
Receiver -integrated delay)
Clock Cycle tCYC 7.2 8 8.8 ns
Duty Cycle for Gigabit Duty_G 45 50 55 %
Duty Cycle for 10/100 Duty_T 40 50 60 %
Rise/Fall Time (20-80%) tR/tF .75 ns
MII Interface
TXCLK to output delay tDELAY 0 - 25 ns
Data to RXCLK Setup tSETUP 10 - - ns
Data to RXCLK Hold tHOLD 10 - - ns
40
(100BaseT)
Clock Cycle tCYC - - ns
400
(10BaseT)
Reverse MII Interface
RXCLK to output delay tDELAY 0 - 25 ns
Data to TXCLK Setup tSETUP 10 - - ns
Data to TXCLK Hold tHOLD 10 - - ns
40
(100BaseT)
Clock Cycle tCYC - - ns
400
(10BaseT)
Parameter Symbol Min Duration- Max Units Notes

DDR SDRAM interface
PRECHARGE command period tRP - 1~4 - tCK 10, 11, 12
LOAD MODE REGISTER command period tMRD - 1~4 - tCK 10, 11, 13
AUTO-REFRESH command period tRFC - 1~16 - tCK 10, 11, 14
ACTIVE to READ or WRITE command period tRCD - 1~4 - tCK 10, 11, 15
ACTIVE to PRECHARGE command period tRAS - 1~8 - tCK 10, 11, 16
Write recovery period tWR - 1~4 - tCK 10, 11, 17

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Orion: STR91XX
CNS11XX
Data Sheet
Flash/SRAM Interface
Access setup time tAST - 1~4 - tCK 3, 4
Write-enable to chip-enable delay tWTC - 0~4 - tCK 3, 5
Read-enable to chip-enable delay tRTC - 0~4 - tCK 3, 5
Access time tAT1 - 1~256 - tCK 3, 6
Chip-disable to write-disable delay tCTW - 0~4 - tCK 3, 7
Chip-disable to read-disable delay tCTR - -1~3 - tCK 3, 7
Address hold time tAHT - 1~4 - tCK 3, 8
Turn-around time tTRAN - 1~256 - tCK 3, 9
Read data latch time before SOE_n de-assert tLATCH - 1 - tCK 3
PCMCIA Interface
Access setup time tAS - 1~16 - tCK 3, 18
Access pulse tAP - tAPREG + tWW - tCK 3, 19
Access hold time tAH - 1~16 - tCK 3, 20

WAIT_n valid from PWE_n or POE_n or
tWV - - tAPREG-1 tCK 3, 19
IORD_n or IOWR_n assert
WAIT_n width tWW 0 - - ns
Read Data hold time from POE_n or IORD_n
tDH 0 - - ns
de-assert
IORD_n and IOWR_n valid before CE1_n or
tRWV 1 - - tCK 3, 21
CE2_n assert
IORD_n and IOWR_n invalid after CE1_n or
tRWIV 1 - - ns 21
CE2_n de-assert
66MHz 33MHz
Parameter Symbol Units Notes
Min Max Min Max
PCI Interface
PCICLK Cycle Time tCYC 15 30 ns 22, 23
PCICLK High Time tHIGH 6 11 ns

PCICLK Low Time tLOW 6 11 ns
PCICLK Slew Rate 1.5 4 1 4 V/ns 24
PCICLK to Signal Valid Delay tVAL 2 6 2 11 ns 25
Float to Active Delay tON 1 1 ns 26
Active to Float Delay tOFF 15 30 ns 26
Input Setup Time to PCICLK tSU 3 7 ns 27

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CNS11XX
Data Sheet
Input Hold Time to PCICLK tH 0 0 ns 27

UART Interface
666.66 104160
Baud rate period tBIT ns 28
(1.5Mbps) (9.6kbps)
ARM-Like ICE Interface
ICK Low period tBSCL 50 - ns 29
ICK High period tBSCH 50 - ns 29
IDIO(out) valid from ICK(falling) tBSOD - 10 ns 30
IDIO(in) and IMS setup to ICK(rising) tBSIS 2 ns 31
IDIO(in) and IMS hold from ICK(rising) tBSIH 2 ns

Multi-ICE Interface
TCK Low period tBSCL 50 - ns 32
TCK High period tBSCH 50 - ns 32
TDO valid from TCK(falling) tBSOD - 10 ns 33
TDI and TMS setup to TCK(rising) tBSIS 2 ns 34
TDI and TMS hold from TCK(rising) tBSIH 2 ns
Notes
1. Different skew adjustment for RGMII tx clock and tx data/enable can be fine tuned by port0_tx_skew[1:0] and
port1_tx_skew[1:0] as follows,
00: 0 ns.
01: 1.5 ns.
10: 2.0 ns. (This is recommended value for RGMII 1.3 and 2.0 spec. with no PCB trace delay)
11: 2.5 ns.
The port0_tx_skew[1:0] is set by bit [27:26] of “Test 0 Register” (offset address: 0x094) of GbE Switch
Controller block.
The port1_tx_skew[1:0] is set by bit [31:30] of “Test 0 Register” (offset address: 0x094) of GbE Switch
Controller block.
2. Different skew adjustment for RGMII rx clock and rx data/enable can be fine tuned by port0_rx_skew[1:0] and
port1_rx_skew[1:0] as follows,
00: 0 ns. (This is recommended value for RGMII 2.0 spec. with no PCB trace delay)
01: 1.5 ns.
10: 2.0 ns. (This is recommended value for RGMII 1.3 spec. with no PCB trace delay)
11: 2.5 ns.
The port0_rx_skew[1:0] is set by bit [25:24] of “Test 0 Register” (offset address: 0x094) of GbE Switch
Controller block.
The port1_rx_skew[1:0] is set by bit [29:28] of “Test 0 Register” (offset address: 0x094) of GbE Switch
Controller block.
3. HCLK is an internal system clock running at 125/112.5/100/87.5 MHz. This corresponds to a period of tCK is
8/8.89/10/11.4 ns.

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Data Sheet
4. The cycle time is set by bit [19:18] of “memory bank n configuration register” (offset address: 0x4 and 0xC) of
Static Memory Controller (SMC) block.
SMC block.
6. The cycle time is set by bit [27:24] and [15:12] of “memory bank n configuration register” (offset address: 0x4
and 0xC) of SMC block.
SMC block.
SMC block.
9. The cycle time is set by bit [31:28] and [3:0] of “memory bank n configuration register” (offset address: 0x4
and 0xC) of SMC block.
10. CK is an output clock to DDR device. Clock cycle time is equal to that of internal system clock.
11. CK can run at 125/112.5/100/87.5 MHz. This corresponds to a period of tCK is 8/8.89/10/11.4 ns.
12. The cycle time is set by bit [7:6] of “DDRC Timing Parameter 0 Register “(offset address: 0x0) of DDR
SDRAM Control(DDRC) block.
13. The cycle time is set by bit [18:17] of “DDRC Timing Parameter 0 Register “(offset address: 0x0) of DDRC
block.
block.
block.
block.
block.
18. The cycle time is set by bit [7:4] of “Memory Access Timing Control Register 1” and “IO Access Timing Control
Register 1“(offset address: 0x18 and 0x20) of PCMCIA block for memory mode access and I/O mode access
respectively.
19. The tAP basically is set by bit [7:0] of “Memory Access Timing Control Register 0” and “IO Access Timing
Control Register 0“(offset address: 0x14 and 0x1c) of PCMCIA block for memory mode access and I/O mode
access respectively. It can be set from 1 to 256, presented as tAPREG. And the final access pulse width is
“tAPREG+tWW”, where tWW is pulse width of WAIT_n.
20. The cycle time is set by bit [3:0] of “Memory Access Timing Control Register 1” and “IO access Timing
Control Register 1“(offset address: 0x18 and 0x20) of PCMCIA block for memory mode access and I/O mode
access respectively.
21. Since pins IORD_n and IOWR_n are shared with SA[21] and SA[20] of SRAM/Flash interface respectively,
these 2 I/O mode read/write control signals are only valid at PCMCIA I/O mode access phase.
22. In general, all 66MHz PCI components must work with any clock frequency up to 66 MHz. PCICLK
requirements vary depending upon whether the clock frequency is above 33Mhz.
23. The minimum clock period must not violate for any single clock cycle; i.e., shall account for all system jitters.
24. Slew rate ratio is measured from 10% to 90%.
25. Applicable to AD[31:0], C_BE_n[3:0], PAR, FRAME_n, IRDY_n, TRDY_n, STOP_n, DEVSEL_n, PERR_n,
SERR_n, GNT0_n, GNT1_n, GNT2_n, and PCIRST_n.
and SERR_n.
SERR_n, REQ0_n, REQ1_n, REQ2_n, INT0_n, INT1_n, and INT2_n.
28. tBIT can be configured via UART internal Registers (Base address is 7800_0000) – DLL (offset is 0x00) /
DLM (offset is 0x04) / PSR (offset is 0x08) when DLAB (offset is 0x0C) is set to 1. For example, if DLL =
8’h01, DLM = 8’h00 and PSR = 2’b01, the baud rate is 1.5MHz (tBIT). Please refer to the details in register

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CNS11XX
Data Sheet
definition. .
29. The ARM-Like ICE server software allows user to change the ICK LOW and HIGH periods between the
values shown in Table. The other parameters shown in Table must be considered with the specific values of
tBSCL and tBSCH that you have chosen. The default values for an auto-configured single-TAP system are,
nominally, tBSCL=50ns and tBSCH=50ns.
30. tBSOD is the maximum delay between the falling edge of ICK and valid levels on the IDIO(out) ARM-like ICE
output signals. The target samples these signals on the following rising edge of ICK and so the minimum setup
time for the target, relative to the rising edge of ICK, is tBSCL–tBSOD.
31. tBSIS is the minimum setup time for the IDIO(in) and IMS input signal, relative to the rising edge of ICK when
ARM-like ICE samples this signal. The target changes its IDIO(in) and IMS value on the previous falling edge
of ICK and so the maximum time for the target IDIO(in) and IMS level to become valid, relative to the falling
edge of ICK, is tBSCL–tBSIS.
32. The Multi-ICE server software allows user to change the TCK LOW and HIGH periods between the values
shown in Table. The other parameters shown in Table must be considered with the specific values of tBSCL
and tBSCH that you have chosen. The default values for an auto-configured single-TAP system are,
nominally, tBSCL=50ns and tBSCH=50ns.
33. tBSOD is the maximum delay between the falling edge of TCK and valid levels on the TDO Multi-ICE output
signals. The target samples these signals on the following rising edge of TCK and so the minimum setup time
for the target, relative to the rising edge of TCK, is tBSCL–tBSOD.
34. tBSIS is the minimum setup time for the TDI and TMS input signal, relative to the rising edge of TCK when
Multi-ICE samples this signal. The target changes its TDI and TMS value on the previous falling edge of TCK
and so the maximum time for the target TDI and TMS level to become valid, relative to the falling edge of TCK,
is tBSCL–tBSIS.

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Orion: STR91XX
CNS11XX
Data Sheet
4.6 Interface Timing Waveforms
tCYC
TXCLK with internal
TXCLK(source of data) delay added
tSETUP_T
TXD[3:0] TXD[3:0] TXD[7:4]
tHOLD_T
TXCTL TXEN TXERR
tSETUP_R
TXCLK(at receiver)
tHOLD_R
tCYC
RXCLK with internal
RXCLK(source of data) delay added
tSETUP_T
RXD[3:0] RXD[3:0] RXD[7:4]
tHOLD_T
RXCTL RXDV RXERR
tSETUP_R
RXCLK(at receiver)
tHOLD_R
Figure 4-1. RGMII Interface Timing

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Orion: STR91XX
CNS11XX
Data Sheet
tCYC
TXCLK
TXD[3:0], TXEN
tDELAY
tCYC
RXCLK
RXD[3:0], RXDV
tSETUP
tHOLD
Figure 4-2. MII Interface Timing
tCYC
RXCLK (output)
RXD[3:0], RXDV (input)
tDELAY
tCYC
TXCLK (output)
TXD[3:0], TXEN (output)

tSETUP
tHOLD
Figure 4-3. Reverse MII Interface Timing

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Orion: STR91XX
CNS11XX
Data Sheet
Figure 4-4. Flash/SRAM Interface Write Timing
Figure 4-5. Flash/SRAM Interface Read Timing

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Orion: STR91XX
CNS11XX
Data Sheet
tCK
CKn
CK
Command NOP PRE EMRS MRS PRE AR AR MRS
DA[9:0]
CODE CODE CODE
DA[12:11]
DA[10] CODE CODE CODE
BA[0]=H BA[0]=L BA[0]=L

BA[1:0] BA[1]=L BA[1]=L BA[1]=L
tRP tMRD tMRD tRP tRFC tRFC
Figure 4-6. DDR SDRAM Interface Timing 0
tCK
CKn
CK
Command NOP ACT NOP WRITE NOP NOP NOP NOP PRE
DA[9:0]
RA Col n
DA[12:11]
All Banks/
DA[10] RA One Banks
BA[1:0] Bank x Bank x Bank x
tRCD tWR
tRAS
DQS
DDQ DQn DQn+1 DQn+2 DQn+3
DM
Figure 4-7. DDR SDRAM Interface Timing 1

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CNS11XX
Data Sheet
Figure 4-8. PCMCIA Interface Memory Write Timing
Figure 4-9. PCMCIA Interface Memory Read Timing

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CNS11XX
Data Sheet
Figure 4-10. PCMCIA Interface I/O Write Timing

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Orion: STR91XX
CNS11XX
Data Sheet
Figure 4-11. PCMCIA Interface I/O Read Timing
tCYC tHIGH
tLOW
PCICLK
tSU
tH
INPUT
PCICLK
tVAL
OUTPUT
DELAY
Tri-State
OUTPUT
tON
tOFF
Figure 4-12. PCI Interface Timing
tBIT
UR_TXD/UR_RXD
data bit
start bit stop bit
Figure 4-13. UART Interface Timing

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Data Sheet
tBSCL tBSCH
ICK
tBSOD
IDIO(out)
tBSIS tBSIH
IMS and
IDIO(in)
Figure 4-14. ARM-Like ICE Interface Timing
tBSCL tBSCH
TCK
tBSOD
TDO
tBSIS tBSIH
TMS
and TDI
Figure 4-15. Multi-ICE Interface Timing

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Orion: STR91XX
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Data Sheet
5.0 Mechanical Specifications
5.1 PQFP-208 Package Outline and Dimensions
Figure 5-1. CNS1101/CNS1109/STR9101/STR9109 Package Outline and Dimensions— 208-pins

28mm*28mm PQFP

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Orion: STR91XX
CNS11XX
Data Sheet
5.2 BGA-304 Package Outline and Dimensions
Figure 5-2. CNS1102/CNS1105/STR9102/STR9105 Package Outline and Dimensions— 304-pins

27mm*27mm BGA

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Orion: STR91XX
CNS11XX
Data Sheet
5.3 LFBGA-257 Package Outline and Dimensions
Figure 5-3. CNS1104/STR9104 Package Outline and Dimensions— 257-pins 14mm*14mm LFBGA

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Orion: STR91XX
CNS11XX
Data Sheet
6.0 Part Order Numbering and Package Marking
Figure 6-1 is an example of the part order numbering scheme for the CNS11XX/STR91XX family.
STR91XX - AD 00 X g u
Speed Grade
Part Number u = 250MHz
STR9102 else 200MHz
Mask Version
AC = 3rd revision Green Package Type
AD = 4th revision g: lead-free
Software ID Code Customer Code

(00, 01, 10, 11) (optional)
Figure 6-1. Sample Part Order Number
Table 6-1. CNS11XX/STR91XX AD version Part Order Number List

CPU
Part Number Part Number CPU Clock
Clock
STR9101-AD00g 200MHz STR9101-AD00gu 250MHz
STR9104-AD00g 200MHz 250MHz
Table 6-2. CNS11XX/STR91XX AD version Part Order Number List with Specific Customer Code
CPU
Clock
STR9101-AD00Mgu 250MHz
STR9202-AD00Bg 200MHz STR9202-AD00Bgu 250MHz

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Orion: STR91XX
CNS11XX
Data Sheet
CPU
Clock
STR9203-AD00Bg 200MHz
Figure 6-2 is an example of the package marking and pin 1 location for the CNS1101/STR9101 package.
Star Logo
Part Number
Date Code
Mask Version, Software ID Code,

Package Type, and Speed Grade
Figure 6-2. Package Marking and Pin 1 Location

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CNS11XX STR91XX DS V1.4

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Dissemination or disclosure of this proprietary and confidential

Equuleus with 10/100 Phy STR813X CNS213X

Orion Evaluation Board STR91XX-EVB CNS11XX-EVB

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© 2004-2008 by Cavium Networks

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z Other Function Blocks

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SRAM I-cache D-cache I-scratch D-scratch

Figure 1. CNS11XX/STR91XX System Block Diagram

Form Factor 28mmX28mm 27mmX27mm 14mmX14mm 27mmX27mm 28mmX28mm

Parallel Flash 8/16-bit 8/16-bit 8/16-bit 8/16-bit 8/16-bit

DDR SDRAM 16-bit 16/32-bit 16-bit 16/32-bit 16-bit

Ethernet MAC 1x 10/100 2x 10/100/1000 2x 10/100 2x 10/100 1x 10/100/1000

PCI 2.2 Host(66/33MH

GPIO (shared pins) Y (11) Y (21) Y(21) Y (21) Y (11)

16-bit local bus Y Y Y Y Y

JTAG-ICE ARM-like ARM/ARM-like ARM/ARM-like ARM/ARM-like ARM-like

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1.0 Functional Descriptions.................................................................................................................................... 14

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Figure 1-1. ARM-922 Compatible Processor.

1.2 System Bus Architecture

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1.3 Double Data Rate SDRAM Controller (DDRC)

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AHB Slave 3 Memory Control DDR

Figure 1-2. DDR Controller

1.4 Static Memory Controller (SMC)

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AHB Slave (Reg)

Figure 1-3. SMC Controller.

1.5 Generic DMA Engine (GDMA)

1.6 Embedded 4-port Gigabit Switch Engine

1.6.1 Packet Format

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1.6.3 Address Resolution Logic

1.6.3.1 Address Table Format

SA Filter My_MAC VLAN AGE Port_Map MAC Address

The relevant sub-fields are specified as below:

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