MICROPROCESSOR

S A T U R D AY, O C T O B E R 3 , 2 0 0 9 FOLLOWERS

8086 pin diagram description

8086
Pin
diagr
am
And
Expla BLOG ARCHIVE
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n ▼ October (1)

The 8086 8086 pin diagram description

can operate
in two
modes these
ABOUT ME
are the
MICROPROCESSOR
minimum
mode and VIEW MY COMPLETE PROF ILE
maximum
mode .For
minimum
mode, a unique processor system with a single 8086 and for Maximum
mode a multi processor system with more than one 8086.

MN/MX- is an input pin used to select one of this mode .when

MN/MX is high the 8086 operates in minimum mode .In this mode
the 8086 is configured to support small single processor system using a
few devices that the system bus .when MN/MX is low 8086 is
configured to support multiprocessor system.

The AD0-AD15 lines are a 16bit multiplexed addressed or data bus.

During the 1st clock cycle AD0-AD15 are the low order 16Bit adders.
The 8086 has a total of 20 address line ,the upper 4 lines are
multiplexed with the state signal that is A16/S3 , A17/S4 , A18/S5 ,
A19 /S6.During the first clock period of a best cycle the entire 20bit
address is available on these line. During all other clock cycles for
memory and i/o operations AD15-AD0 contain the 16 bit data and
S3,S4,S5,S6 become the status line .S3 and S4 are decoded as follows

A17/S4 A16/S3 Function

0 0 Extra Segment

0 1 Stack Segment

1 0 code or No segment

1 1 Data Segment

There for the 1st clock cycle of an instruction execution the A17/S4 And
A16/S3 pins Specify which Segment register generate the segment
portions of the 8086 address

BHE/S7 is used as best high enable during the 1st click cycle of an
instruction execution .the BHE can be used in conjunction with AD0 to
select the memory

RD is low when the data is read from memory or I/O location .

TEST is an input pin and is only used by the wait instruction .the 8086
enter a wait state after execution of the wait instruction until a low is
Sean on the test pin.

INTR is a maskable interrupt input.

NIM is the non maskable interrupt input.

RESET is the system set reset input signal it terminates all the
activities it clear PSW,IP,DS,SS,ES and the instruction Queue.

DT/R(Data Transmit or receive ):is an o/p signal required in system

that uses the data bus transceiver

ALE is an address latch enable . Is an o/p signal provided by the

8086 and can be used to demultiplexed AD0 to AD15 in to A10 toA15
and D0 to D15.

M/IO is an 8086 output signal to distinguish a memory access and i/o

access.

WR is used by the 8086 for performing write memory or write i/o

operation .

INTA(interrupt acknowledgement signal )

INTA is the interrupt acknowledgment signal

HOLD and HOLDA

a high on the HOLD pin indicates that another master is required to

take over the S/M bus

CLK clock provides the basic timing signals for the 8086 and bus
controls .

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POSTED BY MICROPROCESSOR AT 12:08 AM

38 COMMENTS:

Silvester Philip January 5, 2013 at 6:36 AM

thanks............ very helpful..........thanks
Reply

Replies

deepak kumar September 15, 2013 at 12:23 AM

ur welcome

Reply

sumanth kumar February 23, 2013 at 8:11 AM

Thankyou very much...
Reply

Replies

devanshi soni July 24, 2013 at 11:29 PM

wt thanks its wrong...

sumanth kumar January 11, 2015 at 10:58 PM

wt ? & wre is wrong in this explanation

Reply

jinson kv March 20, 2013 at 6:22 AM

helpfulllllll
Reply

Kundan Roy March 22, 2013 at 11:03 AM

thanks
Reply

sakshi jha April 23, 2013 at 11:16 PM

thanks
Reply

Replies

Ashutosh Shukla April 6, 2014 at 11:14 PM

It's wrong...No thanks Needed at all

Reply

Nadeem Wasiullah April 27, 2013 at 4:11 AM

its very beneficial... thanks alot.....
Reply

Irshad Hussan May 1, 2013 at 8:24 AM

thx
Reply

chandan kumar singh June 21, 2013 at 9:39 AM

thnxxxxx a lot budy
Reply

Deepak Kumar June 21, 2013 at 1:18 PM

nice work................thnx
Reply

Veeraj Poojary July 1, 2013 at 9:54 PM

thank u :)
Reply

Akash kumar July 21, 2013 at 12:17 AM

so easy to understand
Reply

devanshi soni July 24, 2013 at 11:08 PM

This comment has been removed by the author.
Reply

devanshi soni July 24, 2013 at 11:26 PM

there are some mistakes in writing it pls correct it..
i.e. BHE/s7 its BUS HIGH ENABLE
NMI: NON MASKABLE INTERRUPT
ITS NOT HOLDA ITS HLDA

THANKS..
Reply

Sandeep Reddy September 1, 2013 at 3:14 AM

simple and superbzz
Reply

praveen dwivedy September 4, 2013 at 7:57 AM

verry verry thankyou bcz its very es
Reply

Sarang S November 23, 2013 at 7:17 AM

thnx bro.. :D :D
Reply

Pratosh Kumar November 28, 2013 at 11:12 PM

thanxx alot.....
Reply

aziz serkikhel January 24, 2014 at 3:14 AM

thanks alot
Reply

Durga Satish January 28, 2014 at 7:27 AM

thanku friend. but some spellind and notation mistakes are
there. please check it out.
Reply
NAGASREENIVASARAO PUPPALA February 10, 2014 at
8:43 PM
Dear author,
will you please give me the function of status signals: So to S7.
it was given for only S3 and S4.
Reply

bharathi February 13, 2014 at 9:11 AM

why there is two grounds..? what for those two..?
Reply

Replies

vikas chinna February 20, 2014 at 7:27 AM

both the two grounds are same there is no
difference between them

suryateja polina January 21, 2016 at 8:59 AM

No difference in two grounds it is to differentiate 20
pins & 20 pins separately.

suryateja polina January 21, 2016 at 9:00 AM

No difference in two grounds it is to differentiate 20
pins & 20 pins separately.

Reply

vikas chinna February 20, 2014 at 7:24 AM

thanx a lot
Reply

deepu prajapati March 23, 2014 at 3:37 AM

very importent is 8086of microprocesser
Reply

deepu prajapati March 23, 2014 at 3:41 AM

8086 can the operate in two modes these r the minimum
modes and maximum modes.
Reply

eng mohmmad al_junaid April 3, 2014 at 8:59 AM

thanks
Reply

Kulvir Singh Dandiwal April 3, 2014 at 9:35 PM

Incomplete
Reply

Mudasar Ikhlaq May 9, 2014 at 6:18 PM

So very nice explanation
Reply

praveen shirigeri April 16, 2016 at 5:47 PM

Thanks
Reply

Rahulsai October 17, 2016 at 8:20 AM

The image is not clear....and there is some faults in the
description...
Reply

Unknown November 29, 2016 at 7:29 PM

two mistakes:
its nmi not nim
holda to be hlda
bhe is to be bus high enable not best high enable
Reply

Unknown December 27, 2016 at 5:14 AM

thanks you are good person
Reply
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