INDIAN INSTITUTE OF TECHNOLOGY, BOMBAY

ELECTRICAL ENGINEERING DEPARTMENT

EE 618 CMOS Analog Design

Common Data : VDD = 1.8V , Lmin = 0.18µm, µ0N = 350cm2 /V s, µ0P = 100cm2 /V s,
|VT H | = 0.55,tox = 3.8nm, λ = 0.07V −1 , χ = 0.1.

1
 Topic Number 1 : VLSI and MOS Fundamentals

Q–1 You are given a MOS Capacitor whose gate material has a work function of 4.1eV ,
oxide (SiO2 ) thickness is 10nm and whose body consists of p-type Silicon with doping
concentration NA = 10 × 1015 /cm3 . Assume that the dielectric constant of SiO2 is 3.9
and that of Si is 11.68. The electron affinity (E0 − Ec ) of Silicon is 4.05eV , and the
band-gap Ec −Ev of Silicon is 1.1eV (thus, the Fermi level and work function of intrinsic
Silicon is 4.6eV ). The magnitude of the electron charge q is 1.6 × 1019 Coulombs. At
room temperature, assume that for Silicon, ni = 1010 /cm3.

Q–2 Plot the transit frequency of NMOS as a function of VGS for the biasing configuration
shown in figure Fig. 1. Calculate the transit frequency of MOSFET for VGS = 1.5V .
Assume W = 1µm, L = 180nm, CGS = 1.2f F and CGD = 1f F . Given VDS = 1.8V .
Note: transit frequency is defined as the frequency at which small signal current gain of
the device drops to unity while the drain and source are held at ac ground.

+ VDS
−

+ VGS
−

Figure 1: Figure fro Question 2

Q–3 For an NMOS and PMOS device operating in saturation region sketch W/L versus
V GS − VT H if

a) ID is constant
b) gm is constant

Q–4 Plot the following parameters as function of body to source voltage of an NMOS device.

a) Effective channel length of device

b) gmb of NMOS when NMOS is in saturation and gm is constant
c) Drain current when gate and drain are biased at fixed voltage.

2
Q–5 An NMOS device operating in subthreshold region has a ξ = 1.2 (ξ is the nonideaelity
factor of subthreshold conduction). What variation in VGS results in a ten-fold change
in ID ? If ID = 8µA, what is gm ? Solution :

a) For subthreshold conduction we have

VGS1
ID1 = I0 e ξVT

For ID = 10ID , we can write

VGS2
ID2 = I0 e ξVT

Dividing the above equations we can write

VGS1 VGS2
− ξV
0.1 = e ξVT T

Solving for VGS1 − VGS2 ,

VGS1 − VGS2 = −71mV
b) For subthreshold conduction

ID 8µ
gm = = = 256µA/V
ξVT 1.2 × 26mV

3
 Topic Number 2 : Basics of MOS amplifiers

Q–1 For a MOSFET operating in the linear (triode) region (ignore body effect and channel-
length modulation), find an expression for:

(a) the small-signal transconductance gm

(b) the small-signal drain-source output resistance rout

Comment upon your findings. Is it desirable for an amplifier to work in the linear
region? Explain.

Q–2 Consider the simple MOS amplifier shown in Figure 2. Assume λ = 0 and VDD = 1.8V.

VDD

RD

Vout
Vin

Figure 2: Circuit for Q2

Assume that the biasing for the gate side of the MOS is taken care of.

(a) For maximum symmetrical swing in Vout and for a drain current of 0.8 mA, find
the required value of RD .
(b) Calculate the maximum symmetrical output swing, and also the small-signal volt-
age gain in this case.
(c) How would the design values and the voltage gain change, if λ = 0.07 V−1 ?

4
Q–3 Consider the circuit in Figure 3.

VDD

RD

Vout
Vin

RS

Figure 3: Circuit for Q3

If ID = 0.5mA, RD = 1.5kΩ and RS = 300Ω, calculate:

(a) the small-signal voltage gain
(b) the input voltage which will place the NMOS on the border of linear/saturation
region, assuming γ = λ = 0. What would be voltage gain under this condition?
Q–4 Consider the circuit shown in Figure 4. Assume VDD = 1.8V . The amplifier has to be
designed such that ID = 100 µA.

VDD
Vb
M2

Vout
Vin
M1

Figure 4: Circuit for Q4

(a) What should be the bias voltage Vb for the required ID ?

(b) What are the maximum and minimum values of Vout required to keep both M1 and
M2 in saturation?
(c) Calculate the small-signal voltage gain offered by this circuit.

5
Q–5 Consider the circuit shown in Figure 5.

VDD

M2

Vout
Vin
M1

Figure 5: Circuit for Q5

(a) What are the maximum and minimum values of Vout required to keep both M1 and
M2 in saturation?
(b) Obtain an expression for the small-signal voltage gain offered by this circuit.

Q–6 Consider the circuit in Figure 6. Assume VDD = 1.8 V.

VDD
Vb
M2 ,W/L = 2µm/0.5µm

Vout
Vin
M1 ,W/L = 1µm/0.5µm

Figure 6: Circuit for Q6

(a) What should be the bias voltage Vb if this amplifier is to provide a small-signal
voltage gain of 25?
(b) What are the maximum and minimum values of Vout required to keep both M1 and
M2 in saturation?
(c) How would the voltage gain change if M2 were replaced by an ideal current source
that provides the same current as required in part (a)?

Solution:

6
(a) What should be the bias voltage Vb if this amplifier is to provide a small-signal
voltage gain of 25?

Since M2 is a current-source load, it should be in saturation. Also, M1 should

be in saturation. The small-signal gain of the circuit is thus given by

Av = gm1 (ro1 ||ro2 )

Since the λ of both transistors are equal, we have ro1 = ro2 = ro . Thus,
ro
Av = gm1
2
2ID 1
= .
VGS − VT H 2λID
VA
=
VGS − VT H

Substituting the values, we find, VGS − VT H = 0.57V. Thus, the current through
M1 is approximately 0.2mA. The same current should flow through M2 as well.
So we obtain the VGS for M2 to be approx. -1 V. Thus, Vb = VDD − VSG = 0.8 V.
(b) What are the maximum and minimum values of Vout required to keep both M1 and
M2 in saturation?

For M2 to be in saturation, we need VDS < VGS − VT H , i.e Vout − VDD < −0.45 ⇒
Vout < 1.35 V. Thus, the maximum allowed Vout is 1.35 V. For M1 , we need
Vout > VGS − VT H ⇒ Vout > 0.57V. Thus, the minimum allowed Vout is 0.57V.

7
(c) How would the voltage gain change if M2 were replaced by an ideal current source
that provides the same current as required in part (a)?

An ideal current source would have an infinite resistance. Thus, there would be no
ro2 as offered by M2 . The gain expression would thus have reduced to Av = gm ro ,
hence for the same current as in part (a), the gain would now be 25 × 2 = 50.

8
 Topic Number 3 : Cascode Amplifiers

Q–1 Design Cascode amplifier (Fig. 7 ) for a gain AV > −50V /V , V outmax of 1.3V, V outmin
of 0.4V. The slew rate with 5pF load should be at least 10V /µsec. Supply voltage is
1.8V and maximum power dissipation is 200µW .

VDD

Vbp

Vbn2

Cbig
Vin

Rbig

Vbn1

Figure 7: Figure for Question 1

9
Q–2 Calculate the transconductance and output resistance of the cascode circuit shown in
Fig. 8 . Assume both transistors are in saturation and gm = 2mA/V and r0 = 20kΩ.
Ignore body effect. Repeat the calculation including body effect and observe the per-
centage of error.

VDD

Vbn2

Cbig
Vin

Rbig

Vbn1

Figure 8: Figure for Question 2

Q–3 Calculate the output impedance of the circuit shown in Fig. 9 and state the advantages
and disadvantages of the circuit.

10
 VDD

Vbn2 +
A
−

Cbig
Vin

Rbig

Vbn1

Figure 9: Figure for Question 3

Q–4 Find the output resistance for the active cascode circuit shown in Fig. 10 excluding
resistor R. What is the maximum allowable output swing?

VDD

R
Ibias

Vin

Figure 10: Figure for Question 4

Q–5 Determine input resistance, transconductance, output resistance and maximum open
circuit voltage gain of cascode if ID = 300µA, W/L = 200.

11
 VDD

Vbn

Vin

Figure 11: Figure for Question 5

Q–6 Consider the cascode amplifier shown in Fig. 12. Given gm1 = 1mA/V , gm2 =
0.5mA/V , calculate the gain of the amplifier and the swing on node X. Ignore channel
length modulation and body effect.

12
 VDD

RD

Vbn gm2

Vin
gm1

Figure 12: Figure for Question 6

Solution The gain of the amplifier is given by gm1 ∗ Rout

Rout = gm2 ro1 ro2 ||RD ∼ RD
Hence the gain is approximately 10. The net impedance from node X to ground is
ro1||(1/gm2) ∼ (1/gm2 ) which is about 2kΩ. The current through M1 is given by gm1 vin .
Hence the swing at node X is given by
VX = vin × 1m × 2k
VX = 2 × vin
Note that here the cascode transistor reduces the swing on node X thus providing
shielding between the output and the input.This shielding property is important in
high gain and large signal amplifiers.

13
 Topic Number 4 : Differential Amplifier

Q–1 Calculate the unloaded voltage gain Vo /Vi and output resistance of the circuit in Fig.
13 Assume (W/L)N = 50, (W/L)P = 1, Itail = 200µA. Ignore body effect.

VDD

Vin + Vbias Vbias

Itail

Figure 13: Figure for Question 1

Q–2 Derive the expression for VIC (max) and VIC (min) for the p-channel input differential
amplifier.

Q–3 Design the current and W/L values of the current mirror load differential amplifier to
satisfy the following specification VDD = −VSS = 0.9V , slew rate > 10V /µs, CL = 3pF ,
f3dB ≥ 400KHz, and a small signal gain of 60V /V . −0.5V ≥ ICMR ≥ 0.5V , and
Pdiss ≤ 0.2mW .

Q–4 For a folded cascode current mirror differential amplifier shown in Fig. 14 assume
W/L = 200µm/1µm for all the transistors.

a) Find the maximum input common mode voltage VICmax , and the minimum com-
mon mode voltage VICmin .
b) What is the ICMR?
c) Find the small signal gain Vo /Vi if Vi = V1 − V2 .
d) If a 20pF capacitor is connected from the output to ground, what is the −3dB
frequency for Vo (jω)/Vi (jω) in hertz

14
 Vout

Vi1 Vi2

100µA

Figure 14: Figure for Question 4

Load

Vip Vin
Vip Vin

Load

Figure 15: Figure for Question 5

Q–5 Consider the NMOS and PMOS input stages as shown in Fig. 15. Given that VDD =
1.8V , VGSp = VGSn = 0.6V , VDSsatn = VDSsatp = 0.2V ans the saturation voltages of the
current sources is also VDSsat determine

a) The common input range of the Pchannel input pair

b) The common input range of the Nchannel input pair
c) The common input range of the complementary input stage shown in Fig. 16

Solution: The common mode input range for the Pchannel input stage is given by
0 < Vcommon < VDD − VDSsat − VGSp Thus the ICMR is 0 < Vcommon < 1V .
The common mode input range for the Nchannel input stage is given by
VDSsat + VGSn < Vcommon < VDD Thus the ICMR is 0.8 < Vcommon < 1.8

15
 Vbn
Vip Vin
Vout
Vip Vin

Figure 16: Figure for Question 5

For the complementary input stage the ICMR is rail to rail, i.e. 0 to 1.8V , due to the
overlap of the two ICMR’s of the complementary stage.

16
 Topic Number 5 : Current sources and References

Q–1 Design a simple MOS current mirror of the type shown in Fig. 17 to meet the following
constraints.

VDD

Iin

Iout

Vin M1 M2 Vo

Figure 17: Figure for Question 1

a) Transistor M2 must operate in the active region for values of Vout to within 0.3
from ground.
b) The output current must be 30µA
c) The output current must change less than 5% for change in output voltage of 0.4V

Make M1 and M2 identical. You are to minimize the total device area within given
constraints. The device area is the total gate area (W × L). Assume Xd = 0.

Q–2 Design a voltage reference using the Beta-multiplier. Using spice simulation show the
temperature performance of your design, by plotting reference voltage vs temperature

Q–3 Consider the circuit of Fig. 18 assuming (W/L)1−3 = 15µm/0.18µm, IREF = 0.1mA,
and γ = 0.

a) Determine Vb ias such that VX = VY

b) If Vb deviates from the value calculated by 70mV, what is the mismatch between
Iout and IREF ?

17
 VDD
P
Iref
Iout
Vbias
M3
X
Y

VIN M1 M2

Figure 18: Figure for Question 3

c) If the circuit fed by cascode current source changes VP by 0.3V by how much does
VY change?

Q–4 Consider the circuit of Fig. 19 with (W/L)1−5 = 50µm/0.5µm and ISS = 0.5mA
VDD

M3 M4

F Vout

1.5V 1.5V
M1 M2

Vbias

Figure 19: Figure for Question 4

18
 a) Calculate the deviation of Vout from VF if |VT H3 | is 1mV less than |VT H4 |
b) Determine the CMRR of the amplifier

Q–5 Calculate the quiscent curent and temperature coefficient of the circuit shown in Fig.
20 where (W/L)1 = 25, VDD = 1.8V and R = 100kΩ. The resistor has a temperature
coefficient of 1400ppm/o C. α( dV
dT
t
= 2 × 10−3 V /oC.

VDD

I2
I1

Figure 20: Figure for Question 6

Solution :
We have

s
VT 1 1 1 2VT 1 1
I2 = + 2
+ +
R βR R β1 R βR2

19
 β1 = µN Cox (W/L)
= 7.9 × 10−3
β1 R = 795
β1 R2 = 79.5 × 106

Hence

I2 = 5.8µA

The temperature coefficient is given by

−α 1 dR
T CF = −
VT R dT
−2 × 10−3
= − 1400 × 10−6 /o C
0.55
= 5036ppm/o C

20
 Topic Number 6 : Frequency Response

Q–1 Use the Miller approximation to calculate the −3dB frequency of the small signal voltage
gain of a MOS common source stage as shown in Fig. 21, using Rs = 20kΩ, RL =
10kΩ, ID = 0.5mA, and the following NMOS transistor data. Ignore channel-length
modulation.
W = 50µm, L = 1um, Cgd = 5f F .

RL

VO
Rs
Vi

Figure 21: Figure for question 1

Q–2 Calculate the −3dB frequency of the circuit in Fig. 22 assuming the following parameter
values.
VDD

RL1 RL2

Vo

M1 M2
Vi

Figure 22: Figure for question 2

Rs = 6kΩ, RL1 = 8kΩ, RL2 = 6kΩ, Cgs1 = 3pF , Cgs2 = 8pF , Cgd1 = Cgd2 = 1.5pF ,
Cdb1 = Cdb2 = 2.5pF , gm1 = 4mA/V , gm2 = 8mA/V .
Assume Cgb ||Cgs ∼ Cgs .

21
 IIN
IOU T

Vi

Figure 23: Figure for question 3

Q–3 Use zero value time constant method to estimate the small signal dominant pole for the
current gain of the MOS cascode current mirror shown in Fig. 23. Assume an input ac
current source in parallel with IIN and a zero load impedance with Vout = Vgs3 + Vgs4.
The bias current IIN = 100µA. Compare your answer with the fT value of the devices.

Device parameters are W = 8µm, L = 1µm. Ignore channel length modulation and
substrate effect. Given Cgs = 35f F , Cgd = 2f F , Csb = Cdb = 7f F .
Q–4 The ac schematics of a common source stage and a common source common gate(cascode)
stage are shown below, with Rs = 6kΩ and RL = 12kΩ. Using the transistor and oper-
ating point data as ID = 0.5mA. Given Cgs1 = 3pF , Cgs2 = 8pF , Cgd1 = Cgd2 = 1.5pF ,
Cdb1 = Cdb2 = 2.5pF , gm1 = 4mA/V , gm2 = 8mA/V .
Assume Cgb ||Cgs ∼ Cgs .
M2
VO
VO
RS RS RL
Vi M1 RL Vi M1

Figure 24: Figure for question 4

a) Calculate the low frequency small signal voltage fain for each circuit
b) Use the zero value time constant method to calculate and compare the −3dB
frequencies of teh gains of the two circuits

22
 c) Estimate the 10% to 90% rise times for each circuit for a small step input and
sketch the output voltage waeform over 0 to 300ms for a 1mV step input

Q–5 Find an expression for the transfer function of an NMOS source follower amplifier (Fig.
25). Ignore body effect.

VDD

Vin Rs X
Y Vout
CL

Figure 25: Figure for Question 6

Solution : Consider the ac equivalent of the source followe as shown in Fig. 26.
Applying KCL at the outout node we can write

Vin Rs

CGD CGS
V1 gm V1

Vout

CL

Figure 26: Figure for Question 6

V1 CGS s + gm V1 = Vout CL s
Thus
CL s
V1 = Vout
gm + CGS s
Applying KVL for the input section we can write

Vin = Rs [V1 CGS s + (V1 + Vout )CGD s] + V1 + Vout

23
From above two equations we can write the transfer function as
Vout gm + CGS s
(s) =
V in Rs (CGS CL + CGS CGD + CGD CL )s2 + (gm Rs CGD + CL + CGS )s + gm

Note : Note that the transfer function has a zero. Thus the estimation of bandwidth
cannot be done using the dominant pole approximation. i.e. the zero value time constant
technique cannot be used for circuits with zero’s in the transfer function. Such circuits
can be identified by inspecting for a direct capacitive path from the input to output. The
pole value estimated by the zero value technique will be correct but will not correspond
to the bandwidth of the circuit due to the zero.

24
 Topic Number 7 : Opamps

Q–1 Consider the amplifier in Fig. 27, where W/L of the PMOS transistors are 20µm/1µm
and that of NMOS are 10µm/1µm. Given Iref = 200µA and I = 20µA.

VDD

Iref I

M1 M2 CA
Vin
B
A

Vbias CB
M3 M4

Figure 27: Figure for Question 1

a) Calculate the poles at nodes A and B, if CA = 0.5pF and CB = 0.1pF . Also

calculate the phase margine for unity gain feedback.
b) How will you redesign the amplifier to have a phase margine of 55o?
c) Calculate the slew rate of the opamp for b part only.

Solution :

a) The pole at node A is given by

1
PA = CA (ro2 ||ro3
Here

25
 ro = λI1D
1
ro2 = ro3 = 0.07×100µ = 143kΩ
Threfore PA = 27.97Mrad/sec
The pole at node B is given by
PB = gCm4
√B √
2ID µP Cox (W/L) 2×20µ×90µ×20
PB = CB
P B = 0.1p
PB = 2.68Grad/sec
The net gain of the amplifier is given by
Av = Av1 Av2
Av = pgm2 (ro2 ||ro3 ) × 1
Av = √ 2ID µP Cox (W/L) × 71.5k
Av = 2 × 100µ × 90µ × 20 × 71.5k
Av = 42.9 = 32.65dB
Next we find the gain at the second pole frequency as follows.
A(PB ) = 32.65 − [20log(PB /PA )]
A(PB ) = 32.65 − [20log(2.68G/27.97M)]
A(PB ) = −7dB
Hence we can conclude that the gain touches 0dB at a slope of 20dB/decade. Hence
we calculate the unity gain frequency as
ωunity
20log( 27.97M = 32.65
Hence
ωunity = 42.9 × 27.97M
ωunity = 1.2Grad/sec
Now we can calculate the phase margin as
ω ω
φ = −tan−1 ( unityPA
− tan−1 ( unity
PB
−1 1.2G −1 1.2G
φ = −tan ( 27.97M − tan ( 2.68G
φ = −112.78o
Therefore the phase margin is
P M = 180 − φ = 67.22o

b) To redesign the amplifier for a phase margin of 55o , we first find the desired position
of PB and the corresponding value of gm4 . Since PM=55o , we have φ = 125o . We
can write
1.2G
−125 = − − tan−1 ( 27.97M − tan−1 ( 1.2G
PB
−36.33 = −tan−1 ( 1.2G
PB
PB = 1.63Grad/sec
PB = gCm4
B
gm4 = p
1.63G × 0.1p = 163µS
gm4 = 2ID µP Cox (W/L)

26
 Therefore
ID = 7.4µA
will give the required phase margin.

Q–2 An amplifier has forward gain of A = 500 with two poles at P1 and P2 frequencies.

a) For P1 = 1MHz, find the phase margine with unity gain feedback if
i) P2 = P1
ii) P2 = 2P1
iii) P2 = 4P1
b) If the unity gain closed loop amplifier exhibits a frequency peaking of 60% near
the gain crossover frequency, then what is the phase margine?

Q–3 Consider the circuit shown in Fig. 28

VDD

M3 M4 M9

M11
Vbias3
M7 M8 M10
Rz CC
Vo
Vbias2
M5 M6

M1 M2
Vin

Vbias1
M13 M12

Figure 28: Figure for Question 3

a) What is the advantage of using transistors M9 and M10 ?

27
 b) Determine the ICMR of the opamp
c) Derive the maximum output swing
d) Derive the value of Rz needed for a phase margine of 60o at unity gain feedback
when Cc = 1pF
e) Determine the slew rate of the opamp

Q–4 Consider the opamp shown in Fig. 29

VDD

WP WP WP WP

WPP

VBp VBn
W P /2 W N/2
WN WN
Vin
W NN

RL CL

WN WN

Figure 29: Figure for Question 4

a) Calculate the gain of opamp if WP P = WP and WN N = WN for

i) RL = 1Ω
ii) RL = 10kΩ
iii) RL = 100MΩ
b) Calculate the output swing of the opamp
c) Calculate slew rate if CL = 1pF and RL → ∞
i) WP P = WP and WN N = WN
ii) WP P = 10WP and WN N = 10WN

Q–5 Design a PMOS input stage two stage opamp. The specifications to be met are
VDD = 1.8V , GBW = 10MHz, CL = 1pF , Ao > 2000V /V , Slew rate > 10V /µs, ICMR
0.3V to 1.5V, Pdiss ≤ 2mW
Assume gm1 = gm2 and stability needed is P M = 60o .

28
Q–6 Consider the amplifier shown in Fig. 30 employing a cascode stage ans a CS amplifier.
Assume node A is dominant. Sketch the frequency response and explain how the circuit
can be compensated.

VDD

A B Vo
CA
VB2

Vin

Figure 30: Figure for Question 6

29
a) If the circuit is modified as shown in Fig. 31, then sketch the frequency response
for
VDD

Cc
A B Vo
VB2

Vin

Figure 31: Figure for Question 6

i) CC = CA ii) CC = 2CA and iii) CC = 10CA

30
b) If the circuit is modified as shown in Fig. 32, then sketch the frequency response
for CC = CA and

VDD

Cc Rz
A B Vo
VB2

Vin

Figure 32: Figure for Question 6

i) Rz = 1/gm5 ii) Rz = 10/gm5 and iii) Rz = 1/10gm5

31
 Topic Number 8 : Noise

Q–1 Consider circuits shown in Fig. 33. Which of these source degenerated circuits have
higher input referred noise voltage, and by what factor?
VDD VDD

RL RL RL RL

Vout
Vout
M1 M2 M1 M2

Vin Vin

RS RS 2RS

M3
Vbias Vbias
M3 M4

(a) (b)

Figure 33: Source Degenerated Circuits

√
Q–2 Design circuit in Fig. 34 for an input referred thermal noise voltage of 5nV / Hz and
maximum output swing. Assume ID1 = 0.4mA,(W/L)1 = (W/L)2 and VDS 1 = VDS 2 .

VDD

RL
Ibias

Vout

M1 Vbias

Vin
M2 M3
Co

Figure 34: Common Gate Stage

32
Q–3 The circuit in Fig. 35 is designed with (W/L)1 =40/0.4 and ID1 =0.4mA. If an output
swing of 2 V is required, estimate the dimension of M2 and M4 , such that the input
referred thermal noise current is minimum.
VDD

M5 M4
Ibias
Vout
I2
M1 Vbias

Vin
M2 M3
Co

Figure 35: Common Gate Stage

Q–4 Assume (W/L)1 =(40/0.4), ID1 =0.2mA for Fig. 36. If the contribution of M2 to the
input referred noise voltage must be one-fifth of that of M1 , what is the maximum
output voltage swing of the amplifier?

VDD VDD

M2 Vbias M1 Vin

Vout Vout

M1 Vin M2 Vbias

(a) (b)

Figure 36: (a) Common Source Amplifier (b) Source Follower

Q–5 Consider the circuit of Fig. 37 - Fig. 38. To decrease overall noise of circuit,

(a) Whether transconductance of M2 should be kept high or low in two cases of Fig. 37?

33
 VDD VDD

M2 Vbias M2

Vout Vout

M1 Vin M1 Vin

(a) (b)

Figure 37: (a) Common Source Amplifier (b) Inverter

(b) Whether RS should be minimized to reduce noise in Fig. 38?

VDD

RL

Vout

M1 Vin

Rs

Figure 38: Source Degenerated Stage

Q–6 Consider input stage of op-amp shown in Fig. 39,

(a) Should transconductance of M1 be decreased to decrease input-referred thermal

noise?

(b) How sizing of M1 and M3 should be done to reduce flicker noise?

Solution: Part (a)

Step 1: Find gains from each noise source to the output node.

34
 VDD
Vbias

Vin+ M1 M2 Vin-

Vout

M3 M4

Figure 39: Input stage of CMOS Opamp

VDD
Vn5
Vbias

Vn1 Vn2
Vin+ M1 M2 Vin-

Vout
Vn3 Vn4
M3 M4

Figure 40: Opamp input MOSFET noise sources

i) Gain from Vn1 and Vn2 : | VVn1

no
| = | VVn2
no
| = gm1 Ro
ii) Gain from Vn1 and Vn2 : | VVn3
no
| = | VVn4
no
| = gm3 Ro
gm5
iii) Gain from Vn5 to output: | VVn5
no
| = 2g m3
(This gain factor is relatively small compared to the others, so, it could be ignored
for further calculations.)

Step 2: Using the gain factors, find the output noise.

2
Vno (f ) = 2(gm1 Ro )2 Vn1
2
(f ) + 2(gm3 Ro )2 Vn3
2
(f )

35
 Step 3: Find input referred thermal noise voltage by dividing output noise value with
gain gm1 Ro which results in
 2
2 2 2 gm3
Vneq (f ) = 2Vn1 (f ) + 2Vn3 (f ) (1)
gm1
1
where, Vni2 (f ) = 4kT ( 23 )( gmi )

       
2 16 1 16 gm3
⇒ Vneq (f ) = kT 2
+ kT 2
3 gm1 3 gm1

Thus, noise contributed by two pair of transistors is inversely proportional to the

transconductance gm1 . Therefore, gm1 should be made as large as possible to mini-
mize thermal noise contrinution.
Solution: Part (b)
Step 1: In output noise equation, substitute transconductance with transistor size as pa-
rameter.
q
Substituting gmi = 2µi Cox ( W ) I in (1),
L i Di
h i
⇒ Vni2 (f ) = 2Vn1
2 2
(f ) + 2Vn3 (f ) (W/L) 3 µn
(W/L)1 µp

Ki
Step 2: Substitute noise sources with spectral density Vni2 (f ) = Wi Li Cox f
.
   
2 K1 µn K3 L1
⇒ Vni2 (f ) = +
Cox f W1 L1 µp W1 L23

Thus, from the input-referred flicker noise equation,

(i) Taking L3 longer greatly helps due to inverse squared relationship in the second term.

(ii) The input noise is independent of W3 , and therefore it could be made large to maxi-
mize signal swing at the output.

(iii) Taking W1 wider also helps to minimize 1/f noise.

(iv) Taking L1 longer increases the noise because the second term is domnant (due to
µn > µp . Thus, large L1 decreases the input-referred noise of p-channel drive transistors
which are not the dominant noise source, but, increases the input-referred noise of n-channel
load transistors, which are dominant noise sources.

36
 Topic Number 9 : Oscillators

Q–1 Consider a variable delay inverter with delay td = t0 + t1 × Vc , where Vc is a control

voltage to adjust the delay. If this inverter is used to make a three stage ring oscillator,
find the oscillation frequency with respect to the control voltage Vc considering t0 >> t1 .
Q–2 Consider a three stage ring oscillator shown in Fig. 41. The varactor capacitance is
given by C = Co + αVc .

VDD

RD RD RD

VC

Figure 41: Figure for Question 2

a) Derive an expression for small signal open loop gain of the circuit in terms of Vc .
b) From the above expression derive the frequency of oscillation

Q–3 A three stage ring oscillator is made with inverters that have asymmetric delay for the
rising and falling edge, due to difference in channel mobilities of NMOS and PMOS
devices.
Given td(0−1) = 1ns and td(1−0) = 0.8ns. Will this circuit oscillate. If yes calculate the
frequency of oscillation and the duty cycle of the oscillator output.
Q–4 Consider the small signal equivalent of an oscillator as shown in Fig. 42. The inductor
has a series resistance of rs . Estimate the maximum permissible value of rs in terms of
L, C1 , C2 and gm , for sustained oscillations.
C0
Q–5 Consider the oscillator shown in Fig. 43. Capacitance of the varactor is given by 1+α/Vc
.
α << Vc

37
 L

C2
C1

Figure 42: Figure for Question 4

VDD

VC

Figure 43: Figure for Question 5

a) Estimate the VCO gain KV CO .

b) If a sinusoidal signal (Vm × cos(ωm t)) overrides over the DC control voltage, deter-
mine the frequency components at the output. Given Vm << Vc .

Q–6 Consider the oscillator shown in Fig. 44. Treating the transistors to be ideal switches
(the output voltage has only fundamental harmonic), sketch the spectrum of the current
through the inductor, capacitor and resistor.
Solution : Given sinusoidal output voltage, fundamental component of the current
through inductor and capacitor are equal and out of phase. The current through the
transistors is square. This square current will have all odd harmonics. The LC tank
together presents open circuit for the fundamental frequency. Hence this current flows
through the resistor. The higher harmonics flow through the capacitor as it presents
a low impedance as compared to the inductor and resistor. The bias current for the
transistor flows only through the inductor as it has zero DC resistance.
Fig. 45 shows the sketch spectrum of the currents through the inductor, capacitor and
resistor.

38
 VDD

R L L R

C C

Figure 44: Figure for Question 6

freq

freq

freq
f 2f 3f 4f 5f

Figure 45: Solution to Question 6 : Spectra of currents through R L and C

39