module valid_ack_synchronizer

#(

parameter DATA_WIDTH = 32

)(

input wire clk_in,

input wire rstn_in,

input wire [DATA_WIDTH-1 : 1] data_in,

input wire clk_out,

input wire rstn_out,

output wire [DATA_WIDTH-1:1] data_out

);

reg

always @ (posedge clk_in, negedge rstn_in)

begin

if(~rstn_in)

begin

req_in <= 1'b0;

data_in_r <= {DATA_WIDTH{1'b0}};

end

else

begin

data_in_r <= data_in;

if(data_in_r != data_in && ack_out_rr == req_in)

req_in <= ~req_in;

 end

end

double_flop_sync

.clk_in(clk_in),

.rstn_in(rstn_in),

.data_in(req_in),

.clk_out(clk_out),

.rstn_out(rstn_out),

.data_out(req_in_rr)

);

endmodule