Embedded System Design (EEMS140)

Dr. Prasanna Kumar Misra

IIIT Allahabad
Outline

1. Review of Microprocessors

2. Embedded system design challenges

3. Design Methodologies (ASIC, FPGA)

4. Analog and Digital IP

5. ARM processors and instruction set

6. Conclusion and Summary

Classification

Following parameters are used to classify the microprocessors

based on its applications.
• Performance
• Cost
• Power consumption

Microprocessor

General Purpose Application Specific

Classification

General Purpose
•Die size = 112 mm2
• 90 nm Process Technology
• 16 kB L1 Cache, 1 MB L2
Cache
• 125000000 transistors

Intel Pentium 4 Processor [ISSCC 2004]

Classification

Application Specific
• Die size = 2.25 mm2
• Core size = 1 mm2
• 180 nm Process Technology
• No Cache memory (Used
only registers)
• Clock Freq = 20 MHz

Network Processor [IITK-2011]

process the incoming IPv4 packet headers of 20 bytes
Classification

Following parameters are used to classify the microprocessors

based on its design.

• Semiconductor Technology (CMOS/BiCMOS)

• Technology node (500/350/250/180/130/90/65/45/32/22 nm)
• Data Width (8bit/16 bit/32 bit/64 bit)
• Instruction set (CISC or RISC)

CISC: Complex Instruction Set Computer

RISC: Reduced Instruction Set Computer
CISC and RISC

RISC minimizes CISC minimizes

Example

1 2 3 4 5

1
2
CISC: MULT 2:3, 5:2
3
Main Memory
4
RISC: LOAD A, 2:3 5
LOAD B, 5:2
MUL A, B
STR 2:3, A
Register

Execution
+-×
Learning Approach

Microprocessor, DSP
Systems Microcontroller

Sub-Systems ALU, Control Logic, PLL

Power Supply, HW-IP

Basic Circuit Blocks Amplifier, Oscillator, Memory

Logic Gates (NAND, NOR,..)

Devices MOSFETs (NMOS, PMOS),

BJTs, R, L, C
Basic
Semiconductor Physics, Mathematics
Foundation
 System Architecture Verilog
Design CAD Circuits and Systems
Circuit Design SPICE

Device Models + Design Rules

Device Physics Device Simulations,

Technology CAD Modelling, Characterization
Devices
Process Technology Process Simulations,
Fabrication
Intel 4004 Microprocessor

• First µP (1971)
• 10 µm process technology
• 2300 transistors
• 400-800 KHz
• 4- bit word size
• 16 pin DIP package

[1] WILLIAM ASPRAY, “The Intel 4004 Microprocessor: What Constituted Invention”
IEEE Annals of the History of Computing, Vol. 19, No. 3, 1997, pp.4-15.
Intel 8008 Microprocessor

•1972
• 10 µm process technology
• 3500 transistors
• 400-800 KHz
• 8- bit word size
• 18 pin DIP package
Intel 8080 Microprocessor

•1974
• 6 µm process technology
• 4500 transistors
• 2 MHz
• 8- bit word size
• 40 pin DIP package
Intel 8086 Microprocessor

•1979
• 3 µm process technology
• 29000 transistors
• 5-10 MHz
• 16- bit word size
• 40 pin DIP package

* X86 Instruction set architecture

* 20-bit adddresses (220 = 1 MB memory locations
Intel 80286 Microprocessor

•1982
• 1.5 µm process technology
• 134000 transistors
• 6-12 MHz
• 16- bit word size
• 68 pin DIP package

* Virtual Memory
* 20-bit adddresses (220 = 1 MB memory locations
Intel 80386 Microprocessor
•1985
• 1.5 µm process technology
• 275000 transistors
• 16-33 MHz
• 32- bit word size
• L1 Cache (off chip)
• 100 pin PGA
Intel 80486 Microprocessor

•1989
• 1 µm process technology
• 1200000 transistors
• 25-100 MHz
• 32- bit word size
• L1 (on chip) + L2 (off chip)
• 168 pin PGA
Pentium Processor

• Pentium -1993 (800 nm Process technology)

• Pentium II (350 nm Process technology)
• Pentium III (250 nm Process technology)
• Pentium IV- 2001(180 nm Process technology)
• Xeon-2003 (90 nm, Strained silicon)
• Dual core xeon -2005 (65 nm, Strained silicon, 3.5 GHz, 8-copper layer)
• Quad core xeon- 2007 (45 nm, High-K metal gate)
• Xeon 8 core -2009 (32 nm, High-K metal gate, 64-bit), 9-copper layer, L3)
• Processor with trigate devices - 2011(22 nm, L3)

* In Pentium processors separate instruction and data cache (on chip)

Moore’s and Amdahl’s law

Moore’s Law: It states that the number of transistors on an

integrated circuit doubles every 1-2 years.

Amdahl’s Law: It states that if one enhances a fraction (f) of a

computation by a speed up (s), then the overall speedup is

• If f is small optimizations have little effect.

• If s goes very high, speedup = 1/(1-f).
Performance gap (Microprocessor and Memory)

• Microprocessor performance has been improving nearly

60% per year.
• Memory Performance (access time) however has been
improving nearly 10% per year.
• The resulting gap between microprocessor and memory
performance forced microprocessor designs toward complex
and power hungry architectures. This is due to introduction of
large cache hierarchies to hide main memory latency.
• Average time to access memory
IBM z196 Processor

45 nm SOI CMOS Technology

512 mm2
5.2 GHz speed
1.4 Billion transistors
1.5 MB L2 Cache,24 MB L3 cache

IBM z196 Processor [ICICDT-2011]

Power7 Processor

IBM Power7 Processor [ICICDT 2010] Core Area [ICICDT 2010]

45 nm SOI CMOS Technology
567 mm2
4 GHz speed
1.2 Billion transistors
256 kB L2 Cache and 32 MB L3 cache
Power8 Processor

IBM Power8 Processor [ISSCC 2014]

22 nm SOI CMOS Technology
649 mm2
4.8 GHz clock
4.2 Billion transistors
256 kB L2 Cache and 32 MB L3 cache
Memory Hierarchy

• A cache hit is a state in which data requested for processing by

a component/ application is found in the cache memory.
• It is a faster method of delivering data to the processor.
• A cache hit occurs when an application/software requests data.

Registers
Cache (L1,L2,L3)
Main Memory
Integration density Flash Memory Speed

Hard drive
Hardware/Software Interface

Software

Instruction Set Architecture

Hardware

Instruction Set Architecture provides a well defined hardware/software

interface that has complete collection of instructions understood by CPU.

Applications

Operating System
Compiler Firmware

Instruction Set Architecture

CPU Memory I/O
Digital Circuit
Transistors (NMOS, PMOS)
Basic Components
S G D S G D

+++++ -------
------ +++++
N+ N+ P+ P+

P Substrate n Substrate

NMOS PMOS

C B E B C

N+
P

NPN Bipolar Junction Transistor

Thank You