GAL®22V10 Device Datasheet

September 2010

All Devices Discontinued!

Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.

The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.

Product Line Ordering Part Number Product Status Reference PCN

GAL22V10D-7LP
PCN#09-10
GAL22V10D-7LPN
GAL22V10D-10LP
GAL22V10D-10LPN
GAL22V10D-15LP
PCN#13-10
GAL22V10D-15LPN
GAL22V10D-25LP
GAL22V10D-25LPN
GAL22V10D-7LPI
PCN#09-10
GAL22V10D-7LPNI
GAL22V10D-10LPI
GAL22V10D-10LPNI
GAL22V10D-15LPI
GAL22V10D-15LPNI
GAL22V10D-20LPI
GAL22V10D GAL22V10D-20LPNI Discontinued
GAL22V10D-25LPI
PCN#13-10
GAL22V10D-25LPNI
GAL22V10D-10QP
GAL22V10D-10QPN
GAL22V10D-15QP
GAL22V10D-15QPN
GAL22V10D-25QP
GAL22V10D-25QPN
GAL22V10D-10LS
GAL22V10D-15LS PCN#06-07
GAL22V10D-25LS
GAL22V10D-4LJ
PCN#09-10
GAL22V10D-4LJN
GAL22V10D-5LJ
PCN#13-10
GAL22V10D-5LJN

5555 N.E. Moore Ct.  Hillsboro, Oregon 97124-6421  Phone (503) 268-8000  FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line Ordering Part Number Product Status Reference PCN
GAL22V10D-7LJ
GAL22V10D-7LJN
GAL22V10D-10LJ
GAL22V10D-10LJN
PCN#13-10
GAL22V10D-15LJ
GAL22V10D-15LJN
GAL22V10D-25LJ
GAL22V10D-25LJN
GAL22V10D-7LJI
GAL22V10D-7LJNI
PCN#09-10
GAL22V10D-10LJI
GAL22V10D GAL22V10D-10LJNI
Discontinued
(Cont’d) GAL22V10D-15LJI
GAL22V10D-15LJNI
GAL22V10D-20LJI
GAL22V10D-20LJNI
GAL22V10D-25LJI
GAL22V10D-25LJNI
PCN#13-10
GAL22V10D-10QJ
GAL22V10D-10QJN
GAL22V10D-15QJ
GAL22V10D-15QJN
GAL22V10D-25QJ
GAL22V10D-25QJN

5555 N.E. Moore Ct.  Hillsboro, Oregon 97124-6421  Phone (503) 268-8000  FAX (503) 268-8347
Internet: http://www.latticesemi.com
 ree Specifications GAL22V10
Lead-Fage
P a c k ns
GAL22V10
Optio le! High Performance E2CMOS PLD
b
Availa Generic Array Logic™

Features Functional Block Diagram

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY I/CLK
RESET

— 4 ns Maximum Propagation Delay 8

— Fmax = 250 MHz OLMC I/O/Q
— 3.5 ns Maximum from Clock Input to Data Output I

— UltraMOS® Advanced CMOS Technology 10

OLMC I/O/Q
• ACTIVE PULL-UPS ON ALL PINS I

N ES
• COMPATIBLE WITH STANDARD 22V10 DEVICES 12

— Fully Function/Fuse-Map/Parametric Compatible I

OLMC I/O/Q
with Bipolar and UVCMOS 22V10 Devices

PROGRAMMABLE
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR

ED
14
I OLMC I/O/Q
— 90mA Typical Icc on Low Power Device

AND-ARRAY
— 45mA Typical Icc on Quarter Power Device

(132X44)
16

N VIC
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
I

I
16
OLMC

OLMC
I/O/Q

I/O/Q

U
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention I 14
OLMC I/O/Q
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs I
C DE
12
OLMC
• PRELOAD AND POWER-ON RESET OF REGISTERS I/O/Q

— 100% Functional Testability

I
TI
10
• APPLICATIONS INCLUDE: OLMC I/O/Q
— DMA Control
— State Machine Control I
8
— High Speed Graphics Processing OLMC I/O/Q
— Standard Logic Speed Upgrade I
D LL

PRESET
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS Pin Configuration
O

ESCRIPTION PLCC
I/CLK

I/O/Q

I/O/Q

Description
Vcc
NC

DIP
I
I

4 2 28 26
A

The GAL22V10, at 4ns maximum propagation delay time, combines I 5 25 I/O/Q

I/CLK 1 24 Vcc
a high performance CMOS process with Electrically Erasable (E2) I I/O/Q
I/O/Q
floating gate technology to provide the highest performance avail- I 7 23 I/O/Q I
NC
GAL22V10
able of any 22V10 device on the market. CMOS circuitry allows Top View
NC I I/O/Q
IS

I 9 21 I/O/Q
the GAL22V10 to consume much less power when compared to I GAL I/O/Q
I
bipolar 22V10 devices. E2 technology offers high speed (<100ms) I/O/Q
I I/O/Q
erase times, providing the ability to reprogram or reconfigure the I 11
12 14 16 18
19 I/O/Q 22V10
device quickly and efficiently. I 6 I/O/Q
I
I

NC
GND

I/O/Q
I/O/Q

I 18 I/O/Q
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by SOIC I I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q

the user. The GAL22V10 is fully function/fuse map/parametric com-

Vcc

I I/O/Q
patible with standard bipolar and CMOS 22V10 devices.
I

I I/O/Q
18
24

13

Unique test circuitry and reprogrammable cells allow complete AC, I I/O/Q
GAL22V10
DC, and functional testing during manufacture. As a result, Lat- Top View GND 12 13 I
tice Semiconductor delivers 100% field programmability and func-
12
6
1

tionality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.
I/CLK

GND
I
I
I
I
I
I
I
I
I
I

Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

22v10_12 1
 Specifications GAL22V10
GAL22V10 Ordering Information
Conventional Packaging
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
4 2.5 3.5 140 GAL22V10D-4LJ 28-Lead PLCC
5 3 4 140 GAL22V10D-5LJ 28-Lead PLCC
7.5 4. 5 4.5 140 GAL22V10D-7LP 24-Pin Plastic DIP
4.5 4.5 140 GAL22V10D-7LJ 28-Lead PLCC
10 7 7 55 GAL22V10D-10QP 24-Pin Plastic DIP

N ES
55 GAL22V10D-10QJ 28-Lead PLCC
130 GAL22V10D-10LP 24-Pin Plastic DIP
130 GAL22V10D-10LJ 28-Lead PLCC

ED
30 GAL22V10D-10LS1 24-Pin SOIC
15 10 8 55 GAL22V10D-15QP 24-Pin Plastic DIP
55 GAL22V10D-15QJ 28-Lead PLCC

N VIC 90
90
90
GAL22V10D-15LP
GAL22V10D-15LJ
GAL22V10D-15LS1
24-Pin Plastic DIP
28-Lead PLCC
24-Pin SOIC

U
25 15 15 55 GAL22V10D-25QP 24-Pin Plastic DIP
55 GAL22V10D-25QJ 28-Lead PLCC
90 GAL22V10D-25LP 24-Pin Plastic Dip
90 GAL22V10D-25LJ 28-Lead PLCC
C DE
90 GAL22V10D-25LS1 24-Pin SOIC

1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
TI
Industrial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
7.5 5 4.5 160 GAL22V10D-7LPI 24-Pin Plastic DIP
D LL

4.5 4.5 160 GAL22V10D-7LJI 28-Lead PLCC

10 7 7 160 GAL22V10D-10LPI 24-Pin Plastic DIP
O

160 GAL22V10D-10LJI 28-Lead PLCC

15 10 8 130 GAL22V10D-15LPI 24-Pin Plastic DIP
130 GAL22V10D-15LJI 28-Lead PLCC
20 14 10 130 GAL22V10D-20LPI 24-Pin Plastic DIP
A

130 GAL22V10D-20LJI 28-Lead PLCC

25 15 15 130 GAL22V10D-25LPI 24-Pin Plastic DIP
130 GAL22V10D-25LJI 28-Lead PLCC
IS

2
 Specifications GAL22V10
Lead-Free Packaging
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
4 2.5 3.5 14 0 GAL22V10D-4LJN Lead-Free 28-Lead PLCC
5 3 4 140 GAL22V10D-5LJN Lead-Free 28-Lead PLCC
7.5 4.5 4. 5 14 0 GAL22V10D-7LPN Lead-Free 24-Pin Plastic DIP
4.5 4.5 14 0 GAL22V10D-7LJN Lead-Free 28-Lead PLCC
10 7 7 55 GAL22V10D-10QPN Lead-Free 24-Pin Plastic DIP
55 GAL22V10D-10QJN Lead-Free 28-Lead PLCC
130 GAL22V10D-10LPN Lead-Free 24-Pin Plastic DIP

N ES
130 GAL22V10D-10LJN Lead-Free 28-Lead PLCC
15 10 8 55 GAL22V10D-15QPN Lead-Free 24-Pin Plastic DIP
55 GAL22V10D-15QJN Lead-Free 28-Lead PLCC

ED
90 GAL22V10D-15LPN Lead-Free 24-Pin Plastic DIP
90 GAL22V10D-15LJN Lead-Free 28-Lead PLCC
25 15 15 55 GAL22V10D-25QPN Lead-Free 24-Pin Plastic DIP

N VIC 55
90
90
GAL22V10D-25QJN
GAL22V10D-25LPN
GAL22V10D-25LJN
Lead-Free 28-Lead PLCC
Lead-Free 24-Pin Plastic Dip
Lead-Free 28-Lead PLCC

U
Industrial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
7.5 5 4.5 160 GAL22V10D-7LPNI Lead-Free 24-Pin Plastic DIP
C DE
4.5 4.5 160 GAL22V10D-7LJNI Lead-Free 28-Lead PLCC
10 7 7 160 GAL22V10D-10LPNI Lead-Free 24-Pin Plastic DIP
TI
160 GAL22V10D-10LJNI Lead-Free 28-Lead PLCC
15 10 8 130 GAL22V10D-15LPNI Lead-Free 24-Pin Plastic DIP
130 GAL22V10D-15LJNI Lead-Free 28-Lead PLCC
20 14 10 130 GAL22V10D-20LPNI Lead-Free 24-Pin Plastic DIP
130 GAL22V10D-20LJNI Lead-Free 28-Lead PLCC
D LL

25 15 15 130 GAL22V10D-25LPNI Lead-Free 24-Pin Plastic Dip

130 GAL22V10D-25LJNI Lead-Free 28-Lead PLCC
O

Part Number Description

A

XXXXXXXX _ XX X XX X
IS

GAL22V10D Device Name

Speed (ns) Grade Blank = Commercial

I = Industrial

L = Low Power Power Package P = Plastic DIP

Q = Quarter Power PN = Lead-Free Plastic DIP
J = PLCC
JN = Lead-Free PLCC
S = SOIC

3

Output Logic Macrocell (OLMC)
The GAL22V10 has a variable number of product terms per OLMC.
Of the ten available OLMCs, two OLMCs have access to eight
product terms (pins 14 and 23, DIP pinout), two have ten product
terms (pins 15 and 22), two have twelve product terms (pins 16 and
21), two have fourteen product terms (pins 17 and 20), and two
OLMCs have sixteen product terms (pins 18 and 19). In addition
to the product terms available for logic, each OLMC has an addi-
tional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
N ES
This allows each output to be individually configured as either active
high or active low.
ED
N VIC A R
U
D
C DE
CLK
TI
SP
2 TO 1
MUX
D LL
GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
O
Output Logic Macrocell Configurations
A
Each of the Macrocells of the GAL22V10 has two primary functional
modes: registered, and combinatorial I/O. The modes and the
output polarity are set by two bits (SO and S1), which are normally
IS
controlled by the logic compiler. Each of these two primary modes,
and the bit settings required to enable them, are described below
and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
Specifications GAL22V10
The GAL22V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
4 TO 1
Q
MUX
Q
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
4
 Specifications GAL22V10
Registered Mode

AR AR

D Q D Q

N ES
CLK Q CLK Q

ED
SP SP

N VIC ACTIVE LOW ACTIVE HIGH

U
S0 = 0 S0 = 1
S1 = 0 S1 = 0
C DE

Combinatorial Mode
TI
D LL
O
A
IS

ACTIVE LOW ACTIVE HIGH

S0 = 0 S0 = 1
S1 = 1 S1 = 1

5
 Specifications GAL22V10
GAL22V10 Logic Diagram / JEDEC Fuse Map
DIP (PLCC) Package Pinouts
1 (2)
0 4 8 12 16 20 24 28 32 36 40

0000
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0044
. 8
. OLMC
. S0 23 (27)
0396 5808
S1
5809

0440
.
. 10 OLMC
.
S0
22 (26)

N ES
.
0880 5810
S1
5811
2 (3)
0924
.
. 12

ED
. OLMC 21 (25)
. S0
. 5812
1452 S1
5813
3 (4)

N VIC 1496
.
.
.
.
.
.
14 OLMC
S0
5814
S1
20 (24)

U
2112
5815
4 (5)
2156
.
.
. 16 19 (23)
. OLMC
.
C DE
S0
. 5816
. S1
2860 5817

5 (6)
TI
2904
.
.
. 16 18 (21)
.
.
OLMC
. S0
. 5818
3608 S1
5819
D LL

6 (7)
3652
.
.
O

. 14 OLMC 17 (20)
.
. S0
. 5820
4268 S1
5821
7 (9)
A

4312
.
. 12
. OLMC 16 (19)
. S0
. 5822
4840 S1
IS

5823
8 (10)
4884
.
. 10 OLMC
. S0 15 (18)
. 5824
5324 S1
5825
9 (11)
5368
. 8
. OLMC
. S0 14 (17)
5720 5826
S1
10 (12) 5827
5764 SYNCHRONOUS PRESET
(TO ALL REGISTERS)
11 (13) 13 (16)

5828, 5829 ... Electronic Signature ... 5890, 5891

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
M L
S S
B B

6
 Specifications
SpecificationsGAL22V10D
GAL22V10
Absolute Maximum Ratings1 Recommended Operating Conditions
Supply voltage VCC ....................................... -0.5 to +7V Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Input voltage applied ........................... -2.5 to VCC +1.0V
Supply voltage (VCC)
Off-state output voltage applied........... -2.5 to VCC +1.0V
with Respect to Ground ..................... +4.75 to +5.25V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Industrial Devices:
Power Applied ......................................... -55 to 125°C
Ambient Temperature (TA) ............................ -40 to 85°C
1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These Supply voltage (VCC)
are stress only ratings and functional operation of the device with Respect to Ground ..................... +4.50 to +5.50V

N ES
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

ED
DC Electrical Characteristics

N VIC
SYMBOL
Over Recommended Operating Conditions (Unless Otherwise Specified)

PARAMETER CONDITION MIN. TYP.3 MAX. UNITS

U
VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

C DE
IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 μA

TI
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

IOL Low Level Output Current — — 16 mA

D LL

IOH High Level Output Current — — –3.2 mA

O

IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –130 mA

COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-4/-5/-7 — 90 140 mA
A

Supply Current ftoggle = 15MHz Outputs Open L-10 — 90 130 mA

L-15/-25 — 75 90 mA
IS

Q-10/-15/-25 — 45 55 mA

INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA
Supply Current ftoggle = 15MHz Outputs Open L-15/-20/-25 — 75 130 mA

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C

7
 Specifications
SpecificationsGAL22V10D
GAL22V10
AC Switching Characteristics
Over Recommended Operating Conditions

COM COM COM/IND

TEST -4 -5 -7
PARAM DESCRIPTION UNITS
COND.1
MIN. MAX. MIN. MAX. MIN. MAX.
tpd A Input or I/O to Combinatorial Output 1 4 1 5 1 7.5 ns

tco A Clock to Output Delay 1 3.5 1 4 1 4.5 ns

tcf2 — Clock to Feedback Delay — 2.5 — 3 — 3 ns

N ES
tsu — Setup Time, Input or Fdbk before Clk↑ 2.5 — 3 — 4.5 — ns

th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — ns

ED
A Maximum Clock Frequency with 167 — 142.8 — 111 — MHz
External Feedback, 1/(tsu + tco)

fmax3
N VIC A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
200 — 166 — 133 — MHz

U
A Maximum Clock Frequency with 250 — 200 — 166 — MHz
No Feedback

twh — Clock Pulse Duration, High 2 — 2.5 — 3 — ns

C DE
twl — Clock Pulse Duration, Low 2 — 2.5 — 3 — ns

ten B Input or I/O to Output Enabled 1 5 1 6 1 7.5 ns

TI
tdis C Input or I/O to Output Disabled 1 5 1 5.5 1 7.5 ns
tar A Input or I/O to Asynch. Reset of Reg. 1 4.5 1 5.5 1 9 ns

tarw — Asynch. Reset Pulse Duration 4.5 — 4.5 — 7 — ns

D LL

tarr — Asynch. Reset to Clk↑ Recovery Time 3 — 4 — 5 — ns

O

tspr — Synch. Preset to Clk↑ Recovery Time 3 — 4 — 5 — ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.
A

3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these
parameters.
IS

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V

CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V

*Characterized but not 100% tested.

8
 Specifications
SpecificationsGAL22V10D
GAL22V10
AC Switching Characteristics
Over Recommended Operating Conditions

COM / IND COM / IND IND COM / IND

TEST -10 -15 -20 -25

PARAM. DESCRIPTION UNITS
COND.1 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tpd A Input or I/O to Comb. Output 1 10 3 15 3 20 3 25 ns

tco A Clock to Output Delay 1 7 2 8 2 10 2 15 ns

tcf2 — Clock to Feedback Delay — 2.5 — 2.5 — 8 — 13 ns

N ES
tsu — Setup Time, Input or Fdbk before Clk↑ 6 — 10 — 12 — 15 — ns
th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — ns

ED
A Maximum Clock Frequency with 83.3 — 55.5 — 41.6 — 33.3 — MHz
External Feedback, 1/(tsu + tco)

fmax3
N VIC A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
110 — 80 — 45.4 — 35.7 — MHz

U
A Maximum Clock Frequency with 125 — 83.3 — 50 — 38.5 — MHz
No Feedback

twh — Clock Pulse Duration, High 4 — 6 — 10 — 13 — ns

C DE
twl — Clock Pulse Duration, Low 4 — 6 — 10 — 13 — ns

ten B Input or I/O to Output Enabled 1 10 3 15 3 20 3 25 ns

TI
tdis C Input or I/O to Output Disabled 1 9 3 15 3 20 3 25 ns

tar A Input or I/O to Asynch. Reset of Reg. 1 13 3 20 3 25 3 25 ns

tarw — Asynch. Reset Pulse Duration 8 — 15 — 20 — 25 — ns

D LL

tarr — Asynch. Reset to Clk↑ Recovery Time 8 — 10 — 20 — 25 — ns

O

tspr — Synch. Preset to Clk↑ Recovery Time 8 — 10 — 14 — 15 — ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.
A

3) Refer to fmax Description section.

Capacitance (TA = 25°C, f = 1.0 MHz)

IS

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V

CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V

*Characterized but not 100% tested.

9
 Specifications GAL22V10
Switching Waveforms

INPUT or
INPUT or VALID INPUT
VALID INPUT I/O FEEDBACK
I/O FEEDBACK
tsu th
t pd
CLK
COMBINATORIAL
OUTPUT tco
REGISTERED
OUTPUT

N ES
Combinatorial Output
1/ fmax
(external fdbk)

ED
Registered Output

N VIC
INPUT or
I/O FEEDBACK

t dis t en

U
OUTPUT
CLK
1/ f max (internal fdbk)
C DE
Input or I/O to Output Enable/Disable t cf tsu
REGISTERED
TI
FEEDBACK

fmax with Feedback

tw h tw l
D LL

CLK
O

1 / fm a x
(w/o fdbk)
A

Clock Width
IS

INPUT or
INPUT or
I/O FEEDB ACK
I/O FEEDBACK
DRIVI NG AR
DRIVING SP tarw
tsu th t spr
CLK
CLK

tco tarr
R E G I S T ER E D
REGISTERED
OUTPUT
OUTPUT
tar

Synchronous Preset Asynchronous Reset

10
 Specifications GAL22V10
fmax Descriptions
CL K
CLK

LOGIC
LOGIC
R EG I S T E R ARRAY
ARR AY
REGISTER

ts u tc o
fmax with External Feedback 1/(tsu+tco)

N ES
t cf
Note: fmax with external feedback is cal- t pd
culated from measured tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)

ED
CLK

Note: tcf is a calculated value, derived by sub-

N VIC LOGIC
ARRAY
REGISTER
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from

U
clocking a register to a combinatorial output
(through registered feedback), as shown above.
tsu + th For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
fmax with No Feedback
C DE
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
TI
clock duty cycle of other than 50%.
D LL
O
A
IS

11
 Specifications GAL22V10
Switching Test Conditions

Input Pulse Levels GND to 3.0V GAL22V10D-4 Output Load Conditions (see figure below)

Input Rise and D-4/-5/-7 1.5ns 10% – 90% Test Condition R1 CL

Fall Times D-10/-15/-20/-25 2.0ns 10% – 90%
A 50Ω 50pF
Input Timing Reference Levels 1.5V
B Z to Active High at 1.9V 50Ω 50pF
Output Timing Reference Levels 1.5V
Z to Active Low at 1.0V 50Ω 50pF
Output Load See Figure
C Active High to Z at 1.9V 50Ω 50pF
3-state levels are measured 0.5V from steady-state active Active Low to Z at 1.0V 50Ω 50pF

N ES
level.

+1.45V

ED
Output Load Conditions (except D-4) (see figure below) TEST POINT

A
N VIC
Test Condition R1

300Ω
R2

390Ω 50pF
CL

FROM OUTPUT (O/Q)

UNDER TEST Z0 = 50Ω, CL*
R1

U
B Active High ∞ 390Ω 50pF
Active Low 300Ω 390Ω 50pF
C Active High ∞ 390Ω 5pF
C DE
Active Low 300Ω 390Ω 5pF

+5V
TI
R1
D LL

FROM OUTPUT (O/Q)

UNDER TEST TEST POINT
O

C L*
R2
A
IS

*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

12

Electronic Signature
An electronic signature (ES) is provided in every GAL22V10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the se-
curity cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
Specifications GAL22V10
Output Register Preload
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.

N ES
choose a Lattice Semiconductor 22V10 device type when com-
piling a set of logic equations. In addition, many device program-
mers have two separate selections for the device, typically a
GAL22V10 and a GAL22V10-UES (UES = User Electronic Sig-
The GAL22V10 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If

ED
nature) or GAL22V10-ES. This allows users to maintain compat- necessary, approved GAL programmers capable of executing test
ibility with existing 22V10 designs, while still having the option to vectors perform output register preload automatically.
use the GAL device's extra feature.

N VIC
The JEDEC map for the GAL22V10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However,
Input Buffers
GAL22V10 devices are designed with TTL level compatible in-

U
the GAL22V10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device pro-
grammer.
C DE
Security Cell
A security cell is provided in every GAL22V10 device to prevent
TI
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always avail-
D LL
put buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than bi-
polar TTL devices.
The input and I/O pins also have built-in active pull-ups. As a re-
sult, floating inputs will float to a TTL high (logic 1). However,
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins be connected to an adjacent active input, Vcc,
or ground. Doing so will tend to improve noise immunity and
reduce Icc for the device. (See equivalent input and I/O schemat-
ics on the following page.)

able to the user, regardless of the state of this control cell. Typical Input Current
O

Latch-Up Protection
I n p u t C u r r e n t (u A )

GAL22V10 devices are designed with an on-board charge pump -20

to negatively bias the substrate. The negative bias is of sufficient
A

magnitude to prevent input undershoots from causing the circuitry

-40
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
-60
IS

sibility of SCR induced latching.

0 1.0 2.0 3.0 4.0 5.0

In p u t V o lt ag e ( V o lt s)
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Com-
plete programming of the device takes only a few seconds. Eras-
ing of the device is transparent to the user, and is done automati-
cally as part of the programming cycle.

13
 Specifications GAL22V10
Power-Up Reset

Vcc (min.)
Vcc

t su

CLK t wl

t pr
INTERNAL REGISTER Internal Register

N ES
Q - OUTPUT Reset to Logic "0"

ACTIVE LOW

ED
Device Pin
OUTPUT REGISTER Reset to Logic "1"

N VIC ACTIVE HIGH

OUTPUT REGISTER
Device Pin
Reset to Logic "0"

U
Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1μs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
C DE
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
TI
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be
met to guarantee a valid power-up reset of the GAL22V10. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.

Input/Output Equivalent Schematics

D LL

PIN PIN
O

Feedback
A

Vcc
(Vref Typical = 3.2V) Active Pull-up Active Pull-up
Circuit Circuit
(Vref Typical = 3.2V)
IS

Vcc
Vcc Vref Vcc Tri-State Vref
ESD Control
Protection
Circuit

PIN Data
PIN
Output

ESD
Protection
Circuit

Feedback
(To Input Buffer)

Typical Input Typical Output

14
 Specifications GAL22V10
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc
1.1 1.1 1.1

RISE
RISE
FALL
Normalized Tpd

1.05 1.05 1.05

Normalized Tco

Normalized Tsu
RISE FALL
FALL

1 1 1

0.95 0.95 0.95

N ES
0.9 0.9 0.9
4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5

Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

ED
Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp
1.3 1.2 1.3

N VIC 1.2 RISE RISE 1.2 RISE

Normalized Tco
Normalized Tpd

FALL

Normalized T
FALL FALL
1.1
1.1 1.1

U
1 1
1

0.9
0.9
C DE
0.9 0.8
0.8 -55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
-55 -25 0 25 50 75 100 125

Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)

TI
Delta Tpd vs # of Outputs Delta Tco vs # of Outputs
Switching Switching
0 0
D LL

-0.1
Delta Tpd (ns)

Delta Tco (ns)

-0.1
O

-0.2

-0.2 RISE RISE

FALL -0.3 FALL
A

-0.3 -0.4
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching Number of Outputs Switching
IS

Delta Tpd vs Output Loading Delta Tco vs Output Loading

12 12

RISE RISE
Delta Tpd (ns)

8 8
Delta Tco (ns)

FALL FALL

4 4

0 0

-4 -4
0 50 100 150 200 250 300 0 50 100 150 200 250 300

Output Loading (pF) Output Loading (pF)

15
 Specifications GAL22V10
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
Vol vs Iol Voh vs Ioh Voh vs Ioh
0.6 4 3.95

3.85

3 3.75
0.4
3.65

Voh (V)
Voh (V)
Vol (V)

2 3.55

3.45
0.2
1 3.35

3.25

N ES
0 0 3.15
0 5 10 15 20 25 30 35 40 0 5 10 1 5 2 0 2 5 3 0 3 5 4 0 4 5 50 55 60 0.00 1.00 2.00 3.00 4.00 5.00

Iol (mA) Ioh(mA) Ioh(mA)

ED
Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq
1.2 1.3 1.2

N VIC 1.1
1.2
1.15
Normalized Icc

Normalized Icc

Normalized Icc
1.1
1.1
1 1

U
1.05
0.9
0.9
1
0.8

0.8
C DE
0.7 0.95
4.5 4.75 5 5.25 5.5 -55 -25 0 25 50 88 100 125 1 15 25 50 75 1 00
Supply Voltage (V) Temperature (deg. C) Frequency (MHz)
TI
Delta Icc vs Vin (1 input) Input Clamp (Vik)
6 0

5 20
Delta Icc (mA)

D LL

4
40
Iik (mA)

3
60
O

2
80
1
100
A

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
-3 -2.5 -2 -1.5 -1 -0.5 1

Vin (V) Vik (V)

IS

16
 Specifications GAL22V10
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc
1.1 1.2
1.1

RISE RISE
1.1

Normalized Tsu
FALL

Normalized Tco
1.05 RISE FALL
Normalized Tpd

FALL 1.05

1
1

1
0.9
0.95

N ES
0.95 0.8
0.9
4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5
4.5 4.75 5 5.25 5.5

Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

ED
Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp
1.3 1.2 1.3

N VIC 1.2 RISE

1.1
RISE 1.2 RISE
Normalized Tpd

Normalized Tco

FALL

Normalized Tsu
FALL FALL

1.1 1.1

U
1
1 1

0.9
0.9 0.9
C DE

0.8 0.8 0.8

-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
TI
Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Tco vs # of Outputs

Switching Switching
0 0
-0.1 -0.1
D LL

-0.2 -0.2
-0.3 -0.3
Delta Tpd (ns)

Delta Tco (ns)

O

-0.4 -0.4
-0.5 -0.5
-0.6 -0.6
-0.7 -0.7
RISE
A

-0.8
RISE
-0.8 FALL
FALL
-0.9 -0.9
-1 -1
-1.1 -1.1
IS

1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching Number of Outputs Switching

Delta Tpd vs Output Loading Delta Tco vs Output Loading

12 12

RISE RISE
8 8
FALL
Delta Tpd (ns)

Delta Tco (ns)

FALL

4 4

0 0

-4 -4
0 50 100 150 200 250 300 0 50 100 150 200 250 300

Output Loading (pF) Output Loading (pF)

17
 Specifications GAL22V10
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams
Vol vs Iol Voh vs Ioh Voh vs Ioh
0.5 4 3.8

3.7
0.4 3.6
3
3.5

Voh (V)
0.3 3.4

Voh (V)
Vol (V)

2 3.3
0.2 3.2
3.1
1
0.1 3

N ES
2.9
0 0 2.8
0 5 10 15 20 25 30 0 5 10 15 20 25 30 35 40 0.00 1.00 2.00 3.00 4.00 5.00
Iol (mA) Ioh (mA) Ioh (mA)

ED
Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq

N VIC 1.15

1.1
1.3

1.2
1.2

1.15
Normalized Icc

Normalized Icc

Normalized Icc

U
1.05 1.1
1.1
1 1
1.05
0.95 0.9
C DE
0.9 1
0.8
TI
0.85 0.7 0.95
4.5 4.75 5 5.25 5.5 -55 0 25 100 1 15 25 50 75 100
Supply Voltage (V) Temperature (deg. C) Frequency (MHz)

Delta Isb vs Vin (1 input) Input Clamp (Vik)

D LL

10 0
9 10
O

8 20
Delta Icc (mA)

7 30
6 40
Iik (mA)

5 50
A

4 60
3 70
2 80
IS

1 90
0 100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -2.5 -2 -1.5 -1 -0.5 0
Vin (V) Vik (V)

18
 Specifications GAL22V10
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc
1.1 1.15 1.2

1.1 RISE RISE

Normalized Tpd

1.05 RISE

Normalized Tco

Normalized Tsu
FALL 1.1
FALL
FALL
1.05
1 1
1

0.95 0.9
0.95

N ES
0.9
0.9 0.8
4.5 4.75 5 5.25 5.5
4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5
Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

ED
Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp

N VIC 1.3

1.2 RISE
1.3

1.2
RISE
1.45

1.35
RISE
Normalized Tpd

FALL FALL
Normalized Tco

FALL

Normalized Tsu
1.25
1.1

U
1.1
1.15

1
1 1.05

0.9 0.95
0.9
C DE
0.85
0.8
-55 -25 0 25 50 75 100 125 0.8 0.75
-55 -25 0 25 50 75 100 1 25 -55 -25 0 25 50 75 100 1 25
Temperature (deg. C)
TI
Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Tco vs # of Outputs

Switching Switching
0 0
D LL Delta Tpd (ns)

Delta Tco (ns)

-0.4 -0.4
O

RISE
RISE
FALL
FALL
-0.8 -0.8
A

-1.2 -1.2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
IS

Number of Outputs Switching Number of Outputs Switching

Delta Tpd vs Output Loading Delta Tco vs Output Loading

20 20

16 16
RISE RISE
Delta Tpd (ns)

Delta Tco (ns)

12 FALL FALL
12
8
8
4
4
0

-4 0

-8 -4
0 50 100 150 200 250 3 00 0 50 100 150 200 250 3 00

Output Loading (pF) Output Loading (pF)

19
 Specifications GAL22V10
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
Vol vs Iol Voh vs Ioh Voh vs Ioh
0.6 4.5 4.5

3.5 4
0.4 3

Voh (V)

Voh (V)
Vol (V)

2.5
3.5
2

0.2 1.5

1 3

0.5

N ES
0 0 2.5
0 5 10 15 20 25 30 35 40 0 20 40 60 0.00 1.00 2.00 3.00 4.00 5.00

Iol (mA) Ioh (mA) Ioh (mA)

ED
Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq
1.2 1.35 1.4

N VIC 1.25 1.3

Normalized Icc

Normalized Icc

Normalized Icc
1.1
1.15
1.2

U
1 1.05
1.1
0.95
0.9
1
0.85
C DE
0.8 0.75 0.9
4.5 4.75 5 5.25 5.5 -55 -25 0 25 50 88 100 1 25 1 15 25 50 75 1 00

Supply Voltage (V) Temperature (deg. C) Frequency (MHz)

TI
Delta Icc vs Vin (1 input) Input Clamp (Vik)
7 0

10
6
D LL

20
Delta Icc (mA)

5
30
Iik (mA)

4 40

3 50

60
2
A

70
1 80

0 90
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -2.5 -2 -1.5 -1 -0.5 0
IS

Vin (V) Vik (V)

20
 Specifications GAL22V10
Notes
Revision History

Date Version Change Summary

- 22v10_08 Previous Lattice release.
August 2004 22v10_09 Added lead-free package options.
July 2006 22v10_10 Corrected SOIC pin configuration diagram. Pin 13.
August 2006 22v10_11 Updated for lead-free package options.
December 2006 22v10_12 Corrected Icc in the Ordering Part Number section on pages 2-3.

N ES
ED
N VIC
U
C DE
TI
D LL
O
A
IS

21