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STEP 1:
Load the 4 main Inputs i.e.
Lef contains :
No of metal layers,
Direction of metal layer H/V,
Resistance and capacitance per unit square,
width
spacing and pitch of all metal layers,
area,
thickness,
Via information [double cut and single cut]
a subset of DRC rules.
Macro Lef: All macro information ex dimensions and coordinates, macro pin information.
Std cell Lef: All physical dimensions of the std cells and input pin a b and out, their geometry.
Libs: NLDM’s
All timing information of the standard cells ex nand, and, or flip-flop.
Like cell delay information for that much input transition and that much output load.
timing sense i.e. Positive or negative unate.
Setup and hold constraints of the sequential circuits. For that much data transition and that
much clock transition Setup time and hold times.
Recovery and removal checks.
Power information: depending upon Input transition and output capacitance internal and
external power. Cell Leakage information.
STEP 3:
Floor planning talk about giving large area to the std cells and placing memories to the
boundaries how it will cause IR drop.
Congestion issue and how you solved it.
STEP 4:
Power planning:
The main goal of power planning is to achieve the Limit or % of IR drop that is given. Like 2% or
1% or 0.9% of total power.
Initially we design power structure to meet half i.e. if target is 2% we build power structure to
meet 1%, its more pessimistic. Then once Routing is done the target of 2% will be met due to
more cells after optimization.
External switching power is the power dissipated for charging and discharging output loads.
Different areas of the chip function at different frequencies on area may be slow one area may
be fast. So if we design power structure for dynamic power the after CTS more buffers will be
added and switching may vary at each stage of optimization, so for that we need to create a
different power structure at each stage which is incorrect.
So we take average of all switching factors [static power is average switching power] and build
a power structure and the fine tune it if there is IR drop.
STEP 5:
Placement:
Timing optimization: Uncertainty included skew+jitter+delay due to OCV derates.
Why we need to give uncertainty
We need to show the post CTS effects in preCts stage itself because once clock is built the
postCTS optimization will not touch flops and clocks. We need to play with cells to solve timing
and we can use usefulskew. But if we give pessimism to show postCTS effects in preCts the tool
will optimize refine placement and give better placement for the later effects.
Why solve only setup at PreCts?
At preCts stage the clock is Ideal it’s not propagated, so if you look at the internal circuit of flop
the clock to q delay + the propagation delay cannot be less that the hold time [Buffer delay]
Hence there can be no hold violations at preCts stage, but still we see some violations because
of the uncertainty values that we have given.
If we clean hold at this stage with the improper uncertainties because we don’t know the
uncertainties we have given is correct so the tool will insert lot of buffers which are
unnecessary. It will increase area, utilization, leakage, congestion.
Once the clock is propagated we can solve the hold after running placement with reduced
uncertainties.
STEP 6:
Clock Tree Synthesis:
Once setup is clean we can move on to build a clock tree.
Input to CTS:
STEP 7:
POST CTS OPTIMIZATION:
Apply Derates and remove CPPR. If we don’t remove CPPR it will be over pessimism Optimize
for both setup and hold.
1.Talk about Derates, OCV’s, CPPR.
STEP 8:
ROUTING:
Route the Design.
After routing you’ll see that the setup violations are increased that’s because till this point the
routing was trial route and delays were estimated based upon the trial route. Once actual
routing is done then we get actual RC’s.
There will be no or less hold violations because the delays are more which will be a plus point
for hold margins.
Signoff Flow
Routing
Setup/Hold Optimization.
Case 1
FF1
FF2
FF2
FF3
Case 2
To solve hold time of FF2.
You need to check setup margin of FF2 and hold margin of FF0.
FF1
FF2
FF0
FF1