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Enhancement-Mode GaN MIS-HEMTs with
LaHfOx Gate Insulator for Power Application
Yueh Chin Lin, Yu Xiang Huang, Gung Ning Huang, Chia Hsun Wu, Jing Neng Yao, Chung Ming Chu,
Shane Chang, Chia Chieh Hsu, Jin Hwa Lee, Kuniyuki Kakushima, Kazuo Tsutsui, Hiroshi Iwai, Life
Fellow, IEEE, and Edward Yi Chang, Fellow, IEEE
 shift and effects the output performance of the E-mode devices.
Abstract—This paper report an E-mode GaN MIS-HEMT
using a composite La2O3/HfO2 gate insulator for power device
applications. The composite dielectric formed an amorphous
LaHfOx layer after post-deposition annealing. The GaN
MIS-HEMT with amorphous LaHfOx gate dielectric showed good
oxide film quality and excellent HfLaOx/GaN interface properties,
as demonstrated by the measured C-V characteristics.
Consequently, the E-mode MIS-HEMT was determined to show
good Vth stability with only a slight increase in the dynamic Ron
after high drain bias stress.
Index Terms—GaN, MIS-HEMT, LaHfOx, gate recessed, gate
insulator, threshold voltage hysteresis.
I. INTRODUCTION
E -nhancement-mode (E-mode) GaN high-electron- mobility
transistors (HEMTs) have been widely investigated
recently for electrical vehicle applications due to the simplicity
of their circuit design and safety issues. The recessed gate
technique is a common approach to achieving an E-mode
device, but it has several disadvantages such as current density
and threshold voltage issues [1]. To improve the device
performance, a gate recess process with a gate insulator
inserted between gate metal and AlGaN has been adopted to
suppress the gate leakage as well as increase the positive gate
voltage swing of the threshold voltage [2]. Although the use of
a gate insulator improves the E-mode device characteristics,
trapping states always exist in the bulk of the oxides and in the
interface between the insulator and III-nitride, resulting in the
threshold voltage hysteresis effect [3]. These deep traps can
capture electrons when the E-mode device is biased with a
positive voltage, which causes the gate threshold voltage to
This work was sponsored by National Chung-Shan Institute of Science &
Technology, Taiwan, under Grant No. NCSIST-103-V312 (106) and TSMC,
NCTU-UCB I-RiCE program, and Ministry of Science and Technology,
Taiwan, under No. MOST106-2911-I-009-301.
Y. C. Lin, C. H. Wu, C. C. Hsu, S. Chang and E. Y. Chang are with the
Department of Materials Science and Engineering, National Chiao Tung
University, Hsinchu 300, Taiwan (e-mail: nctulin@yahoo.com.tw).
Y. X. Huang and J. H. Lee are with Institute of Photonic System, National
Chiao Tung University, Tainan 711, Taiwan.
G. N. Huang, J. N. Yao and E. Y. Chang are with Department of Electronics
Engineering, National Chiao Tung University, Hsinchu 300, Taiwan.
C. M. Chu is with Department of Electrophysics, National Chiao Tung
University, Hsinchu 300, Taiwan.
H. Iwai and E. Y. Chang are International college of Semiconductor
Technology, National Chiao Tung University, Hsinchu 300, Taiwan
K. Kakushima, K. Tsutsui, H. Iwai are with Interdisciplinary Graduate
School of Science and Engineering, Tokyo Institute of Technology, Japan.
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Therefore, the gate insulator and interface qualities are factors
that considerably effect the performance of E-mode
MIS-HEMTs.
Previous studies have indicated that hafnium (Hf)-based
amorphous materials, such as LaHfOx, are emerging as the
promising gate insulators because of their high crystallization
temperature, high permittivity value and low fixed charge
density [4-5]. In this study of a gate-recessed GaN MIS-HEMT
with annealed composite La2O3/HfO2 gate insulator layer,
excellent interface quality was observed for the composite gate
insulator due to the formation of the amorphous LaHfOx layer
after high-temperature annealing. The low defect density of the
amorphous LaHfOx layer was demonstrated from the
capacitance-voltage (C-V) curve of the MOS capacitor, pulse
current-voltage (I-V) and dynamic Ron measurements.
II. DEVICE FABRICATION
Fig. 1 shows the cross section of the fabricated gate-recessed
GaN MIS-HEMT. The epitaxial structure of the device was
grown by metal-organic chemical vapor deposition (MOCVD)
on Si (111) substrate. It consisted of a 1-μm thick GaN buffer
layer and a 25-nm-thick Al0.22Ga0.78N barrier layer with a 3-nm
undoped GaN cap layer on the top of the structure. The
fabrication process started with the multilayer deposition of a
Ti/Al/Ni/Au Ohmic metal stack, after which the metal stack
was annealed at 800 °C for 60 s in N2 ambient for Ohmic
contact formation. Mesa isolation using inductively couple
plasma (ICP) etching was employed to define the active region
of the device. Gate recessing was performed using low-power
BCl3/Cl2 plasma, followed by rapid thermal annealing (RTA) at
500°C for 5 min to remove any plasma damage. The composite
La2O3/HfO2 was deposited by the molecular beam deposition
(MBD) system at 200°C at a pressure of 10-7 Torr.
Post-deposition annealing (PDA) at 600°C was performed to
improve the oxide film quality. Finally, Schottky gate metal of
Ni/Au was deposited by an E-gun system. The gate length of
the device was 2 um, and the gate-to-source and gate-to-drain
distances were 3 um and 15 um, respectively.
III. RESULT AND DISCUSSION
Fig. 1 also shows the schematic of the cross section of the
composite La2O3/HfO2 on the GaN HEMT. The La2O3/HfO2
oxide stack was deposited with 10 La2O3/HfO2 pairs, and each
pair consisted of 0.4-nm La2O3 and 0.4-nm HfO2 with HfO2
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layer at the bottom. Fig. 2 depicts the transmission electron
microscopy (TEM) micrographs and energy dispersive X-ray
(EDX) analysis results of the 10 layers of La2O3/HfO2
composite oxides after annealed at 600°C for 5 min. As
illustrated in the TEM image, the La2O3/HfO2 stack
transformed to amorphous LaHfOx with a sharp interfacial
layer on the GaN layer. The TEM image confirms that
La2O3/HfO2 remained amorphous even after annealing; the
mixing of La2O3 with HfO2 raised the recrystallization
temperature [6]. The EDX analysis showed almost no obvious
diffusion of Hf and Lanthanum (La) into the GaN layer, and the
gate insulator had a sharp interface with the GaN layer.
Fig. 1. Schematic cross section of the E-mode GaN MIS-HEMT with 10
layers of La2O3 (0.4-nm)/HfO2 (0.4-nm) composite gate insulator.
Fig. 2 Cross-sectional TEM image of the LaHfOx layer of the E-mode GaN
MIS-HEMT.
Fig. 3 presents the typical C-V characteristics of the
La2O3/HfO2/GaN MOS capacitor measured at different
frequencies. Nearly no Vth shift occurred when the bias swept
from -5V to 2V and 2 V to -5V at different frequencies. A
positive threshold voltage shift would occur during
acceptor-like states existed at the interface [7]. The C-V curve
of the La2O3/HfO2/GaN MOS capacitor indicates that the
interface between the La2O3/HfO2 and GaN has very low
interface states and border trap density. In addition, negligible
hysteresis and lack of frequency dispersion could be observed
(Fig.3). This therefore demonstrates amorphous HfLaOx
induces a very small degradation of interface properties and
bulk quality. Thus, very low interface and bulk traps existed in
the MOS capacitor. This phenomenon was also observed in
another study [6]. The DC characteristics of the E-mode GaN
MIS-HEMT with the 10 annealed pairs of La2O3 (0.4nm)/HfO2
(0.4nm) gate insulator are shown in Fig. 4. The maximum drain
current was 648 (mA/mm) at a gate voltage of 6 V and the
on-resistance was 9.4 Ω.mm. The device exhibited the
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normally-off HEMT behavior with a Vth value of +0.35V, as
determined by linear extrapolation of the transfer curve. A
maximum transconductance of 165 mS/mm and a subthreshold
slope of 114 mV/decade were achieved when the drain bias was
10V. In addition, the Ion/Ioff current ratio was 3.6×106. Table I
presents a comparison of the DC characteristics of the LaHfOx
device with others gate dielectric GaN MIS-HEMT. The
LaHfOx device exhibits high current density, high maximum
transconductance and low hysteresis when compared with other
GaN MIS-HEMTs with different gate dielectrics.
Fig. 3. C–V curves of the GaN MOSCAP with 8-nm LaHfOx gate insulator
after PDA at 6000C for 5 min.
Fig. 4 DC characteristics of the E-mode GaN MIS-HEMT with 8-nm LaHfOx
gate insulator, PDA at 6000C for 5 min.: (a) IDS-VDS curves, (b) IDS & Gm vs.
VGS curves, and (c) transfer curve.
Magnetization
Fig.5 shows as aOutput
function I–V
of applied
and field. Note characteristics
transfer that “Fig.” is abbreviated.
of the
There is a period after the figure number, followed by two spaces. It is good
E-mode GaN MIS-HEMT with 8-nm LaHfOx gate
practice to explain the significance of the figure in the caption. insulator
measured using the sweep measurement. Fig. 5(a) shows that
the IDS vs. VDS curve has no obvious current slump with step-up
and step-down measurements. A very small hysteresis (45.5mV)
was observed when the gate was swept from −3V to 3V and
from 3V to −3V with a drain bias of 10V, indicating good
interface quality between amorphous HfLaOx and GaN. The
trap density was estimated using Dit = Coxide·ΔVth/q [2, 8].
For the LaHfOx gate insulator device in this study, the
estimated k value was 23.8, and the calculated Dit value was
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7.5 × 1011 cm−2. The trap density is comparable to those of other resistance was sampled after 0.1 s to calculate the dynamic Ron.
gate insulators in previous studies (2.6 × 1012 cm−2[8] and 1.6 × The switching time of the Agilent High Voltage/High Current
1011 cm−2[2]). To further investigate Vth hysteresis stability, the Switch component was 0.1 s. Compared with the data of the
sweep transfers characteristics were examined by pulsed device without the gate oxide layer, the gate-recessed GaN
IDS-VGS measurements with a 20-ms pulse period and a 2-ms MIS-HEMT with the annealed LaHfOx gate insulator exhibited
pulse width, as illustrated in the Fig. 6. Because the only a slight increase in the dynamic Ron after high drain bias
field-assisted detrapping effect is associated with the applied stress. This demonstrates that the current collapse phenomenon
VDS voltage [7], the drain bias was reduced to 1V from 6V to was less severe for the device with the LaHfOx gate insulator
investigate the shallow and deep traps at the LaHfOx gate due to the improvement of the electron trapping at the surface
insulator. Fig. 6 indicates only a slight Vth shift and nearly no states [11].
Vth hysteresis when VDS swept from 6V to 1V for the
gate-recessed GaN MIS-HEMT with the 8-nm LaHfOx gate
insulator/GaN interface. The Vth stability can be attributed to
the reduction of the Ga-O bond after annealing [10] and the low
fixed charge density in the amorphous LaHfOx dielectric film
[6]. The low interface trap density and the excellent oxide
quality can be attributed to the formation of the LaHfOx gate
insulator.
Table I: Comparison of DC characteristics of the LaHfOx with others gate
dielectric GaN MIS-HEMTs.
This work Ref. [2] Ref. [8] Ref. [9]
Oxide/ LaHfOx/ Al2O3/AlN Al2O3/ Al2O3/ SiO3
Thickness Fig. 6. Transfer sweep curves measured by pulse mode with different V DS
(nm) 8 8/2 10 7/9 from 6V to 1V for the E-mode GaN MIS-HEMT with 8-nm LaHfOx gate
LG (m) 2 2 1.5 0.12 insulator (PDA at 6000C for 5 min)
VTH (V) 0.35 1.5 1.7 0.8
IDS, max:
(mA/mm)/ 648/15 530/14.5 528/3 530/10
LGD (um)
Gm, max:
(mS/mm)/ 165/15 140/14.5 114/3 100/10
LGD (um)
Hysteresis
(mV) 45.5 65 700 -

Fig. 7. Comparison of the dynamic on-resistance (Ron) measurements of the

E-mode GaN MIS-HEMT with 8-nm LaHfOx gate insulator (PDA at 6000C
for 5 min) and the conventional GaN HEMT.

Fig. 5. (a) IDS-VDS, and (b) transfer characteristics of the E-mode GaN
MIS-HEMT with 8-nm La2O3/HfO2 oxides stack up and down sweep
measurements.
To investigate the dynamic switching characteristics of the
8-nm LaHfOx E-mode GaN MIS-HEMT with high drain
voltage, an Agilent B1505A power device analyzer system was
used. Fig. 7 shows the normalized dynamic on-resistance (Ron)
as a function of the off-state VDS for devices with and without
the 8-nm LaHfOx gate insulator. The measurement steps are
detailed as follows. First, the device was turned OFF with 1-s
hold time at stress voltage (Vstress), while the gate bias was set
at VGS = 0 V. Subsequently, the device was turned ON at VDS =
1V, and VGS = 3V for the devices with the 8-nm LaHfOx gate
insulator, and VGS =1V for the device without it. The ON state
IV. CONCLUSION
In conclusion, a gate-recessed GaN MIS-HEMT with an
annealed LaHfOx gate insulator is demonstrated as having
excellent device characteristics for power application. From the
TEM image, the multilayer La2O3/HfO2 composite oxide
structure was determined to transform into an amorphous
LaHfOx film after thermal annealing. A low bulk trap density
for the LaHfOx film and low interfacial trap density between
the oxide and the AlGaN layer after thermal annealing were
observed, and the typical C-V characteristics showed a stable
Vth without hysteresis and no frequency dispersion. Based on
the C-V, DC, pulse I-V, and dynamic Ron measurements. The
gate-recessed MIS-HEMT with the amorphous LaHfOx gate
insulator showed very stable Vth and high Ion/Ioffr ratio. These
results demonstrate that the annealed amorphous LaHfOx gate
insulator is an excellent dielectric layer to be used in GaN
E-mode MIS-HEMT devices.

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