IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO.

1, FEBRUARY 1988 159

A High-Speed CMOS Comparator

for Use in an ADC
BENJAMIN J. McCARROLL, MEMBER, IEEE, CHARLES G. SODINI, MEMBER, IEEE,
AND HAE-SEUNG LEE, MEMBER, IEEE

..-htracf —A high-speed CMOS comparator has been designed and lation to begin as the dynamic latch is enabled. Power and
fabricated using a standard 3- pm process. A dynamic latch preceded by an
area are optimally distributed within the amplifier so that
offset-cancelled amplifier is used to obtain a response time of 43 ns. The
the comparator response time is minimized.
offset-cancelled amplifier reduces the input-referred offset so that
medium-resolution analog-to-digital converters (ADC’S) can be built with Section 11 deals with the comparator topology where
this comparator. The use of pipefining within the comparator enables the power and area constraints, the motivation for offset
offset cancellation to be done as the dynamic latch is enabled. Fhudly, cancellation, and the amplifier and dynamic latch optimi-
power and area are optimafly distributed within the amplifier to minimize
zation are discussed. Section III describes the device-level
response time.
circuit design of the amplifier and dynamic latch. Section
IV presents the experimental results from a single 3-pm
I. INTRODUCTION CMOS comparator designed and fabricated to verify the
architecture.

s
quencies
EVERAL
recently
between
analog-to-digital
been reported
200 and 400 MHz
that
converters
operate
[1]–[3].
(ADC’S)
at sampling
However,
have
fre-
the
II. CHOICE OF TOPOLOGY

fastest 8-bit CMOS ADC can sample up to only 25 MHz

A, Comparator Constraints
[4]. CMOS flash ADC’S, with their cost-effectiveness and
VLSI logic compatibility, are well suited for use in the When designing an N-bit flash ADC, 2N – 1 compara-
growing field of digital video-signal processing. tors are required. For medium-resolution ADC’S, the
In a flash ADC, internal comparators must amplify amount of power and area consumed per comparator is of
small voltages into logic levels. Once the result is stored the utmost importance. Therefore, when evaluating differ-
into a latch, logic is enabled to encode the outputs of the ent comparator topologies for use in a flash ADC, the
2N – 1 comparators into iV bits. Depending on the al- amount of power and area consumed must be held con-
gorithm used, encoding process can often be pipelined stant. Assume initially that a single-stage amplifier is com-
with the comparator function. Since the encoding process pared to a two-stage amplifier. The single-stage amplifier
is faster than the comparator function, the maximum draws 1 current and uses A area. The two-stage amplifier
conversion rate for the ADC is limited by the response draws 11+ 12 current and uses Al+ AZ area where the 1
time of its comparators. Therefore, the design and optimi- and 2 subscripts designate the first and second stage,
zation of the comparators is critically important. respectively. Therefore
The, comparator architecture consists of dynamic latch
11+12=1 (1)
preceded by an offset-cancelled amplifier. The positive
feedback of the dynamic latch is used to efficiently charge A1+AZ=A. (2)
and discharge the comparator output nodes. The offset-
cancelled amplifier reduces the input-referred offset so Since designing high-speed circuits is the ultimate goal, it
that medium-resolution ADC’S are possible. The use of is assumed that the channel length L is held at a minimum
pipelining within the comparator enables the offset cancel- and that the area is controlled by the device width W.
Therefore, (2) becomes

W1+W2=W. (3)
Manuscript receivedJuly 22, 1987;revisedSeptember28, 1987.
This work wassupportedby AT&T, Analog Devices,Digital Equipment
Corporation, and Generaf Electric Company. Circuit fabrication and
In order to maintain constant node voltages, as the
support was provided by DARPA under Grant NO014-80-C6622.
B. J. McCarroll was with MassachusettsInstitute of Technology, current in stage one of the two-stage amplifier increases,
Cambridge, MA 02139. He 1snow with the Lab Instruments Dmsion, the channel width must also increase. Thus
Tektronix Corporation, Beaverton,OR.
C. G. Sodini and H.-S. Lee are with the Department of Electncaf
Engineering and Computer Sciences,MassachusettsInstitute of Technol- II Iz
—=_ (4)
ogy, Cabridge, MA 02139.
IEEE Log Number 8718031. WI W2 “

0018-9200/88/0200-0159$01.00 @1988 IEEE

160 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO 1, FEBRUARY 1988

v~,J

A
F
9ml(vln-vref) D Q
S5 v In -0 YL ?L
::

fzii-
OA
UL
s, A ~; RT Q
Vref - RO
AC
Mg Cw
Mlo EE
IH :H
S3 S3 Fe / R
c

L
Mll Mlz Vpass

w’
s,
9m2v0f f

b A co:, -

L-J
S4 S5 Voff
t
s,
+

coc~ ~
b r“
v~*
Fig 1. The dynamic latch Fig. 2. The comparator block diagram,

The transconductance is given by gm = {21LC4(W/L. ).

Therefore

(gm, + gin,)’ =

Fig. 3. A one-stage single-pole amplifier

—
voltage gain of the high-gain amplifier and is given by

— RL ( %lvml + gm2vos2 )
Vo,f = (7)
%lRL(I+ gW2RL) “
Thus
The amplify cycle begins by throwing the switch ~ to
(gin, +gm2)2= G:. (5) sample the input voltage and opening the switch S1. Now,
the amplifier output voltage VP=, is a rising exponential
Equation (5) shows that if the total power and area are whose final value is the product of V,n – V,,~ and the
held constant, the total transconductance is also constant. voltage gain gnlR L.
Once the voltage VP=, is large enough (about 50 mV),
B. Comparator Architecture the dynamic latch is enabled. Since it has positive feed-
back, it is able to “amplify” the pass voltage to near logic
The dynamic latch (Fig. 1), often used as a sense ampli- levels in a short period of time. Then the storage latch is
fier in dynamic RAM’s, is a fast CMOS comparator. turned on to hold the result until the encode logic is
However, its large offset voltage limits its resolution to enabled.
about 5 bits. A linear amplifier may precede the dynamic
latch so that the voltage applied to the, latch is large C. Motivation for Offset Cancellation
enough to overcome this offset. Since a linear amplifier
can be offset-cancelled, medium-resolution ( = 8-bit) con- The initial motivation for offset cancellation is clear:
verters are possible. without it, an MOS comparator could not resolve small
Fig. 2 shows the comparator block diagram, which con- enough voltages so that it could be used in a medium-reso-
sists of a dynamic latch preceded by an offset-cancelled lution ADC. Since it takes a finite amount of time to
amplifier [5]. The Qfset-cancellation cycle begins by complete the offset-cancellation cycle before the compara-
throwing the switch SI to ground and closing the switch tor can be enabled, it seems that the comparator response
S1. The offset-cancellation amplifier (g~2) forces its offset time must be increased. However, if the offset-cancellation
(V0,2) and the offset (VO~l) from the high-gain amplifier cycle is pipelined with the dynamic latch cycle, it does not
(g~l) onto the offset-cancellation capacitors COCIand COC2. degrade the response time.
This voltage VOff is given by Consider the simple one-stage, single-pole amplifier
shown in Fig. 3. The step response for the amplifier is
given by
R L ( grnl%l + b%’%’ )
Voff = (6)
1+%2RL VOUt(t) = [g~R~V,n(O+ )(1 – e-’/c’)’)

The input-referred offset voltage VO, is reduced by the i-VOU,(0) e-t/RLc’ 1(4) u t)
McCARROLL et al.: HIGH-SPEED ChfOs COMPARATOR FOR uSE IN AN ADC 161

0.2
I , I t T I I 1 1
I 1 ,
— Threshold =50mV /
—— A“ .20 /“
0,15 – ----- A. ,50 /“ .--”-”?
z –-– AV =80 ./:.. --””
.,<--- “
$ 0.1 –
; ,x”’~” _ _ _ _ — —. Fig. 5. Single-stage amplifier driving the dynamic latch.
>0 >. ,’,--
?-
0,05
/’
o : ,/ ing the optimization for three different amplifier config-
I I , 1,11)11,,1-
0 I 2 3 4 5 urations: single-stage, single-stage plus source follower,
Time (nsec)
and two-stage plus source follower. The results can be
(a)
extended to higher-order amplifiers.
0.2
1. Single-Stage Amplifier: Consider the single-stage am-
0.15 —Threshold =50mV
—— Av =20 plifier shown in Fig. 5. A transconductance amplifier g~l
o. I
drives the input capacitance of the latch c~a~ch ad the
0,05 parasitic capacitance CPI. If the output voltage VP,S, is
0 nulled before the amplify cycle, the output voltage is given
-0.05 by
-0.1

-0.15 Vingmlt
0.2 v= u(t) (9)
0 I 2 3 4 5 “ss Cpl + c~atc~
Time (nsec)

(b)
and the time delay td to reach a desired pass voltage is
Fig. 4. (a) One-stage amplifier step response for I&(0)= O. (b) One-
stage amplifier step response for J&t (0) = – 0.15 V.
Vpa,, CP1+ c~atc~
td=—.— (lo)
Vin gml .
The first term is a rising exponential with the magnitude
determined by the voltage gain g~R~ times the input step
The offset-cancellation time constant is given by
Vi~(O + ). The second term is just the exponential decay of
the residual voltage from the last comparison V(QUt(0).
Cpl + Coc
Consider the one-stage amplifier for two cases. First, q-= (11)
assume that the initial output voltage VOUt(0) is zero and gt?-lz

that ,the following conditions hold: g~ = 0.001 S, CL= 100

fF, F’,.(o + ) = 5 mV, and that the voltage gain is varied where CO= is the offset-cancellation hold capacitance and
from 20 to 80 by adjusting R ~. The result is shown in Fig.
g~z is the offset-cancellation amplifier transconductance.
4(a). For any time t, the highest-gain configuration has The total comparator response time t, is then
“amplified” the 5-mV input voltage into the largest output
voltage. For small t, the slope of the step response for each v Cpl + cLatc~ Cpl + Coc
configuration is given by g~ /C~ so that the response time t, – p=’
+&l (12)
~n gml gniz
can be improved by increasing g~ or decreasing CL and is
independent of R L (only for t << R/L).
Now, assume that the same conditions hold as above where ill is the number of time constants used to perform
except that V@(0) = – 0.15 V. Due to the decaying resid- the offset cancellation. Due to the power and area con-
ual voltage from the last sample, the high-gain amplifier is straints, gml + gm2 = Gm. The partial derivative of t,with
no longer the best choice. In fact, the lowest-gain amplifier respect to g~l can be taken and set equal to zero to
reaches the 50-mV threshold before the other configura- determine the minimum comparator response time:
tions in this example (Fig. 4(b)), and the “best” choice is
highly dependent on this residual voltage. However, if this at, V& Cpl + c~atc~ Cpl + co=
=— = o. (13)
residual output voltage is nulled in an offset-cancellation
8%1 ~n dl + ‘(Gm - gml)’
cycle as in the first example, the high-gain amplifier is
always optimum. Therefore, a high-gain amplifier with
offset cancellation is used in designing the flash ADC Solving (13) for g~l gives
comparator.
v

D. Amplifier Optimization Gm -&w,, +Gad

/
. (14)
Our goal is to determine how the power and area should
be distributed throughout the amplifier in order to mini- ‘“’=wwZJ:/w
m
mize the comparator response time. We begin by determin-
162 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 1, FEBRUARY 1988

The optimum comparator response time can now be de- determined in terms of G,.. Thus
termined for a given power and area constraint.
2. Single-Stage Amplifier Plus Source Follower: By add-
ing a source follower,
from the high-gain
the latch capacitance is buffered
amplifier at the expense of adding some g,,ll =
‘ml%=izi
group delay. Also, the source follower has the added
benefit of buffering the high-gain amplifier from the l+l%zi+G
kickback charge of the dynamic latch.
(21)
The step response for the single-stage amplifier plus
source follower is approximated by

v=~—
pass
~mgml

pl ()
~ _ cLatch

gm3
u(t) (15)
g,,,2 =

‘+ti+lzz (22)

where gm3 is the source-follower transconductance. The c Latch

Gn,
time delay is thus M(CP1 + Coc)
/

‘d=
v pass Cp,
——+—
Vi. g~~
c~atc~

gm3
(16)
‘“3=1+
/%zrz+L5z” (23)
and the comparator response time is given by
Once the optimum transconductances are known, they
can be substituted back into (17) to determine the opti-
v C,l cLatc~ CP1+ Coc
~r=2!s-+ mum comparator response time for the single-stage plus
—+M (17)
‘in gml gm3 gm2 “ source-follower configuration.
3. Two-Stage Amplifier Plus Source Follower: Taking
this a step further, consider two single-pole amplifier stages
Since the total transconductance G~ must be held con-
cascaded together and buffered by a source follower. The
stant, then g~3 = Gm – g~l – g~z. Therefore, (17) becomes
transconductance for the two gain stages must be divided
by two in order to keep the total transconductance con-
stant. If the parasitic capacitance CPI is domiriated by gate
capacitance, it must also be divided by two. The resulting
pass voltage can be approximated by

By taking separate partial derivatives of (18) with respect

vp=,=:(~)2(t-R)2u(t). (24,
to g~l and g~ z and setting them equal to zero, the
following relationship results:
The time delay is

‘p11=gm2Ez3=
‘1’)
The comparator response time is given by
In order to determine the relationship between g~~ and
La. substitute g-, = G,,, – f!~j –%, into 07). Then take
separate partial derivatives of t, with respect to g~3 and
g,,,z and set them both
gives
equal to zero. Solving this result ‘=FEla+%+McpL
’26)
Note that (26) is the same as (17) with VPa,,/ V,. re-
c Latch placed by ~=. Therefore, the optimum transcon-
gm3 = gm2 (20) ductances ~an” be determined by making the above sub-
{ M(CP1 + co. )“
stitution into (21)–(23). Then, these transconductances can
be substituted into (26) to determine the optimum com-
By taking (19), (20), and remembering that g~l + gw,~+ parator response time for the two-stage plus source-fol-
gm,q= G,,,v the three individual transconductances can be lower configuration.
McCARROLL et al.: HIGH-SPEED CMOS COMPARATOR FOR USE IN AN ADC 163

I I I I 20 I I I I r
4 : J
18
‘,
2 E ----- I Stoge + SourceFollower ~16 — toc
‘1
—-2 Stoges t Source Follower . ----- fLatch
: 14 ‘1
o c
-=[2 ‘,
8
;10
-~ ‘,
6 8 ~.
v ..
..>>
4 ~6
....
-: 4 .-
-----
2 -------- ...-.--~~
:~ o I I , I , , , I I
o 0.02 0.04 006 0.08 0. [ o 0.02 0.04 0.06 0,08 0.1
Vpo$s (volts) (volts)
VP9SS

Fig. 6. Optimized comparator response time for three high-gain amph- Fig. 7. Latch and offset-cancellation amplifier response times versus
fier configurations for CPI = 200 fF, C~l,ch = 300 fF, COC= 200 fF, pass voltage for C ~ = 200 fF, C~a,Ch= 300 fF, CO, = 200 fF, P’&= 10
V,n = 10 mV, and G~ = 1 mS. mV, Gm=l mS, #=10 pm, L=2 pm, and AL= 0,1 pm.

4. Amplifier Optimization Results: Fig. 6 shows the opti- voltage is given by

mized time delay td versus pass voltage Vp,,, for the three
IAK AK
amplifier configurations considered above. It is interesting
VO, = Au + — = AK + ‘“’”C’ (29)
to note that the fastest amplifier configuration depends on &hL.t&K 4K2 -
the desired pass voltage. For pass voltages between O and
45 mV, the single-stage amplifier is fastest; for pass volt- By taking the partial derivative with respect to
of t~a,ch
ages between 45 and 80 mV, the single-stage amplifier g??!=.,=,and setting it equal to zero, the optimum response
source follower is fastest; for pass voltages greater than 80 time for a dynamic latch with a worst-case opposing offset
mV, the two-stage amplifier is fastest; etc. If a large pass voltage can be determined:
voltage were desired or if the input voltage were smaller (it
at Latch c Latch 1 a Vo,
is 10 mV in this example) higher order amplifiers become
optimum. For an 8-bit ADC with a dynamic range of dgmLa,ch= gm=atc, VP,., – V’o, I?gmL,,ch
2.5 V, 10 mV corresponds to 1 LSB and, as will be shown
c v out
in the next subsection, 50 mV is the optimum pass voltage. —
= in = o. (30)
Therefore, the one-stage amplifier plus source follower is d v – V*,
Latch () pass
the optimum amplifier configuration.
Since from (29)

E. Dynamic Latch Optimization dVO, AK

(31)
~gm.a,ch= 4K 2
It was previously mentioned that the dynamic latch has
a large offset voltage. Unlike the offset of the high-gain and since
amplifier, it is difficult to cancel the dynamic latch offset. AK AL
Therefore, it is important to understand the origin of this —= —— (32)
K L
offset so that its effects can be minimized.
Consider the dynamic latch shown in Fig. 1. Assume (30) becomes
that the initial voltage VP.,, has been applied by closing
atLatch AL
and then opening S3. The switches S5 are initially opened —=0=
~fkatch gm ,atc,AL
and switch S4 is thrown to the right. Since no current can 4KL VPa,, – AK –
flow through them, transistors 114gand J410 are initially ( 4KL )
off. Either or both transistors Mll and Nllz are on and the 1 \
small-signal voltage across their gates is given by 1 v out
–—in (33)
AL “
‘mLatch Vp=, _ Afi _ ‘mL.lch _
~out = ( ~pa~, – ~o,) 6? ’gmLatch/c’”” (27) 1 I
4KL

where the offset voltage VO~is assumed to oppose the pass Equation (33) can be solved iteratively for the optimum
voltage VPa~. The dynamic latch response time t Latch 1s gm ~ which can be substituted into (28) to obtain the
given by op~~um Since the dynamic
tL,,ch. latch-response time
t~,tchmust fit into
the offset-cancellation time t.C,the

()
CL v out can be found by plotting the
(28) optimum pass voltage VPa~~
t Latch= — in
g. v pass– Vo, “ optimum tLatchand t.C with respect to VP.,, and noting
Latch
where they intersect. This is done in Fig. 7 for VOUt= 1 V.
Using the square law approximation for an MOS transistor An optimum pass voltage of 50 mV has been chosen in our
Id= K(V~, – ~)2 where K = (pCOx/2)( W,/L) the offset design.
.,-.
104 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 1, FEBRUARY 1988

After a few nanoseconds, the switches S5 are closed ~dd

(Fig. 1) and the differential output of the dynamic latch

quickly approaches logic levels. Then, the storage latch is
enabled to hold the result.

NII 72 H
4 ‘}.,<’

III. CIRCUIT DESCRIPTION

optimum
For an 8-bit
topology
flash ADC it has been shown
consists of a single-stage amplifier
that the
plus
w“
1
“o t’””’ w“ C“C2T
1 J
@
T
source follower, an offset-cancellation amplifier, a dy- A
v%,
namic latch, and a storage latch as shown in Fig. 2. A
Fig. 8. Schematic diamms of hi~h-min anmlifier IIIUS source follower
detailed discussion of the circuit implementation of these
and offset-can;ell;tion am’ptifier.-
blocks in now given.
Fig. 8 shows the high-gain amplifier plus source follower
‘dd Vdd
and the offset-cancellation amplifier. The differential pair
? ?
consisting of transistors Ml and Mz constitutes the high- F F
R R
gain amplifier. Transistors M5 and M6 make up the
offset-cancellation amplifier. Since the drains of Ml and
A !49
Mz connect to the drains of M5 and M6, both the high-gain
F S3
amplifier and the offset-cancellation amplifier are cascoded
by transistors M3 and Md. This increases the output
MII
resistance of the amplifiers, thus increasing the voltage
gain. It also reduces the Miller effect, thus improving the
comparator response time. Transistors MT and M8 are the
source followers.
To insure that transistors Ml throug~ ~~ in the high
1
gain and offset-cancellation amplifiers are all operating in 1
v Ss
‘CONTROL % s

the saturation region, a simple common~mode feedback A

circuit is employed. The high impedance nodes of each

Fig. 9. Schematic of dynamic and storage latches,
differential amplifier are tied to the gates of source fol-
lowers. The output current of these two source followers is
summed into a diode-connected transistor producing a
voltage CMFB. This voltage is tied to the gate of the
current source transistor for the differential pair. The sum
of the currents from these source followers remains con-
stant with a small signal differential voltage at the high
impedance nodes. If a common mode voltage appears at
the high impedance nodes, the sum of the source follower
currents causes a change in voltage CMFB to return the
common mode voltage near O. This common mode feed-
back circuit has only one pole and therefore is unity gain
stable without compensation. A more complete explana-
tion of this circuit is discussed in [6].
The dynamic and storage latches are shown in Fig. 9. Fig. 10. Comparator die photo.

Transistors Mg through Mlz are the dynamic latch and

transistors ML3 through M16 make up the storage latch. IV. EXPERIMENTAL RESULTS
The dynamic latch is first turned on slowly by throwing
switch Sa to the right. The current source 1 is chosen to In order to verify the comparator architecture, a 3-pm
establish the optimum g~,,,C~.After a few nanoseconds, the CMOS comparator has been fabricated by MOSIS (see die
S5 switches are closed to quickly bring the dynamic latch photo in Fig. 10). Fig. 11 shows the comparator response
output near logic levels. (bottom trace) to a 900-mV peak-to-peak 1.44-MHz sine
A tri-state inverter separates the two latches. It is en- wave sampled at 23 MHz. Due to the time delay of the
abled one-half of a cycle after the dynamic latch is en- comparator, the storage latch, and the pad drivers, the
abled. Then, switches designated by Se are closed and the comparator output lags the input sine wave. The results
storage latch holds the result until the encode logic is agree quite well with SPICE simulations that predict the
enabled. 3-pm comparator will function up to 25 MHz.
McCARROLL et a[.: HIGH-SPEED CMOS COMPAWiTOR FOR USE IN AN ADC 165

ACKNOWLEDGMENT

Special thanks to L. Weaver for his initial work.

REFERENCES

[1] A. Matsuzawa, A. Kanda, M. Kagawa, and H. Yamada, “A 200

Msps 8-bit A/D converter with duplex gray coding,” in Proc. Symp.
VLSI Circuits, May 1987, pp. 109-110.
[2] Y. Yoshii, M. Nakamura, K. Hirasawa, A. Kayanuma, and K.
Asano, “An 8b 350-MHz flash ADC~’ in ISSCC Dig. Tech. Papers,
Feb. 1987, pp. 96-97,
[3] Y. Akazawa, A. Iwata, T. Wakimoto, T. Kamato, H. Nakamura, and
Fig. 11. Comparator response to a 1.44-MHz sine wave while being
H. Ikawa, “A 400 MSPS 8b flash AD conversion LSI,” in LSSCC
clocked at 23 MHz. Dig. Tech. Papers, Feb. 1987, pp. 98-99.
[4] T. Tsukada, Y. Nakatani, E. Imaizmni, Y. Toba, and S. Ueda,
“CMOS 8b 25 MHz flash ADC,” in ZSSCC Dig. Tech. Papers, Feb.
1985, pp. 34-35.
[5] M. Degrauwe, E. Vittoz, and L Verbauwhede, “A micropower
CMOS-instrumentation amplifier;’ IEEE J. Solid-State Circuits, vol.
SC-20. . rm.
. . 805-807. June 1985.
[6] J. W. Scott, W. L. Lee? C. H. Giancarlo, and C. G. Sodiui, “CMOS
implementation of an Immediately adaptive delta modulator,” IEEE
J. Solid-State Circuits, vol. SC-21, pp. 1088-1095, Dec. 1986.

Benjamin J. McCarroll was born in Ontario, OR,

on November 10, 1960. He received the B.S.
degree from the University of Idaho, Moscow, in
1983. In 1985 he began attending the Massachu-
setts Institute of Technology, Cambridge, where
he received the S.M. degree in 1987.
Fig. 12. Comparator noise and hysteresis while being clocked at For two years beginning in 1983, he worked
23 MHz. designing spectrum analyzers for Tektronix,
Beaverton, OR. He is currently working in the
Lab Instruments Division of Tektronix where he
Fig. 12 shows the comparator noise and hysteresis by designs high-speed integrated circuits.
applying a triangle wave to both the comparator input and
the X axis of the oscilloscope. The 10-mV noise window is
Charles G. Sodini (S’80-M’82) was born in Pitts-
due mostly to clock feedthrough in a track and hold that burgh, PA, in 1952. He received the B. S.E.E.
precedes the comparator. Two complementary strobes are degree from Purdue University, Lafayette, IN, in
1974, and the M. S.E.E. and Ph.D. degrees from
needed to control the track and hold. Since one is buffered
the University of California, Berkeley, in 1981
on chip and the other is not, truly complementary strobes and 1982, respectively.
are not being applied internally. He was a member of the technicrd staff at
Hewlett-Packard Laboratories from 1974 to 1982,
A 2-pm CMOS flash ADC using the comparator archi-
where he worked on the design of MOS memory
tecture discussed here is being fabricated. The clock and later on the development of MOS devices
feedthrough in the track and hold is reduced by the use of with very thin gate dielectrics. He joined the
faculty of the Massachusetts Institute of Technology, Cambridge, in 1983,
on-chip clock generation. The 2-~m comparator used in
where he is currently an Associate Professor in the Department of
the flash ADC has the dimensions 130 pm by 500 pm. Electrical Engineering and Computer Sciences. His research interests are
focused on IC fabrication, device modeling and device-level circuit de-
sign, with emphasis on analog and memory circuits.
V. CONCLUSIONS Dr. Sodini has served on a variety of IEEE Conference Committees
including the International Electron Device Meeting of which he is the
1987 Technical Program Vice Chairman.
A CMOS comparator design and optimization proce-
dure has been developed for use in an ADC. A dynamic
Hae-Seung Lee (M85) was born in Seoul, Korea,
latch preceded by an offset-cancelled amplifier has been
in 1955. He received the B.S. and M.S. degrees in
used to build a fast and precise comparator. The use of electrical engineering from Seoul National Uni-
pipelining within the comparator enabled the offset-cancel- versity, Seoul, Korea, in 1978 and 1980, respec-
tively. He received the Ph.D. degree in 1984 from
lation and latch functions to be accomplished simulta-
the University of California, Berkeley.
neously. In addition, an optimal distribution of power and In 1980, he was a Member of the Technicaf
area within the amplifier was developed so that the com- Staff in the Department of Mechanical Engineer-
ing, Korean Institute of Science and Technology,
parator response time was minimized.
where he was involved in the development of
Using a 3-pm CMOS process, a single comparator has electro-mechanical systems. In 1984. he ioined
been built and tested. It operated at a minimum response the faculty of the Massachusetts Institute of Technology, Cam&idge,
where he is now an Assistant Professor. Since 1985, he has acted as
time of 43.5 ns with a noise and hysteresis window of
Consultant to Analog Devices Semiconductor and Lincoln Laboratory.
10 mV that is limited by clock feedthrough in the input His research interests include CMOS and BiCMOS integrated circuits, IC
track and hold. fabrication technologies, and solid-state sensors.