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4. In the next wizard dialog, click the Add files button to open the Add Files to Design dialog box.
5. In the Add Files to Design dialog box, select the counter.vhd source file from the src folder of the
Loadable_counter sample design folder.
6. Select the Make local copy check box, and then click Add to copy the counter.vhd file to your design directory.
Then click Next to display the last wizard dialog.
7. Specify desired synthesis and implementation tools for the current design (if there are any installed). Choose
the default family, block diagram configuration and default HDL language. Click the Next button.
9. The next wizard dialog shows a summarized design specification so that you can view it before the design will
be created.
Select the Compile source files after creation check box, and then click Finish.
The design will be created and the counter.vhd file will be compiled.
Choose the counter as a top-level.
After this operation, the Design Browser window should look as shown below:
5. The first Test Bench Wizard dialog will appear in which you have to choose the desired testbench type.
The Signals found in file box will display input ports found in the specified waveform file, and the UUT ports box
will display the input ports of the COUNTER entity. Note, that the COUNTER entity is the UUT entity. Click Next.
8. The next wizard dialog allows you to specify the names of the testbench entity, architecture and VHDL source
file. The wizard automatically suggests default names. Click Next to accept them and go to the next wizard dialog.
9. The last dialog displays the paths of the files that will be generated by the wizard.
They are:
• the testbench source files
• a simulation macro file which automatically compiles the testbench files, inserts the UUT ports into the
Waveform Editor window and runs simulation of the testbench
• an additional source file containing a configuration declaration for timing simulation (generated optionally)
10. Select the Generate check box to generate the optional configuration file, and then click Finish.
11. The wizard will generate the testbench files and attach them to the design in a special file folder, WAVES.
Note, that Design Browser uses a special icon for testbench source files to distinguish them from regular sources.
The Counter_TB.vhd file will open in the HDL Editor window. View the source code to see how the testbench has
been constructed by the wizard.
12. In addition to the files created by the wizard, the WAVES folder also contains external auxiliary files that have
been attached to the design. The external files are represented in Design Browser by the icon.
13. Click the icon to the left of the WAVES folder on the Files tab of the Design Browser. The WAVES folder
contents is as shown in the figure below:
Timing Simulation
The final stage of the design development process is the verification of the design behavior after its
implementation. The Place & Route implementation tools produce structural VHDL code. Such code is usually
supplied with SDF file with timing information. So obtained source file can be verified with the same testbench that
has been used for functional simulation. In this tutorial, you will not have to run implementation software by
yourself. Instead, you will use implementation files from the original sample design Loadable_counter, suitably
modifying the testbench macro for the needs of timing simulation.
1. Select Add Files to Design from the Design menu. In the Add Files to Design dialog select the src folder
located in the Loadable_counter folder, and then select the following two files:
• counter_tim.vhd - the backannotated post place-and-route VHDL structural code
• counter_tim.sdf - SDF (standard delay format) timing file
Make sure that the Make local copy check box is selected, then click Add.
2. Switch to the Files tab of Design Browser.
Now you will have to edit the counter_TB_tim_cfg.vhd configuration and the counter_TB_runtest.do macro so that
they can be used for timing simulation.
3. Double-click the counter_TB_tim_cfg.vhd file on the Files tab. The file will open in the HDL Editor. Uncomment
the line:
use entity work.ENTITY_NAME (ARCH_NAME);
Replace the ENTITY_NAME and ARCH_NAME with the entity and architecture names from the backannotated
VHDL file. The line should read as follows:
use entity work.COUNTER (STRUCTURE);
7. View the results of timing simulation in the Waveform Editor window and compare them with the results of the
functional simulation.
As the frequency of 125 MHz has been chosen for the CLK input signal, which is too high for the real
synchronous counter implementation, the output ACTUAL_Q signal value does not change as expected. Note,
that the ERR_STATUS signal value is 1, indicating discrepancies between EXPECT_Q and ACTUAL_Q signals.
View the log file to see how discrepancies are represented in it.
To do so, switch to the Resource tab of Design Browser, click the icon to the left of the Logs folder, and then
double-click the src\WAVES\counter_report.log label.
a) In Waveform Editor, switch to the Edit mode by clicking the toolbar button.
b) Rest the mouse pointer over the origin of the waveform area to be selected. Press and hold the mouse button.
The mouse pointer will adopt a new shape: . If the mouse pointer tends to switch to the event-dragging mode,
hold the Ctrl key.
c) Move the mouse so as to select the desired area. The selection should contain all waveforms. The tooltip will
show the time range of the current selection.
d) Release the mouse button.
4. Click the right mouse button, then select the Stretch command from the shortcut menu. This will open the
dialog shown below:
5. In the Scale box enter 1000%, and then click OK. This will change the CLK frequency to 12.5 MHz.
8. Select the Waves vectors (*.VEC) from the Save as type box, select the Functional.vec file from the
\\src\WAVES folder, and then click Save. Click Yes when asked if you want to replace an existing file.
Select the L_counter design library on the Files tab of the Design Browser, click the right mouse button, and
then choose Delete simulation data from the shortcut menu.
Note, that the asim TIMING_FOR_counter -sdftyp /UUT=$DSN\SRC\counter_tim.sdf command instructs the
simulator to apply the time delays from the counter_tim.sdf file. This will result in certain delays of the output
signal relative to the falling edge of the clock signal. The WAVES-based testbench declares the window frames, in
which it will compare the actual signal values with the expected signal values during simulation. For the purpose
of the functional simulation the default WND_BEGIN_DEFAULT and WND_END_DEFAULT window parameters
have been used. The appropriate declarations can be found in the counter_TB_declaration.vhd file:
constant WND_BEGIN_DEFAULT: EVENT_TIME := 1 ps;
9. Double-click the counter_TB_declaration.vhd file on the Files tab of Design Browser to open the file for editing.
In the editing window, enter WND_BEGIN_DEFAULT in the Find box located on the left of the Find Next toolbar
button . Next, click the Find Next button, and then replace the values in the constant declarations as shown
below:
constant WND_BEGIN_DEFAULT: EVENT_TIME := 40 ns;
constant WND_END_DEFAULT: EVENT_TIME := 50 ns;
The Console window still shows many VitalGlitch warnings. Choose End Simulation from the Simulation menu.
If you want to disable the VitalGlitch warnings edit the counter_tb_runtest.do macro, adding the switch -noglitch to
the asim command line.
Applies To: