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I. Introduction

The Objective of this lab work is to implement and

test registers on FPGA development board by mean of
Verilog HDL, which used to design and document
electronic systems. At the lab work will be used NI
Digital Electronincs FPGA board of XC3S500E series
Fig 1.1 Schematic high-level diagram of MIPS datapath from an
and XILINX ISE compiler programming environment. implementational perspective, adapted from [Maf01].
To simulate work of a Flip-flop with a Positive Edge
Implementation of the datapath for I- and J-format
Clock register and to generate a few states of it, and to
instructions requires two more components - a data
simulate work of 4-bit Register with Positive-Edge
memory and a sign extender, illustrated in Figure 1.2.
Clock, Asynchronous Set and Clock Enable on FPGA
The data memory stores ALU results and operands,
board and to generate a few possible states of the
including instructions, and has two enabling inputs
register. Each instance of Q output (1 or 0), has to be
(MemWrite and MemRead) that cannot both be active
recorded in the corresponding truth table.
(have a logical high value) at the same time. The data
The datapath is the "brawn" of a processor, since it memory accepts an address and either accepts data
implements the fetch-decode-execute cycle. The general (WriteData port if MemWrite is enabled) or outputs data
discipline for datapath design is to (1) determine the (ReadData port if MemRead is enabled), at the indicated
instruction classes and formats in the ISA, (2) design address. The sign extender adds 16 leading digits to a
datapath components and interconnections for each 16-bit word with most significant bit b, to product a
instruction class or format, and (3) compose the datapath 32-bit word. In particular, the additional 16 digits have
segments designed in Step 2) to yield a composite the same value as b, thus implementing sign extension in
datapath. twos complement representation.

Simple datapath components include memory

(stores the current instruction), PC or program counter
(stores the address of current instruction), and ALU
(executes current instruction). The interconnection of
these simple components to form a basic datapath is
illustrated in Figure 1.1. Note that the register file is
written to by the output of the ALU. As in Section 4.1,
the register file shown in Figure 1.2 is clocked by the
Fig 1.2 Schematic diagram of Data Memory and Sign Extender,
RegWrite signal.
adapted from [Maf01].
II. Methodology


 NI Digital Electronics FPGA Board (XC3S500E)

Fig 2.2. Truth Table: Flip-flop with Positive Edge Clock
 USB Connector
2.2 Assignment for a 4-Bit Register with Positive
 +15V DC Power Adapter
-Edge Clock Asynchronous Set and Clock Enable

 PC
2.2.1 Conducting the Experiment for a 4-Bit
Register with Positive -Edge Clock Asynchronous
Set and Clock Enable

2.2.2 The Truth Table

Fig 2.1. Materials

2. Datapath: Register Set Implementation Fig 2.3 Truth Table: 4-Bit Register with Positive Edge
2.1 Assignment for a Flip-flop Register
III. Results and Discussion
2.1.1 Conducting the Experiment for a

1. Hardware Setup

2. Creating New Project

3. Creating Verilog Source

4. Entering Timing Constraints

5. Implementing the Design

Fig 3.1 Timing Constraints
6. Assigning Pin Location Constraints

7. Reimplementing the Design and

Verifying Pin Lcation

8. FPGA Programming

2.1.2 The Truth Table

The output of state circuitry does not just depend on its
input — it also depends on the past history of its inputs.
In other words, the circuitry has memory.

State circuitry includes anything that can "remember"

bits of information. This includes memory, registers, and
the program counter.

Fig 3.2 Pin Location Constraints

The basic element of state circuitry is a flip-flop. A
flip-flop stores one bit of data. Multiple flip-flops can be
combined to form a multi-bit state element called a
register. Multiple registers can be combined into a
register bank.

Logic circuits use two different values of a physical

quantity, usually voltage, to represent the boolean values
true (or 1) and false (or 0). Logic circuits can have
inputs and they have one or more outputs that are, at
least partially, dependent on their inputs. In logic circuit
diagrams, connections from one circuit's output to
Fig 3.3 Simulation
another circuit's input are often shown with an
arrowhead at the input end.

In terms of their behavior, logic circuits are much

like programming language functions or methods. Their
inputs are analogous to function parameters and their
outputs are analogous to function returned values.
However, a logic circuit can have multiple outputs.

V. References

Fig 3.4 Summary Reports 

IV. Conclusion
A processor's datapath is conceptually organized into cuits.xhtml
two parts: State elements hold information about the
state of the processor during the current clock cycle. All
registers are state elements. Combinational logic
determines the state of the processor for the next clock
cycle. The ALU is combinational logic