A Survey on Sign Detection in Residue Number System Using

Various Adders
S.Pradeep1, S.Selvi2
Assistant Professor, Dept. of ECE,M.Kumarasamy College of Engineering(Autonomous),Thalavapalayam, Karur.
sspradeep20@gmail.com, selvi0412@gmail.com

Abstract : RESIDUE number systems (RNS) have been for a long time a topic of intensive
research. Various methods have been proposed so far for the efficient operation of systems using
RNS. One of the complex part in a RNS is the sign detection unit. This paper gives a survey on
the design of an optimized SD Unit by replacing the adder part of the SD Unit with various
efficient adders which have been proposed day to day. Adders are the basic circuits which have
been used in various logic circuits for arithmetic and logic operations. Improving the adder
circuit improves the performance of the whole circuit. Optimization is achieved through the use
of various adders in the SD unit of RNS. Sign Detection (SD) in base uses an adder part which
can be modified with various adders in order to improve RNS. In the conclusion part, an idea
have been proposed to further improve the SD unit by using the D-Latch based Carry Select
adder (CSA).
Keywords-RNS, SD Unit, CSA,D Latch
1. Introduction
Residue Number System is a topic of interesting research for a long period. It is
specifically used in digital signal processor ICs in the form of ASICs. It is of interest as it
subdivides a larger number system into a small group of residues and carry out the operations in
parallell. By using this parallelism method it also reduces the power consumption.
The benefit of RNS is there is no carry propagation. The arithmetic operations in RNS are
calculated in terms of modulus operations. Even though the arithmetic operations such as
addition and multiplication are done easily, the sign detection part involves a complex method in
this residue number system.
Some methods such as full mapping of residues to positional system and also a class of
monotonic functions have been developed to identify the sign of a residue number system.
Various methods have been proposed to identify the sign in an easier manner for a
residue number system. Some of the methods are based on a specific moduli set[1].Some
algorithms follow mixed radix conversion algorithm.[2].
This paper discuss about the various Mixed Radix Conversion methods based on the
Chinese Remainder theorem(CRT) and modified Chinese Remainder Theorem(MCRT). The
method described in this required only one comparison for detecting sign of the result.
2. Survey on Various Sign Detection Units
More researches were carried out for converting RNS to other number systems. Hardware
implementations were made easier from day to day. This paper discusses about the various
methods used for detecting sign in a Residue Number System.
 2.1 Sign Detection for integers in Extended Moduli Set {2n-1,2n-k,2n+1}
The Sign detection can be made easier by calculating the digits using the following
formula :
d1=x1,
d2=<(x2-x1)*2n-1>2n-1,
d3=<(x1-x3)+d2,k-1:0*2n+d2>2n+k
Here[1], it checks the logic value of the most significant bit d3,the following architecture
shown in fig.1 is used along with the arithmetic unit for sign detection.
This architecture uses carry look ahead adder to calculate MSB d3 instead of carry
propagation adder CPA. It also reduces the complexity of detecting overflow.
If overflow is detected, the result can be assigned residues with respect to the maximum
positive or minimum negative numbers depending on its correct sign.

Figure 1. Sign Detection Unit

This particular architecture used prefix adders in the sign detection unit and targeted the
ASIC market where it can be used for specific applications.
This architecture also showed an considerable improvement on Area Delay product (AD)
and energy consumption.
2.2 Sign Detection based on MRC II Theorem
In this paper [2], the sign detection unit was designed based on the Modified MRC II
Theorem.
Modified MRC II Theorem :
The following algorithm can be used to calculate MRC coefficients (a1,a2,...,an) for the
RNS number (r1,r2,...,rn) over the moduli set (m1,m2,...,mn)
If |M-1i-1|mi=1, then ai= (Xi-Xi-1) for 2 ≤ i ≤n
where Xi=aiMi-1+Xi-1,X1=a1=r1,Mi-1=∏𝑖−1 𝑗=1 𝑚 j= mi-1 Mi-2 = Mi-2 mi-1,M1=m1,m0=1.
The figures corresponding to this are shown in figure 2 and 3.Sign detection is done
based on the modified MRC II theorem.
Theorem :(Optimum sign detection algorithm based on MRC-II).If mn is even in the moduli set
(m1,m2,...,mn), then the sign detection algorithm that is based on MRC coefficients is optimum.
This sign detection algorithm requires at most one comparison to detect sign. Also it
eliminates the use of look up table which was used in the MRC theorem.It does not require a set
of look up table for non modular RNS operations. The module architecture is shown in fig.2 and
the sign Detection architecture is shown in fig.3Thus this method comes over the complexity of
the earlier used methods.
2.3 Residue to Binary Converter adder for Sign Detection Unit
To implement the modulo (22k-1) addition of three2k-bit numbers efficiently, we may use
2k full adders as carry save adders (CSA) to convert the three 2k -bit numbers into two [3].The
carry-out from the most significant bit is fed to the least-significant-bit position. Then, a fast 2k -
bit carry propagate adder (CPA), with its carry-out connected to its carry-in, is used to perform
the modulo (22k-1) addition of the two numbers to yield the final result. The same weighted bits
from each number are the inputs to a full adder.
This new architecture shown in fig.4 reduced the delay upto 40 % and the hardware
complexity was also reduced than the earlier existing methods.

Figure 2. Modified MRC II Sign Detection Unit-Single Block

Figure 3. Residue Number System Sign Detection Unit-Operational Diagram

 Figure 4. Modulo (22k-1) addition of three 2k-bit numbers Implementation

Similarly there are so many systems to do conversion between RNS system to binary and
to convert between RNS and decimal system.Hence this adder can be tested on the adder part of
our RNS Systems in order to get an optimized sign detection unit.
2.4. Fast Sign Detection Algorithm for RNS
A fast algorithm for the sign detection of numbers given in RNS is presented. The sign
detection function can be done by 3 bit wide addition operation of which two are performed
parallel. It uses the Residue to binary converter which will be used for many arithmetic
operations. It subdivides the RNS representation into RNS positive and RNS negative and then
the conversion is done. This sign detection algorithm is based on the new Chinese Remainder
Theorem II.
In case of this Multi operand adder one can also use a carry select adder in place of the
Prefix adder. Whereas this Carry Select Adder has shown to be in better performance than the
normal parallel prefix adders.Also here the sign detection units are based on the reverse
converter which can be used for a longer bit conversion. This method was also proved to be
faster by two logic levels. As the RNS range is splitted , the sign detection operation is also made
faster. Hence this type of sign detection unit in RNS is used in high precision systems.

2.5 Delay and Area Efficient Adder based Sign Detector

As it has been discussed in the last session, the efficiency in terms of delay can be
increased by using a carry generator unit as shown above in the Multi-operand adder.

Figure 5. Modified Chinese Remainder Theorem Based Sign Identification Unit

 Figure 6. Adder for Multi Operands
This is in case actually a part of a carry- look ahead adder which is more fast and area
efficient too than the already used prefix adder.

Figure 7. Cin carry Generator

Also it has been shown that this carry generator based sign detector shows better
performance than the earlier proposed systems in terms of all three basic factors namely area,
power and delay.

Figure 8. Sign Identification Unit With Carry Propagation based Carry Generation Unit

3.Conclusion:
This paper has given you an overall idea of the complexity that is faced in the sign
detection unit of RNS system and how the factors like area, delay and power has been improved
in each and every work. We can also try to improve further performance of the Sign detector unit
by replacing the Multi operand adder by a still more efficient adder such as carry select adders
based on binary to one conversion or a CSA based on a D latch.

ACKNOWLEDGMENT
Our thanks to M.Kumarasamy college of Engineering for offering us the opportunity to
do this wonderful project, and to Dr. V. Kavitha , Principal,Dr.K.Sundararaju,Dean(Electrical
Engineering) and our HoD Prof. A. Sridevi whose contribution in stimulating suggestions and
encouragement, helped us to coordinate our project, especially in writing this paper.

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