PH-315 Portland State University

DIGITAL TO ANALOG CONVERTER (DAC)

1. PURPOSE:
Construction of digital-to-analogue converters using different techniques, namely the
scaled resistors into summing junction, and the R-2R ladder.

Figure. 1 Digital vs analog signal processing.

2. CONVERTING DIGITAL TO ANALOG SIGNALS:

It is often necessary to convert analog signal to an accurate digital number, and vice versa.
For example, in applications where a microprocessor is controlling an experiment, the
analogue signal from a sensor needs to be converted into digital form so it can be
communicated to the microprocessor. After the processing takes place in the digital form,
the output from the microcontroller needs to be converted back to the analogue form to
communicate with the analogue world.
In this lab session we will consider the case of digital to analogue conversion (DAC). The
DAC techniques presented here are not aimed at developing skills in converter designs.
Instead, they aim at presenting the advantages and disadvantages of each method. In most
cases, when embarked in an electronic project, one rather buys commercially available chips
instead of building a converter from scratch. An understanding of DAC methods, however,
will guide you in selecting the more suitable one for the project at hand.

2.1 Scaled resistors into summing junction

Implement the circuit shown in Fig. 2.
a) Notice that the circuit has an input count from 0 (when all the inputs are OFF) to 15 (when
all the inputs are HIGH.)
b) Verify that the circuit generates an output voltage from zero to (almost) 5 Volts. The exact
value is estimated below.
EXACT CALCULATION
b1) Verify that the total maximum current through the gain resistor is given by,
 1 1 1 1
I f  Vref (1   2  3 )
10k 2 2 2

b2) Verify that the circuit generates an output voltage from zero to,
5 k 1  (1 / 2) 4
Vmax  Vref
10 k 1  (1 / 2)
15
Vmax   Vref 
16

Vref = 5 Volt

MSB 23 10k, 1%
i3
5k, 1%
20k, 2%
22 If
i2 VCC
- Vout
40k, 4% i1 If + Analog
21 LM358AP
-VCC output
i0
80k, 8%
LSB 20
Digital input

Fig. 2 Four-bit DAC.

Example of a binary input: 1 0 1 0

MSB LSB

We need an experimental implementation that reflect the corresponding weight of the

binary digits,
23 23 23 23

Calibration voltage: Contribution to the total output voltage from bit,

5𝑉
𝑉𝑗,𝑜𝑢𝑡 = − 𝑅 5𝑘, j= 0, 1, 2, 3
𝑗
 MSB 23 5V 10k, 1%
i3
5k, 1%
20k, 2%
22 0V If
i2 VCC
- Vout
5V 40k, 4% i1 If + Analog
21 LM358AP
-VCC output
i0
80k, 8%
LSB 20 0V

Theory Experimental implementation

Experimental implementation of the binary input: 1 0 1 0

c) GENERALIZATION (for n-bits DAC)

In Fig. 2, consider adding input bits on the left side (i.e. adding resistors whose values
increase by a factor of 2) until n inputs are completed.
Show that the maximum input count is 2n-1 (when all the n bits set to 1.)
Show analytically that the circuit generates output voltages from zero to
2n  1
Vmax  Vref [ n ]
2

d) REQUIRED PRECISION of the RESITORS

d1) Show that for a given input of resistance R in the DAC circuit, the contribution (only
Vref
from that input) to the output voltage is Vout   5k .
R
Hence, a smaller resistance R produces larger currents (Vref/R) and has a larger
contribution to the output voltage.
This explains why in Fig. 2:
 the input with smaller resistance (10 kin this case) is assigned to represent the
most-significant-bit (MSB); and
 the input with higher resistance (80 kis assigned to represent the least-
significant-bit (LSB).
 d2) If the value of the resistor “R” were to have an uncertainty R show that the
corresponding uncertainty in the out voltage Vout is given by,
Vout R

Vout R
Thus, for a given required precision in the output voltage, a higher value of R can
afford a larger R uncertainty (lower precision). Hence, the resistance at the MSB
input (lower resistance R) requires smaller R uncertainty (i. e. higher precision) in
the resistance value.

e) Make a table of the digital inputs in one column and the corresponding output voltage in
another column, and verify if the obtained experimental values correspond with the
predicted ones.

2.2 R-2R ladder

The scaled resistor technique becomes awkward for higher bits DAC. (A 12-bit converter
would need a 2000:1 range of resistor values) with corresponding precision in the MSB
input. This becomes impractical. The R-2R ladder, shown in Fig. 3 offers an elegant
alternative.
 Only two resistor values are needed.
 Although the resistors must be precisely matched, the actual value of the resistors is not
critical.

2i i i /2 i /4 i /8
VREF vin
R= 50k
= 5 Volts R R R 2R
2R 2R 2R 2R

50 k
If
VCC
- Vout
3 2 1 0 +
2 2 2 2 LM358AP Analog
output
MSB LSB -VCC
Fig. 2 Four-bit DAC.

a) Check if suggested distribution of currents along the network of resistance is correct.

b) Calculate and verify experimentally that the contribution to the output voltage from
the MSB is -2.5 V.
 Verify that the contribution to the output voltage from the other inputs decrease by a
factor of 2, from bit to the next.
c) Make a table of the digital inputs in one column and the corresponding output voltage
in another column, and verify if the obtained experimental values correspond with the
predicted ones.
d) Calculate (show all your steps) and verify experimentally that the maximum
magnitude of the output voltage is Vref 15/16.