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This paper proposes a new design and analysis of Single DC Source H-bridge inverter (SDSI) topology as a multilevel
inverter to reduce the cost, installation space of marine electric systems. This new design converts the SDSI into a buck
converter (BC) and multilevel inverter (MLI). The newly designed single DC source multilevel inverter (ND-SDCMI) does
not require a change its structure and blocking voltage to create n numbers of levels. The ND-SDCMI is compared with
existing single DC source multilevel inverter (SDCMI) topologies in terms of the number of levels of output voltage,
blocking voltage, switching devices, total harmonic distortion (THD), and other components. Simulation results of THD,
efficiency, blocking voltage, and output voltage for a 12-level ND-SDCMI are discussed in detail. Prototype 12-level ND-
SDCMI is implemented and programed using a relatively inexpensive F28027 microcontroller.
voltage waveform. This paper proposes a new design Table 1 presents the current flowing through the
and analysis for the conventional SDSI depicted in circuit and load voltage for operational modes I and II
Fig. 1. The new design converts the conventional and for D > 0.5, D < 0.5. The analysis has been
SDSI into a BC; it creates a positive and negative described below:
voltage from a single DC source by suitable control of In mode I, the voltage across the inductor increases
the duty cycle. The values of the duty cycle, inductor, as given in Eq. (1).
and capacitor have been selected to create n number
di
of levels in the output voltage of ND-SDCMI. The VL L … (1)
ND-SDCMI offers numerous advantages in terms of dt
size, complexity, installation space, number of VL
i TON S 11 , S 14 … (2)
components, and blocking voltage over the existing L
SDCMI.
By applying Kirchhoff’s voltage law to mode I, Eq.
Materials and Methods (3) is obtained
V in V L V RL 2V Q
New Design of SDSI … (3)
The circuit diagram of the conventional SDSI is
Substituting the Eq. (3) in (2), we can obtain the rate
depicted in Fig. 1. The circuit consists of a single DC
of rise of current in the circuit given by Eq. (4).
source, an H-bridge, an inductor, and a capacitor.
Rate of rise of current
Basically, the proposed design enables an SDSI to
Vin VRL 2VQ
function as a BC, which, by suitable design and i ( ) TON S 11, S 14
control of the duty cycle, can be converted into an L … (4)
MLI. The design and operation of the SDSI as BC or By applying Kirchhoff’s voltage law to mode II,
MLI is discussed in next section. Eq. (5) is obtained
The topology works in two modes as a BC. The V L V in V RL 2V Q … (5)
two operational modes are described in TABLE 1.
Now, substituting Eq. (5) in (2), the rate of decrease
of current, when the inductor is discharged can be
written as Eq. (6).
Rate of decrease of current
T
V in 2 V
Q
ONS11 ,S14 OFFS11, S
Operational D > 0.5 D < 0.5
14
mode Current Load Current Load The duty cycle is defined by Eq. (8)
Flowing voltage VRL Flowing voltage
through the through the VRL
circuit circuit TON S
D 11 , S14
m =1 to n for even n (when zero level is not considered) The settling time of the output voltage of the ND-
Figure 2 shows the 13 level load voltage as per SDCMI is given by Eq. (16). Equation (16) must be
Eq. 11. To create 13 levels, d = 12, m = 1 to 12 and satisfied to create n levels of output voltage. To
the 12 different values of are required, as shown in satisfy this condition, the value of Lmin is calculated
Fig. 2. The duty cycle Dm is constant for the period using Eq. (17).
m 1 m . If the value of m is known, as shown in Fig. (2),
the value of inductor can be calculated.
R L min ( m 1 m )
L
4L … (19)
The other method determines the value of the
inductor using Eq. (18) and Eq. (19). In this paper, the
value of the angles of output voltage m has been
calculated by comparison of multilevel waveform
Fig. 2 — The 13-level load voltage of ND-SDCMI steps with the sinusoidal wave depicted in Fig. 2.
1202 INDIAN J. MAR. SCI., VOL. 47, NO. 06, JUNE 2018
Step 5: Determine the minimum value of filter depicts that the blocking voltage remains constant
capacitor using Eq. (20). when n number of levels are created, which also
indicates that the cost of the semiconductor device of
VRL max
VRL max (1 ) the ND-SDCMI is independent of the THD or number
Vin of levels in the load voltage. If the number of levels in
C min 2
8Lf s … (20) load voltage increases, the THD decreases. Therefore,
the basic advantage of the new designed topology is
The cost of semiconductor switches depends upon that the overall cost of the proposed ND-SDCMI
the blocking voltage and number of semiconductor remains constant despite an increase in the power
devices used in a topology19. The maximum quality of the output voltage.
blocking voltage of the H-bridge based MLI has been
The efficiency of the ND-SDCMI is calculated
calculated20-21. Maximum blocking voltage of ND-
using Eq. (25). The analysis of the switching losses,
SDCMI was calculated using Eq. (21).
conduction losses of semiconductor devices, and
Vblock 4Vin Vblock11 Vblock14 Vblock12 Vblock13 conduction losses of diodes of the ND-SDCMI is
… (21) performed using MATLAB/Simulink.
In this topology S11 and S14 work together while The output power (Pout) and input DC voltage
S12 and S13 work simultaneously. The blocking (Vin) are assumed to be 1 kW and 200 V,
voltage for the ND-SDCMI can be written using respectively. The switching time, RON and diode
Eq. (22). forward voltage are calculated using the MOSFET
IRF640 datasheet. The analysis of the efficiency is
Vblock11 Vblock14orVblock12 Vblock13 performed by substituting power losses in Eq. (25)
… (22)
when the duty cycle varies from 0 to 1 as shown in
By substituting Eq. (22) in Eq. (21), the maximum Fig. 4(a). Figure 4 (a) shows that the maximum
blocking voltage is given by Eq. (23). efficiency of the ND-SDCMI
Vblock 2(Vblovk11 Vblock12 ) 2(Vblock13 Vblock14 ) Pout
… (23) Efficiency
The THD is calculated using the MATLAB/ Pout PLoss … (25)
SIMULINK-FFT toolbox as the number of level
increases in the output voltage. The THD of output The analysis of the efficiency is performed by
voltage of the ND-SDCMI is given in Eq. (24) substituting power losses in Eq. (25) when the duty
cycle varies from 0 to 1 as shown in Fig. 4(a).
49
vx Figure 4 (a) shows that the maximum efficiency of the
THD v1 ND-SDCMI is 98.57% and 99.58% at the minimum
x2
… (24)
and maximum duty cycle, respectively. The selection
The blocking voltage of the ND-SDCMI depends of the duty cycle improves the efficiency. The
upon the input voltage given in Eq. (21). Figure 3 efficiency varies from 98% to 92% when the duty
cycle varies from 0 to 0.45 and from 99% to 94%
when the duty cycle varies from 1 to 0.55, as depicted
in Fig. 4 (a). If the duty cycle of the ND-SDCMI
operates from 0 to 0.45 and from 0.55 to 1,
the losses are minimum and the efficiency improves.
The duty cycles are selected and the efficiency and
THD are calculated upto 13 levels as depicted in
Fig. 4(b).
Figure 4 (b) shows that the maximum efficiency of
the ND-SDCMI is 99.5% for two levels; however,
when the number of levels in the output voltage
increases, the efficiency marginally decreases. Figure
Fig. 3 — THD and blocking voltage obtained by simulation as the 4 (b) shows that to obtain a THD less than 5% of
number of levels increases in the output voltage (Vin = 12 V) the fundamental voltage, ND-SDCMI requires at least
SINGH et al.: LOW COST MULTILEVEL INVERTER FOR MARINE ELECTRIC SYSTEMS 1203
TABLE 2 — Comparison of different parameters of an ND-SDCMI with reported SDCMI, when h=1
Ref. Vblock in volts No. of levels No. of No. of switches THD for
Expression Vdc = 12V Expression h=1 levels Expression h=1 h=1
h=1 shown in
reported
study
[22] >(4 Vdc ) >48 3 3 3 4 4 <5%
Fig. 10 — Experimental results of the 12-level load voltage, the voltage across the inductor, and gate pulses are obtained from
microcontroller for semiconductor switches S11, S14 and S12, S13.
Conclusion 3 Colak, I., Kabalci, E., Bayindir, R., Review of multilevel
The ND-SDCMI uses fewer components than voltage source inverter topologies and control schemes,
Energy conversion and management Elsevier, 52(2011)
existing topologies do to generate the same number of 1114-1128
levels of output voltage. Maximum blocking voltage 4 Rodriguez, J., Lai, J.S, Peng, F.Z., Multilevel inverter: A
of the ND-SDCMI topology does not change with an survey of topologies, controls and application, IEEE Trans.
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5 Fan, B., Tan, G.Z., Fan, S., Ye J., Comprehensive predictive
cost of the MLI is reduced. Electronic circuit for
control of neutral-point clamped balancing for back-to-back
experimental study has been designed. The efficiency three-level NPC converter. Journal of Central South
of the proposed topology is greater than 92% if it is University: Science & Technology, 21(2014) 4210-4219
operated at duty cycles varying from 0 to 4.5 and 6 Gupta, K.K., Jain, S., A novel multilevel inverter based on
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Experimental results have been obtained for the switched-diode multilevel converter with minimum number
output voltage, THD, voltage across the inductor and of power electronic components, IEEE Trans. on Ind.
gate pulses of H-bridge. The experimental results Electron, 61 (2014) 5300-5310
8 Palanivel, P., Dash S.S., Analysis of THD and output voltage
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less than 5% THD in the output voltage. Experimental pulse width modulation techniques, Journal of IET power
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