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Indian Journal of Geo Marine Sciences

Vol. 47 (06), June 2018, pp. 1199-1207

Single DC source H-bridge topology as a low cost multilevel inverter for


marine electric systems
Jiwanjot Singh*, Ratna Dahiya & Lalit Mohan Saini
Department of Electrical Engineering, National Institute of Technology,
Kurukshetra, Haryana, India,
*[E-mail: jiwanjot18@yahoo.co.in]

Received 19 September 2016; revised 28 November 2016

This paper proposes a new design and analysis of Single DC Source H-bridge inverter (SDSI) topology as a multilevel
inverter to reduce the cost, installation space of marine electric systems. This new design converts the SDSI into a buck
converter (BC) and multilevel inverter (MLI). The newly designed single DC source multilevel inverter (ND-SDCMI) does
not require a change its structure and blocking voltage to create n numbers of levels. The ND-SDCMI is compared with
existing single DC source multilevel inverter (SDCMI) topologies in terms of the number of levels of output voltage,
blocking voltage, switching devices, total harmonic distortion (THD), and other components. Simulation results of THD,
efficiency, blocking voltage, and output voltage for a 12-level ND-SDCMI are discussed in detail. Prototype 12-level ND-
SDCMI is implemented and programed using a relatively inexpensive F28027 microcontroller.

[Keywords- Buck converter, multilevel inverter, single DC source multilevel inverter]

Introduction the CHBMLI, a single DC source CHBMLI has been


Multilevel inverters have been used in electric used with single-phase and three-phase transformers10-11.
propulsion system, power quality improvement However, the presence of a transformer increases the
systems for marine application. Multilevel inverters complexity, installation space and cost. A toroidal
(MLIs), which constitute a new class of power transformer with a high-frequency link has been used
inverters in the field of power electronics, offer for an asymmetrical MLI to reduce the number of
several advantages over 2-level inverters, such as high transformers12-13. The demerits of this topology are
power quality, low switching loss, and high voltage that it uses an extra unit of AC/DC or DC to DC
application1. The cost, power quality, efficiency, converter, number of H bridges, and capacitors.
installation space, complexity, and reliability are the To overcome these demerits, a transformer-less
key factors for the selection of the MLI for marine topology of SDCMI was proposed using an AC to DC
electric system. A 3-level MLI has been reported converter, filters and isolators14. This topology
initially to increase the power quality2. In the required a large number of passive components,
conventional topologies of MLIs, the cascaded thereby decreasing its reliability. Recently, a
H-bridge multilevel inverter (CHBMLI) is more transformer-less buck converter (BC) based H-bridge
advantageous than the diode clamped MLI (DCMLI) topology was implemented to obtain variable DC
and flying capacitor MLI (FCMLI) because it has voltage from a single DC source15. The disadvantage
a modular structure and low electromagnetic of this topology is that it requires an additional BC
interference3-6 (EMI). Furthermore, CHBMLI does unit. Unfortunately, the major drawbacks of the
not require any clamping diodes and capacitors unlike aforementioned topologies are the installation space,
the DCMLI and FCMLI, respectively6-8. cost, complexity, losses, inadequate control, and low
The primary issue with the CHBMLI is that it reliability. A new design or topology is required to
requires different DC sources for each H-bridge9. overcome the aforementioned demerits.
The large number of DC sources increases the cost The conventional SDSI has been described using
and installation space of the CHBMLI. Moreover, an H-bridge with an LC filter16-18 as depicted in Fig. 1.
the large number of DC sources affect the reliability The H-bridge generates a 3-level output voltage and
and efficiency of the MLI9-10. To solve this issue of the LC filter reduces the harmonics from the 3-level
1200 INDIAN J. MAR. SCI., VOL. 47, NO. 06, JUNE 2018

voltage waveform. This paper proposes a new design Table 1 presents the current flowing through the
and analysis for the conventional SDSI depicted in circuit and load voltage for operational modes I and II
Fig. 1. The new design converts the conventional and for D > 0.5, D < 0.5. The analysis has been
SDSI into a BC; it creates a positive and negative described below:
voltage from a single DC source by suitable control of In mode I, the voltage across the inductor increases
the duty cycle. The values of the duty cycle, inductor, as given in Eq. (1).
and capacitor have been selected to create n number
di
of levels in the output voltage of ND-SDCMI. The VL  L … (1)
ND-SDCMI offers numerous advantages in terms of dt
size, complexity, installation space, number of VL
i  TON S 11 , S 14 … (2)
components, and blocking voltage over the existing L
SDCMI.
By applying Kirchhoff’s voltage law to mode I, Eq.
Materials and Methods (3) is obtained
V in  V L  V RL  2V Q
New Design of SDSI … (3)
The circuit diagram of the conventional SDSI is
Substituting the Eq. (3) in (2), we can obtain the rate
depicted in Fig. 1. The circuit consists of a single DC
of rise of current in the circuit given by Eq. (4).
source, an H-bridge, an inductor, and a capacitor.
Rate of rise of current
Basically, the proposed design enables an SDSI to
Vin  VRL  2VQ
function as a BC, which, by suitable design and i (  )  TON S 11, S 14
control of the duty cycle, can be converted into an L … (4)
MLI. The design and operation of the SDSI as BC or By applying Kirchhoff’s voltage law to mode II,
MLI is discussed in next section. Eq. (5) is obtained
The topology works in two modes as a BC. The V L  V in  V RL  2V Q … (5)
two operational modes are described in TABLE 1.
Now, substituting Eq. (5) in (2), the rate of decrease
of current, when the inductor is discharged can be
written as Eq. (6).
Rate of decrease of current

Vin  VRL  2VQ


i()  TOFFS 11, s14
L … (6)

To obtain the load voltage, VRL as a function of the


duty cycle D, Eqs. (4) and (6) are equated as follows:
 TOFFS , S 
Vin  2VQ  11 14

Fig. 1 — Structure of the SDSI  T ONS11, S14  T OFFS11, S14 
VRL   
 T  … (7)
TABLE 1 — Operational modes of the SDSI as a BC T
ONS11 , S14

 T
 V in  2 V 
Q 
 ONS11 ,S14 OFFS11, S

Operational D > 0.5 D < 0.5
14

mode Current Load Current Load The duty cycle is defined by Eq. (8)
Flowing voltage VRL Flowing voltage
through the through the VRL
circuit circuit TON S
D 11 , S14

I Vin to S11 to Positive Vin to S12 to C Negative TON S  TOFF S


L to C and and RL to L to 11 , S14 11 , S14 … (8)
RL to S14 S13
II L to C and Positive L to D11 to Vin Negative
After substituting Eq. (8) in (7), the load voltage
RL to D12 to toD14 to C and and load current are given by Eq. (9) and (10),
Vin to D13 RL respectively: Load voltage
SINGH et al.: LOW COST MULTILEVEL INVERTER FOR MARINE ELECTRIC SYSTEMS 1201

V RL  V in 2 D  1  2V Q … (9) Step 2: Define the minimum and maximum output


power of ND-SDCMI
Load current Pout max  V RL m max I RL max … (12)
VRL Pout min  V RLm min I RL min … (13)
iRL 
RL … (10) Step 3: Determine the value of load resistance of ND-
From Eq. (9) and (10), when D is greater than 0.5, SDCMI
the load voltage and current are positive. Furthermore, VRLm min
if D is less than 0.5, the load voltage and load current RL min 
I RL max … (14)
are negative. The newly designed buck converter
produced a different magnitude of load voltage VRLmmax
RL max 
ranging from -Vin to +Vin by varying the duty cycle I RL min … (15)
from 0 to 1.
Step 4: Select the number of levels (n) in the output
Design of the SDSI as an SDCMI
voltage and hence determine the minimum value of
The ND-SDCMI can be explained in following
the inductor.
steps:
1
Step 1: Find the value of the duty cycle to create Let the output frequency of ND-SDCMI be F 
the desired number of levels in the load voltage TF
The load voltage, which depends upon the duty The settling time of the load voltage, VRL at any
m
cycle is given by Eq. (9). The load voltage of the BC
duty cycle is, TS  4 L
is modified to create n number of levels in the output R L min
voltage. The modified equation that converts the BC
into an MLI is given by Eq. (11). The number of duty TF or 4 L T
cycles required to create n number of levels is d = n-1 Ts   F
n RL min n
(for odd n), d = n (for even n). … (16)
The minimum value of inductor of the ND-SDCMI
V RL m  V in 2 D m  1  2V Q
… (11) TF R L min
Lmin 
m = 1 to n–1 for odd n 4n … (17)

m =1 to n for even n (when zero level is not considered) The settling time of the output voltage of the ND-
Figure 2 shows the 13 level load voltage as per SDCMI is given by Eq. (16). Equation (16) must be
Eq. 11. To create 13 levels, d = 12, m = 1 to 12 and satisfied to create n levels of output voltage. To
the 12 different values of  are required, as shown in satisfy this condition, the value of Lmin is calculated
Fig. 2. The duty cycle Dm is constant for the period using Eq. (17).
 m 1   m . If the value of  m is known, as shown in Fig. (2),
the value of inductor can be calculated.

T s   m 1   m , Here m = 1 to n−1 … (18)


So 4 L     or
m 1 m
RL min

R L min ( m 1   m )
L
4L … (19)
The other method determines the value of the
inductor using Eq. (18) and Eq. (19). In this paper, the
value of the angles of output voltage  m has been
calculated by comparison of multilevel waveform
Fig. 2 — The 13-level load voltage of ND-SDCMI steps with the sinusoidal wave depicted in Fig. 2.
1202 INDIAN J. MAR. SCI., VOL. 47, NO. 06, JUNE 2018

Step 5: Determine the minimum value of filter depicts that the blocking voltage remains constant
capacitor using Eq. (20). when n number of levels are created, which also
indicates that the cost of the semiconductor device of
VRL max
VRL max (1  ) the ND-SDCMI is independent of the THD or number
Vin of levels in the load voltage. If the number of levels in
C min  2
8Lf s … (20) load voltage increases, the THD decreases. Therefore,
the basic advantage of the new designed topology is
The cost of semiconductor switches depends upon that the overall cost of the proposed ND-SDCMI
the blocking voltage and number of semiconductor remains constant despite an increase in the power
devices used in a topology19. The maximum quality of the output voltage.
blocking voltage of the H-bridge based MLI has been
The efficiency of the ND-SDCMI is calculated
calculated20-21. Maximum blocking voltage of ND-
using Eq. (25). The analysis of the switching losses,
SDCMI was calculated using Eq. (21).
conduction losses of semiconductor devices, and
Vblock  4Vin  Vblock11  Vblock14  Vblock12  Vblock13 conduction losses of diodes of the ND-SDCMI is
… (21) performed using MATLAB/Simulink.
In this topology S11 and S14 work together while The output power (Pout) and input DC voltage
S12 and S13 work simultaneously. The blocking (Vin) are assumed to be 1 kW and 200 V,
voltage for the ND-SDCMI can be written using respectively. The switching time, RON and diode
Eq. (22). forward voltage are calculated using the MOSFET
IRF640 datasheet. The analysis of the efficiency is
Vblock11  Vblock14orVblock12  Vblock13 performed by substituting power losses in Eq. (25)
… (22)
when the duty cycle varies from 0 to 1 as shown in
By substituting Eq. (22) in Eq. (21), the maximum Fig. 4(a). Figure 4 (a) shows that the maximum
blocking voltage is given by Eq. (23). efficiency of the ND-SDCMI
Vblock  2(Vblovk11  Vblock12 )  2(Vblock13  Vblock14 ) Pout
… (23) Efficiency  
The THD is calculated using the MATLAB/ Pout  PLoss … (25)
SIMULINK-FFT toolbox as the number of level
increases in the output voltage. The THD of output The analysis of the efficiency is performed by
voltage of the ND-SDCMI is given in Eq. (24) substituting power losses in Eq. (25) when the duty
cycle varies from 0 to 1 as shown in Fig. 4(a).
49
vx Figure 4 (a) shows that the maximum efficiency of the
THD   v1 ND-SDCMI is 98.57% and 99.58% at the minimum
x2
… (24)
and maximum duty cycle, respectively. The selection
The blocking voltage of the ND-SDCMI depends of the duty cycle improves the efficiency. The
upon the input voltage given in Eq. (21). Figure 3 efficiency varies from 98% to 92% when the duty
cycle varies from 0 to 0.45 and from 99% to 94%
when the duty cycle varies from 1 to 0.55, as depicted
in Fig. 4 (a). If the duty cycle of the ND-SDCMI
operates from 0 to 0.45 and from 0.55 to 1,
the losses are minimum and the efficiency improves.
The duty cycles are selected and the efficiency and
THD are calculated upto 13 levels as depicted in
Fig. 4(b).
Figure 4 (b) shows that the maximum efficiency of
the ND-SDCMI is 99.5% for two levels; however,
when the number of levels in the output voltage
increases, the efficiency marginally decreases. Figure
Fig. 3 — THD and blocking voltage obtained by simulation as the 4 (b) shows that to obtain a THD less than 5% of
number of levels increases in the output voltage (Vin = 12 V) the fundamental voltage, ND-SDCMI requires at least
SINGH et al.: LOW COST MULTILEVEL INVERTER FOR MARINE ELECTRIC SYSTEMS 1203

12 levels in the output voltage. The efficiency for


12-level ND-SDCMI is 94%. From Fig. 4 and the
above discussion, an improvement in THD appears to
be accompanied by a marginal decrease in the
efficiency of the ND-SDCMI.

Comparison of reported topology of an SDCMI with


that of the ND-SDCMI
Table 2 shows the comparison of an SDCMI with
the ND-SDCMI. A comparative analysis shows that,
when one H-bridge is used, that is, h = 1, the ND-
SDCMI has less blocking voltage (48 V) to create
n number of levels. Table 2 shows that blocking
voltage is calculated for the number of H-bridges used
in a single-phase SDCMI topology. The THD of the
output voltage of the SDCMI is below 5%. According
to the IEEE-519 or IEC 555-2 standard, the THD in
the output voltage should be less than five percent19.
When only one H bridge is used (h = 1), only three
topologies have a THD less than 5%. From Table 2,
when THD is below 5%, ND-SDCMI and the
topologies reported in ref. [15] and [22] require
only four semiconductor devices; whereas, other
topologies require a larger number of semiconductor
devices. The ND-SDCMI uses a smaller number of
components than existing topologies do. Therefore,
Fig. 4 — Efficiency and THD of the ND SDCMI, (a) Efficiency
when duty cycle varies, (b) Efficiency and THD when the number the ND-SDCMI requires less installation space and
of levels increases. costs less than existing topologies do.

TABLE 2 — Comparison of different parameters of an ND-SDCMI with reported SDCMI, when h=1
Ref. Vblock in volts No. of levels No. of No. of switches THD for
Expression Vdc = 12V Expression h=1 levels Expression h=1 h=1
h=1 shown in
reported
study
[22] >(4 Vdc ) >48 3 3 3 4 4 <5%

[14] (4 Vdc )h 48 3h 3 27 4h 4 >5%


[10] (4 Vdc )h 48 2h+1 3 13 4h 4 >5%
[13]  V V 48 3h 3 27 4h 4 >5%
4Vdc dc dc
 9 3
[3] (>4 Vdc ) >48 - 3 5 8 4 >5%
[15] >4 Vdc >48 n n 3 to 255 6 4 <5%
[12] >(4 Vdc h) >48 3h 3 upto 27 4h 4 >5%
[4] (4 Vdc )h 48 2h+1 3 7 4h - -
[4] (4 Vdc )h 48 2h+1 3 7 4h - -
[11] (4 Vdc )h 48 2h+1 2T+1 7 4h 3 >5%
[24] >4 Vdc >48 5 - 5 6 - -
[23] - - 3 - 5 8 - -
ND-SDCMI (4 Vdc ) 48 n n 13 4 4 <5%
1204 INDIAN J. MAR. SCI., VOL. 47, NO. 06, JUNE 2018

TABLE 3 — Performance and circuit parameters of


single-phase SDCMI for THD <5
Ref. Vblock h n Nothers
(Vdc =12 V)
[22] >48 1 3 Four LC filters,
Four AC to DC
converters, four
isolators
[14] 48*3 3 27 Four Capacitors, A to
D converter with
differential amplifier,
an inductor
[10] 48*9 9 13 3-phase Transformer
[13] 67 3 27 HFT with auxiliary
10–20 kHz H-bridge
[12] >48*3 3 23 and 27 Main converter,
Variable DC source,
2 H-bridges
[15] >48 1 21 One DC to DC
converter
ND- 48 1 13 Inductor and
SDCMI capacitor

Table 3 shows the comparison of a single DC


source topology when THD is less than 5% of the
fundamental voltage. From Table 3, when THD is less
than 5% and input DC voltage is 12 V, the ND-
SDCMI generates 13 output levels. The blocking
voltage is 48 V, which is less than that of existing
topologies. Table 3 shows that apart from
semiconductor devices, the other topologies require
transformers, which are heavy to install and require
two or more passive devices. The ND-SDCMI,
however, requires only an inductor and capacitor to
perform multilevel operations.
Results and Discussion
Figures 5(a) and 5(b) depict the 12-level output
voltage and current of the ND-SDCMI when a
resistive load has been connected. The voltage across
the inductor of a 12-level ND-SDCMI is depicted in
Fig. 5(c).
Figure 5(d) depicts the blocking voltage across
switches S11 and S14. The blocking voltage across S12
and S13 is shown in Fig. 5(e). From the simulation Fig. 5 — Simulation results of ND-SDCMI, (a) 12-level load
results we analyzed that the maximum blocking voltage of ND-SDCMI, (b) Load current, (c) Voltage across
voltage of the ND-SDCMI is 48 V when Vin =12 V. inductor, (d) Blocking voltage across switch S11 and S14, and (e)
Blocking voltage across S12 and S13.
Figure 6 depicts that the THD of the load voltage of
the ND-SDCMI is 4.6%, and the rms value of load that were selected for the simulation (Table 4)
voltage is 8 V. were selected for experimental work. The IRF-640
The experimental results are validated with MOSFET device is used for the H-bridge and the gate
simulation results by the implementation of the driver TLP250 is used to drive the MOSFET device.
prototype 12-level ND-SDCMI. The same parameters The look-up table of the duty cycle has been
SINGH et al.: LOW COST MULTILEVEL INVERTER FOR MARINE ELECTRIC SYSTEMS 1205

Fig. 6 — THD of load voltage of the ND


ND-SDCMI
Fig. 7 — The experimental setup of the ND-SDCMI
ND
TABLE 4 — Specification and designed pa
parameters of the
ND-SDCMI
Specification of ND- Vin 12 V
SDCMI RLmin 1000
RLmax 500
fsw 10 kHz
F 50 Hz
n 12
Designed Parameters L 780 μH
C 5 μF
d 12
D1 = 0.55, D2 = 0.63,
D3 = 0.75, D4 = 0.85,
D5 = 0.92, D6 = 1
D7 = 0, D8 = 0.8, D9 = 0.15,
D10 = 0.25, D11 = 0.37,
D12 = 0.45 Fig. 8 — THD of output voltage obtained experimentally using
power quality analyzer
programed to create 12 levels using a TMS320F28027
microcontroller kit (C2000 series, Texas instruments),
and it is programed by interfacing it with Matlab/
Simulink.
The output voltage, voltage across inductor, and
gate signal of H-bridgebridge obtained using the
microcontroller are measured using a mixed signal
oscilloscope (MSO) MSO7045B (Agilent Technologies).
A single-phase
phase FLUKE 43 B power quality analyzer
is used to measure the THD and harmonic order of
the output voltage. The apparatus used for the
experimental study is depicted in Fig. 7.
Figure 8 shows the harmonic spectrum of output
voltage obtained up to 49th order. The electronic circuit
Fig. 9 — Electronic circuit of the ND-SDCMI
ND
of the ND-SDCMI
SDCMI is depicted in Fig. 9. Figure 10
shows the 12-level
level output voltage of ND ND-SDCMI, the output voltage has 12 levels, the rms value of
voltage across the inductor, and pulses obtained using output voltage is 7.9 V, and the THD is 4.7%. The
the microcontroller. Experimental results indicate that experimental results concur with simulation results.
1206 INDIAN J. MAR. SCI., VOL. 47, NO. 06, JUNE 2018

Fig. 10 — Experimental results of the 12-level load voltage, the voltage across the inductor, and gate pulses are obtained from
microcontroller for semiconductor switches S11, S14 and S12, S13.
Conclusion 3 Colak, I., Kabalci, E., Bayindir, R., Review of multilevel
The ND-SDCMI uses fewer components than voltage source inverter topologies and control schemes,
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