SHAKTI PROCESSOR CORES: FEATURE LIST

RISE LAB, CSE DEPARTMENT

INDIAN INSTITUTE OF TECHNOLOGY MADRAS
Repository: https://bitbucket.org/casl/shakti_public

E-CLASS 32-BIT COMMON FEATURES

Features and Specs: Design :
• 3- stage in-order core.
• Supports RV32IMA ISA as defined by RISC-V spec version 2.1. • All the cores including the slave peripherals
• Supports RISC-V privilege spec 1.9.1 for user and machines modes. are designed in Bluespec System Verilog
• Parameterized set-associative I-Cache and D-Cache. • Heavily parameterized without loosing out on
• PIPT and blocking caches
performance or area.
• CSR mapped UART interface for communication with host.
• AHB bus support with single master. • Generic interface definition has enabled plug-
• Debug control hooks integrated play environment.
Target Applications: • Since Bluespec generates synthesizable
• Simple microcontroller-based verilog, the RTL infrastructure for synthesis
FPGA Results: and low level simulation is easily maintained.
• Area: Slice-LUTs on the Nexys4-DDR development board • Parameterized TLMs allow easy exploration
• Frequency: xMHz on the Nexys4-DDR development board amongst various bus-interconnects (AHB,
Future Milestones: Target Applications: AXI, APB, etc) and peripheral devices.
• Advanced JTAG Debug interface • Basic micro-controllers
• I2C and QSPI slaves • Low power applications Verification Strategy:

The common verification strategy across all the

C-CLASS 32/64 BIT cores is to compare the execution dumps of each
core against those generated by SPIKE (from UC
Features and Specs: Berkeley). The dumps include register values at the
• 6 - stage in-order core. end of each instruction commit. Each core passes
• Supports RV32IMAF ISA as defined by RISC-V spec version 2.1 through a regression run of 4 test-suites:
• Supports RISC-V privilege spec 1.9.1. for user and machine mode.
• Parameterized set-associative I-Cache and D-Cache.
• RISC-V TESTS: Smoke tests for every
• PIPT blocking caches.
instruction and
• CSR mapped UART interface for communication with host.
• AXI4 bus support with multi-master multi-slave configuration. • AAPG: Shakti’s in-house pseudo-random
• Parameterized bimodal branch prediction unit. assembly program generator. Enables
• Single precision floating point unit optimized for area and power. specification of percentage of hazards such as
Target Applications: RAW, WAR, etc. required in the generated
• Simple microcontroller-based program.
FPGA Results: • RISC-V TORTURE a test-suit provided by
• Area: 18K Slice LUTs on Nexys4-DDR development board UC-Berkeley for generating random assembly
• Frequency: 40MHz on Nexys4-DDR development board program.
Target Applications:
Future Milestones:
• IoT applications • CMITH A random C program generator.
• DMA, I2C, QSPI and other slaves.
• Smart-cards Typically used to find bugs in compilers.
• MMU support Provides good coverage of instructions,
• Security applications
address dependencies and branches as
compared to other techniques.
I-CLASS 64 BIT
FPGA Emulation & OS Support:
Features and Specs: Features and Specs:
• 8- stage Out-of-Order core. • Double Issue Each core will be validated through an OS port on
• Supports RV32IMAFD ISA as defined by RISC-V spec version 2.1. • Prioritized for selecting instructions from issue queue based on age a suitable sized FPGA:
• Supports RISC-V privilege spec 1.9.1 all modes. • MMU support modeling the Power 3-level PTW • E-Class: FreeRTOS with basic features on the
• Parameterized set-associative I-Cache and D-Cache • CAM based speculative load store unit Nexys4-DDR
• VIPT Caches + Non-Blocking • Single & Double precision Pipelined floating point unit optimized for • C-Class: FreeRTOS with basic Features and
• AXI bus support with multiple masters. maximum performance. Minimal Linux port on Nexys4-DDR.
• Parameterized tournament branch prediction unit • I-Class: A full Linux port on emuPro FPGAs
• Out-of-order execution through explicit register re-naming.
• 2 ALU units and FPU Unit. The STING SoC verification framework, from
Valtrix, will also be used in the future to verify
basic functionality of each core/SoC configuration.
Benchmarks
• Coremarks/MHz: 3.6
• Dhrystone: 2.6 DMIPS/MHz
DEVELOPMENT TEAM

Target Applications:
Member Name Task/Role
• High-end desktops Abhinaya Agarwal E-Class
• Mobile applications
• Workstations and low-end Rahul Bodduna I-Class
servers
Neel Gala C-Class
Vinod Ganesan C/I - Class
Future Milestones:
• Linux porting. Prof. V. Kamakoti Project Lead
• DDR3/4, SPI, etc as slaves
• Ring based Multi-core system.
G. S. Madhusudan Project Lead
Contact us: shakti.iitm@gmail.com