Beruflich Dokumente
Kultur Dokumente
Of
Computer Architecture
(BEG474CO)
B.E
Electronics & communication
VII Semester
Presented by:
www.jayaram.com.np
Your easy access to complete study material…………………..
Syllabus: 4. Instruction Sets. (6 Hours)
4.1 Machines Instruction Characteristics.
COMPUTER ARCHITECTURE BEG474CO 4.2 Types of Operands.
Year: IV Semester: I 4.3 Types of Operations.
4.4 Assembly Language.
Teaching Schedule Examination Scheme 4.5 Addressing.
Hour/week 4.6 Instruction Formats.
Theory Tutorial Practical Internal Assessment Final Total 5. CPU Structure Function. (6 Hours)
2 1 3/2 Theory Practical* Theory** Practical 125 5.1 Processor Organization.
20 25 80 - 5.2 Register Organization.
5.3 The instruction Cycle.
*Continuous 5.4 Instruction Pipelining.
**Duration:3 hours 5.5 The Pentium Processor .
Course Objective: The course provides foundation knowledge of 5.6 The Power PC Processor.
Computer Architecture. 6. Reduced Instruction Set Computers (RISC). (7 hours)
1. Introduction (4 hours) 6.1 Instruction Execution Characteristics.
1.1 History of Computer. 6.2 The use of Large Register File.
1.2 Organization and Architecture. 6.3 Compiler-Based Register Optimization.
1.3 Structure and Function. 6.4 Reduced Instruction Set Architecture.
1.4. Pentium and Power PC Evolution. 6.5 RISC Pipelining.
2. Computer System. (6 hours) 6.6 The RISC versus CISC.
2.1 Computer Components. 7. Control unit and Microprogrammed Control. (6 hours)
2.2 Computer Function. 7.1 Micro-Operations.
2.3 Interconnection Structures. 7.2 Control of the CPU.
2.4 Bus Interconnection. 7.3 Hardwired Implementation .
2.5 PCI 7.4 Microinstruction Sequencing.
2.6 Internal Memory. 7.5 Microinstruction Execution.
2.7 External Memory. 7.6 Applications of Microprogramming.
2.8 Input/output System. 8. Parallel Organization. (5 hours)
2.9 Operating System Support. 8.1 Multiprocessing.
3. The Central Processing Unit. (5 Hours) 8.2 Cache Coherence and MESI Protocol.
3.1 The architecture and Logic Unit. 8.3 Vector Computation.
3.2 Integer Representation. 8.4 Parallel Processors.
3.3 Integer Arithmetic. Laboratory:
3.4 Floating-Point Representation.
3.5 Floating-Point Arithmetic.
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Student will be required to Design and Built a Project related to the
computer architecture.
References:
1. Mano, Pearson Education, “ Logic and Computer Design
Fundamentals”.
2. Sima, personal Education, “Advance Computer Architectures: A
Design Space Approach”.
3. Heuring Pearson Education, “Computer System Design
Architecture”.
4. M.Morris Mano, “Computer System Architecture”.
5. The Economics of Development and Planning by M.L.Jhingan.
6. Modern Economic Theory by K.K Dwett.
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /2
History of computer: Main memory: which store both data and instruction(program).
1. First generation computer: (Vacuum tube): ALU:ALU capable of operating on binary data.
- ENIAC (electronic Numerical integrator and computer) Control unit: Which interprets the instruction and memory and
designed by and constructed under the supervision of John causes them to be executed.
Mauchly and John prespereckrt at the university of Input/ output unit: I/o equipment operated by control unit.
pennsyevenia was the world’s first general purpose
electronic digital computer. Second Generation:(Transistor): The first major change in
The resulting machine was enormous weighting in 30 tones, electronic computer came with the replacement of vacuum tube
occupying 1500 sq feet floor space and containing more then by the transistor. The transistor is smaller cheaper and dissipates
18000 vacuum tubes. When operating it consumes 140kw of less heat then a vacuum tube but can be used in same way as a
power. It was substantially faster then any electro-mechanical vacuum tube to construct computer. Unlike the vacuum tube
computer being capable of 5000 addition per second. which requires the wire, metal plate, glass capsule and vacuum.
ENIAC was decimal machine i.e numbers were represented in The transistor is sold state device made from silicon.
decimal form ring of 10 vacuum tubes represent each digit. At The use of transistor define the second generation of
any time only one vacuum tube was in ON state representing one computer. The second generation saw the introduction of more
of 10 digits. The major drawback of ENIC was that it had to be complex arithmetic and logic unit and control unit, use of high
programmed manually by setting swithches and plugging and level languages and provision of system software with the
unplugging cables. computer.
In 1964, Von-Neumann and his colleagues begin the design of
new stored program computer referred to as IAS computer at the Third generation: (integrated circuit):A single self contain
Princeton institute for advance study. Figure shows the general transistor is called discrete component. Through out the 1950’s
structure of IAS computer. and early 1960’s electronic equipment was composed largely of
discrete components – transistor, capacitor, resistor and so on.
ALU
Discrete component will manufacture separately packed in their
I/O
own container and solder together on circuit board. Which were
Main memory Equipment
then instilled in computer oscilloscope and other electronic
Program equipment. The entire manufacturing process from transistor to
Control
Unit circuit board was expensive and cumbersome.
In 1958 came the achievement that revolutionized electronic
Fig. Structure of IAS computer. and started the era of micro electronics; the invention of
It consist of following: electronic circuit. It is the integrated circuit that defines third
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generation of computer. The integrated circuit exploits the facts Structure and function:
that such component as transistor resistor and conductors can be A computer is a complex system contains million of elementary
fabricated from semiconductor such as silicon. It is merely electronic component.
extension of solid state art to fabricate entire circuit in tiny peace Structure: The way in which the component are interrelated.
of silicon rather then assemble discrete component made from Function: The operation of each individual component is a part
separate peace of silicon. Initially only a few gates could be of structure.
reliably manufacture and package together these early integrated
circuit are referred as Small scale integration. (SSI). Figure:
Later generation: Beyond the third generation there is less
general agreement of defining generation of computer. With the
Operating enviroment
introduction of large scale integration (LSI) more then one (Source and destination of data)
thousand component can be placed on single integrated circuit
chip define 4th generation computer. Very large scale integration
VLSI achieve more then ten thousand component per chip and Data movement
current VLSI chip can contain more then one lakh components appratus
Date: 2065/11/8
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /4
- Data movement
- Control CPU
Internal CPU
interconnection
Computer
control unit
Fig: CPU
Computer
There are four main structural components: 8080: Eight bit machine with eight bit data path to the memory.
i) Central processing units: Controls the operation of 8086: 16 bit machine with wider data path and larger register and
computer and performs its data processing function. instruction queue that prefetch a few instructions before they are
ii) Main memory: Stores data. executed.
iii) I/O : moves data between the computer and its external 80286: Extension of 8086 enabled addressing 16MB memory
environment. instead of just 1 MB.
iv) System interconnection: Some mechanism that 80386: 32 bit machine support multitasking meaning it could run
provides for communication among CPU, main multiple programs at the same time.
memory and I/O.
300 PC
300 1 94 0
Fetch Execute HALT
START instruction 301 5 94 1 AC
302 2 94 1 1 94 0 IR
301 PC 302 PC
300 1 94 0 300 1 94 0
301 5 94 1 0 00 3 AC 301 5 94 1 0 00 5 AC
302 2 94 1 1 94 0 IR 302 2 94 1 2 94 1 IR
940 0 00 3 940 0 00 3
941 0 00 2 941 0 00 2
Step: 3 Step: 6
CPU Registor CPU Registor
301 PC 303 PC
300 1 94 0 300 1 94 0
301 5 94 1 0 00 3 AC 301 5 94 1 0 00 5 AC
302 2 94 1 5 94 1 IR 302 2 94 1 2 94 1 IR
940 0 00 3 940 0 00 3
941 0 00 2 941 0 00 2
Step: 4
CPU Registor
302 PC
300 1 94 0
The program fragment shown adds the contents of memory
301 5 94 1 0 00 5 AC
words at address 940 to the contents of memory word at address
302 2 94 1 5 94 1 IR
940 and stores the result in latter location.
Three instruction which can be describe as three fetch and
940 0 00 3
three execute cycles are require:
941 0 00 2 1. Pc contains 300, the address of 1st instruction. This
instruction is loaded into the IR and PC is incremented.
Step:5 2. The first four bits in IR indicate that AC is to be loaded .
The remaining 12 bits specify the address (940) from
which data are to be stored.
3. The next instruction 5941 is fetch from the location 301
and PC is incremented.
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /8
4. The old contents of AC , and contents of location 941 are User Program Interrupt handeler
PC is incremented. 2
Interrupt
disable Interconnection Structure:
Fetch Execute
Interrupt Check for
enable
A computer consist of set of components or module of three
interrupt;
Start next
instruction
instruction process interrupt basic types, (processor , memory , I/O) that communicate with
each other. The collection of path connecting various module is
called interconnection structure. The design of this structure will
depend on exchanges that must be made.
HALT
Figure suggest the type of exchanges that must be needed by
Fig: Instruction cycle with interrupt. indicating the major for of input and output for each module
type.
In the interrupt cycle the processor checks to see if any interrupt Read Memory
Read
Internal Data
N word
have occur , indicated by the presence of interrupt signal. If no Write
o
Write
Address I/O module
M port External Data
interrupt are pending , the processor proceeds to fetch cycle and Address
N-1
Data
Internal Data
Interrupt
fetch the next instruction of current program of interrupt is Data
External Data
Signal
C PU mem ory m em ory I/O .... I/O If a great number of devices are connected to the bus
performance will suffer. In general the more devices attached to
the bus length and hence the greater propagation delay. Most
computer system used multiple buses. A typical traditional
structure is shown in figure.
Figure: Bus interconnection Scheme.
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /10
Local bus
Processor main memory
Cache
local bus
processor catch/bridge System bus
Main Local I/O
Memory Controller
SCSI Firewire Graphic Video LAN
expansion Expansion
Network SCSI bus Modem Serial Fax bus modem serial
interface interface
Cache
System bus
Bridge
Memory Audio Motion
/controller DRAM video
Host bridge
Host bridge
Expansion Expansion
bus bridge bus bridge
SCSI SCSI CAN CAN PCI to
LAN SCSI Expansion PCI bridge
bus Basic Graphics
I/O
Bridge
device Fig: Typical server system.
In multiprocessor system one or more PCI configuration may be
connected by bridges to processor system bus. The system bus
Expansion
bus interface supports only the processor/catch unit, main memory and PCI
bridge.
Fig: Typical desktop system.
Internal memory:
A combine DRAM controller and bridge a PCI bus provides RAM: One distinguishing characteristics of RAM is that it is
tight coupling with the processor and ability to deliver data at possible both to read data from the memory and write new data
high speed. The bridge acts data buffer so that the speed of PCI into the memory easily and rapidly. Other distinguishing
bus may differ from that of processor I/O capability. characteristics of RAM is that it is volatile. Ram most be
provided with constant power supply. The two tradition form of
RAM used in computer are DRAM and SRAM.
T3 T4
T5 C1 T6 track
C2
T1 T2
Bit line(B)
Bit line(B)
Read/write
head
Address line
Figure: SRAM line.
Input/output system: Examples of human readable devices are VDV and printers.
Examples of machine readable devices are magnetic discs and
tapes. Communication devices allow a computer to exchange
data with remote device. Which may be a human readable
Address lines device, a machine readable device or another computer.
The most common means of computer/user interaction is
Data lines System bus
keyboard/monitor arrangement. The user provides input through
Control lines the keyboard. This input is then transmitted to the computer and
may also be displayed on monitor. In addition, the monitor
display the data provided by the computer.
I/O module
In very general terms, the nature of external devices is
indicated in fig below.
Links to
peripheral
Control signal
Control signal to i/o module Data bits to &
form i/o module from i/o module
Figure: Model of I/O module
storage
Processor Processor os register register
program
data
Data are presented to ALU in register and the result of operation
are stored in register. These registers are temporarily storage
A computer is a set of resources for the movement storage and location within the processor that are connected by signal path to
processing of data for the control of these function. The the ALU. The ALU may also set flags as the result of an
operation system is responsible for managing these resources. operation. The flags values are also stored in registers within the
Figure suggest the main resources that are managed by operating processor. The control unit provide signals that control the
system. operation of ALU and the movement of data into an out of ALU.
A portion of operating system is in main memory. The reminder
of main memory contains other user programs and data. The Integer Representation: (Fixed-point representation):
operating system decide when i/o device can be used by a An eight bit word can be represent the numbers form zero to 255
program in execution and controlled access to and use of files. including
The processor is itself resources and the os must determine how 00000000 = 0
much processor time is to be devoted to the execution of 00000001 = 1
particular user program.
Arithmetic and Logic Unit : ALU is the part of computer that In general if an n-bit sequence of binary digits an-1, an-2 …..a1, ao
actually performs arithmetic and logical operations on data. All Is interpreted as unsigned integer A. It’s value is
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A = ∑n-1i=0 2iai interpreted. For negation take the Boolean complement of each
bit of corresponding positive number, then add one to the
Sign magnitude representation: rustling bit pattern viewed as unsigned integer.
There are several alternative convention used to represent –ve as Consider n bit integer A in twos complement representation. If
well as +ve integers, all of which involves treating the most A is +ve then the sign bit an-1 is zero. The remaining bit
significant (left most) bit in the word as sign bit. If the sign bit is represent the magnitude of the number.
0 the number is +ve and if the sign bit is 1 the number is –Ve. In A = ∑n-2i=0 2iai for A ≥ 0
n bit word the right most n-1 bits hold the magnitude of integer. The number zero is identified as +ve and therefore has zero sign
E g. bit and magnitude of all 0’s. We can see that the range of +ve
+18 = 00010010 integer that may be represented is from 0 ( all the magnitude bits
- 18 = 10010010 ( sign magnitude) are zero) through 2n-1-1 (all of the magnitude bits are 1.)
The general case can be expressed as follows: Now for –ve number integer A. The sign bit an-1 is 1. The
A = ∑n-2i=0 2iai if an-1 = 0 . range of –ve integer that can be represented its from -1 to -2n-1
= -∑ n-2i=0 2iai if an-1 =1 Twos complement, A = -2n-1an-1+∑n-2i=0 2iai
Defines the twos complement of representation of both positive
There are several drawbacks to sign-magnitude representation. and negative number.
One is that addition or subtraction require consideration of both E.g
signs of number and their relative magnitude to carry out the Decimal Sign magnitude Twos complement
required operation. Another draw back is that there are two representation representation
representation of zero. Eg. +7 0111 0111
+010 = 00000000 -7 1111 1001
-010 = 10000000 which is inconvenient. -128 64 32 16 8 4 2 1
OF Adder
The first four examples illustrate successful operation if the
result of the operation is +ve then we get +ve number in ordinary
binary notation. If the result of the operation is –ve we get Fig: Block diagram of hardware for subtraction and addition.
negative number in twos complement form. Note that in some
1011 Multiplicand 11
instants there is carry bit beyond the end of what which is ignore.
1101 Multiplier 13
On any addition the result may larger then can be held in word
1011
size being use. This condition is called over flow. When 0000 partial product
overflow occur ALU must signal this fact so that no attempt is 1011
1011
made to use the result. To detect overflow the following rule
10001111 product (143)
observed. If two number are added, and they are both +ve or
both –ve. Then overflow occurs if and only if the result has the Fig. Multiplication of unsigned binary integers.
opposite sign.
The figure suggest the data path and hardware elements need ot
accomplish addition and subtraction. 1. The multiplication involve the generation of partial product 1
for each digit in the multiplier. This partial products are then
sum to produce final product.
2. The partial product are easily define. when the multiplier bit
is zero the partial product is zero. When the multiplier is 1
the partial product is the multiplicand.
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /20
3. The total product is produce by summing the partial Control logic reads bits of multiplier one at a time. If Q0 is 1 the
products. For this operation each successive partial product is multiplicand is added to A register and result is stored in A
shifted one position to the left relative the perceiving partial register with C bit used for overflow then all of the bits of C , A
product. , and Q register are shifted to the right one bit so that C bit goes
4. The multiplication of two n bit binary integer results in into An-1, A0 goes into Qn-1 and Q0 is lost. If Q0 is zero and no
product of upto 2n bits in length. Eg. 11 ×11= 1001 addition is perform , just the shift. This process is repeated for
Multiplicand each bit of the original multiplier. The resulting 2n bit product is
Add Shift and add contain in A and Q register. A flow chart of the operation is
Mn-1 . . . . . . . . . Mo control logic
Shift
shown in fig.
start
Multiplier
C,A -- 0
M -- Multiplicant
Q -- Multiplier
C An-1 ......... count -- n
Ao
Division:
00001101 Quotient No
Yes
1011) 10010011 Divident A<0
Diviser 1011
Q0 1
001110
partial 1011
Qo 0
Remainder 001111 C,A A+M
1011
100 Remainder count count-1
No
count=0 Yes End
Quotient in Q
? Remainder in A
Transfer of control: For all of the operation types discussed so Address Instructions
far, the next instruction to be performed is the one that 101 LDA 201
immediately follows in memory the current instruction. How 102 ADD 202
ever a significant fraction instruction in any program have as 103 ADD 203
their function changing the sequence of instruction execution. 104 STA 204
201 DAT 2
Assembly language: A CPU can understand and execute 202 DAT 3
machine instruction. Such instruction are simply binary numbers 203 DAT 4
stored in the computer. If a programmer wished to program 204 DAT 0.
directly in machine language , then it would be necessary to inter (c ) Symbolic program
the program as binary data.
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /28
Label Operation Operand
FORMUL LDA I Immediate addressing: The simplest form of addressing is
ADD J immediate addressing in which the operand is actually preset in
ADD K the instruction.
STA N Instruction
Operand
I DATA 2
J DATA 3
K DATA 4 This mode can be used to define and use constant or set initial
N DATA 0 value of the variable.
(d) Assembly language.
Direct addressing: A very simple form of addressing is direct
A slight improvement is to write the program in hexadecimal addressing in which the address filed contains the effective
rather than binary notation. For improvement we can make use address of the operand. EA = A
of symbolic name or mnemonic of each instruction. With the last EA – Effective address of the location containing reference
refinement we have assembly language. Program written in operand.
assembly language are translated into machine language by a Instruction
assembler. This program must not only do the symbolic A
translation but also assign some form of memory address to
symbolic address. Memory
Date: 2065/12/27
Operand
Addressing:
The most common addressing techniques are: Indirect addressing: With the indirect addressing the length of
- Immediate addressing field is less than the word length thus limiting the
- Direct address length. One solution is to have the address field referred
- Indirect to address of a word in memory which in term contains full
- Register length address of the operand. This is know as invalid
- Register indirect addressing.
- Displacement EA = (A)← contains of A
- Stack
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Instruction
A Displacement addressing: A very powerful mode of addressing
combines the capabilities of direct addressing and register
Memory
indirect addressing.
Operand
FA = A+(R)
Instruction
R A
Memory
+
Register addressing: It is similar to direct addressing. The only
difference is that, the address field refers to register rather than
the main memory address.
Instruction
R
Stack addressing: The stack is the linear array of locations. It is
Register some times referred to as push down list or last in First out
(LIFO) queue. The stack pointer is maintained in register.
Instruction
Operand
Implexit
Fetch Memory
Control
Interrupt Indirect unit
Execute
IR MBR
Memory
Memory
Control Control
unit
unit
MBR MBR
Date: 2066/1/10
CO
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FI DI CO FO EI WO
Instruction 1
FI DI CO FO EI WO
Instruction 2
FI DI CO FO EI WO
Instruction 3 Yes Conditional
FI DI CO FO branch ?
Instruction 4
FI DI CO
Instruction 5 FI DI
Instruction 6 Update PC
FI
Instruction 7
FI DI CO FO EI WO WO FO
Instruction 15
FI DI CO FO EI
Instruction 16 Empty pipe
EI
WO
Fig: Effect of conditional branch on instruction pipeline
instruction.
Branch or No
In the figure the branch is taken. This is not determine until the Yes
interrupt ?
end of time unit 7. At this point the pipe line must be cleared of
instruction that are not useful. During item unit 8 the instruction
15 enters the pipeline. No instruction complete during the time Fig: six stage CPU instruction pipeline.
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /36
Tag word: 16 bit register contains 2 bit tag for each floating
The Pentium Processor: point numeric register, Which indicates the nature of contents of
corresponding register. The four possible values are valid, zero,
Register organization: special (infinity) and empty.
The register organization include the following type of register:
General: There are eight 32 bit register. This may be used for all The power PC organization:
type of Pentium instruction. They can also hold operand for Register organization: The fixed point unit includes
address calculation. General: There are 32 sixty four bit general purpose registers.
Segment: There are six 16 bit segment register. The code These may be used to load, store and manipulate data operands
segment register references the segment containing the and may also used for register indirect addressing.
instruction being executed. The stack segment register references Accept ional register: Includes 3 bit that repot exceptions in
the segment containing the user visible stack. integer arithmetic operations.
Flags: It includes six condition codes (carry, parity, auxiliary, The floating point unit includes addition user visible register
zero, sign, overflow). Which report the results of integer General: There are 32 sixty four bit general purpose register used
operation. In addition there are bits in the register that may be for all floating point operation.
referred to as control bits. Interrupt enable flags when set the Floating pint status and control register: This 32 bit register
processor will recognize external interrupt. contains bits that control the operation of floating point unit and
Instruction Pointer: It contains the address of instruction. bits that record status resulting form floating point operation.
Control register: The Pentium employs four 32 bit control The branch processing unit contains user visible registers.
registers. Control various aspect of processor operation. Condition register: Consists of 8 four bit condition code.
There are also register specifically devoted to the floating point Link register: This register is used for call/return instructions . If
unit: the LK bit in condition branch instruction is set then the address
Numeric: Each registers holds extended precision 80 bit floating following the branch instruction is fetched in the link register
point number. and it can be used for later return.
Count: The count register can be used to control the iteration
Control: 16 bit control register contains bits that control the loop. The count register is decremented each time, it is tested in
operation of floating point unit. conditional branch instruction.
Status: 16 bit status register contains the bits that reflect the
current state of floating point unit.
1. Load R1 I A E
2. Load R2 I A E
uop uop uop
3. No operation I A E
4. Add R1 +R2 I A E Fig: constituent element of program execution.
5. Store R3 I A E
Fetch cycle: It causes an instruction to be fetched form memory.
Fetch cycle actually consist of three steps and four micro
operations.
Date: 2066/1/22 t1: MAR ← (PC)
Chapter:7 t2: MBR ←Memory
Control unit and micorprogrammed control PC ←PC+1
t3: IR ←(MBR)
Micro-operation. The notion (t1,t2,t3) represent successive time units.
The operation of computer is executing a program consists of
sequence of instruction cycle. Each instruction cycle is made up Indirect cycle: once an instruction is fetch , the next step is to
off no of smaller units, one subdivision that we found convienent fetch source operand.
is fetch, indirect execute and interrupt with only fetch and t1: MAR ← (IR (address))
execute cycle always occurring. Each of the smaller cycle t2: MBR ←Memory
involve series of steps, each of which involve processor register. t3: IR(address) ←(MBR(address))
We will refer to these steps as micro operations. Fig depict the
relationship among the various concepts we have been Interrupt cycle: At the completion of execution cycle a test is
discussing. made to determine weather any enabled interrupts have occur if
so the interrupt cycle occurs.
t1: MBR ← (PC)
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t2: MAR ←save address - External data path.
PC ←Routine address - Control unit
t3: Memory ←(MBR) -
All micro operation fall into of the following category.
Execute cycle: The fetch indirect and interrupt cycle are simple - Transfer data from one register to another.
and predictable. Each involve fix sequence of micro operation. - Transfer data from one register to external interface.
This is not true of the execute cycle for a machine with N - Transfer data from external interface to register.
different upcodes, there are N different sequence of micro - Perform the arithmetic or logic operation using register for
operation that can occur. Consider ADD instruction. input and output.
ADD R1,X Instruction register
Date: 2066/1/24
Cntrol bus
Control of processor: Fig: model of control unit.
We can define the functional requirements for the control unit. A
definition of these functional requirement is the basis for design Hardwire implementation: In hardwire implementation the
and implementation of the control unit. The following three steps control unit is essentially a combinatorial circuit. Its input logic
process lead to characterization of control unit. signal are transform into set of output logic signal which are the
1. Define the basic elements of the processor control signal.
2. Describe the micro operation that the processor performs. The key inputs are instruction register, clock , flag and
3. Determine the functions that the control unit must perform control bus signal. The control unit makes the use of op-code and
to cause the micro operations to be performed. will perform the different actions for different instructions. To
The basic functional elements of processor are: simplify the control unit logic, there should be unique logic input
- ALU for each op-code. This function can be performed by decoder
- Register. which takes encoded input and produces and single output.
- Internal data path.
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /42
IR - Micro instruction sequencing:- Get then next micro
instruction from the control memory.
- Micro instruction execution:- Generates the control signals
needed to execute the micro instruction.
Decoder
Let us consider a single control signal c5. This signal causes data
to be read from external data bus into MBR. Let us define two Address decoder
new control signal P and Q that have following interpretation.
PQ = 00 Fetch cycle. contorl memory
PQ = 01 Indirect cycle .
PQ = 10 Execute cycle .
CBR contorl address address
PQ = 11 Interrupt cycle. 2 3
flags
Then the following Boolean expression define c5. Branch
logic MUX
C5 = P’Q’T2 +p’.Q.T2 address
selection
i.e the control signal c5 will be asserted during the 2nd time unit IR
of both fetch and indirect cycle.
Fig: branch control logic, two address fields.
Microinstruction sequencing: The two basic task performed
by micro programmed control unit are as follows: A multiplexer is provided that serves as destination for both
address field plus instruction register based on the address
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selection input the multiplexer transmits the op-code or one of IR
contorl
memory
contorl memory
CBR
contorl address
+1 CAR
Fig: Branch control logic single address field. Fig: control unit organization.
Micro instruction execution: The sequencing logic module generates a address of next micro
The effect of execution of micro instruction is to generate control instruction using as inputs instruction register flags, CAR(for
signal. Some of these signals control points internal to the implementing), control buffer register. The module is driven by
processor. The remaining signal go to the external control bus. clock that determine the timing of micro instruction cycle. The
control logic module generate the control signal as a function of
some of the bits in micro instruction.
Application of microprogramming:
The set of current application for micro programming include:
- Realization of computer.
- Micro program approach offer a systematic technique for
control unit implementation. A relative technique is
emulation. Emulation refer to used of microprogramming
on one machine to execute program original written for
another.
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /44
- Another used of microprogram is in the area of operating instruction is executed on different set of data by different
system supports. processes.
- Realization of special purpose device a good example of 3. Multiple instruction single data(MISD)stream:- A
this is data communication bore sequence of data is transmitted to a set of processor. Each
- High level language support microprogramming can be of which executes different instruction sequence. This
used to support monitoring detection, isolation and repair structure is not commercially implemented.
of system error. These feature are known as micro 4. Multiple instruction multiple data(MIMD) stream:- A set
diagnostics and significantly enhance the system processor simultaneously execute different instruction
maintenance facility. sequence on different data set.
- User tailoring, a no of machine produced writable control
store that is control memory implemented in RAM rather CU
IS
PU
DS
MU
than ROM and allows the user to write micro programs.
These allows the user to tailor the machine to the desire a) SISD
application. DS
PU1 LM1
DS
CU PU2 LM2
Date:2066/1/29
Chapter:- 8
DS
PUn LMn
Parallel organization:-
Parallel processor system:- b) SIMD( with distributed memory)
The most common way of categorizing computer system are: CU1 PU1
1. Single instruction single data stream(SISD): A single
processor executes a single instruction stream to operate CU2 PU2 Shared
on data stored in single memory. Memory
elements has associated data memory so that each c) MIMD (with shared memory)
Downloaded from www.jayaram.com.np /45
memory multiple processor or distributed memory
PU1
DS
LM1 multiprocessor.
CU1
PU2
DS
LM2 Interconnection Multiprocessing: A multiprocessor system is interconnection
CU2
Network system of two more CPU with memory and I/O equipment.
Multiprocessor are classified as multiple instruction multiple
data string (MIMS). Multiprocessing improves the reliability of
DS
CUn PUn LMn the system so that filer or error in one part has limited effect on
rest of the system. If a fault causes one processor to fail, second
d) MIMD(with distributed memory)
processor can be assign to perform the disabled processor.
The benefit derived from multiprocessor
organization is include system performance. The system derives
its high performance from the fact that computation can proceed
in parallel in one of the two ways.
Fig: Alternative computer organization.
1. Multiple independent jobs can be made to operate in
CU = control unit.
parallel.
PU= processing unit.
2. A single job can partition in to multiple parallel task.
IS = Instruction stream.
The interconnection between the components of multiprocessor
DS= Data stream.
can have different physical configuration depending on the
MU= Memory unit.
number of transfer path that are available between the processor
LM= Loosely packed memory (distributed memory)
and memory. Some of them are:
TM= trgutly packed memory.
1. Time shared common bus.
2. Multi port memory.
With SISD there is some sort of control unit (shared memory)
3. Crossbar switch.
that provide instruction string to processing unit. The processing
unit operate on single data stream from memory unit. With
Time shared common bus:
SIMD there is single control unit, now feding single instruction
unit to multiple processing unit. Each PU may have its own
dedicated memory or there may be a shred memory. Finally with
MIMD there are multiple control units each feeding a separate
instruction stream to its own PU. The MIMD may be sheared
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /46
Memory
unit
A multiple memory system employs separate buses between
each memory module and each CPU. This is shown in figure for
four CPU and four memory module. Each processor bus is
connected to each memory module. The memory module is said
CPU1 CPU2 CPU3 CPU4 CPU5
to have four ports and each ports accommodates one of the
buses. The module must have internal control logic to determine
which port will have to access to memory at any given time.
Fig: Time shared common bus organization. Memory access conflict results are reserve by assigning fixed
priority to each memory ports. Thus CPU1 will have priority
A common bus multiprocessor system consist of number of over CPU2, CPU2 will have priority over CPU3, and CPU4 will
processor connected through common path to a memory unit. A have lowest priority.
time shear common bus for 5 five processor is shown in fig .
Only one processor can communicate with memory or another
processor at a given time. Crossbar switch:-
CPU1
CPU1
CPU2
CPU2
CPU3
CPU3
CPU4
Processors
P1 P2 P3 P1 P2 P3
Fig: cache configuration after load on x. b) with write back cache policy.
Processors memory
P1 P2 P3 CPU1 CPU2 CPU3
A A
a) with write through cache policy.
CPU2 reads block A
Shared Shared
Bus
- By Er. Manoj Basnet (Teaching Assistant), PU school of Engineering and Technology ,Biratnagar. /50
stages can operate on different sets of data concurrently. Floating
point addition is broken up into four stages: Compare, shift, Add
and Normalize. A vector of numbers is presented sequentially to
the first stage as the processing proceeds four different stets of
numbers will be operated on concurrently in the pipeline.
C S A N
xi
compare Shift Add
exponent Significant Significant Normalize
yi
x1 y1 C S A N Z1
x2 y2 A Z2
C S N
x3 y3 A Z3
C S N
x4 y4 C S A N Z4