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A B C D E

Volvi2 Block Diagram Project code: 91.4X101.001


PCB P/N : 55.4X101.0SA
REVISION : 07220-SA

SA-0606
4 Mobile CPU SYSTEM DC/DC 4
MAX8744 31
CLK GEN. Merom 479 G792 PCB STACKUP INPUTS OUTPUTS
RTM875T-605
(ICS 9LPRS502) 3
Celeron M 20
2.0G : 71.MEROM.A0U TOP
5V_S5(6A)
2.33G : 71.MEROM.B0U DCBATOUT
4, 5 VCC 3D3V_S5(6A)

HOST BUS 533/667MHz@1.05V S

DDR2 S SYSTEM DC/DC


533/667MHz SVIDEO/COMP TPS51124 32
533/667 MHz Intel GL960
AGTL+ CPU I/F
TVOUT 15 GND

BOTTOM
INPUTS OUTPUTS
12,13 LVDS 14" WXGA
DDR Memory I/F
LCD 14 DCBATOUT
1D05V_S0(8A)
INTEGRATED GRAHPICS
DDR2 533/667MHz LVDS, CRT I/F RGB CRT
1D8V_S3(12A)

CRT 15
3 533/667 MHz 71.GL960.00U, SLA5V 6,7,8,9,10,11 TPS51100(G2997) 33 3
12,13 DDR_VREF_S0
X4 DMI 1D8V_S3
C-Link0 (1.5A)
400MHz DDR_VREF_S3
Audio BD REVISION:07551-SA
10/100 LAN TXFM RJ45 APL5913 33
Codec AZALIA Marvell 88E8039 22 22
ALC268 ICH8M 22 1D8V_S3 1D25V_S0
(1.5A)

MIC In 24 6 PCIe ports G909 28


PCI/PCI BRIDGE Mini Card
abgn/bg 23 5V_AUX_S5 3D3V_AUX_S5
25 ACPI 1.1 (100mA)

INT.MIC 3 SATA
PCIex1 PWR SW APL5915 33
1 PATA 66/100
10 USB 2.0/1.1 ports
New card
23 P2231NFC
23 1D8V_S3 1D5V_S0
25 OP AMP ETHERNET (10/100/1000MbE)
(1.5A)

G1431Q 25 High Definition Audio CHARGER


2 MAX8731 34 2
INT.SPKR LPC I/F LPC BUS
Serial Peripheral I/F INPUTS OUTPUTS
OP AMP Matrix Storage Technology(DO)
G1412 CHG_PWR
25
Active Managemnet Technology(DO)
KBC SPI I/F BIOS LPC 18V 4.0A
Line Out Winbond W25X80-VSS DCBATOUT
DEBUG UP+5V
WPC8763L 27 5V 100mA
(No-SPDIF) 26 CONN. 36
MODEM 71.ICH8M.C0U, SLA5Q, B3 CPU DC/DC
RJ1122 MDC Card 16,17,18,19 MAX8770
21 Touch INT. 30
USB
SATA

PATA

Pad 27 KB 27 INPUTS OUTPUTS

DCBATOUT
VCC_CORE_S0
0~1.3V
47A
1 HDD CDROM USB USB BD RTM
1
21 21 1 PORT 2 PORT
21 21 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
REVISION:06628-1 Taipei Hsien 221, Taiwan, R.O.C.

Title

BLOCK DIAGRAM
Size Document Number Rev
A3
Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 1 of 36
A B C D E
ICH8M Functional Strap Definitions
ICH8-M EDS 21762 2.0V1 page 16
ICH8M Integrated Pull-up Crestline Strapping Signals and
Signal Usage/When Sampled Comment and Pull-down Resistors Configuration Crestline EDS 20954
page 7
1.0
ICH8-M EDS 21762 2.0V1
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: SIGNAL Resistor Type/Value CFG[2:0] FSB Frequency Select 001 = FSB533
offset 224h) HDA_BIT_CLK PULL-DOWN 20K 011 = FSB667
010 = FSB800
HDA_RST# NONE others = Reserved
4 HDA_SYNC PCIE config1 bit0, This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h) CFG[4:3] Reserved
4
Rising Edge of PWROK. HDA_SDIN[3:0] PULL-DOWN 20K
GNT2# PCIE config2 bit0, This signal has a weak internal pull-up. HDA_SDOUT PULL-DOWN 20K CFG5 DMI x2 Select 0 = DMI x2
Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) 1 = DMI x4 (Default)
HDA_SYNC PULL-DOWN 20K CFG[8:6] Reserved
GPIO20 Reserved This signal should not be pulled high.
GNT[3:0] PULL-UP 20K 0 = Normal mode
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. Low Power PCI Express 1 = Low Power mode (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop GPIO[20] PULL-DOWN 20K ?
and mobile. 0 = Reverse Lanes,15->0,14->1 ect..
LDA[3:0]#/FHW[3:0]# PULL-UP 20K CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
Lane Reversal Numbered in order
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for LAN_RXD[2:0] PULL-UP 10K
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the LDRQ[0] PULL-UP 20K CFG[11:10] Reserved
Top-Swap bit until the system is rebooted XOR/ALL Z test 00 = Reserved
without GNT3# being pulled down. LDRQ[1]/GPIO23 PULL-UP 20K
CFG[13:12] straps 01 = XOR mode enabled
PME# PULL-UP 20K 10 = All Z mode enabled
GNT0#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit 11 = Normal Operation (Default)
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). PWRBTN# PULL-UP 20K
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. CFG[15:14] Reserved Reserved
SATALED# PULL-UP 15K
Integrated VccSus1_05, Enables integrated VccSus1_05, VccSus1_5 and CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
INTVRMEN VccSus1_5 and VccCL1_5 VccCL1_5 VRM's when sampled high SPI_CS1# PULL-UP 20K 1 = Dynamic ODT Enabled (Default)
VRM Enable/Disable.
Always sampled. SPI_CLK PULL-UP 20K
CFG[18:17] Reserved
3 Integrated VccLAN1_05 Enables integrated VccLAN1_05 and VccCL1_05 VRM's
SPI_MOSI PULL-UP 20K
0 = Normal operation (Default):lane 3
LAN100_SLP and VccCL1_05 VRM when sampled high SPI_MISO PULL-UP 20K CFG19 DMI Lane Reversal Numbered in order
Enable/Disable.
Always sampled. TACH_[3:0] PULL-UP 20K ? 1 =Reverse Lane,4->0,3->1 ect...

SPKR PULL-DOWN 20K 0 = Only SDVO or PCIE x1 is


PCI Express Lane Signal has weak internal pull-up. Sets bit 27 CFG20 SDVO/PCIE operational (Default)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) TP[3] PULL-UP 20K Concurrent 1 =SDVO and PCIE x1 are operating
of PWROK. simultaneously via the PEG port
USB[9:0][P,N] PULL-DOWN 15K
SPKR No Reboot. If sampled high, the system is strapped to the SDVOCRTL SDVO Present 0 = No SDVO Card present (Default)
Rising Edge of PWROK. "No Reboot" mode(ICH8 will disable the TCO Timer CL_RST# PULL-UP 13K _DATA
system reboot feature). The status is readable 1= SDVO Card present
via the NO REBOOT bit.
NOTE: All strap signals are sampled with respect to the leading
TP3 XOR Chain Entrance. This signal should not be pull low unless using edge of the Crestline GMCH PWORK in signal.
Rising Edge of PWROK. XOR Chain testing.

GPIO33/ Flash Descriptor This signal has a weak internal pull-up.


History
HDA_DOCK Security Override Strap Sampled low:the Flash Descriptor Security will be
_EN# Rising Edge of PWROK overridden. If high,the security measures will be 2007/05/02
in effect.This should only be used in manufacturing 1 Based on Tahoe to modify schematics.
environments. ===========================================================
2007/05/14
1.Page 34:Replace "D25" with "BAS16-1-GP".
2.Page 27:Replace "R485" with "2K7R2j".
2 3.Page 27:DY:C379" 2
4.Page 27:Add "C682" D1u capacitor on "LID1.PIN1"
ICH8M IDE Integrated Series 5.Page 27:Replace "R238" with "0R2".
6.Page 25:Replace "INTMIC1" & "SPKR1" with main source follow connector list.
7.Page 5:Add C115, C116, C141, C149, C169, C171 for Colay with TC25.
Termination Resistors 8.Page 10:Replace "L20" with "68.00217.141".
9.Page 10:Replace "L10" & "L23" with "68.00217.101"
===========================================================
DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
DDACK#, IORDY, DA[2:0], DCS1#,
DCS3#, IDEIRQ

USB Table
PCIE Routing USB
LANE1 LAN Marvell Pair Device
LANE2 MiniCard WLAN 0 USB1
LANE3 NewCard WLAN 1 NC
2 USB2
3 NC
1 RTM
1
4 USB3
5 NC Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
6 NC Taipei Hsien 221, Taiwan, R.O.C.

7 MINICARD Title

8 CCD Reference
Size Document Number Rev
9 NEW1 A3
Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 2 of 36
A B C D E

3D3V_S0
-1 3D3V_S0 -1 R74
3D3V_S0 -1 R63 Do Not Stuff
Do Not Stuff Do Not Stuff 3D3V_CLKGEN_S0 1 2
1 2 3D3V_48MPWR_S0 3D3V_CLKPLL_S0 1 2

1
R244 C154 C403 C393 C409 C399

Do Not Stuff
1

1
C407 C404 C400 C124 C398 C397 C396 DY SCD1U16V2ZY-2GP
DY C394 Do Not Stuff SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

2
SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

2
SC1U16V3ZY-GP

4 4
3D3V_S0
U12

3D3V_CLKGEN_S0 2 55
VDDPCI SDATA SMBD_ICH 12,19
2

2
3D3V_48MPWR_S0 9 56
DY DY DY 16
VDD48 SCLK SMBC_ICH 12,19
R243 R240 R233 R229 VDD
53 VDDREF
10KR2J-3-GP Do Not Stuff Do Not Stuff Do Not Stuff 13 DREFCLK_1 4 1 RN34 DREFCLK 7
DOTT_96/SRCCLKT0 DREFCLK#_1
31 14 3 CKS 2 SRN0J-6-GP DREFCLK# 7
1

1
VDDSRC DOTC_96/SRCCLKC0
47 VDDCPU
PCLKCLK2 17 CLK_PCIE_NEW_R 2 3 RN33 CLK_PCIE_NEW 23
PCLKCLK3 3D3V_CLKPLL_S0 SRCCLKT1/SE1 CLK_PCIE_NEW#_R
12 VDD96I/O SRCCLKC1/SE2 18 1 CKS 4 SRN0J-6-GP CLK_PCIE_NEW# 23
PCLKCLK4 20
PCLKCLK5 VDDPLL3I/O CLK_PCIE_SATA_1 RN31
26 VDDSRCI/O SRCCLKT2/SATACLKT 21 2 3 CLK_PCIE_SATA 16
37 22 CLK_PCIE_SATA_1# 1 CKS 4 SRN0J-6-GP CLK_PCIE_SATA# 16
VDDSRCI/O SRCCLKC2/SATACLKC
41 VDDCPUI/O
2

2
24 CLK_MCH_3GPLL_1 2 3 RN30
DY RTM Do Not Stuff
TP27 PCLKCLK0 1
SRCCLKT3/CR#_C
25 CLK_MCH_3GPLL_1# 1 CKS 4 SRN0J-6-GP
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
R242 R236 R230 R231 PCICLK0/CR#_A SRCCLKC3/CR#_D
Do Not Stuff 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP Do Not Stuff
TP26 PCLKCLK1 3 27 CLK_PCIE_MINI_12 2 3 RN29 CLK_PCIE_MINI1 23
PCICLK1/CR#_B SRCCLKT4 CLK_PCIE_MINI_12#
28 1 CKS 4 SRN0J-6-GP CLK_PCIE_MINI1# 23
1

R245 2 SRCCLKC4
36 PCLK_FWH 1 22R2J-2-GP PCLKCLK2 4 PCICLK2/LTE
PCI_STOP#/SRCCLKT5 30 PM_STPPCI# 17
PCLKCLK3 5 29 PM_STPCPU# 17
PCICLK3 CPU_STOP#/SRCCLKC5
26 PCLK_KBC R238 2 1 22R2J-2-GP PCLKCLK4 6 33 CLK_PCIE_ICH_1 1 4 RN5 CLK_PCIE_ICH 17
PCICLK4/SRC5_EN SRCCLKT6 CLK_PCIE_ICH_1#
CL=20pF±0.2pF SRCCLKC6 32 2 CKS 3 SRN0J-6-GP CLK_PCIE_ICH# 17
C159 17 PCLK_ICH R224 2 1 22R2J-2-GP PCLKCLK5 7
3 SC27P50V2JN-2-GP PCI_F5/ITP_EN DREFSSCLK_1 RN6 3
36 3 2
1 2 GEN_XTAL_IN R77 2
DY 1 Do Not Stuff 51
SRCCLKT7/CR#_F
35 DREFSSCLK#_1 4 CKS 1 SRN0J-6-GP
DREFSSCLK 7
DREFSSCLK# 7
R76 X2 SRCCLKC7/CR#_E
1 2 Do Not Stuff GEN_XTAL_OUT 52 X1
1

X2 CLK_PCIE_LAN_R RN7
-1 R226 2 1 22R2J-2-GP CLK48 CPUCLKT2_ITP/SRCCLKT8 39
CLK_PCIE_LAN#_R
1 4
3 SRN0J-6-GP
CLK_PCIE_LAN 22
17
X-14D31818M-44GP 4,7
CLK48_ICH
R223 2
10 USB_48MHZ/FSLA CPUCLKC2_ITP/SRCCLKC8 38 2 CKS CLK_PCIE_LAN# 22
CPU_SEL0 1 2K2R2J-2-GP
C158 4,7 CPU_SEL1 49 43 CLK_MCH_BCLK_1 1 4 RN8 CLK_MCH_BCLK 6
2

GEN_XTAL_OUT_R FSLB/TEST_MODE CPUCLKT1 CLK_MCH_BCLK_1#


1 2 CPUCLKC1 42 2 CKS 3 SRN0J-6-GP CLK_MCH_BCLK# 6
4,7 CPU_SEL2 R241 2 1 2K2R2J-2-GP CPU_SEL2_R 54
SC27P50V2JN-2-GP FSLC/TEST_SEL/REF0 CLK_CPU_BCLK_1 RN9
CPUCLKT0 46 1 4 CLK_CPU_BCLK 4
17 CLK_ICH14 R237 2 1 22R2J-2-GP 8 45 CLK_CPU_BCLK_1# 2 CKS 3 SRN0J-6-GP CLK_CPU_BCLK# 4
GNDPCI CPUCLKC0
11 GND48
15 GND
19 48 3D3V_CLKGEN_S0
GND CK_PWRGD/PD# CLK_PWRGD 17
23 GNDSRC
34 40 Do Not Stuff
GNDSRC NC#40 Tahoe
44 GNDCPU 1 DY 2
50 R232
GNDREF

ICS9LPRS502PGLFT-GP
71.09502.B0W
RTM:71.00875.B0W
PCLK_FWH 1 2 EC25
DY Do Not Stuff
PCLK_KBC 1 2 EC86
DY Do Not Stuff
2 CLK48_ICH 2
1 2 EC85
DY Do Not Stuff

EMI capacitor

ICS9LPR502HGLFT-GP setting table RTM875T-605 setting table


PIN NAME DESCRIPTION PIN NAME DESCRIPTION
Byte 5, bit 7 Byte 5, bit 7
0 = PCI0 enabled (default) 0 = PCI0 enabled (default) SEL2 SEL1 SEL0
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair CPU FSB
PCI0/CR#_A Byte 5, bit 6 PCI0/CR#_A Byte 5, bit 6 FSC FSB FSA
0 = CR#_A controls SRC0 pair (default), 0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair 1= CR#_A controls SRC2 pair
1 0 1 100M X
Byte 5, bit 5 Byte 5, bit 5
0 = PCI1 enabled (default) 0 = PCI1 enabled (default) 0 0 1 133M X
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
PCI1/CR#_B Byte 5, bit 4 PCI1/CR#_B Byte 5, bit 4 0 1 1 166M 667M
0 = CR#_B controls SRC1 pair (default) 0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair 1= CR#_B controls SRC4 pair 0 1 0 200M 800M
1 RTM 1
0 = Overclocking of CPU and SRC Allowed 0 = Overclocking of CPU and SRC Allowed
PCI2/TME 1 = Overclocking of CPU and SRC NOT allowed PCI2/TME 1 = Overclocking of CPU and SRC NOT allowed

0 = Pin29 as CPU_STOP# , pin 30 as PCI_STOP#. Wistron Corporation


PCI3/SRC-5_EN 1 = Pins29,30 as SRC-5 differential pair. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
0 = Pin29 as CPU_STOP# , pin 30 as PCI_STOP#. 0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96#
PCI4/SRC5_EN 1 = Pins29,30 as SRC-5 differential pair. PCI4/27M_SEL 1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0# Title

0 =SRC8/SRC8# 0 =SRC8/SRC8# Clock Generator


PCI_F5/ITP_EN 1 = ITP/ITP# PCI_F5/ITP_EN 1 = ITP/ITP# Size Document Number Rev
Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 3 of 36
A B C D E
A B C D E

H_A#[35..3]
6 H_A#[35..3]
H_DINV#[3..0]
H_DINV#[3..0] 6
U38A 1 OF 4 TP11 Do Not Stuff H_DSTBN#[3..0]
H_DSTBN#[3..0] 6
H_A#3 J4 H1 1D05V_S0 H_DSTBP#[3..0]
A3# ADS# H_ADS# 6 H_DSTBP#[3..0] 6
H_A#4 L5 E2 H_BNR# 6
H_A#5 A4# BNR# H_D#[63..0]
4 L4 A5# BPRI# G5 H_BPRI# 6 H_D#[63..0] 6 4

ADDR GROUP 0
H_A#6 K5 A6#

1
H_A#7 M3 H5 H_DEFER# 6
H_A#8 A7# DEFER# R40
N2 F21

CONTROL
A8# DRDY# H_DRDY# 6
H_A#9 J1 E1 56R2J-4-GP
A9# DBSY# H_DBSY# 6
H_A#10 N3
H_A#11 A10#
P5 F1 H_BREQ#0 6

2
H_A#12 A11# BR0# Place testpoint on
P2 A12#
H_A#13 L2 D20 H_IERR# H_IERR# with a GND
H_A#14 A13# IERR# 0.1" away
P4 A14# INIT# B3 H_INIT# 16,27
H_A#15 P1
H_A#16 A15#
R1 A16# LOCK# H4 H_LOCK# 6
M1 H_CPURST# 6,36 U38B 2 OF 4
6 H_ADSTB#0 ADSTB0#
6 H_REQ#[4..0] RESET# C1 H_RS#[2..0] 6
H_REQ#0 K3 F3 H_RS#0 H_D#0 E22 Y22 H_D#32
H_REQ#1 H2 REQ0# RS0# H_RS#1 H_D#1 D0# D32# H_D#33
REQ1# RS1# F4 F24 D1# D33# AB24
H_REQ#2 K2 G3 H_RS#2 H_D#2 E26 V24 H_D#34
H_REQ#3 J3 REQ2# RS2# H_D#3 D2# D34# H_D#35
REQ3# TRDY# G2 H_TRDY# 6 G22 D3# D35# V26
H_REQ#4 L1 H_D#4 F23 V23 H_D#36
REQ4# D4# D36#

DATA GRP0
DATA GRP2
G6 H_HIT# 6 H_THERMDA H_D#5 G25 T22 H_D#37
H_A#17 HIT# H_D#6 D5# D37# H_D#38
Y2 A17# HITM# E4 H_HITM# 6 E25 D6# D38# U25

1
H_A#18 U5 H_D#7 E23 U23 H_D#39
H_A#19 A18# C35 H_D#8 D7# D39# H_D#40
R3 A19# BPM0# AD4 K24 D8# D40# Y25
H_A#20 W6 XDP/ITP SIGNALS AD3 SC2200P50V2KX-2GP H_D#9 G24 W22 H_D#41

2
A20# BPM1# D9# D41#
ADDR GROUP 1

H_A#21 U4 AD1 H_THERMDC H_D#10 J24 Y23 H_D#42


H_A#22 A21# BPM2# AS14 -SA H_D#11 D10# D42# H_D#43
Y5 A22# BPM3# AC4 J23 D11# D43# W24
H_A#23 U1 AC2 H_D#12 H22 W25 H_D#44
H_A#24 A23# PRDY# XDP_BPM#5 TP24 Do Not Stuff H_D#13 D12# D44# H_D#45
R4 A24# PREQ# AC1 F26 D13# D45# AA23
H_A#25 T5 AC5 XDP_TCK TP23 Do Not Stuff H_D#14 K22 AA24 H_D#46
3 H_A#26 A25# TCK XDP_TDI TP16 Do Not Stuff1D05V_S0 H_D#15 D14# D46# H_D#47 3
T3 A26# TDI AA6 H23 D15# D47# AB25
H_A#27 W2 AB3 XDP_TDO TP22 Do Not Stuff J26 Y26 H_DSTBN#2 6
A27# TDO 6 H_DSTBN#0 DSTBN0# DSTBN2#
H_A#28 W5 AB5 XDP_TMS TP21 Do Not Stuff H26 AA26 H_DSTBP#2 6
A28# TMS 6 H_DSTBP#0 DSTBP0# DSTBP2#
H_A#29 Y4 AB6 XDP_TRST# TP19 Do Not Stuff H25 U22 H_DINV#2 6
A29# TRST# 6 H_DINV#0 DINV0# DINV2#

1
H_A#30 U2 C20 XDP_DBRESET# TP8 Do Not Stuff
A30# DBR#

56R2J-4-GP
H_A#31 V4
H_A#32 A31# R42 H_D#16 N22 H_D#48
W3 A32# D16# D48# AE24
H_A#33 AA4 THERMAL H_D#17 K25 AD24 H_D#49
H_A#34 A33# H_D#18 P26 D17# D49# H_D#50
AB2 AA21

2
H_A#35 A34# CPU_PROCHOT#_R H_D#19 R23 D18# D50# H_D#51
AA3 A35# PROCHOT# D21 D19# D51# AB22
V1 A24 H_THERMDA 20 H_D#20 L23 AB21 H_D#52
6 H_ADSTB#1 ADSTB1# THRMDA D20# D52#
B25 H_THERMDC 20 H_D#21 M24 AC26 H_D#53
THRMDC D21# D53#

DATA GRP1
DATA GRP3
16 H_A20M# A6 H_D#22 L22 AD20 H_D#54
A20M# H_D#23 M23 D22# D54# H_D#55
16 H_FERR# A5 FERR# THERMTRIP# C7 PM_THRMTRIP-A# 7,16,28 D23# D55# AE22
ICH

16 H_IGNNE# C4 H_D#24 P25 AF23 H_D#56


IGNNE# H_D#25 P23 D24# D56# H_D#57
D25# D57# AC25
16 H_STPCLK# D5 H_D#26 P22 AE21 H_D#58
STPCLK# H_D#27 T24 D26# D58# H_D#59
16 H_INTR C6 LINT0 HCLK BCLK0 A22 CLK_CPU_BCLK 3 D27# D59# AD21
16 H_NMI B4 A21 CLK_CPU_BCLK# 3 H_D#28 R24 AC22 H_D#60
LINT1 BCLK1 H_D#29 L25 D28# D60# H_D#61
16 H_SMI# A3 SMI# D29# D61# AD23
PM_THRMTRIP# 1D05V_S0 H_D#30 T25 AF22 H_D#62
should connect to H_D#31 N25 D30# D62# H_D#63
M4 RSVD#M4 D31# D63# AC23

2
N5 ICH8 and MCH L26 AE25
RSVD#N5 6 H_DSTBN#1 DSTBN1# DSTBN3# H_DSTBN#3 6
T2 without T-ing M26 AF24 H_DSTBP#3 6
RESERVED

RSVD#T2 ( No stub) Layout Note: 1KR2F-3-GP 6 H_DSTBP#1 DSTBP1# DSTBP3#


V3 RSVD#V3 6 H_DINV#1 N24 DINV1# DINV3# AC20 H_DINV#3 6
Tahoe B2 "CPU_GTLREF0" R67
RSVD#B2 0.5" max length. CPU_GTLREF0 COMP0 R200 1 27D4R2F-L1-GP
C3 AD26 R26 2

1 1
RSVD#C3 GTLREF COMP0 COMP1 R2021 54D9R2F-L1-GP
D2 RSVD#D2 C23 TEST1 MISC COMP1 U26 2
D22 D25 AA1 COMP2 R64 1 2 27D4R2F-L1-GP
2 RSVD#D22 R65 TEST2 COMP2 COMP3 R60 1 54D9R2F-L1-GP 2
D3 RSVD#D3 C24 TEST3 COMP3 Y1 2
F6 2KR2F-3-GP Do Not Stuff
TP25 TEST4 AF26
RSVD#F6 Do Not Stuff
TP6 TEST5 TEST4
AF1 TEST5 DPRSTP# E5 H_DPRSTP# 7,16,30
Do Not Stuff
TP53 RSVD_CPU_B1 B1 Do Not Stuff
TP7 TEST6 A26 B5 H_DPSLP# 16

2
KEY_NC TEST6 DPSLP#
DPWR# D24 H_DPWR# 6
BGA479-SKT6-GPU3 3,7 CPU_SEL0 B22 D6 H_PWRGD 16,28,36
BSEL0 PWRGOOD
62.10079.001 3,7 CPU_SEL1 B23 BSEL1 SLP# D7 H_CPUSLP# 6
3,7 CPU_SEL2 C21 BSEL2 PSI# AE6 PSI# 30
2nd source: 62.10053.401
1D05V_S0 BGA479-SKT6-GPU3

Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
XDP_TMS R66 1 2 39R2F-GP trace length shorter than 0.5" .
Net "TEST4" as short as possible, Comp1, 3 connect with Zo=55 ohm, make
XDP_TDI R62 1 2 150R2F-1-GP trace length shorter than 0.5" .
make sure "TEST4" routing is
reference to GND and away other
noisy signals

1 RTM 1

XDP_TCK R68 1 2 27D4R2F-L1-GP Wistron Corporation


21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
XDP_TRST# R69 1 2 649R2F-GP Taipei Hsien 221, Taiwan, R.O.C.

All place within 2" to CPU Title

CPU (1 of 2)
Size Document Number Rev

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 4 of 36
A B C D E
A B C D E

U38D 4 OF 4
VCC_CORE_S0
A4 VSS VSS P6
VCC_CORE_S0 VCC_CORE_S0 A8 P21
VSS VSS
4 A11 VSS VSS P24 4
U38C 3 OF 4 VCC_CORE_S0 A14 R2
VSS VSS
A16 VSS VSS R5

1
A7 AB20 C339 C362 C344 C351 A19 R22
VCC VCC VSS VSS
A9 VCC VCC AB7 A23 VSS VSS R25

1
4
SCD1U10V2KX-4GP

Do Not Stuff

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
A10 AC7 Do Not Stuff
TP42 CPU_AF2 AF2 T1

2
VCC VCC TC1 VSS VSS
A12 VCC VCC AC9 POLY DY POLY POLY Do Not Stuff
B6 VSS VSS T4
A13 VCC VCC AC12 B8 VSS VSS T23
A15 AC13 Do Not Stuff B11 T26
VCC VCC VSS VSS
A17 AC15 PROADLIZER B13 U3

2
3
VCC VCC VSS VSS
A18 VCC VCC AC17 B16 VSS VSS U6
A20 VCC VCC AC18 B19 VSS VSS U21
B7 VCC VCC AD7 B21 VSS VSS U24
B9 VCC VCC AD9 B24 VSS VSS V2
B10 VCC VCC AD10 C5 VSS VSS V5
B12 VCC VCC AD12 C8 VSS VSS V22
B14 VCC VCC AD14 C11 VSS VSS V25
B15 AD15 VCC_CORE_S0 C14 W1
VCC VCC VSS VSS
B17 VCC VCC AD17 C16 VSS VSS W4
B18 VCC VCC AD18 C19 VSS VSS W23
B20 VCC VCC AE9 C2 VSS VSS W26

1
C9 AE10 C37 C38 C45 C46 C59 C132 C135 C136 C144 C145 C338 C340 C374 C375 C22 Y3
VCC VCC VSS VSS
C10 VCC VCC AE12 C25 VSS VSS Y6

Do Not Stuff

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Do Not Stuff

SC10U6D3V5MX-3GP

Do Not Stuff

Do Not Stuff

SC10U6D3V5MX-3GP
C12 AE13 D1 Y21

2
VCC VCC VSS VSS
C13 VCC VCC AE15 DY POLY POLY DY DY DY DY POLY POLY DY POLY DY DY POLY D4 VSS VSS Y24
C15 VCC VCC AE17 D8 VSS VSS AA2
C17 VCC VCC AE18 D11 VSS VSS AA5
C18 VCC VCC AE20 D13 VSS VSS AA8
D9 VCC VCC AF9 D16 VSS VSS AA11
3 D10 AF10 D19 AA14 3
VCC VCC VSS VSS
D12 VCC VCC AF12 D23 VSS VSS AA16
D14 VCC VCC AF14 D26 VSS VSS AA19
D15 VCC VCC AF15 E3 VSS VSS AA22
D17 VCC VCC AF17 E6 VSS VSS AA25
D18 VCC VCC AF18 E8 VSS VSS AB1
E7 AF20 1D05V_S0 E11 AB4
VCC VCC VSS VSS
E9 VCC E14 VSS VSS AB8
E10 VCC VCCP G21 E16 VSS VSS AB11
E12 VCC VCCP V6 E19 VSS VSS AB13
E13 VCC VCCP J6 E21 VSS VSS AB16
E15 VCC VCCP K6 E24 VSS VSS AB19
1

E17 VCC VCCP M6 F5 VSS VSS AB23


SCD1U10V2KX-4GP

E18 J21 C119 F8 AB26


VCC VCCP VSS VSS
SCD1U10V2KX-4GP

E20 K21 C55 F11 AC3


2

VCC VCCP 1D05V_S0 VSS VSS


F7 VCC VCCP M21 F13 VSS VSS AC6
F9 VCC VCCP N21 F16 VSS VSS AC8
F10 VCC VCCP N6 layout note: "1D5V_VCCA_S0" F19 VSS VSS AC11
F12 R21 F2 AC14
F14
VCC VCCP
R6 as short as possible F22
VSS VSS
AC16
VCC VCCP VSS VSS
F15 VCC VCCP T21 F25 VSS VSS AC19

1
F17 T6 C104 C87 C126 C95 C63 C72 G4 AC21
VCC VCCP 1D5V_VCCA_S0 1D5V_S0 VSS VSS
F18 VCC VCCP V21 G1 VSS VSS AC24

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
F20 W21 G23 AD2

2
VCC VCCP VSS VSS
AA7 VCC G26 VSS VSS AD5
AA9 B26 1 L5 2 H3 AD8
VCC VCCA VSS VSS
SCD01U16V2KX-3GP

AA10 C26 0R3-0-U-GP H6 AD11


VCC VCCA VSS VSS
1

AA12 C36 H21 AD13


VCC C39 UMA VSS VSS
AA13 VCC VID0 AD6 H_VID0 30 VCC_CORE_S0 H24 VSS VSS AD16
2 SC4D7U6D3V3KX-GP 2
AA15 AF5 H_VID1 30 J2 AD19
2

VCC VID1 VSS VSS


AA17 VCC VID2 AE5 H_VID2 30 J5 VSS VSS AD22
AA18 VCC VID3 AF4 H_VID3 30 J22 VSS VSS AD25
1

AA20 AE3 H_VID4 30 J25 AE1 CPU_AE1 TP41 Do Not Stuff


VCC VID4 R71 VSS VSS
AB9 VCC VID5 AF3 H_VID5 30 K1 VSS VSS AE4
AC10 AE2 100R2F-L1-GP-U K4 AE8
VCC VID6 H_VID6 30 VSS VSS
AB10 VCC K23 VSS VSS AE11
AB12 K26 AE14
2

VCC VSS VSS


AB14 VCC VCCSENSE AF7 VCC_SENSE 30 L3 VSS VSS AE16
AB15 VCC L6 VSS VSS AE19
AB17 VCC L21 VSS VSS AE23
AB18 AE7 VSS_SENSE 30 L24 AE26 CPU_AE26 TP44 Do Not Stuff
VCC VSSSENSE VSS VSS CPU_A2
M2 VSS VSS A2 TP39 Do Not Stuff
1

Layout Note: M5 AF6


R72 VSS VSS
M22 VSS VSS AF8
BGA479-SKT6-GPU3 100R2F-L1-GP-U VCCSENSE and VSSSENSE lines M25 AF11
should be of equal length. VSS VSS
N1 VSS VSS AF13
N4 AF16
2

VSS VSS
N23 VSS VSS AF19
Layout Note: N26 AF21
Provide a test point (with VSS VSS CPU_A25
P3 VSS VSS A25 TP40 Do Not Stuff
no stub) to connect a AF25 CPU_AF25
VSS TP43 Do Not Stuff
differential probe
between VCCSENSE and
VSSSENSE at the location BGA479-SKT6-GPU3
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (2 of 2)
Size Document Number Rev

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 5 of 36
A B C D E
A B C D E

U37A 1 OF 10
H_D#[63..0] H_A#[35..3]
4 H_D#[63..0] H_A#[35..3] 4
H_D#0 E2 J13 H_A#3
H_D#1 H_D#0 H_A#3 H_A#4
G2 H_D#1 H_A#4 B11
4 H_D#2 G7 C11 H_A#5 4
H_D#3 H_D#2 H_A#5 H_A#6
M6 H_D#3 H_A#6 M11
H_D#4 H7 C15 H_A#7
1D05V_S0 H_D#5 H_D#4 H_A#7 H_A#8
H_SWING routing Trace width and H3 H_D#5 H_A#8 F16
H_D#6 G4 L13 H_A#9
Spacing use 10 / 20 mil H_D#6 H_A#9

1
H_D#7 F3 G17 H_A#10
R173 H_D#8 H_D#7 H_A#10 H_A#11
N8 H_D#8 H_A#11 C14
221R2F-2-GP H_D#9 H2 K16 H_A#12
H_D#10 H_D#9 H_A#12 H_A#13
H_SWING Resistors and M10 H_D#10 H_A#13 B13
H_D#11 N12 L16 H_A#14

2
Capacitors close MCH H_D#12 N9
H_D#11 H_A#14
J17 H_A#15
H_SWING H_D#13 H_D#12 H_A#15 H_A#16
500 mil ( MAX ) H5 H_D#13 H_A#16 B14

SCD1U10V2KX-4GP
H_D#14 P13 K19 H_A#17
H_D#14 H_A#17

1
C315 H_D#15 K9 P15 H_A#18
H_D#15 H_A#18
1

R174 H_D#16 M2 R17 H_A#19


100R2F-L1-GP-U H_D#17 H_D#16 H_A#19 H_A#20
W10 H_D#17 H_A#20 B16
H_D#18 Y8 H20 H_A#21
2

H_D#19 H_D#18 H_A#21 H_A#22


V4 L19

2
H_D#20 H_D#19 H_A#22 H_A#23
M3 H_D#20 H_A#23 D17
H_D#21 J1 M17 H_A#24
H_D#22 H_D#21 H_A#24 H_A#25
N5 H_D#22 H_A#25 N16
H_D#23 N3 J19 H_A#26
H_D#24 H_D#23 H_A#26 H_A#27
W6 H_D#24 H_A#27 B18
H_D#25 W9 E19 H_A#28
H_D#26 H_D#25 H_A#28 H_A#29
H_SCOMP and H_SCOMP# Resistors and N2 H_D#26 H_A#29 B17
H_D#27 Y7 B15 H_A#30
Capacitors close MCH 500 mil ( MAX ) H_D#28 Y9
H_D#27 H_A#30
E17 H_A#31
H_D#29 H_D#28 H_A#31 H_A#32
P4 H_D#29 H_A#32 C18
H_D#30 W3 A19 H_A#33
3 H_D#31 H_D#30 H_A#33 H_A#34 3
N1 H_D#31 H_A#34 B19
H_D#32 AD12 N19 H_A#35
1D05V_S0 H_D#33 H_D#32 H_A#35
AE3 H_D#33
H_D#34 AD9 G12

HOST
H_D#34 H_ADS# H_ADS# 4
1 2 H_SCOMP H_D#35 AC9 H_D#35 H_ADSTB#0 H17 H_ADSTB#0 4
R184 54D9R2F-L1-GP H_D#36 AC7 G20
H_D#36 H_ADSTB#1 H_ADSTB#1 4
1D05V_S0 H_D#37 AC14 C8 H_BNR# 4
H_D#38 H_D#37 H_BNR#
AD11 H_D#38 H_BPRI# E8 H_BPRI# 4
1 2 H_SCOMP# H_D#39 AC11 H_D#39 H_BREQ# F12 H_BREQ#0 4
R185 54D9R2F-L1-GP H_D#40 AB2 D6
H_D#40 H_DEFER# H_DEFER# 4
H_D#41 AD7 C10 H_DBSY# 4
H_D#42 H_D#41 H_DBSY#
AB1 H_D#42 HPLL_CLK AM5 CLK_MCH_BCLK 3
H_D#43 Y3 AM7 CLK_MCH_BCLK# 3
H_D#44 H_D#43 HPLL_CLK#
AC6 H_D#44 H_DPWR# H8 H_DPWR# 4
H_RCOMP routing Trace width and H_D#45 AE2 K7 H_DRDY# 4
H_D#46 H_D#45 H_DRDY#
AC5 E4 H_HIT# 4
Spacing use 10 / 20 mil H_D#47 AG3
H_D#46 H_HIT#
C6 H_HITM# 4
H_D#48 H_D#47 H_HITM#
AJ9 H_D#48 H_LOCK# G10 H_LOCK# 4
H_D#49 AH8 B7 H_TRDY# 4
H_D#49 H_TRDY#
1 2 H_RCOMP H_D#50 AJ14 H_D#50
R182 24D9R2F-L-GP H_D#51 AE9
H_D#52 H_D#51
AE11 H_D#52
H_D#53 AH12 H_DINV#[3..0]
H_D#53 H_DINV#[3..0] 4
H_D#54 AJ5 K5 H_DINV#0
H_D#55 H_D#54 H_DINV#0 H_DINV#1
AH5 H_D#55 H_DINV#1 L2
H_D#56 AJ6 AD13 H_DINV#2
H_D#57 H_D#56 H_DINV#2 H_DINV#3
Place them near to the chip ( < 0.5") H_D#58
AE7
AJ7
H_D#57 H_DINV#3 AE13
H_DSTBN#[3..0]
H_D#58 H_DSTBN#[3..0] 4
H_D#59 AJ2 M7 H_DSTBN#0
2 H_D#60 H_D#59 H_DSTBN#0 H_DSTBN#1 2
AE5 H_D#60 H_DSTBN#1 K3
H_REF Decoupling Crestline H_D#61 AJ3 AD2 H_DSTBN#2
H_D#62 H_D#61 H_DSTBN#2 H_DSTBN#3
AH2 AH11
close Crestline 100 mil H_D#63 AH13
H_D#62 H_DSTBN#3 H_DSTBP#[3..0]
H_DSTBP#[3..0] 4
H_D#63 H_DSTBP#0
H_DSTBP#0 L7
K2 H_DSTBP#1
H_SWING H_DSTBP#1 H_DSTBP#2
B3 H_SWING H_DSTBP#2 AC2
H_RCOMP C2 AJ10 H_DSTBP#3
1D05V_S0 H_RCOMP H_DSTBP#3
H_REQ#[4..0] 4
H_SCOMP W1 M14 H_REQ#0
H_SCOMP# H_SCOMP H_REQ#0 H_REQ#1
W2 H_SCOMP# H_REQ#1 E13
2

A11 H_REQ#2
R169 H_REQ#2 H_REQ#3
4,36 H_CPURST# B6 H_CPURST# H_REQ#3 H13
1KR2F-3-GP E5 B12 H_REQ#4
4 H_CPUSLP# H_CPUSLP# H_REQ#4
H_RS#[2..0] 4
E12 H_RS#0
1

H_AVREF H_RS#0 H_RS#1


B9 H_AVREF H_RS#1 D7
A9 D8 H_RS#2
H_DVREF H_RS#2
1

R177 C313 CRESTLINE-GP-U-NF


2KR2F-3-GP SCD1U16V2ZY-2GP
1
2

CRB v0.9 REQUEST


1 RTM 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GMCH (1 of 6)
Size Document Number Rev

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 6 of 36
A B C D E
A B C D E

U37B 2 OF 10 3D3V_S0 1D05V_S0

P36 RSVD#P36 SM_CK0 AV29 M_CLK_DDR0 12

1
P37 RSVD#P37 SM_CK1 BB23 M_CLK_DDR1 12

8
7
6
5
R35 BA25 M_CLK_DDR2 12 R50
RSVD#R35 SM_CK3 RN27
N35 RSVD#N35 SM_CK4 AV23 M_CLK_DDR3 12 24D9R2F-L-GP
AR12 RSVD#AR12 SRN10KJ-6-GP
AR13 AW30 M_CLK_DDR#0 12 U37C 3 OF 10

2
RSVD#AR13 SM_CK#0
AM12 RSVD#AM12 SM_CK#1 BA23 M_CLK_DDR#1 12
AN13 AW25 M_CLK_DDR#2 12 14 L_BKLTCTL J40 N43 PEG_CMP

1
2
3
4
RSVD#AN13 SM_CK#3 L_BKLT_CTRL PEG_COMPI
J12 RSVD#J12 SM_CK#4 AW23 M_CLK_DDR#3 12 26 GMCH_BL_ON H39 L_BKLT_EN PEG_COMPO M43
AR37 LCTLA_CLK E39
RSVD#AR37 LCTLB_DATA L_CTRL_CLK
AM36 BE29 M_CKE0 12,13 E40

DDR MUXING
RSVD#AM36 SM_CKE0 L_CTRL_DATA
4 AL36 RSVD#AL36 SM_CKE1 AY32 M_CKE1 12,13 14 CLK_DDC_EDID C37 L_DDC_CLK PEG_RX#0 J51 4
AM37 RSVD#AM37 SM_CKE3 BD39 M_CKE2 12,13 14 DAT_DDC_EDID D35 L_DDC_DATA PEG_RX#1 L51
D20 RSVD#D20 SM_CKE4 BG37 M_CKE3 12,13 14 GMCH_LCDVDD_ON K40 L_VDD_EN PEG_RX#2 N47
PEG_RX#3 T45
SM_CS#0 BG20 M_CS0# 12,13 2 1 R43 LIBG L41 LVDS_IBG PEG_RX#4 T50
BK16 M_CS1# 12,13 2K4R2F-GP L_LVBG L43 U40
SM_CS#1 Do Not Stuff
TP9 LVDS_VBG PEG_RX#5
SM_CS#2 BG16 M_CS2# 12,13 N41 LVDS_VREFH PEG_RX#6 Y44
H10 RSVD#H10 SM_CS#3 BE13 M_CS3# 12,13 N40 LVDS_VREFL PEG_RX#7 Y40
B51 RSVD#B51 14 GMCH_TXACLK- D46 LVDSA_CLK# PEG_RX#8 AB51

RSVD
BJ20 RSVD#BJ20 SM_ODT0 BH18 M_ODT0 12,13 14 GMCH_TXACLK+ C45 LVDSA_CLK PEG_RX#9 W49

LVDS
BK22 RSVD#BK22 SM_ODT1 BJ15 M_ODT1 12,13 14 GMCH_TXBCLK- D44 LVDSB_CLK# PEG_RX#10 AD44
BF19 RSVD#BF19 SM_ODT2 BJ14 M_ODT2 12,13 14 GMCH_TXBCLK+ E42 LVDSB_CLK PEG_RX#11 AD40
BH20 RSVD#BH20 SM_ODT3 BE16 M_ODT3 12,13 PEG_RX#12 AG46
BK18 RSVD#BK18 14 GMCH_TXAOUT0- G51 LVDSA_DATA#0 PEG_RX#13 AH49
BJ18 BK31 SM_RCOMP_VOH 14 GMCH_TXAOUT1- E51 AG45
RSVD#BJ18 SM_RCOMP_VOH SM_RCOMP_VOL LVDSA_DATA#1 PEG_RX#14
BF23 RSVD#BF23 SM_RCOMP_VOL BL31 14 GMCH_TXAOUT2- F49 LVDSA_DATA#2 PEG_RX#15 AG41
BG23 RSVD#BG23 C48 LVDSA_DATA#3
BC23 BL15 M_RCOMPP Do Not Stuff
TP3 GMCH_TXAOUT3- J50
RSVD#BC23 SM_RCOMP M_RCOMPN PEG_RX0
BD24 RSVD#BD24 SM_RCOMP# BK14 14 GMCH_TXAOUT0+ G50 LVDSA_DATA0 PEG_RX1 L50
14 GMCH_TXAOUT1+ E50 LVDSA_DATA1 PEG_RX2 M47
SM_VREF#AR49 AR49 14 GMCH_TXAOUT2+ F48 LVDSA_DATA2 PEG_RX3 U44
BH39 AW4 DDR_VREF_S3 D47 T49
RSVD#BH39 SM_VREF#AW4 Do Not Stuff
TP4 GMCH_TXAOUT3+ LVDSA_DATA3 PEG_RX4
AW20 RSVD#AW20 PEG_RX5 T41
BK20 RSVD#BK20 14 GMCH_TXBOUT0- G44 LVDSB_DATA#0 PEG_RX6 W45
14 GMCH_TXBOUT1- B47 LVDSB_DATA#1 PEG_RX7 W41
B42 DREFCLK 14 GMCH_TXBOUT2- B45 AB50

PCI_EXPRESS GRAPHICS
DPLL_REF_CLK DREFCLK# DREFCLK 3 LVDSB_DATA#2 PEG_RX8
B44 RSVD#B44 DPLL_REF_CLK# C42 DREFCLK# 3 PEG_RX9 Y48
C44 H48 DREFSSCLK AC45
RSVD#C44 DPLL_REF_SSCLK DREFSSCLK# DREFSSCLK 3 PEG_RX10
A35 RSVD#A35 DPLL_REF_SSCLK# H47 DREFSSCLK# 3 14 GMCH_TXBOUT0+ E44 LVDSB_DATA0 PEG_RX11 AC41
3 B37 1D8V_S3 A47 AH47 3
RSVD#B37 14 GMCH_TXBOUT1+ LVDSB_DATA1 PEG_RX12
B36 RSVD#B36 PEG_CLK K44 CLK_MCH_3GPLL 3 14 GMCH_TXBOUT2+ A45 LVDSB_DATA2 PEG_RX13 AG49
B34 K45 20R2F-GP R228 AH45

CLK
RSVD#B34 PEG_CLK# CLK_MCH_3GPLL# 3 PEG_RX14
C34 M_RCOMPP 2 1 AG42
RSVD#C34 PEG_RX15
20R2F-GP R227 N45
M_RCOMPN PEG_TX#0
-1 2 1 15 TV_DACA E27 TVA_DAC PEG_TX#1 U39
AN47 DMI_TXN0 15 TV_DACB G27 U47
DMI_RXN0 DMI_TXN1 DMI_TXN0 17 TVB_DAC PEG_TX#2
DMI_RXN1 AJ38 DMI_TXN1 17 15 TV_DACC K27 TVC_DAC PEG_TX#3 N51
3,4 CPU_SEL0 R153 1 2 Do Not Stuff CPU_SEL0_1 P27 AN42 DMI_TXN2 R50
CFG0 DMI_RXN2 DMI_TXN2 17 3D3V_S0 PEG_TX#4

TV
3,4 CPU_SEL1 R157 1 2 Do Not Stuff CPU_SEL1_1 N27 AN46 DMI_TXN3 F27 T42
R154 1 CFG1 DMI_RXN3 DMI_TXN3 17 TVA_RTN PEG_TX#5
3,4 CPU_SEL2 2 Do Not Stuff CPU_SEL2_1 N24 CFG2
R31 RN3 J27 TVB_RTN PEG_TX#6 Y43
C21 AM47 DMI_TXP0 2 150R2F-1-GP
1 TV_DACA 8 1 PM_EXTTS#1 L27 W46
DMI

CFG3 DMI_RXP0 DMI_TXP1 DMI_TXP0 17 PM_EXTTS#0 TVC_RTN PEG_TX#7


C23 CFG4 DMI_RXP1 AJ39 DMI_TXP1 17 7 2 PEG_TX#8 W38
F23 AN41 DMI_TXP2 R30 6 3 TV_DCONSEL0 M35 AD39
CFG5 DMI_RXP2 DMI_TXP3 DMI_TXP2 17 TV_DCONSEL0 PEG_TX#9
N23 CFG6 DMI_RXP3 AN45 DMI_TXP3 17 2 150R2F-1-GP
1 TV_DACB 5 4 TV_DCONSEL1 P33 TV_DCONSEL1 PEG_TX#10 AC46
G23 CFG7 PEG_TX#11 AC49
CFG

J20 AJ46 DMI_RXN0 R39 SRN10KJ-6-GP AC42


CFG8 DMI_TXN0 DMI_RXN0 17 PEG_TX#12
1 R175 2 CFG9 C20 CFG9 DMI_TXN1 AJ41 DMI_RXN1
DMI_RXN1 17 2 150R2F-1-GP
1 TV_DACC
PEG_TX#13 AH39
Do Not Stuff R24 AM40 DMI_RXN2 AE49
CFG10 DMI_TXN2 DMI_RXN3 DMI_RXN2 17 PEG_TX#14
L23 CFG11 DMI_TXN3 AM44 DMI_RXN3 17 PEG_TX#15 AH44
J23 R35
CFG12 DMI_RXP0
E23 CFG13 DMI_TXP0 AJ47 DMI_RXP0 17 2 150R2F-1-GP
1 GMCH_BLUE
PEG_TX0 M45
E20 AJ42 DMI_RXP1 15 GMCH_BLUE GMCH_BLUE H32 T38
CFG14 DMI_TXP1 DMI_RXP2 DMI_RXP1 17 R34 CRT_BLUE PEG_TX1
K23 CFG15 DMI_TXP2 AM39 DMI_RXP2 17 G32 CRT_BLUE# PEG_TX2 T46
M20 AM43 DMI_RXP3 2 150R2F-1-GP
1 GMCH_GREEN 15 GMCH_GREEN GMCH_GREEN K29 N50
CFG16 DMI_TXP3 DMI_RXP3 17 CRT_GREEN PEG_TX3
M24 CFG17 J29 CRT_GREEN# PEG_TX4 R51
L32 R36 15 GMCH_RED GMCH_RED F29 U43
CFG18 CRT_RED PEG_TX5

VGA
N33 CFG19 2 150R2F-1-GP
1 GMCH_RED E29 CRT_RED# PEG_TX6 W42
2 2
L35 Y47
GRAPHICS VID

CFG20 PEG_TX7
PEG_TX8 Y39
E35 15 GMCH_DDCCLK GMCH_DDCCLK K33 AC38
GFX_VID0 GMCH_DDCDATA G35 CRT_DDC_CLK PEG_TX9
GFX_VID1 A39 15 GMCH_DDCDATA CRT_DDC_DATA PEG_TX10 AD47
17 PM_BMBUSY# G41 C38 15 GMCH_VSYNC 1 UMA 2 GMCH_VS E33 AC50
PM_BM_BUSY# GFX_VID2 R165 33R2F-3-GP CRT_VSYNC PEG_TX11
4,16,30 H_DPRSTP# L39 PM_DPRSTP# GFX_VID3 B39 C32 CRT_TVO_IREF PEG_TX12 AD43
PM_EXTTS#0 L36 E36 15 GMCH_HSYNC 1 UMA 2 GMCH_HS F33 AG39
PM_EXT_TS#0 GFX_VR_EN CRT_HSYNC PEG_TX13
PM

Do Not Stuff R212 PM_EXTTS#1 J36 R164 33R2F-3-GP AE50


PWROK_GD PM_EXT_TS#1 Tahoe PEG_TX14
2 1 AW49 AH43
17,30 VGATE_PWRGD DY RSTIN# AV20
PWROK
1 2 CRT_IREF PEG_TX15
R216 1 Do Not2Stuff NB_THERMTRIP# N20 RSTIN# 1D25V_S0 R176 1K3R2F-1-GP
17,20 PWROK THERMTRIP#
17,26,36 PLT_RST1# 2 1 G36 DPRSLPVR

2
R207 100R2J-2-GP CRESTLINE-GP-U-NF
R195
AM49 1KR2F-3-GP FOR Calero: 255 ohm
CL_CLK CL_CLK0 17
BJ51 NC#BJ51 CL_DATA AK50 CL_DATA0 17 Crestline: 1.3k ohm
-1 BK51 AT43
ME

PWROK 17,20
1
NC#BK51 CL_PWROK 1D8V_S3
BK50 NC#BK50 CL_RST# AN49 CL_RST#0 17 CRT_IREF routing Trace
BL50 AM50 MCH_CLVREF R234 1KR2F-3-GP
Do Not Stuff BL49
NC#BL50 CL_VREF
2 1 width use 20 mil
NC#BL49
1

R152 1 2 BL3 3D3V_S0 C359


4,16,28 PM_THRMTRIP-A# NC#BL3
1
SCD1U10V2KX-4GP

17,30 PM_DPRSLPVR BL2 R194 SM_RCOMP_VOH


NC#BL2
NC

BK1 392R2F-GP
NC#BK1
1

1
BJ1 H35 C401 C405
2

NC#BJ1 SDVO_CTRL_CLK R38 R239


E1 K36
2

NC#E1 SDVO_CTRL_DATA CLK_3GPLLREQ# 10KR2J-3-GP 3K01R2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP


A5 G39

2
NC#A5 CLKREQ#
C51 NC#C51 ICH_SYNC# G40 MCH_ICH_SYNC# 17
B50
MISC

NC#B50 SM_RCOMP_VOL
1 A50 NC#A50 1
A49 NC#A49 TEST1 A37
2

1
BK2 NC#BK2 TEST2 R32 TEST2_GMCH C402 C406
R235
Wistron Corporation
1

R46 1KR2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP


2

2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
20KR2J-L2-GP

CRESTLINE-GP-U-NF Taipei Hsien 221, Taiwan, R.O.C.


1

Title
2

GMCH (2 of 6)
Size Document Number Rev

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 7 of 36
A B C D E
A B C D E

4 4

U37D 4 OF 10
M_A_DQ[63..0] U37E 5 OF 10
12 M_A_DQ[63..0] M_B_DQ[63..0]
M_A_DQ0 AR43 BB19 M_A_BS#0 12,13
SA_DQ0 SA_BS0 12 M_B_DQ[63..0]
M_A_DQ1 AW44 BK19 M_A_BS#1 12,13 M_B_DQ0 AP49 AY17 M_B_BS#0 12,13
M_A_DQ2 SA_DQ1 SA_BS1 M_B_DQ1 SB_DQ0 SB_BS0
BA45 SA_DQ2 SA_BS2 BF29 M_A_BS#2 12,13 AR51 SB_DQ1 SB_BS1 BG18 M_B_BS#1 12,13
M_A_DQ3 AY46 M_A_CAS# 12,13 M_B_DQ2 AW50 BG36 M_B_BS#2 12,13
M_A_DQ4 SA_DQ3 M_B_DQ3 SB_DQ2 SB_BS2
AR41 SA_DQ4 SA_CAS# BL17 AW51 SB_DQ3 M_B_CAS# 12,13
M_A_DQ5 AR45 M_A_DM[7..0] M_B_DQ4 AN51 BE17
SA_DQ5 M_A_DM[7..0] 12 SB_DQ4 SB_CAS#
M_A_DQ6 AT42 AT45 M_A_DM0 M_B_DQ5 AN50 M_B_DM[7..0]
SA_DQ6 SA_DM0 SB_DQ5 M_B_DM[7..0] 12
M_A_DQ7 AW47 BD44 M_A_DM1 M_B_DQ6 AV50 AR50 M_B_DM0
M_A_DQ8 SA_DQ7 SA_DM1 M_A_DM2 M_B_DQ7 SB_DQ6 SB_DM0 M_B_DM1
BB45 SA_DQ8 SA_DM2 BD42 AV49 SB_DQ7 SB_DM1 BD49
M_A_DQ9 BF48 AW38 M_A_DM3 M_B_DQ8 BA50 BK45 M_B_DM2
M_A_DQ10 SA_DQ9 SA_DM3 M_A_DM4 M_B_DQ9 SB_DQ8 SB_DM2 M_B_DM3
BG47 SA_DQ10 SA_DM4 AW13 BB50 SB_DQ9 SB_DM3 BL39
M_A_DQ11 BJ45 BG8 M_A_DM5 M_B_DQ10 BA49 BH12 M_B_DM4
M_A_DQ12 SA_DQ11 SA_DM5 M_A_DM6 M_B_DQ11 SB_DQ10 SB_DM4 M_B_DM5
BB47 SA_DQ12 SA_DM6 AY5 BE50 SB_DQ11 SB_DM5 BJ7
M_A_DQ13 BG50 AN6 M_A_DM7 M_B_DQ12 BA51 BF3 M_B_DM6
M_A_DQ14 SA_DQ13 SA_DM7 M_A_DQS[7..0] M_B_DQ13 SB_DQ12 SB_DM6 M_B_DM7
BH49 SA_DQ14 M_A_DQS[7..0] 12 AY49 SB_DQ13 SB_DM7 AW2
M_A_DQ15 BE45 AT46 M_A_DQS0 M_B_DQ14 BF50 M_B_DQS[7..0]
SA_DQ15 SA_DQS0 SB_DQ14 M_B_DQS[7..0] 12
M_A_DQ16 AW43 BE48 M_A_DQS1 M_B_DQ15 BF49 AT50 M_B_DQS0
M_A_DQ17 SA_DQ16 SA_DQS1 M_A_DQS2 M_B_DQ16 SB_DQ15 SB_DQS0 M_B_DQS1
BE44 SA_DQ17 SA_DQS2 BB43 BJ50 SB_DQ16 SB_DQS1 BD50
M_A_DQ18 BG42 BC37 M_A_DQS3 M_B_DQ17 BJ44 BK46 M_B_DQS2
M_A_DQ19 SA_DQ18 SA_DQS3 M_A_DQS4 M_B_DQ18 SB_DQ17 SB_DQS2 M_B_DQS3
BE40 SA_DQ19 SA_DQS4 BB16 BJ43 SB_DQ18 SB_DQS3 BK39
M_A_DQ20 BF44 BH6 M_A_DQS5 M_B_DQ19 BL43 BJ12 M_B_DQS4
M_A_DQ21 SA_DQ20 SA_DQS5 M_A_DQS6 M_B_DQ20 SB_DQ19 SB_DQS4 M_B_DQS5
BH45 SA_DQ21 SA_DQS6 BB2 BK47 SB_DQ20 SB_DQS5 BL7
M_A_DQ22 BG40 AP3 M_A_DQS7 M_A_DQS#[7..0] M_B_DQ21 BK49 BE2 M_B_DQS6
SA_DQ22 SA_DQS7 M_A_DQS#[7..0] 12 SB_DQ21 SB_DQS6
M_A_DQ23 BF40 AT47 M_A_DQS#0 M_B_DQ22 BK43 AV2 M_B_DQS7 M_B_DQS#[7..0]
M_B_DQS#[7..0] 12
DDR SYSTEM MEMORRY A

M_A_DQ24 SA_DQ23 SA_DQS#0 M_A_DQS#1 M_B_DQ23 SB_DQ22 SB_DQS7 M_B_DQS#0


AR40 SA_DQ24 SA_DQS#1 BD47 BK42 SB_DQ23 SB_DQS#0 AU50
3 M_A_DQ25 AW40 BC41 M_A_DQS#2 M_B_DQ24 BJ41 BC50 M_B_DQS#1 3

DDR SYSTEM MEMORY B


M_A_DQ26 SA_DQ25 SA_DQS#2 M_A_DQS#3 M_B_DQ25 SB_DQ24 SB_DQS#1 M_B_DQS#2
AT39 SA_DQ26 SA_DQS#3 BA37 BL41 SB_DQ25 SB_DQS#2 BL45
M_A_DQ27 AW36 BA16 M_A_DQS#4 M_B_DQ26 BJ37 BK38 M_B_DQS#3
M_A_DQ28 SA_DQ27 SA_DQS#4 M_A_DQS#5 M_B_DQ27 SB_DQ26 SB_DQS#3 M_B_DQS#4
AW41 SA_DQ28 SA_DQS#5 BH7 BJ36 SB_DQ27 SB_DQS#4 BK12
M_A_DQ29 AY41 BC1 M_A_DQS#6 M_B_DQ28 BK41 BK7 M_B_DQS#5
M_A_DQ30 SA_DQ29 SA_DQS#6 M_A_DQS#7 M_B_DQ29 SB_DQ28 SB_DQS#5 M_B_DQS#6
AV38 SA_DQ30 SA_DQS#7 AP2 BJ40 SB_DQ29 SB_DQS#6 BF2
M_A_DQ31 AT38 M_A_A[14..0] M_B_DQ30 BL35 AV3 M_B_DQS#7
SA_DQ31 M_A_A[14..0] 12,13 SB_DQ30 SB_DQS#7
M_A_DQ32 AV13 BJ19 M_A_A0 M_B_DQ31 BK37 M_B_A[14..0]
SA_DQ32 SA_MA0 SB_DQ31 M_B_A[14..0] 12,13
M_A_DQ33 AT13 BD20 M_A_A1 M_B_DQ32 BK13 BC18 M_B_A0
M_A_DQ34 SA_DQ33 SA_MA1 M_A_A2 M_B_DQ33 SB_DQ32 SB_MA0 M_B_A1
AW11 SA_DQ34 SA_MA2 BK27 BE11 SB_DQ33 SB_MA1 BG28
M_A_DQ35 AV11 BH28 M_A_A3 M_B_DQ34 BK11 BG25 M_B_A2
M_A_DQ36 SA_DQ35 SA_MA3 M_A_A4 M_B_DQ35 SB_DQ34 SB_MA2 M_B_A3
AU15 SA_DQ36 SA_MA4 BL24 BC11 SB_DQ35 SB_MA3 AW17
M_A_DQ37 AT11 BK28 M_A_A5 M_B_DQ36 BC13 BF25 M_B_A4
M_A_DQ38 SA_DQ37 SA_MA5 M_A_A6 M_B_DQ37 SB_DQ36 SB_MA4 M_B_A5
BA13 SA_DQ38 SA_MA6 BJ27 BE12 SB_DQ37 SB_MA5 BE25
M_A_DQ39 BA11 BJ25 M_A_A7 M_B_DQ38 BC12 BA29 M_B_A6
M_A_DQ40 SA_DQ39 SA_MA7 M_A_A8 M_B_DQ39 SB_DQ38 SB_MA6 M_B_A7
BE10 SA_DQ40 SA_MA8 BL28 BG12 SB_DQ39 SB_MA7 BC28
M_A_DQ41 BD10 BA28 M_A_A9 M_B_DQ40 BJ10 AY28 M_B_A8
M_A_DQ42 SA_DQ41 SA_MA9 M_A_A10 M_B_DQ41 SB_DQ40 SB_MA8 M_B_A9
BD8 SA_DQ42 SA_MA10 BC19 BL9 SB_DQ41 SB_MA9 BD37
M_A_DQ43 AY9 BE28 M_A_A11 M_B_DQ42 BK5 BG17 M_B_A10
M_A_DQ44 SA_DQ43 SA_MA11 M_A_A12 M_B_DQ43 SB_DQ42 SB_MA10 M_B_A11
BG10 SA_DQ44 SA_MA12 BG30 BL5 SB_DQ43 SB_MA11 BE37
M_A_DQ45 AW9 BJ16 M_A_A13 M_B_DQ44 BK9 BA39 M_B_A12
M_A_DQ46 SA_DQ45 SA_MA13 M_A_A14 M_B_DQ45 SB_DQ44 SB_MA12 M_B_A13
BD7 SA_DQ46 SA_MA14 BJ29 BK10 SB_DQ45 SB_MA13 BG13
M_A_DQ47 BB9 M_B_DQ46 BJ8 BE24 M_B_A14
M_A_DQ48 SA_DQ47 M_B_DQ47 SB_DQ46 SB_MA14
BB5 SA_DQ48 SA_RAS# BE18 M_A_RAS# 12,13 BJ6 SB_DQ47
M_A_DQ49 AY7 AY20 SA_RCVEN# M_B_DQ48 BF4 AV16 M_B_RAS# 12,13
M_A_DQ50 SA_DQ49 SA_RCVEN# TP17 Do Not Stuff M_B_DQ49 SB_DQ48 SB_RAS# SB_RCVEN#
AT5 SA_DQ50 BH5 SB_DQ49 SB_RCVEN# AY18 TP18 Do Not Stuff
M_A_DQ51 AT7 BA19 M_A_WE# 12,13 M_B_DQ50 BG1
M_A_DQ52 SA_DQ51 SA_WE# M_B_DQ51 SB_DQ50
AY6 SA_DQ52 BC2 SB_DQ51 SB_WE# BC17 M_B_WE# 12,13
M_A_DQ53 BB7 M_B_DQ52 BK3
2 M_A_DQ54 SA_DQ53 M_B_DQ53 SB_DQ52 2
AR5 SA_DQ54 Place Test PAD Near to Chip BE4 SB_DQ53
M_A_DQ55 AR8 M_B_DQ54 BD3 Place Test PAD Near to Chip
M_A_DQ56 SA_DQ55 as could as possible M_B_DQ55 SB_DQ54
AR9 SA_DQ56 BJ2 SB_DQ55 ascould as possible
M_A_DQ57 AN3 M_B_DQ56 BA3
M_A_DQ58 SA_DQ57 M_B_DQ57 SB_DQ56
AM8 SA_DQ58 BB3 SB_DQ57
M_A_DQ59 AN10 M_B_DQ58 AR1
M_A_DQ60 SA_DQ59 M_B_DQ59 SB_DQ58
AT9 SA_DQ60 AT3 SB_DQ59
M_A_DQ61 AN9 M_B_DQ60 AY2
M_A_DQ62 SA_DQ61 M_B_DQ61 SB_DQ60
AM9 SA_DQ62 AY3 SB_DQ61
M_A_DQ63 AN11 M_B_DQ62 AU2
SA_DQ63 M_B_DQ63 SB_DQ62
AT2 SB_DQ63

CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GMCH (3 of 6)
Size Document Number Rev

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 8 of 36
A B C D E
A B C D E

VCC_NCTF + VCC=1573mA
1D05V_S0
U37F 6 OF 10
FOR VCC CORE AND VCC NCTF
FOR VCC CORE
1573mA AT35 T17 1D05V_S0
VCC VCC_AXG_NCTF
SCD1U10V2KX-4GP AT34 VCC VCC_AXG_NCTF T18

SCD1U10V2KX-4GP
AH28 T19 U37G 7 OF 10

Do Not Stuff

Do Not Stuff
VCC VCC_AXG_NCTF
1

1
1D05V_S0
C345

C102

C78

C101
AC32 VCC VCC_AXG_NCTF T21
AC31 VCC VCC_AXG_NCTF T22 AB33 VCC_NCTF
DY DY AK32 T23 AB36
2

2
VCC VCC_AXG_NCTF VCC_NCTF
AJ31 T25 AB37

VCC CORE
VCC VCC_AXG_NCTF VCC_NCTF

1
C88

C80

C86
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AJ28 U15 TC9 C79 C109 AC33 T27

Do Not Stuff
VCC VCC_AXG_NCTF VCC_NCTF VSS_NCTF
AH32 VCC VCC_AXG_NCTF U16 DY AC35 VCC_NCTF VSS_NCTF T37

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
4 AH31 U17 Do Not Stuff DY AC36 U24 4

2
VCC VCC_AXG_NCTF VCC_NCTF VSS_NCTF
AH29 VCC VCC_AXG_NCTF U19 AD35 VCC_NCTF VSS_NCTF U28
AF32 VCC VCC_AXG_NCTF U20 AD36 VCC_NCTF VSS_NCTF V31
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

U21 AF33 V35


Do Not Stuff
VCC_AXG_NCTF VCC_NCTF VSS_NCTF
1

1
C98

C91

C85

-1 VCC_AXG_NCTF U23
U26 308 mils from
AF36
AH33
VCC_NCTF VSS_NCTF AA19
AB17

VSS NCTF
R48 VCC_AXG_NCTF VCC_NCTF VSS_NCTF
DY V16 the Edge AH35 AB35
2

VCC_AXG_NCTF VCC_NCTF VSS_NCTF


1 2VCC_GMCH1R30 VCC VCC_AXG_NCTF V17 Coupling CAP AH36 VCC_NCTF VSS_NCTF AD19
Do Not Stuff V19 AH37 AD37
VCC_AXG_NCTF VCC_NCTF VSS_NCTF
VCC_AXG_NCTF V20 AJ33 VCC_NCTF VSS_NCTF AF17
VCC_AXG_NCTF V21 AJ35 VCC_NCTF VSS_NCTF AF35
VCC_AXG_NCTF V23 AK33 VCC_NCTF VSS_NCTF AK17
Coupling CAP 370 mils from the Edge VCC_AXG_NCTF V24 AK35 VCC_NCTF VSS_NCTF AM17
VCC_AXG_NCTF Y15 AK36 VCC_NCTF VSS_NCTF AM24
Y16 AK37 AP26
POWER VCC_AXG_NCTF
Y17 AD33
VCC_NCTF VSS_NCTF
AP28

VCC NCTF
1D8V_S3 VCC_AXG_NCTF VCC_NCTF VSS_NCTF
VCC_AXG_NCTF Y19 AJ36 VCC_NCTF VSS_NCTF AR15
AU32 VCC_SM VCC_AXG_NCTF Y20 AM35 VCC_NCTF VSS_NCTF AR19
AU33 VCC_SM VCC_AXG_NCTF Y21 AL33 VCC_NCTF VSS_NCTF AR28
AU35 VCC_SM VCC_AXG_NCTF Y23 AL35 VCC_NCTF
3138mA AV33
AW33
VCC_SM VCC_AXG_NCTF Y24
Y26
AA33
AA35
VCC_NCTF
VCC_SM VCC_AXG_NCTF VCC_NCTF
AW35 VCC_SM VCC_AXG_NCTF Y28 VCC_AXG_NCTF + VCC_AXG=7700mA AA36 VCC_NCTF
FOR VCC SM AY35
BA32
VCC_SM VCC_AXG_NCTF Y29
AA16
AP35
AP36
VCC_NCTF
VCC_SM VCC_AXG_NCTF VCC_NCTF
Place CAP where BA33 VCC_SM VCC_AXG_NCTF AA17 AR35 VCC_NCTF
LVDS and DDR2 taps BA35 VCC_SM VCC_AXG_NCTF AB16 AR36 VCC_NCTF
BB33 VCC_SM VCC_AXG_NCTF AB19 Y32 VCC_NCTF
BC32 VCC_SM VCC_AXG_NCTF AC16 UMA Y33 VCC_NCTF
SCD1U10V2KX-4GP

3 3
DY BC33 VCC_SM VCC_AXG_NCTF AC17 Y35 VCC_NCTF
1

1
C127

TC3
Do Not Stuff
C140

C142
SCD1U10V2KX-4GP

BC35 AC19 Y36


POWER
Do Not Stuff

VCC_SM VCC_AXG_NCTF VCC_NCTF

SCD1U10V2KX-4GP
BD32 AD15 Y37
VCC SM

VCC GFX NCTF


VCC_SM VCC_AXG_NCTF VCC_NCTF

C99
DY BD35 AD16 T30
2

VCC_SM VCC_AXG_NCTF C115 C89 VCC_NCTF NB_A3


BE32 AD17 T34 A3 TP84 Do Not Stuff

VSS SCB
VCC_SM VCC_AXG_NCTF SCD1U10V2KX-4GP SC4D7U10V5ZY-3GP VCC_NCTF VSS_SCB NB_B2
BE33 AF16 T35 B2 TP47 Do Not Stuff

2
VCC_SM VCC_AXG_NCTF VCC_NCTF VSS_SCB NB_C1
BE35 VCC_SM VCC_AXG_NCTF AF19 UMA UMA U29 VCC_NCTF VSS_SCB C1
NB_BL1
TP46 Do Not Stuff
BF33 VCC_SM VCC_AXG_NCTF AH15 U31 VCC_NCTF VSS_SCB BL1 TP45 Do Not Stuff
BF34 AH16 U32 BL51 NB_BL51 TP92 Do Not Stuff
VCC_SM VCC_AXG_NCTF VCC_NCTF VSS_SCB NB_A51
BG32 VCC_SM VCC_AXG_NCTF AH17 U33 VCC_NCTF VSS_SCB A51 TP85 Do Not Stuff
Place on the Edge BG33 VCC_SM VCC_AXG_NCTF AH19 U35 VCC_NCTF
BG35 VCC_SM VCC_AXG_NCTF AJ16 U36 VCC_NCTF
BH32 VCC_SM VCC_AXG_NCTF AJ17 V32 VCC_NCTF
BH34 AJ19 V33 1D05V_S0
VCC_SM VCC_AXG_NCTF VCC_NCTF
1

1
C125

C146 C143 BH35 AK16 C107 C100 V36


Do Not Stuff

VCC_SM VCC_AXG_NCTF VCC_NCTF Tahoe


BJ32 VCC_SM VCC_AXG_NCTF AK19 UMA UMA V37 VCC_NCTF
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
DY BJ33 AL16 AT33

VSS AXM
2

2
VCC_SM VCC_AXG_NCTF VCC_AXM
BJ34 VCC_SM VCC_AXG_NCTF AL17 -1 VCC_AXM AT31
BK32
BK33
VCC_SM VCC_AXG_NCTF AL19
AL20
FOR VCC AXM NCTF AND VCC AXM VCC_AXM AK29
AK24
VCC_SM VCC_AXG_NCTF 1D05V_S0 VCC_AXM_S0 VCC_AXM
BK34 VCC_SM VCC_AXG_NCTF AL21 VCC_AXM AK23
BK35 AL23 R57 AJ26
VCC_SM VCC_AXG_NCTF Do Not Stuff VCC_AXM
BL33 VCC_SM VCC_AXG_NCTF AM15 VCC_AXM AJ23
AU30 VCC_SM VCC_AXG_NCTF AM16 1 2 AL24 VCC_AXM_NCTF

SC10U6D3V5MX-3GP
C108

C117

C114

C118

C106

C110
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AM19 AL26

Do Not Stuff

Do Not Stuff
VCC_AXG_NCTF VCC_AXM_NCTF

1
VCC_AXG_NCTF AM20 AL28 VCC_AXM_NCTF
AM21 1D25V_S0 AM26

VSS AXM NCTF


VCC_AXG_NCTF VCC_AXM_NCTF
R20 AM23 DY DY AM28

2
VCC_AXG VCC_AXG_NCTF Do Not Stuff VCC_AXM_NCTF
T14 VCC_AXG VCC_AXG_NCTF AP15 AM29 VCC_AXM_NCTF
2 2
W13 VCC_AXG VCC_AXG_NCTF AP16 2 1 AM31 VCC_AXM_NCTF
W14 AP17 R58 AM32
VCC_AXG VCC_AXG_NCTF VCC_AXM_NCTF
Y12 VCC_AXG VCC_AXG_NCTF AP19 DY AM33 VCC_AXM_NCTF
AA20 VCC_AXG VCC_AXG_NCTF AP20 AP29 VCC_AXM_NCTF
AA23 VCC_AXG VCC_AXG_NCTF AP21 Coupling CAP AP31 VCC_AXM_NCTF
AA26 VCC_AXG VCC_AXG_NCTF AP23 AP32 VCC_AXM_NCTF
AA28 VCC_AXG VCC_AXG_NCTF AP24 Place on the Edge AP33 VCC_AXM_NCTF
AB21 VCC_AXG VCC_AXG_NCTF AR20 AL29 VCC_AXM_NCTF
AB24
AB29
VCC_AXG VCC_AXG_NCTF AR21
AR23
VCC_AXM_NCTF + VCC_AXM=540mA AL31
AL32
VCC_AXM_NCTF
VCC GFX

VCC_AXG VCC_AXG_NCTF VCC_AXM_NCTF


AC20 VCC_AXG VCC_AXG_NCTF AR24 AR31 VCC_AXM_NCTF
AC21 VCC_AXG VCC_AXG_NCTF AR26 AR32 VCC_AXM_NCTF
AC23 VCC_AXG VCC_AXG_NCTF V26 AR33 VCC_AXM_NCTF
AC24 VCC_AXG VCC_AXG_NCTF V28
AC26 VCC_AXG VCC_AXG_NCTF V29
AC28 VCC_AXG VCC_AXG_NCTF Y31
AC29 VCC_AXG
AD20 CRESTLINE-GP-U-NF
VCC_AXG
AD23 VCC_AXG
AD24 AW45SM_LF1_GMCH
VCC SM LF

VCC_AXG VCC_SM_LF
AD28 VCC_AXG VCC_SM_LF BC39 SM_LF2_GMCH
AF21 VCC_AXG VCC_SM_LF BE39 SM_LF3_GMCH
AF26 VCC_AXG VCC_SM_LF BD17 SM_LF4_GMCH
AA31 VCC_AXG VCC_SM_LF BD4 SM_LF5_GMCH
1D05V_S0 AH20 AW8 SM_LF6_GMCH
VCC_AXG VCC_SM_LF
AH21 VCC_AXG VCC_SM_LF AT6 SM_LF7_GMCH
SC1U10V3KX-3GP

SC1U10V3KX-3GP
C121

C128

C133

C137

C139

C138

C382
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

AH23
SCD47U16V3ZY-3GP

VCC_AXG
1

AH24 VCC_AXG
1 AH26 VCC_AXG 1
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

AD31
2

VCC_AXG
1

C316 C76 AJ20 VCC_AXG


UMA UMA AN14 VCC_AXG Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
CRESTLINE-GP-U-NF
Title

GMCH (4 of 6)
Size Document Number Rev

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 9 of 36
A B C D E
A B C D E

1D05V_S0
Place on the edge

SC2D2U6D3V3MX-1-GP
80mA

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

Do Not Stuff

Do Not Stuff
1

1
3D3V_S0

C53

C64

C54

C68

C333

C58
180ohm 100MHz C69
1D25V_S0 850mA

SC10U6D3V5MX-3GP
R181 2 R172 1

2
Do Not Stuff Do Not Stuff

1
1 2 M_VCCA_DPLLA DY
R28
10mA

1
C327 C326 Do Not Stuff U37H 8 OF 10 DY
SC10U6D3V5MX-3GP SCD1U10V2KX-4GP
U13

2
R183 3D3V_SYNC_S0 VTT 1D25V_S0
4 J32 VCC_SYNC VTT U12 4
Do Not Stuff U11
VTT 200mA

1
1 2 M_VCCA_DPLLB UMA C43 3D3V_CRTDAC_S0 A33 U9 Tahoe
SCD1U10V2KX-4GP VCCA_CRT_DAC VTT
B33 VCCA_CRT_DAC VTT U8
1

CRT

SC1U10V3KX-3GP
C361
C331 UMA C30 U7

2
VTT

1
SC10U6D3V5MX-3GP C332 SCD1U10V2KX-4GP U5 C129
SCD1U10V2KX-4GP M_VCCA_DAC_BG A30 VTT
U3
2

2
VCCA_DAC_BG VTT

SC10U6D3V5MX-3GP
U2

2
3D3V_S0 VTT
180ohm 100MHz B32 VSSA_DAC_BG VTT U1

VTT
T13
2 R166 1 M_VCCA_DAC_BG 5mA VTT
VTT T11
Do Not Stuff T10
80mA M_VCCA_DPLLA VTT

1
C321 B49 T9 1D25V_S0
VCCA_DPLLA VTT
UMA 80mA M_VCCA_DPLLB T7
Tahoe SCD1U10V2KX-4GP H49
VTT
T6 350mA

2
VCCA_DPLLB VTT

PLL
T5
50mA M_VCCA_HPLL VTT

SC1U10V3KX-3GP
C322
AL2 VCCA_HPLL VTT T3

1
T2
1D25V_S0
120ohm 100MHz 2nd source:68.00206.021 150mA M_VCCA_MPLL AM2 VCCA_MPLL
VTT
VTT R3 C34
1D8V_TXLVDS_S3 R2 SC10U6D3V5MX-3GP

2
M_VCCA_HPLL VTT
1 2 R1
10mA POWER

A LVDS
VTT
Do Not Stuff

SC10U6D3V5MX-3GP

L22 1 R179 21D8V_TXLVDS A41 VCCA_LVDS


1

1
FCM1608KF-121-GP C357 C358 C323 Do Not Stuff
C347 SCD1U10V2KX-4GP UMA B41 AT23 1D25V_S0
3D3V_S0 VSSA_LVDS VCC_AXD

SCD1U10V2KX-4GP
DY SC1KP50V2KX-1GP AU28
2

2
Tahoe VCC_AXD
VCC_AXD AU24
120ohm 100MHz K50 AT29
100mA

AXD
VCCA_PEG_BG VCC_AXD

C120
VCC_AXD AT25

1
1 2 M_VCCA_MPLL C47 K49 AT30
400uA

A PEG
3 L9 SCD1U10V2KX-4GP VSSA_PEG_BG VCC_AXD 3

2
1

FCM1608KF-121-GP C122 AR29

2
SCD1U10V2KX-4GP 1D25V_S0 VCC_AXD_NCTF 1D8V_S3
2nd source:68.00206.021 1D25V_RUN_PEGPLL U51
200mA
2

VCCA_PEG_PLL Tahoe
VCC_AXF B23

AXF
VCC_AXF B21

SC1U10V3KX-3GP

SC1U10V3KX-3GP
C105

C116
1D25V_S0 C130 C334 AW18 A21
VCCA_SM VCC_AXF

1
Do Not Stuff

SC10U6D3V5MX-3GP

C325
SCD1U10V2KX-4GP
220ohm 100MHz AV19 C141
VCCA_SM

SC10U6D3V5MX-3GP
L21 AU19 AJ50
Do Not Stuff VCCA_SM VCC_DMI
DY AU18

2
1D25V_RUN_PEGPLL VCCA_SM
1 2 AU17 VCCA_SM
VCC_SM_CK BK24
AT22 BK23

A SM

SM CK
VCCA_SM VCC_SM_CK
1

SCD1U10V2KX-4GP AT21 BJ24


C336 1D25V_S0 VCCA_SM VCC_SM_CK 1D8V_TXLVDS_S3 1D8V_S3
AT19 VCCA_SM VCC_SM_CK BJ23
AT18
100mA
2

VCCA_SM R180 1
AT17 VCCA_SM 2
SC1U10V3KX-3GP
C131

AR17 Do Not Stuff

Do Not Stuff
VCCA_SM_NCTF
1

1
3D3V_S0

C134
C111 AR16 A43
VCCA_SM_NCTF VCC_TX_LVDS
SC10U6D3V5MX-3GP

C324
3D3VTVDAC 3D3V_S0 SC1KP50V2KX-1GP
100mA
2

2
180ohm 100MHz DY BC29 C40

A CK
VCCA_SM_CK VCC_HV

HV
L19 BB29 B40
VCCA_SM_CK VCC_HV Tahoe
1 2
FCM1608CF-1-GP M_VCCA_TVDACA C25 1D05V_S0
VCCA_TVA_DAC
2nd source:68.00206.041 40mA M_VCCA_TVDACB B25 VCCA_TVA_DAC VCC_PEG AD51
1200mA
C27 VCCA_TVB_DAC VCC_PEG W50

TV

SC10U6D3V5MX-3GP
PEG
2 R168 1 M_VCCA_TVDACA B27 W51
40mA M_VCCA_TVDACC VCCA_TVB_DAC VCC_PEG

1
Do Not Stuff B28 V49 C96 C341
VCCA_TVC_DAC VCC_PEG
1

2 C318 C312 2
40mA A28 VCCA_TVC_DAC VCC_PEG V50 DY
UMA UMA Do Not Stuff

2
SCD1U10V2KX-4GP SC2D2U6D3V3MX-1-GP 1D5V_S0 1D05V_S0
60mA VCCD_CRT
2

Tahoe M32 AH50


250mA

TV/CRT
VCCD_CRT VCC_RXR_DMI

DMI
L29 AH51
60mA VCCD_TVDAC VCC_RXR_DMI
5mA

1
2 R163 1 M_VCCA_TVDACB 1D25V_S0 1D5VRUN_QDAC N28 C350 C67
Do Not Stuff VCCD_QDAC VTTLF1
A7
250mA

VTTLF
VTTLF
1

C319 C309 AN2 F2 VTTLF2 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP

2
VCCD_HPLL VTTLF VTTLF3
UMA UMA AH1
SCD1U10V2KX-4GP SC2D2U6D3V3MX-1-GP Tahoe 1D25V_RUN_PEGPLL 100mAU48 VTTLF
2

VCCD_PEG_PLL
1

1
C369

C337
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

J41

LVDS
VCCD_LVDS

1
C349

C330

C317
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
H42
150mA
2

VCCD_LVDS
2 R161 1 M_VCCA_TVDACC
Do Not Stuff

2
1

C320 C310
UMA UMA 1D05V_S0
SCD1U10V2KX-4GP SC2D2U6D3V3MX-1-GP CRESTLINE-GP-U-NF D3
2

1 3D3V_S0
1D8V_S3 R29
R37
Do Not Stuff BAS16-1-GP 3 1D05V_HV_S0 2 1
2 11D8V_SUS_DLVDS 83.00016.B11 10R3J-3-GP
1D5V_S0 R45 2
1

Do Not Stuff C41 C40


2 1 VCCD_CRT UMA UMA
SC10U6D3V5MX-3GP
2

2
1

C44 C49 C50 SCD1U10V2KX-4GP


1 DY UMA 1
SCD1U10V2KX-4GP Do Not Stuff SCD1U10V2KX-4GP
2

1D5V_S0
Wistron Corporation
L7 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Do Not Stuff Taipei Hsien 221, Taiwan, R.O.C.
1 2 1D5VRUN_QDAC
Title
1

180ohm 100MHz C51


UMA GMCH (5 of 6)
SCD1U10V2KX-4GP Size Document Number Rev
2

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 10 of 36
A B C D E
5 4 3 2 1

U37I 9 OF 10

A13 VSS VSS AW24


A15 AW29 U37J10 OF 10
VSS VSS
A17 VSS VSS AW32
A24 VSS VSS AW5
AA21 VSS VSS AW7 C46 VSS VSS W11
AA24 VSS VSS AY10 C50 VSS VSS W39
AA29 VSS VSS AY24 C7 VSS VSS W43
AB20 VSS VSS AY37 D13 VSS VSS W47
AB23 VSS VSS AY42 D24 VSS VSS W5
AB26 VSS VSS AY43 D3 VSS VSS W7
D AB28 VSS VSS AY45 D32 VSS VSS Y13 D
AB31 VSS VSS AY47 D39 VSS VSS Y2
AC10 VSS VSS AY50 D45 VSS VSS Y41
AC13 VSS VSS B10 D49 VSS VSS Y45
AC3 VSS VSS B20 E10 VSS VSS Y49
AC39 VSS VSS B24 E16 VSS VSS Y5
AC43 VSS VSS B29 E24 VSS VSS Y50
AC47 VSS VSS B30 E28 VSS VSS Y11
AD1 VSS VSS B35 E32 VSS VSS P29
AD21 VSS VSS B38 E47 VSS VSS T29
AD26 VSS VSS B43 F19 VSS VSS T31
AD29 VSS VSS B46 F36 VSS VSS T33
AD3 VSS VSS B5 F4 VSS VSS R28
AD41 VSS VSS B8 F40 VSS
AD45 VSS VSS BA1 F50 VSS
AD49 VSS VSS BA17 G1 VSS
AD5 VSS VSS BA18 G13 VSS
AD50 VSS VSS BA2 G16 VSS VSS AA32
AD8 VSS VSS BA24 G19 VSS VSS AB32
AE10 VSS VSS BB12 G24 VSS VSS AD32
AE14 VSS VSS BB25 G28 VSS VSS AF28
AE6 VSS VSS BB40 G29 VSS VSS AF29
AF20 VSS VSS BB44 G33 VSS VSS AT27
AF23 VSS VSS BB49 G42 VSS VSS AV25
AF24 VSS VSS BB8 G45 VSS VSS H50
AF31 VSS VSS BC16 G48 VSS
AG2 VSS VSS BC24 G8 VSS
AG38 VSS VSS BC25 H24 VSS
AG43 VSS VSS BC36 H28 VSS
C AG47 BC40 H4 C
VSS VSS VSS
AG50 BC51 H45
AH3
AH40
VSS
VSS
VSS
VSS BD13
BD2
J11
J16
VSS
VSS VSS
AH41
AH7
VSS
VSS VSS VSS
VSS BD28
BD45
J2
J24
VSS
VSS
VSS VSS VSS
AH9 VSS VSS BD48 J28 VSS
AJ11 VSS VSS BD5 J33 VSS
AJ13 VSS VSS BE1 J35 VSS
AJ21 VSS VSS BE19 J39 VSS
AJ24 VSS VSS BE23 K12 VSS
AJ29 VSS VSS BE30 K47 VSS
AJ32 VSS VSS BE42 K8 VSS
AJ43 VSS VSS BE51 L1 VSS
AJ45 VSS VSS BE8 L17 VSS
AJ49 VSS VSS BF12 L20 VSS
AK20 VSS VSS BF16 L24 VSS
AK21 VSS VSS BF36 L28 VSS
AK26 VSS VSS BG19 L3 VSS
AK28 VSS VSS BG2 L33 VSS
AK31 VSS VSS BG24 L49 VSS
AK51 VSS VSS BG29 M28 VSS
AL1 VSS VSS BG39 M42 VSS
AM11 VSS VSS BG48 M46 VSS
AM13 VSS VSS BG5 M49 VSS
AM3 VSS VSS BG51 M5 VSS
AM4 VSS VSS BH17 M50 VSS
AM41 VSS VSS BH30 M9 VSS
AM45 VSS VSS BH44 N11 VSS
B B
AN1 VSS VSS BH46 N14 VSS
AN38 VSS VSS BH8 N17 VSS
AN39 VSS VSS BJ11 N29 VSS
AN43 VSS VSS BJ13 N32 VSS
AN5 VSS VSS BJ38 N36 VSS
AN7 VSS VSS BJ4 N39 VSS
AP4 VSS VSS BJ42 N44 VSS
AP48 VSS VSS BJ46 N49 VSS
AP50 VSS VSS BK15 N7 VSS
AR11 VSS VSS BK17 P19 VSS
AR2 VSS VSS BK25 P2 VSS
AR39 VSS VSS BK29 P23 VSS
AR44 VSS VSS BK36 P3 VSS
AR47 VSS VSS BK40 P50 VSS
AR7 VSS VSS BK44 R49 VSS
AT10 VSS VSS BK6 T39 VSS
AT14 VSS VSS BK8 T43 VSS
AT41 VSS VSS BL11 T47 VSS
AT49 VSS VSS BL13 U41 VSS
AU1 VSS VSS BL19 U45 VSS
AU23 VSS VSS BL22 U50 VSS
AU29 VSS VSS BL37 V2 VSS
AU3 VSS VSS BL47 V3 VSS
AU36 VSS VSS C12
AU49 VSS VSS C16
AU51 VSS VSS C19
AV39 C28 CRESTLINE-GP-U-NF
VSS VSS
AV48 VSS VSS C29
A AW1 VSS VSS C33 A
AW12 VSS VSS C36
AW16 VSS VSS C41
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
CRESTLINE-GP-U-NF Taipei Hsien 221, Taiwan, R.O.C.

Title

GMCH (6 of 6)
Size Document Number Rev

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 11 of 36
5 4 3 2 1
A B C D E

DM2 DM1

8,13 M_B_A[14..0]
M_B_A0 102 108 M_B_RAS# 8,13 MH1 MH2
M_B_A1 A0 RAS# MH1 MH2
101 A1 WE# 109 M_B_WE# 8,13 8,13 M_A_A[14..0]
M_B_A2 100 113 M_B_CAS# 8,13 M_A_A0 102 13 M_A_DQS0
M_B_A3 A2 CAS# M_A_A1 A0 DQS0 M_A_DQS1
99 A3 101 A1 DQS1 31 M_A_DQS[7..0] 8
M_B_A4 98 110 M_CS2# 7,13 M_A_A2 100 51 M_A_DQS2
M_B_A5 A4 CS0# M_A_A3 A2 DQS2 M_A_DQS3
97 A5 CS1# 115 M_CS3# 7,13 99 A3 DQS3 70
M_B_A6 94 M_A_A4 98 131 M_A_DQS4
M_B_A7 A6 M_A_A5 A4 DQS4 M_A_DQS5
92 A7 CKE0 79 M_CKE2 7,13 97 A5 DQS5 148
M_B_A8 93 80 M_CKE3 7,13 M_A_A6 94 169 M_A_DQS6
M_B_A9 A8 CKE1 M_A_A7 A6 DQS6 M_A_DQS7
91 A9 92 A7 DQS7 188
M_B_A10 105 30 M_CLK_DDR2 7 M_A_A8 93 11 M_A_DQS#0
M_B_A11 A10/AP CK0 M_A_A9 A8 DQS0# M_A_DQS#1
90 A11 CK0# 32 M_CLK_DDR#2 7 91 A9 DQS1# 29 M_A_DQS#[7..0] 8
M_B_A12 89 M_A_A10 105 49 M_A_DQS#2
4
M_B_A13 A12 M_A_A11 A10/AP DQS2# M_A_DQS#3 4
116 A13 CK1 164 M_CLK_DDR3 7 90 A11 DQS3# 68
M_B_A14 86 166 M_CLK_DDR#3 7 M_A_A12 89 129 M_A_DQS#4
M_B_A15 A14 CK1# M_A_A13 A12 DQS4# M_A_DQS#5
Do Not Stuff
TP38 84 A15 M_B_DM[7..0] 8 116 A13 DQS5# 146
8,13 M_B_BS#2 85 10 M_B_DM0 M_A_A14 86 167 M_A_DQS#6
A16/BA2 DM0 M_B_DM1 M_A_A15 A14 DQS6# M_A_DQS#7
DM1 26 Do Not Stuff
TP35 84 A15 DQS7# 186
8,13 M_B_BS#0 107 52 M_B_DM2 8,13 M_A_BS#2 85
BA0 DM2 M_B_DM3 A16_BA2
8,13 M_B_BS#1 106 BA1 DM3 67 M_A_DM[7..0] 8
130 M_B_DM4 10 M_A_DM0
DM4 M_B_DM5 DM0 M_A_DM1
DM5 147 8,13 M_A_BS#0 107 BA0 DM1 26
M_B_DQ0 5 170 M_B_DM6 8,13 M_A_BS#1 106 52 M_A_DM2
M_B_DQ1 DQ0 DM6 M_B_DM7 BA1 DM2 M_A_DM3
8 M_B_DQ[63..0] 7 DQ1 DM7 185 DM3 67
M_B_DQ2 17 M_A_DQ0 5 130 M_A_DM4
M_B_DQ3 DQ2 M_A_DQ1 DQ0 DM4 M_A_DM5
19 DQ3 8 M_A_DQ[63..0] 7 DQ1 DM5 147
M_B_DQ4 4 195 SMBD_ICH 3,19 M_A_DQ2 17 170 M_A_DM6
M_B_DQ5 DQ4 SDA 3D3V_S0 M_A_DQ3 DQ2 DM6 M_A_DM7
6 DQ5 SCL 197 SMBC_ICH 3,19 19 DQ3 DM7 185
M_B_DQ6 14 M_A_DQ4 4
M_B_DQ7 DQ6 M_A_DQ5 DQ4
16 DQ7 VDDSPD 199 6 DQ5 CK0 30 M_CLK_DDR0 7
M_B_DQ8 23 M_A_DQ6 14 32 M_CLK_DDR#0 7
M_B_DQ9 DQ8 M_A_DQ7 DQ6 CK0#
25 DQ9 SA0 198 16 DQ7 CK1 164 M_CLK_DDR1 7

1
M_B_DQ10 35 200 DDRB_SA02 1 M_A_DQ8 23 166 M_CLK_DDR#1 7
M_B_DQ11 DQ10 SA1 R89 M_A_DQ9 DQ8 CK1#
37 DQ11 25 DQ9
M_B_DQ12 20 50 10KR2J-3-GP M_A_DQ10 35 198

2
DQ12 NC#50 DQ10 SA0 3D3V_S0

SCD1U16V2ZY-2GP
M_B_DQ13 22 69 C205 M_A_DQ11 37 200
M_B_DQ14 DQ13 NC#69 M_A_DQ12 DQ11 SA1
36 DQ14 NC#83 83 20 DQ12
M_B_DQ15 38 120 M_A_DQ13 22 199
M_B_DQ16 DQ15 NC#120 M_A_DQ14 DQ13 VDD_SPD
43 DQ16 NC#163/TEST 163 36 DQ14
M_B_DQ17 45 M_A_DQ15 38 C180
DQ17 DQ15

1
SCD1U16V2ZY-2GP
M_B_DQ18 55 M_A_DQ16 43 81
M_B_DQ19 DQ18 M_A_DQ17 DQ16 VDD
57 DQ19 VDD 81 45 DQ17 VDD 82
M_B_DQ20 44 82 M_A_DQ18 55 87

2
M_B_DQ21 DQ20 VDD M_A_DQ19 DQ18 VDD
46 87 57 88
REVERSE TYPE

REVERSE TYPE
3 M_B_DQ22 DQ21 VDD M_A_DQ20 DQ19 VDD 3
56 DQ22 VDD 88 44 DQ20 VDD 95
M_B_DQ23 58 95 M_A_DQ21 46 96
M_B_DQ24 DQ23 VDD M_A_DQ22 DQ21 VDD
61 DQ24 VDD 96 56 DQ22 VDD 103
M_B_DQ25 63 103 M_A_DQ23 58 104
M_B_DQ26 DQ25 VDD M_A_DQ24 DQ23 VDD
73 DQ26 VDD 104 61 DQ24 VDD 111
M_B_DQ27 75 111 M_A_DQ25 63 112 1D8V_S3
M_B_DQ28 DQ27 VDD 1D8V_S3 M_A_DQ26 DQ25 VDD
62 DQ28 VDD 112 73 DQ26 VDD 117
M_B_DQ29 64 117 M_A_DQ27 75 118
M_B_DQ30 DQ29 VDD M_A_DQ28 DQ27 VDD
74 DQ30 VDD 118 62 DQ28
M_B_DQ31 76 M_A_DQ29 64 2
M_B_DQ32 DQ31 M_A_DQ30 DQ29 VSS
123 DQ32 VSS 3 74 DQ30 VSS 3
M_B_DQ33 125 8 M_A_DQ31 76 8
M_B_DQ34 DQ33 VSS M_A_DQ32 DQ31 VSS
135 DQ34 VSS 9 123 DQ32 VSS 9
M_B_DQ35 137 12 M_A_DQ33 125 12
M_B_DQ36 DQ35 VSS M_A_DQ34 DQ33 VSS
124 DQ36 VSS 15 135 DQ34 VSS 15
M_B_DQ37 126 18 M_A_DQ35 137 18
M_B_DQ38 DQ37 VSS M_A_DQ36 DQ35 VSS
134 DQ38 VSS 21 124 DQ36 VSS 21
M_B_DQ39 136 24 M_A_DQ37 126 24
M_B_DQ40 DQ39 VSS M_A_DQ38 DQ37 VSS
141 DQ40 VSS 27 134 DQ38 VSS 27
M_B_DQ41 143 28 M_A_DQ39 136 28
M_B_DQ42 DQ41 VSS M_A_DQ40 DQ39 VSS
151 DQ42 VSS 33 141 DQ40 VSS 33
M_B_DQ43 153 34 M_A_DQ41 143 34
M_B_DQ44 DQ43 VSS M_A_DQ42 DQ41 VSS
140 DQ44 VSS 39 151 DQ42 VSS 39
M_B_DQ45 142 40 M_A_DQ43 153 40
M_B_DQ46 DQ45 VSS M_A_DQ44 DQ43 VSS
152 DQ46 VSS 41 140 DQ44 VSS 41
M_B_DQ47 154 42 M_A_DQ45 142 42
M_B_DQ48 DQ47 VSS M_A_DQ46 DQ45 VSS
157 DQ48 VSS 47 152 DQ46 VSS 47
M_B_DQ49 159 48 M_A_DQ47 154 48
M_B_DQ50 DQ49 VSS M_A_DQ48 DQ47 VSS
173 DQ50 VSS 53 157 DQ48 VSS 53
M_B_DQ51 175 54 M_A_DQ49 159 54
M_B_DQ52 DQ51 VSS M_A_DQ50 DQ49 VSS
158 DQ52 VSS 59 173 DQ50 VSS 59
M_B_DQ53 160 60 M_A_DQ51 175 60
2
M_B_DQ54 DQ53 VSS M_A_DQ52 DQ51 VSS 2
174 DQ54 VSS 65 158 DQ52 VSS 65
M_B_DQ55 176 66 M_A_DQ53 160 66
M_B_DQ56 DQ55 VSS M_A_DQ54 DQ53 VSS
179 DQ56 VSS 71 174 DQ54 VSS 71
M_B_DQ57 181 72 M_A_DQ55 176 72
M_B_DQ58 DQ57 VSS M_A_DQ56 DQ55 VSS
189 DQ58 VSS 77 179 DQ56 VSS 77
M_B_DQ59 191 78 M_A_DQ57 181 78
M_B_DQ60 DQ59 VSS M_A_DQ58 DQ57 VSS
180 DQ60 VSS 121 189 DQ58 VSS 121
M_B_DQ61 182 122 M_A_DQ59 191 122
M_B_DQ62 DQ61 VSS M_A_DQ60 DQ59 VSS
192 DQ62 VSS 127 180 DQ60 VSS 127
M_B_DQ63 194 128 M_A_DQ61 182 128
DQ63 VSS M_A_DQ62 DQ61 VSS
VSS 132 192 DQ62 VSS 132
M_B_DQS#0 11 133 M_A_DQ63 194 133
M_B_DQS#1 DQS0# VSS DQ63 VSS
8 M_B_DQS#[7..0] 29 DQS1# VSS 138 VSS 138
M_B_DQS#2 49 139 50 139
M_B_DQS#3 DQS2# VSS NC#50 VSS
68 DQS3# VSS 144 69 NC#69 VSS 144
M_B_DQS#4 129 145 83 145
M_B_DQS#5 DQS4# VSS NC#83 VSS
146 DQS5# VSS 149 120 NC#120 VSS 149
M_B_DQS#6 167 150 163 150
M_B_DQS#7 DQS6# VSS NC#163/TEST VSS
186 DQS7# VSS 155 VSS 155
VSS 156 7,13 M_CS0# 110 CS0# VSS 156
M_B_DQS0 13 161 7,13 M_CS1# 115 161
M_B_DQS1 DQS0 VSS CS1# VSS
8 M_B_DQS[7..0] 31 DQS1 VSS 162 7,13 M_CKE0 79 CKE0 VSS 162
M_B_DQS2 51 165 7,13 M_CKE1 80 165
M_B_DQS3 DQS2 VSS CKE1 VSS
70 DQS3 VSS 168 8,13 M_A_RAS# 108 RAS# VSS 168
M_B_DQS4 131 171 8,13 M_A_CAS# 113 171
M_B_DQS5 DQS4 VSS CAS# VSS
148 DQS5 VSS 172 8,13 M_A_WE# 109 WE# VSS 172
M_B_DQS6 169 177 177
M_B_DQS7 DQS6 VSS SMBC_ICH VSS
188 DQS7 VSS 178 197 SCL VSS 178
DDR_VREF_S3 183 SMBD_ICH 195 183
VSS DDR_VREF_S3 SDA VSS
7,13 M_ODT2 114 OTD0 VSS 184 VSS 184
7,13 M_ODT3 119 OTD1 VSS 187 7,13 M_ODT0 114 ODT0 VSS 187
1 190 119 190 1
VSS 7,13 M_ODT1 ODT1 VSS
1 VREF VSS 193 VSS 193
2 VSS VSS 196 1 VREF VSS 196
1

C202 DY C197
1

DY C181
202 201 201 202
Wistron Corporation
SCD1U16V2ZY-2GP
Do Not Stuff

GND GND C174 GND GND


2

MH1 MH2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


SCD1U16V2ZY-2GP
Do Not Stuff

MH1 MH2 Taipei Hsien 221, Taiwan, R.O.C.


SKT-SODIMM20022U2GP
DDR2-200P-23-GP-U1 Title
62.10017.691
62.10017.A71
2nd source: 62.10017.B51 2nd source: 62.10017.911 DDR2 Socket
Size Document Number Rev
High 9.2mm High 5.2mm Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 12 of 36
A B C D E
A B C D E

DDR_VREF_S0
PARALLEL TERMINATION
RN10 Put decap near power(0.9V) and pull-up resistor Decoupling Capacitor
8 1 M_CKE0 7,12
7 2 M_CKE1 7,12
6 3 M_A_BS#2 8,12
5 4 M_A_A12

SRN56J-5-GP Put decap near power(0.9V)


RN18 DDR_VREF_S0
8 1 M_B_A8 and pull-up resistor
4 7 2 M_B_A9 4
6 3 M_B_A5
5 4

1
C166 C167 C168 C169 C178 C179 C183 C184 C190 C191 C192

Do Not Stuff

Do Not Stuff

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Do Not Stuff

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Do Not Stuff

SCD1U16V2ZY-2GP

Do Not Stuff
SRN56J-5-GP
RN17

2
8 1 M_CKE2 7,12 DY DY DY
7 2 M_CKE3 7,12
6 3 M_B_BS#2 8,12 DY DY
5 4 M_B_A12
SRN56J-5-GP
RN19
8 1 M_B_A3 M_A_A[14..0]
M_A_A[14..0] 8,12
7 2 M_B_A1
6 3 M_B_A10 M_B_A[14..0]
M_B_A[14..0] 8,12
5 4 M_B_WE# 8,12

1
C193 C194 C195 C203 C204 C207 C208 C212 C213 C214 C215

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Do Not Stuff

Do Not Stuff

Do Not Stuff

SCD1U16V2ZY-2GP

Do Not Stuff

Do Not Stuff

SCD1U16V2ZY-2GP

Do Not Stuff

Do Not Stuff
SRN56J-5-GP
RN23

2
8 1 M_B_A13 DY DY DY DY
7 2 M_ODT2 7,12
6 3 M_ODT3 7,12 DY DY DY
5 4 M_B_RAS# 8,12
SRN56J-5-GP

RN22
8 1 M_B_BS#1 8,12
3 M_B_A2 3
7
6
2
3 M_B_A0 1D8V_S3 Place these Caps near DM1
5 4 M_B_A4

SRN56J-5-GP

1
C427 C187 C428 C188 C426

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP
RN21
8 1 M_B_A14

2
7 2 M_B_A6
6 3 M_B_A7
5 4 M_B_A11

SRN56J-5-GP

RN20
8 1 M_B_BS#0 8,12
7 2 M_B_CAS# 8,12
6 3 M_CS3# 7,12
5 4 M_CS2# 7,12

1
C165 C177 C182 C185

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
SRN56J-5-GP

2
RN16
8 1 M_A_A13 DY DY DY DY
7 2 M_ODT0 7,12
6 3 M_CS0# 7,12
5 4 M_A_RAS# 8,12
SRN56J-5-GP
2 2

RN15
8 1 M_A_BS#1 8,12
7 2 M_A_A0
M_A_A2
6
5
3
4 M_A_A4 1D8V_S3 Place these Caps near DM2
SRN56J-5-GP

1
RN13 C199 C216 C200 C209 C217

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP
8 1 M_A_CAS# 8,12
7 2
2

2
6 3 M_CS1# 7,12
5 4 M_ODT1 7,12
SRN56J-5-GP

RN11
8 1 M_A_A9
7 2 M_A_A8
6 3 M_A_A5
5 4 M_A_A3
1

1
C210 C198 C211 C196
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
SRN56J-5-GP
2

2
RN14
8 1 M_A_A6 DY DY DY DY
7 2 M_A_A7
1 6 3 M_A_A11 1
5 4 M_A_A14

SRN56J-5-GP
Wistron Corporation
RN12 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
8 1 M_A_A1 Taipei Hsien 221, Taiwan, R.O.C.
7 2 M_A_A10
6 3 Title
M_A_BS#0 8,12
5 4 M_A_WE# 8,12
DDR2 Termination Resistor
SRN56J-5-GP Size Document Number Rev

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 13 of 36
A B C D E
LCD/INVERTER CONN LED
LCDVDD

LCD1 Q13 on Front Panel


C PWRLED#_DB 3D3V_S0

1
41 C5 B R1 LED6
26 PWR_G_LED
2 1 E 1 R382 2 FRONT_PWRLED#_R 3 1
SCD1U25V3ZY-1GP R2 68R2-GP 3D3V_S5

2
17 USBPN8 2 Do Not Stuff
1 R9 USB_8- 4 3 DDTC143ZUA-7-F-GP
17 USBPP8 2 Do Not Stuff
1 R10 USB_8+ 6 5 84.00143.D1K 1 R381 2 STDBY_LED#_R 4 2
8 7 Q12 100R2J-2-GP
3D3V_S0 10 9 GMCH_TXAOUT2- 7 C STDBY_LED#_DB LED-GY-14-GP
12 11 GMCH_TXAOUT2+ 7 26 PWR_O_LED B R1 83.00195.I70
14 13 GMCH_TXAOUT1- 7 E
CLK_DDC_EDID 16 15 GMCH_TXAOUT1+ 7 ODD CHANNEL R2
DAT_DDC_EDID 18 17 GMCH_TXAOUT0- 7 DDTC143ZUA-7-F-GP
20 19 GMCH_TXAOUT0+ 7 84.00143.D1K
7 L_BKLTCTL R144 1 2 CCD_PWR 22 21 GMCH_TXACLK- 7 Power Button
Do Not StuffDY 24 23 GMCH_TXACLK+ 7 3D3V_S0
26 BRIGHTNESS R143 1 2 BRIGHTNESS_CN 26 25 Power: LED1
0R2J-2-GP BLON_OUT GMCH_TXBOUT2- 7 FRONT_PWRLED#_R
26 BLON_OUT 28 27 3 1
30 29
GMCH_TXBOUT2+ 7 Green : S0 3D3V_S5
Do Not Stuff

Do Not Stuff
GMCH_TXBOUT1- 7
1 10KR2J-3-GP

R12 32 31 EVEN CHANNEL Orange : S3


GMCH_TXBOUT1+ 7
1

1
C6 C295 DCBATOUT 34 33 STDBY_LED#_R 4 2
DY DY F1 36 35
GMCH_TXBOUT0- 7 Orange Blinking : Enter S4
GMCH_TXBOUT0+ 7 LED-GY-14-GP
1 2 38 37
2

GMCH_TXBCLK- 7
40 39 83.00195.I70
2

GMCH_TXBCLK+ 7
1
C4 SC10U25V6KX-1GP FUSE-4A32V-6-GP 42
69.44001.041
Q23 on Front Panel
2

ACES-CONN40A-2GP C CHARGE_LED#_DB 3D3V_S5


R1 LED7
20.F0993.040 26 CHARGE_LED B
E 1 R379 2 CHARGE_LED#_R 4 2
R2 100R2J-2-GP
2nd source: 20.F1048.040 DDTC143ZUA-7-F-GP
84.00143.D1K 1 R380 2 DC_BATFULL#_R 3 1
Q24 68R2-GP
3D3V_S0 C DC_BATFULL#_DB LED-GY-14-GP
26 DC_BATFULL B R1 83.00195.I70
R2
E Charger:
Green: Battary Full
1
2
3
4

DDTC143ZUA-7-F-GP
LCDVDD 3D3V_S0 84.00143.D1K OFF : Battery or DC only
RN2
SRN4K7J-10-GP U35 Orange : Charging
Orange Blink : Battery low
1 9
8
7
6
5

IN#1 GND
7 CLK_DDC_EDID 2 OUT IN#8 8
3D3V_S0

SC1U16V3ZY-GP
7 GMCH_LCDVDD_ON 3 7 D23
EN IN#7

1
SC1U16V3ZY-GP

4 6 2 LED2 LED-G-62-GP
Do Not Stuff

7 DAT_DDC_EDID GND IN#6


1

C293 C292 21 ODD_LED# MEDIA_LED# 1 R27 MEDIA_LED#_R


DY IN#5 5 3 2 2 1
1

DY EC8 C294 220R2J-L2-GP

2
Do Not Stuff 1 BAW56PT-U 83.00190.Q70
2

G5281RC1U-GP 16 SATA_LED# 83.00056.E11


2
1

DY EC7
Do Not Stuff LED3 LED-G-62-GP
1 R53 2 NUM_LED#_R 2 1
2

26 NUM_LED# 220R2J-L2-GP
83.00190.Q70

EMI LED4 LED-G-62-GP


26 CAP_LED# 1 R61 2 CAP_LED#_R 2 1
GMCH_TXBCLK+ GMCH_TXACLK+ GMCH_TXBOUT1+ GMCH_TXAOUT1+ 220R2J-L2-GP
2

2
3D3V_S0 83.00190.Q70
R8 R4 R6 R2
F2 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
CCD_PWR LED5 3D3V_S0
1 DY 2 DY DY DY DY R217
GMCH_TXBCLK- GMCH_TXACLK- GMCH_TXBOUT1- GMCH_TXAOUT1- LED-Y-64-GP
2 1

2 1

2 1

2 1
1

C3 C2 GMCH_TXBOUT2+ GMCH_TXAOUT2+ GMCH_TXBOUT0+ GMCH_TXAOUT0+ 1 2 WLAN_LED# K A


Do Not Stuff Do Not Stuff 23 WLAN_LED#_MC 33R2J-2-GP 83.00190.S7A
R5 R1 R7 R3
DY DY
2

Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff

D
DY DY DY DY Q8
GMCH_TXBOUT2- GMCH_TXAOUT2- GMCH_TXBOUT0- GMCH_TXAOUT0-
1

26 WLAN_TEST_LED G

Buttons 2N7002-11-GP

S
84.27002.W31

3D3V_AUX_S5
1

R340 26 E_BUTTON#
10KR2J-3-GP 26 WIRELESS_BTN#
2

NUM_LED# EC17 1DY 2 Do Not Stuff


KBC_PWRBTN#_CN 1 R341 2 KBC_PWRBTN# 26 EBTN1 WLBTN1 CAP_LED# EC121 1DY 2 Do Not Stuff
1

Do Not Stuff 1 2 EC87 EC102 2 1


DY DY
2

EC114 PWRBTN1 5 5 RTM


Do Not Stuff

Do Not Stuff
2

2
Do Not Stuff

DY 1 2
1

C518 3 4 4 3
1

SCD1U16V2ZY-2GP

5
SW-TACT-45-U1-GP SW-TACT-45-U1-GP Wistron Corporation
2

3 4 62.40009.341 62.40009.341 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
SW-TACT-45-U1-GP
62.40009.341 Title
2nd source: 62.40009.431 2nd source: 62.40009.431 LCD CONN & LED & Buttons
Size Document Number Rev

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 14 of 36
A B C D E

5V_S0
Layout Note:
Place these resistors
close to the CRT-out
Ferrite bead impedance: 10 ohm@100MHz
D16
2
CRT I/F & CONNECTOR
connector
L3
CRT_R 3 DY CRT1
1 2 CRT_R 17
7 GMCH_RED FCB1608CF-GP 1 MH1
6
L2 Do Not Stuff 11
CRT_R 1
D15
1 2 CRT_G 7
7 GMCH_GREEN FCB1608CF-GP 5V_CRT_S0
2
4 DAT_DDC1_5 12 4
CRT_G 3 DY 2 CRT_G
L1

1
C14 8
1 2 CRT_B 1 DY 13 CRT_HSYNC1
7 GMCH_BLUE FCB1608CF-GP Do Not Stuff CRT_B 3

2
1

1
Do Not Stuff

Do Not Stuff

Do Not Stuff
C15 C12 C9 C16 C13 C10 9 5V_CRT_S0 C17
R17 R15 R14 Do Not Stuff CRT_VSYNC1

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP
D14 14
150R2F-1-GP

150R2F-1-GP

150R2F-1-GP
4 C11 SC18P50V2JN-1-GP

2
1
DY DY DY 2 C18 10
2 15 CLK_DDC1_5 SCD01U16V2KX-3GP

2
CRT_B 3 DY SC18P50V2JN-1-GP 5

1
MH2 C8
1 16 DY
Do Not Stuff

2
3D3V_S0
Do Not Stuff VIDEO-15-21-U4-GP
Layout Note: 20.20334.015

1
* Must be a ground return path between this ground and the ground on R16 5V_S0 2nd source: 20.20410.015
D2
the VGA connector. 10KR2J-3-GP
2
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT R13

2
2 1 CRT_DEC_R 3 DY
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN. 26 CRT_DEC# 0R2J-2-GP

1
C7 1

Do Not Stuff
R18 DY
Do Not Stuff

2
Do Not Stuff
DY

2
3 3
Hsync & Vsync level shift

5V_S0

1
5V_S0
C25
SCD1U16V2ZY-2GP
2

2
D1
BAS16-1-GP
14

R19
2 3CRT_HSYNC1_R 1 2CRT_HSYNC1 5V_CRT_S0
7 GMCH_HSYNC 0R2J-2-GP 3D3V_S0

3
U2A
TSAHCT125PW-GP
14

7
4

5
6
7
8
R20
5 6 CRT_VSYNC1_R 1 2CRT_VSYNC1 RN1
7 GMCH_VSYNC 0R2J-2-GP SRN10KJ-6-GP
1

U2B
Do Not Stuff

Do Not Stuff

TSAHCT125PW-GP
DDC_CLK & DATA level shift
7

C19
2

4
3
2
1
C20 DY DY
2 3D3V_S0 2

Q1
C156 TVOUT1

TV CONN L12
1 DY2 Do Not Stuff 9

1
GND
7 GMCH_DDCDATA 4 3 DAT_DDC1_5

LUMA_1 GND 5V_S0


7 TV_DACB 1 2 4 LUMA 5 2
FCM1608K-151T06-GP 2 NC#2 D7
1

C157 C155 5 6 1
R75 SC6P50V2CN-1GP SC6P50V2CN-1GP NC#5
7 COMP 2
150R2F-1-GP 6
2

CRMA LUMA_1 2N7002DW-1-GP


3 GND 3 DY 7 GMCH_DDCCLK
84.27002.D3F CLK_DDC1_5
2

8 GND 1
C151
1 DY2 Do Not Stuff MINDIN7-15-GP-U1
Do Not Stuff
22.10021.F41
D5
L11
1 2 COMP_1 2
7 TV_DACA FCM1608K-151T06-GP
1

C152 C150 CRMA_1 3 DY


R73 SC6P50V2CN-1GP SC6P50V2CN-1GP
150R2F-1-GP 1
2

2
2

Do Not Stuff
1 D6 1
C148
1 DY2 Do Not Stuff 2

L10 COMP_1 3 DY Wistron Corporation


1 2 CRMA_1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
7 TV_DACC FCM1608K-151T06-GP Taipei Hsien 221, Taiwan, R.O.C.
1
1

C149 C147
R70 SC6P50V2CN-1GP SC6P50V2CN-1GP Title
150R2F-1-GP Do Not Stuff
CRT/TV Connector
2

Size Document Number Rev


2

Ferrite bead impedance: 150 ohm@100MHz 100mA(min) design recommend Volvi2 SA


Date: Wednesday, June 06, 2007 Sheet 15 of 36
A B C D E
A B C D E

C173 SC12P50V2JN-3GP
1 2 RCT_X1

4
X3

1
3D3V_AUX_S5
D10 X-32D768KHZ-38GPU R88
2 RTC_AUX_S5 10MR2J-L-GP

2
SC1U16V3ZY-GP
4 4

1
1
C431

RTC_BAT_R
BAS40CW-GP C172 SC12P50V2JN-3GP U17A 1 OF 6

2
83.00040.E81
RTC circuitry 1 2
AG25 E5
RTC1 RTCX1 FWH0/LAD0 LPC_LAD0 26,36
RCT_X2 AF24 F5
RTCX2 FWH1/LAD1 LPC_LAD1 26,36
4 FWH2/LAD2 G8 LPC_LAD2 26,36
1 RTC_BAT 1 2 1 R284 2 20KR2J-L2-GP RTC_RST# AF23 F6
1KR2J-1-GP RTCRST# FWH3/LAD3 LPC_LAD3 26,36

RTC
2 R260 1 R281 2 INTRUDER# AD22 C4 LPC_LFRAME# 26,36
INTRUDER# FWH4/LFRAME#

LPC
SC1U16V3ZY-GP
3 1MR2J-1-GP
DY
2

1
5 C460 INTVRMEN AF25 G9 LDRQ0#_SB 1 2 LDRQ0# 26
C540 LAN100_SLP INTVRMEN LDRQ0# 3D3V_LDRQ1_S0 R305 Do Not Stuff
AD21 E6
MLX-CON3-10-GP-U DY Do Not Stuff
LAN100_SLP LDRQ1#/GPIO23 TP76 Do Not Stuff 1D05V_S0
1

2
20.F1000.003 B24 AF13 KA20GATE 26
GLAN_CLK A20GATE

1
A20M# AG26 H_A20M# 4
Do Not Stuff
TP58 LAN_RSTYNC D22 R267
LAN_RSTSYNC H_DPRSTP# 56R2J-4-GP
2'nd source: 20.F0714.003 DPRSTP# AF26 H_DPRSTP# 4,7,30

LAN/GLAN
C21 LAN_RXD0 DPSLP# AE26 H_DPSLP# 4
B21

2
LAN_RXD1
C22 LAN_RXD2 FERR# AD24 H_FERR# 4

D21 LAN_TXD0 CPUPWRGD/GPIO49 AG29 H_PWRGD 4,28,36


3D3V_S5 E20 R250 1D05V_S0
LAN_TXD1 Do Not Stuff
C20 LAN_TXD2 IGNNE# AF27 H_IGNNE# 4
1D5V_S0 H_PWRGD 1 2
1 2 GLAN_DOCK# AH21 AE24 H_INIT# 4,27
DY
R262 10KR2J-3-GP GLAN_DOCK#/GPIO13 INIT# 1D05V_S0
GLAN_COMP place within 500 mil of ICH8M INTR AC20 H_INTR 4
3 EMI capacitor 1 2 GLAN_COMP D25 GLAN_COMPI RCIN# AH14 KBRCIN# 26
3
2 R291 1 R266 24D9R2F-L-GP C25

CPU
21 ACZ_BTCLK_MDC GLAN_COMPO

2
22R2J-2-GP AD23 H_NMI 4
EC101 R289 1 ACZ_BIT_CLK NMI R254
24 ACZ_BITCLK 2 AJ16 HDA_BIT_CLK SMI# AG28 H_SMI# 4
2 1 ACZ_BITCLK 22R2J-2-GP AJ15 HDA_SYNC 56R2J-4-GP
1 2 ACZ_SYNC_R AA24
DYDo Not Stuff 21,24 ACZ_SYNC
R286 22R2J-2-GP AE14
STPCLK# H_STPCLK# 4 R253

1
Tahoe ACZ_RST#_R HDA_RST# H_THERMTRIP_R
1 2 AE27 1 2
21,24 ACZ_RST#
24 ACZ_SDATAIN0 R295 0R2J-2-GP AJ17
THRMTRIP# DY
Do Not Stuff
PM_THRMTRIP-A# 4,7,28
HDA_SDIN0 ICH_TP8 TP59 Do Not Stuff
AH17 AA23

IHDA
21 ACZ_SDATAIN1 HDA_SDIN1 TP8
ACZ_SDIN2 AH15
Do Not Stuff
TP36 ACZ_SDIN3 HDA_SDIN2
AD13 HDA_SDIN3 DD0 V1 IDE_PDD0 21
3D3V_S0 Do Not Stuff
TP70 U2
DD1 IDE_PDD1 21
21,24 ACZ_SDATAOUT R296 1 2 ACZ_SDATAOUT_R AE13 V3 IDE_PDD2 21
39R2J-L-GP HDA_SDOUT DD2 Layout Note: R133 needs to placed
DD3 T1 IDE_PDD3 21
1 2 HDA_DOCK_EN# AE10 V4 within 2" of ICH7, R334 must be placed
Do Not Stuff
TP37 HDA_DOCK_RST# R309 DY Do Not Stuff AG14
HDA_DOCK_EN#/GPIO33 DD4
T5
IDE_PDD4
IDE_PDD5
21
21
within 2" of R169 w/o stub.
HDA_DOCK_RST#/GPIO34 DD5
DD6 AB2 IDE_PDD6 21
14 SATA_LED# AF10 SATALED# DD7 T6 IDE_PDD7 21
DD8 T3 IDE_PDD8 21
21 SATA_RXN0 C493 1 2 SC3900P50V3KX-GP SATA_RXN0_C AF6 R2 IDE_PDD9 21
C499 SC3900P50V3KX-GP SATA_RXP0_C SATA0RXN DD9
21 SATA_RXP0 1 2 AF5 SATA0RXP DD10 T4 IDE_PDD10 21
21 SATA_TXN0 C486 1 2 SC3900P50V3KX-GP SATA_TXN0_C AH5 V6 IDE_PDD11 21
C476 SC3900P50V3KX-GP SATA_TXP0_C SATA0TXN DD11
21 SATA_TXP0 1 2 AH6 SATA0TXP DD12 V5 IDE_PDD12 21
DD13 U1 IDE_PDD13 21

IDE
AG3 SATA1RXN DD14 V2 IDE_PDD14 21
AG4 SATA1RXP DD15 U6 IDE_PDD15 21
AJ4

SATA
SATA1TXN
AJ3 SATA1TXP DA0 AA4 IDE_PDA0 21
2 Tahoe 2
DA1 AA1 IDE_PDA1 21
AF2 SATA2RXN DA2 AB3 IDE_PDA2 21
AF1 SATA2RXP
AE4 SATA2TXN DCS1# Y6 IDE_PDCS1# 21
AE3 SATA2TXP DCS3# Y5 IDE_PDCS3# 21

3 CLK_PCIE_SATA# AB7 SATA_CLKN DIOR# W4 IDE_PDIOR# 21


3 CLK_PCIE_SATA AC6 SATA_CLKP DIOW# W3 IDE_PDIOW# 21
DDACK# Y2 IDE_PDDACK# 21
SATARBIAS AG1 Y3 INT_IRQ14 21
SATARBIAS# IDEIRQ
1 2 AG2 SATARBIAS IORDY Y1 IDE_PDIORDY 21
R324 24D9R2F-L-GP W5
DDREQ IDE_PDDREQ 21
Place within 500 mils of
ICH8 ball ICH8-M-1-GP-U-NF

Change to 24.9 1% ohm


when use SATA HD

RTC_AUX_S5 RTC_AUX_S5
1

1 RTM 1
R272 R280
330KR2F-L-GP 330KR2F-L-GP
integrated VccSus1_05,VccSus1_5,VccCL1_5 Wistron Corporation
2

INTVRMEN LAN100_SLP INTVRMEN High=Enable Low=Disable 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1

integrated VccLan1_05VccCL1_05
R275 R277 Title
DY Do Not Stuff DY Do Not Stuff LAN100_SLP High=Enable Low=Disable
ICH8-M (1 of 4)
Size Document Number Rev
2

Volvi2 SA
Date: Wednesday, June 06, 2007 Sheet 16 of 36
A B C D E
A B C D E

U17D 4 OF 6
RN37
U17C3 OF 6 AJ26 AJ12 SATA0GP 1 8 3D3V_S0
19,23 SMB_CLK SMBCLK SATA0GP/GPIO21

GPIO
AD19 AJ10 SATA1GP 2 7

SATA
19,23 SMB_DATA SMBDATA SATA1GP/GPIO19

SMB
D20 A4 PCI_REQ#0 SMB_LINK_ALERT#
AG21 AF11 SATA2GP 3 6
E19
AD0
AD1
PCI REQ0#
GNT0# D7 PCI_GNT#0 TP86 Do Not Stuff SMLINK0 AC17
LINKALERT#
SMLINK0
SATA2GP/GPIO36