A 1-V 2.
4-GHz CMOS RF Receiver Front-End for Bluetooth Application
Alan N.L. Chan, Kenneth W.H. Ng, Joseph M.C. Wong, and Howard C. Lziong
Department of Electrical and Electronic Engineering
Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
1. Abstract
A 1-V 2.4-GHz CMOS RF Receiver fi-ont-end, which
includes an LNA, a mixer and a VCO, is designed for
Bluetooth receivers with the emphasis of using on-
chip inductor. Designed in a standard 0.35-pm
CMOS technology and operated at lV, the front-end
is simulated to achieve a gain of 18 dB, a noise figure
of 7.5 dB and an IIP3 of -13 dBm with a total current
of 15.5 mA.
2. Introduction
With the increasing demand of wireless transceivers
with low cost, low power and sinal1 size, recent
research has been focusing on single-chip solution,
for which CMOS is the most promising technology as
radio-frequency (RF) circuits and digital circuits can
be embedded together on the same chip. In this paper,
we will demonstrate the feasibility of a CMOS RF
front-end that employs the heterodyne architecture
with a single intermediate frequency (IF) at a 1-V
supply voltage for 2.4-GHz Bluetooth application.
The proposed block diagram of the RF front-end is
shown in Figure 1. RF signals in between 2.4 GHz
and 2.48 GHz go from the antenna to a high-gain,
low-noise amplifier. It is then downconverted to an
IF of 10.7 MHz. Since a low IF is chosen to relax the
requirement of IF filters and amplifiers, image
rejection cannot be done by using some monolithic
image rejection technique [ 11 as the image is located
in-band.
I vco I
Figure 1. Block diagram of the proposed RF front-end
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0-7803-6685-9/01/$10.0002001
According to the specification of the Bluetooth
system [2], a 20 dB in-band image rejection is
required, which can be easily achieved by using I-Q
image rejection mixers.
3.On-chip Spiral Inductor Modeling
With an emphasis on single-chip solution, it is
necessary to use low-Q on-chip spiral inductors.
Ls Rs
i
RP RP
Figure 2 II model
Figure 2 shows the Il model that is used throughout
the simulation. L, is the inductance, Rsis the series
resistance due to metal loss and eddy current loss, C$,
and % model the substrate loss. Based on past
measurement, we assume the worst-case quality
factor of around 2.5.
4. Front-End Building Blocks
A . LNA
As shown in Figure 2, a differential LNA with
cascode configuration is used because of its high gain
without linearity degradation and its high reverse
isolation. Under a low-voltage design, stacking of
transistor should be avoided. With the scaling down
of technology, this problem can be overcome together
with a careful biasing. To allow much more
headroom at a 1-V supply and hence to improve the
linearity, the bias current source is removed. This
sacrifices the cointnon-mode noise rejection
somewhat. If necessary, a LC tank that resonates at
the frequencies of interest can be used as the bias
current source to reject the common noise.
..........................
On-chip
biasing

................. ....I
I
F pyq
0' ut
................................... j .............................
I

....
On-chip
biasing I
trading off the conversion gain and the LO-RF
feedthrough. A resistive current source & at the RF
input also provides more headroom for the transistors
MI-& to operate at low supply voltages. The value
of Rb is chosen such that it provides adequate current
to M1-M4 with negligible input-referred noise
contribution.
-,+ . ,
: I
t'
RF input r i + j
i >
RF input
The conversion gain of the mixer depends on the
$, !................................. transconductance of the Ml-M4, the output swing of
.$
:

+
2
the VCO and the loading resistors. In general, a
Figure 2. Schematic of LNA larger output swing of VCO will result in a higher
conversion gain. However, if the swing is too high,
Inductive source degeneration and gate inductors are this would cause the cross-coupling transistors to
used for 50 R input matching. An input biasing work in triode region. To solve this problem and to
circuit using current mirror is employed to drive the maximize the output bandwidth, a smaller value of
input devices. the loading resistor is chosen.

A negative Gm cell is embedded for Q-compensation c. vco

of the inductor. [3] proposed a highly linear Q-
compensation circuit. Nevertheless, this Q- The RF front-end employs a classical oscillator,
compensation circuit will inevitably degrade the which includes a LC tank that oscillates at the desired
noise and power consumption. As a result, a simple frequency and a negative conductance to compensate
negative Gm cell is used in our design. As long as for the loss in the LC-tank.
the sizes of the devices are kept small, the linearity
can 'still be acceptable. To keep the same This traditional design works very well at high supply
transconductance, we need to provide more current voltages in terms of the tuning range since the
and thus sacrifice the power consumption. capacitance of the varactor is based on the reverse-
biased voltage. If the supply voltage is higher, the
B. Mixer reverse-biased voltage of varactor is larger, which
results in a larger tuning range. However, when the
The proposed double-balanced mixer is shown in supply voltage is as low as lV, the inaximuin reverse-
Figure 3. biased voltage allowed is limited to only 1 V. The
Vdd tuning range is limited and is not enough for channel
T T selection and process variation.

To overcome the problem with limited tuning range

at low supply voltages, a low-voltage switching
oscillator with wide tuning range [ 5 ] is adopted as
shown in Figure 4. The wide tuning range can be
achieved even at low supply voltage with the
inclusion of switched-capacitor arrays at the output.
The capacitor arrays can be switched on or off to
I
adjust the total output capacitance and thus the output
frequency. As a consequence, the tuning range of the
Figure 3. Schematic of proposed mixer oscillator is no longer bounded by the supply voltage
and can be extended significantly.
As compare to the Gilbert mixer [4], the RF input
coinmon-source transistors are replaced with a In our design, the quality factor of switchable
capacitive-coupling passive network. With such a capacitor array (SCA) is chosen to be around 15. A
passive network, high linearity can be achieved by

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Figure 4. Schematic of low-voltage wide- Figure 5. Frequency response and noise figure of LNA
tuning-range switching oscillator

6-bit switch capacitor arrays can provide a frequency

tuning range of more than 128MHz. Varactors can
also be employed to extend the tuning range further.

4. Simulation Results

The 1-V RF fiont-end was simulated by using

WADS, Spectre RF and Hspice with the Level 49
BSIM3 transistor inodel for 0.35-pm TSMC CMOS <-

process provided by MOSIS and WADS for system 10’ 1 os I og

Input frequency (Hz)
simulation. Figure 6. Conversion gain of the mixer

Sinziilation of Bidding Blocks

Figure 5 illustrates the frequency response and the

noise figure of the LNA. The corresponding gain and
noise figure at 2.4 GHz are 18 dB and 5.7 dB
respectively. Since the noise figure requirement for
bluetooth application is quite relaxed (-2OdB), it is
purposely kept high to maximize linearity and
ininiinize the power consumption.

Using Spectre RF, the noise figure of the inixer is Frequency (Hz)

around 22 dB at 2.4 GHz. Froin Figure 6, a Figure 7. Phase noise logarithmic plot
conversion gain of -2.7 dB is achieved. The
inaxhnuin conversion gain is around 2.4GHz due to
the ac-coupling capacitor at the input. The IIP3 and
1-dB of the inixer are 16.5 dBin and 2 dBm,
respectively.

Figure 7 plots the output spectrum of the VCO

indicating a phase noise of -107dBCBz @ 500kHz
offset. The tuning range of oscillator, shown in Figure
8, is 128MHz even without the use of varactors.
Table 1 shows the suimnary of the performance of
each individual building block. Figure 8 VCO tuning characterisitic

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I Supply voltage I 1v Parameters Simulation results
Process 0.35-um CMOS Voltage supply 1v
RF frequency 2.4 GHz - 2.48 GHZ Total voltage gain 18 dB
IF 10.7 MHz I Noise Figure I 7.5 dB I
1 LNA Gain 18 dB IIP3 -13 dBm
NF 5.7 dB Frequency tuning range 128 MHz
IIP3 -10 dBm Power dissiuation 15.5 mW
SI1 -19 dB
SI2 -48 dB Table 2. Simulated performance of the whole RF ffont-end
Power 8.5 mW
Mixer Conversion Gain -2.7 dB Although the noise figure of the mixer is 22 dB, it is
Noise Figure 22dB suppressed by the high gain of LNA, and the overall
contribution of noise figure fi-om mixer is about 2 dl3
l-dB 2 dBm when referred to the input.
Power 1.5 mW
vco 5. Conclusion

A 1-V 2.4-GHz RF front-end has been presented for

Power
Table 1. Performance sunmary of each building block
A. Sinitilation of the whole RF front-end
Figure 9 shows the simulated IIP3 of the whole RF
fiont-end. Because the highly linear mixer topology
is used, the IIP3 for the whole system is dominated
by the LNA linearity, which is in turn limited due to
the Q-compensation circuit at 1-V supply. Table 2
summarizes the simulated performance of the whole
RF front-end.
Bluetooth receivers. From simulation results, the
fiont-end can operate at 1-V supply while still
achieving a noise figure of 7.5 dB and an IIP3 of -13
dBm. The overall noise figure is kept relatively high
to minimize the power consumption, but it is still
acceptable for Bluetooth specifications, which can be
up to 23 dB. The total power consumption at 1-V
supply is 20.1 mW.
6. Reference
[I1 Jose A. M. and Miles A. Copeland. "A 1.9-GHz Silicon
Receiver with Monolithic Image Filtering", IEEE Joiirnal of
Solid-State Circuits. pp. 378-386, Vol. 33. NO.3. Mar 1998.

Specification of Bluetooth system version 1.OB,

Teletouaktiebolaget LM Ericsson. IBM Corporation. Intel
Corporation. Toshiba Corporation. Copyright 1999.

D. Leung and H. C. Luong. "A Fourth-Order CMOS

Bandpass Amplifier with High Linearity and High Image
Rejection for GSM Receivers." Proceedings of IEEE
International S'~inposiiinz on Circuit and Sjvterizs 1999,
Florida. USA. June 1999.

B.Gilbert. "A Precise Four-Quadrant Multiplier with

Subnanosecond Response." IEEE Joiirnal of Solid-state
Circuits.vol. SC-3. pp. 365-73, Dec. 1968.

C. W. Lo "1.5V 900MHz Monolithic CMOS Fast Switching

Frequency Synthesizer for Wireless Applications."
Sy~zposizrnzon VLSI Circuits 2000. Hawaii. USA. pp. 238-
24 1 . June 2000.

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