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τµΩ INDIABIX ELECTRONICS PART 2

RC CIRCUITS 7. Calculate the phase angle in the given 12. What is the total current in the given
circuit. circuit?
1. In a 20 Vac series RC circuit, if 20 V is
read across the resistor and 40 V is
measured across the capacitor, the
applied voltage is
A. 45 Vac
B. 50 Vac A. 0° A. 0.28 A
C. 60 Vac B. 90° B. 0.399 A
D. 65 Vac C. 22.52° C. 909 A
D. 67.48° D. 0.2 A
2.Which of the following is the reference
vector for parallel RC circuits? 8. What is the phase angle for a parallel 13. Which statement about a series RC
A. R circuit consisting of a 500 kHz, 5 Vac circuit is true?
B. V source with a 47 pF capacitor, and a 4.7 A. The capacitor's voltage drop is
C. I kΩ resistor in parallel? in phase with the resistor's
D. XC A. 55.3° voltage drop.
B. –55.3° B. The current leads the source
3. What is the voltage drop across R1 in
C. 34.8° voltage.
the given circuit?
D. –34.8° C. The current lags the source
voltage.
9.
D. The resistor voltage lags the
current.
14. If the frequency increases in the
A. 10 V given circuit, how would the total
B. 4.80 V current change?
C. 4.00 V
D. 5.80 V
Which circuit is represented by the
4. Power that is measured in volt- frequency response curve in the given
amperes is called figure?
A. impedance power A. High-pass filter A. The total current would
B. reactive power B. Low-pass filter increase.
C. true power C. Band-pass filter B. The total current would
D. apparent power D. Band-stop filter decrease.
C. The total current would remain
5. As frequency increases 10. What is the phase angle in the given the same.
A. both series and parallel RC circuit? D. More information is needed in
impedance decrease
order to predict how the total
B. series RC impedance decreases
current would change.
and parallel RC impedance
increases 15. What is the effect of increasing the
C. series RC impedance increases resistance in a series RC circuit?
and parallel RC impedance A. 14.95° A. There will be no effect at all.
decreases B. 36.88° B. The current will increase.
D. both series and parallel RC C. 0° C. The phase shift will decrease.
impedance increase D. 90° D. The input voltage will increase.
6. Calculate the magnitude of the 11. What is the current through XC1 in
impedance in the given circuit. the given circuit?
RL CIRCUITS
1. As frequency increases
A. both series and parallel RL
impedance decrease
A. 24.1 MΩ A. 32.2 mA B. series RL impedance decreases
B. 10 MΩ B. 16 mA and parallel RL impedance
C. 26.1 MΩ C. 12 ma increases
D. 0Ω D. 48 mA
τµΩ INDIABIX ELECTRONICS PART 2
C. series RL impedance increases 7. What is the magnitude of the phase A. An increase in frequency
and parallel RL impedance angle of a 24 Vac parallel RL circuit when causes an increase in phase
decreases R = 45 Ω and XL = 1100 Ω? lag.
D. both series and parallel RL A. 0.001° B. An increase in frequency causes
impedance increase B. 2.3° an increase in the magnitude of
C. 87.6° the output voltage.
2. Calculate the voltage dropped across
D. 89.9° C. A decrease in frequency causes
R1 in the given circuit.
an increase in phase lag.
8. Which of the following statements is
D. A decrease in frequency causes
true if the frequency decreases in the
a decrease in the magnitude of
circuit in the given circuit?
the output voltage.

A. 14 V TRANSFORMERS
B. 26.8 V
C. 28 V 1. When does maximum power transfer
D. 0V A. The phase angle decreases.
happen from the source to the load?
B. VR decreases.
3. What is the true power of a 24 Vac A. When the source resistance is
C. IT decreases.
parallel RL circuit when R = 45 Ω and XL greater than the load resistance
D. VS decreases.
= 1100 Ω? B. When the source resistance is
A. 313.45 W 9. What is the magnitude of the phase less than the load resistance
B. 12.8 W angle between the source voltage and C. When there is negligible source
C. 44.96 W current when a 100 mH inductor with an resistance
D. 22.3 W inductive reactance of 6 kΩ and a 1 kΩ D. When the source resistance
resistor are in series with a source? equals the load resistance
4. If XL= 100 Ωand R = 100Ω, then A. 0.1°
impedance will be 2. A transformer is plugged into a 120 V
B. 9.0°
A. 141.4 Ω rms source and has a primary current of
C. 61.0°
B. 14.14 Ω 300 mA rms. The secondary is providing
D. 81.0°
C. 100 Ω 18 V across a 10 Ω load. What is the
D. 200 Ω 10. Which of the following statements is efficiency of the transformer?
true if R1 opens in the circuit in the given A. 88%
5. Which of the following statements is circuit? B. 90%
true if the inductor shorts out in the C. 92%
circuit in the given circuit? D. 95%
3. The coefficient of coupling between
two coils is 0.45. The first coil has an
inductance of 75 mH and the second coil
A. IL2 increases. has an inductance of 105 mH. What is
B. ZT decreases. the mutual inductance between the
A. Each component drops 5 V. C. VS increases. coils?
B. The impedance equals 0 Ω. D. VL1 equals 0 V. A. 3.54 mH
C. The power factor equals 1.
11. Which of the following statements is B. 7.88 mH
D. The phase angle equals 90°.
true if R = 100 Ω and XL = 100 Ωin the C. 39.9 mH
6. Calculate the voltage dropped across circuit in the given circuit? D. 189.3 mH
L2 in the given circuit.
4. Increasing the number of turns of wire
on the secondary of a transformer will
A. increase the secondary current
B. decrease the secondary
current
A. Each component drops 5 V. C. have no effect on the secondary
A. 18 V B. The impedance equals 200 Ω. current
B. 6V C. The power factor equals 1. D. increase the primary current
C. 13.5 V D. The phase angle equals 45°.
5. What is the turns ratio of the
D. 0V
12. Which of the following statements is transformer needed to match a 1 kΩ
true about a lag network? source resistance to a 160 Ω load?
τµΩ INDIABIX ELECTRONICS PART 2
A. 2.5:1 11. A special transformer used to convert B. 4.3 V
B. 0.4:1 unbalanced signals to balanced signals is C. 4.75 V
C. 6.25:1 the D. 4.9 V
D. 16:1 A. balun 2. If a periodic pulse waveform is applied
B. autotransformer to an RC differentiating circuit, which
6. What is the secondary voltage in the
C. center-tapped transformer two conditions are possible?
given circuit?
D. step-across transformer A. tw ≥ 5τ or tw > 5τ
B. tw = 5τ or tw > 5τ
12. If the load doubled in value in the
C. tw ≤ 5τ or tw < 5τ
given circuit, what reflected resistance
D. tw ≥ 5τ or tw < 5τ
would the source see?
A. 13.3 V rms in phase with the 3. An RL integrator and an RC
primary differentiator can act as what types of
B. 120 V rms in phase with the filters, respectively?
primary A. low-pass, low-pass
C. 13.3 V rms out of phase with B. low-pass, high-pass
A. 80 Ω
the primary C. high-pass, high-pass
B. 400 Ω
D. 120 V rms out of phase with the D. high-pass, low-pass
C. 2 kΩ
primary D. 10 kΩ 4. In a repetitive-pulse RC integrator
7. The transformer turns ratio circuit, what would the steady-state
13. If the primary power of an ideal
determines voltage equal at the end of the fifth
transformer having a 2:1 voltage ratio is
A. the ratio of primary and pulse? Assume a Vin of 20 V.
100 W, the secondary power is
secondary voltages A. 1.46 V
A. 100 W
B. the ratio of primary and B. 14.62 V
B. 50 W
secondary currents C. 20 V
C. 75 W
C. the reflected impedance D. 0V
D. 200 W
D. all of the above 5. What is a circuit that produces short-
14. A transformer has
8. Mutual induction is dependent on duration spikes?
A. primary and secondary
A. winding ratios A. A trigger pulse generator
windings, both of which are
B. output polarities B. An RL integrator
considered inputs
C. dc voltage levels C. A timing circuit
B. primary and secondary
D. current changes D. A pulse waveform-to-dc
windings, both of which are
converter
9. What is the current through the load considered outputs
in the given circuit? C. a primary winding used as an
output and a secondary winding
used as an input
D. a primary winding used as an
input and a secondary winding
A. 500 µA used as an output 6.
B. 10 mA In the given circuit, what must the pulse
C. 250 mA width and time between pulses be to
D. 1.25 A TIME RESPONSE OF allow the capacitor to completely charge
REACTIVE CIRCUITS by the end of each pulse and to
10. What is the power dissipated in the completely discharge between each
primary of the transformer in the given 1. pulse?
circuit? A. 940 µs
B. 2.82 ms
C. 3.76 ms
D. 4.7 ms

A. 25 mW
B. 500 mW
C. 12.5 W
What voltage will the capacitor charge
D. 62.5 W
up to in the given circuit for the single
input pulse shown?
A. 3.15 V 7.
τµΩ INDIABIX ELECTRONICS PART 2
The given circuit is an What is the voltage across the inductor
A. RL integrator in the given circuit on the falling edge of
A.
B. RC differentiator the first input pulse?
B. Av = IC × RC
C. RL differentiator A. –0.2 V
D. RC integrator B. 0.2 V
C. –9.8 V C.
8. Which of the following is true for a
D. 9.8 V
capacitor?
A. A capacitor acts like a short to D.
instantaneous changes in 7. In a class B push-pull amplifier, the
current. TRANSISTORS AND transistors are biased slightly above
B. A capacitor's voltage cannot APPLICATIONS cutoff to avoid
change instantaneously. A. crossover distortion
C. A capacitor acts like an open to 1. The primary function of the bias circuit B. unusually high efficiency
dc. is to C. negative feedback
D. All of the above A. hold the circuit stable at VCC D. a low input impedance
9. If the capacitor in an RC integrator B. hold the circuit stable at vin
8. The depletion-mode MOSFET
shorts, the output C. ensure proper gain is achieved
A. can operate with only positive
A. is at ground D. hold the circuit stable at the
gate voltages
B. would measure the same as the designed Q-point
B. can operate with only negative
input 2. A JFET gate voltages
C. would measure zero volts A. is a current-controlled device C. cannot operate in the ohmic
D. None of the above B. has a low input resistance region
10. C. is a voltage-controlled device D. can operate with positive as
D. is always forward-biased well as negative gate voltages
3. A source follower has a voltage gain 9. Three different points are
(Av) of shown on a dc load line. The upper point
A. AV = gmRd represents the
B. AV = gmRs A. minimum current gain
B. quiescent point
What has the voltage across the resistor C. saturation point
C. D. cutoff point
decayed to by the end of the pulse in the
given circuit?
10. Which of the following conditions are
A. 0V
D. needed to properly bias an npn
B. 0.75 V
transistor amplifier?
C. 5.55 V 4. The capacitor that produces an ac
A. Forward bias the base/emitter
D. 14.25 V ground is called a(n)
junction and reverse bias the
A. coupling capacitor
11. How long will it take the capacitor in base/collector junction.
B. dc open
the given circuit to discharge? B. Forward bias the collector/base
C. bypass capacitor
junction and reverse bias the
D. ac open
emitter/base junction.
5. The formula used to calculate the C. Apply a positive voltage on the
approximate ac resistance of the base- n-type material and a negative
emitter diode (re) is voltage on the p-type material.
D. Apply a large voltage on the
A. 16.4 µs base.
B. 32.8 µs A.
C. 65.6 µs B. re almostequal.jpg 25 mV × IC 11. Often a common-collector will be the
D. 82 µs last stage before the load; the main
function of this stage is to
12. C. A. provide voltage gain
B. buffer the voltage amplifiers
from the low-resistance load
D. C. provide phase inversion
6. The signal voltage gain of an D. provide a high-frequency path
amplifier, Av, is defined as: to improve the frequency
response
τµΩ INDIABIX ELECTRONICS PART 2
B. the inverted sum of the 13. A two-pole high-pass active filter
12. In order for feedback oscillators to
individual inputs would have a roll-off rate of
have any practical value, the gain has to
C. the sum of the individual inputs A. 40 dB/decade
be
D. the inverted average of the B. –40 dB/decade
A. <1
individual inputs C. 20 dB/decade
B. self-adjusting
D. –20 dB/decade
C. stabilized 6. If the input to a comparator is a sine
D. nonlinear wave, the output is a
A. ramp voltage
13. To get a negative gate-source SPECIAL PURPOSE OP-
B. sine wave
voltage in a self-biased JFET circuit, you
must use a
C. rectangular wave AMP CIRCUITS
D. sawtooth wave
A. voltage divider
B. source resistor 7. A basic series regulator has
C. ground A. an error detector
D. negative gate supply voltage B. a load
C. a reference voltage
D. both an error detector and a 1.
BASIC OP-AMP CIRCUITS reference voltage
8. A comparator is an example of a(n)
1. The center frequency of a band-pass
A. active filter
filter is always equal to the
B. current source
A. bandwidth
C. linear circuit
B. –3 dB frequency
D. nonlinear circuit
C. bandwidth divided by Q
D. geometric average of the
9. Initially, the closed-loop gain (Acl) of a
critical frequencies
Wien-bridge oscillator should be
A. Acl < 3 Which circuit is known as a current-to-
B. Acl > 3 voltage converter?
2. The formula shows that
C. 0 A. a
for a given capacitor, if the voltage
changes at a constant rate with respect D. Acl 1 B. b
to time, the current will 10. In an averaging amplifier, the input C. c
A. increase resistances are D. d
B. decrease A. equal to the feedback 2. When using an OTA in a Schmitt-
C. be constant resistance trigger configuration, the trigger points
D. decrease logarithmically B. less than the feedback are controlled by
3. A zero-level detector is a resistance A. the Iout
A. comparator with a sine-wave C. greater than the feedback B. the Ibias
output resistance C. the Vout
B. comparator with a trip point D. unequal D. both Iout and Ibias
referenced to zero 11. A triangular-wave oscillator can
C. peak detector consist of an op-amp comparator,
D. limiter followed by a(n)
4. A digital-to-analog converter is an A. differentiator
application of the B. amplifier 3.
A. scaling adder C. integrator
B. voltage-to-current converter D. multivibrator
C. noninverting amplifier 12. The ramp voltage at the output
D. adjustable bandwidth circuit of an op-amp integrator
5. If the value of resistor Rf in an A. increases or decreases at a
averaging amplifier circuit is equal to the linear rate
value of one input resistor divided by the B. increases or decreases
number of inputs, the output will be exponentially
equal to C. is always increasing and never
A. the average of the individual decreasing
D. is constant Refer the given circuits. Which circuit is
inputs known as an OTA?
τµΩ INDIABIX ELECTRONICS PART 2
A. a 8. An instrumentation amplifier has a 2. Which of the following characterizes
B. b high an analog quantity?
C. c A. output impedance A. Discrete levels represent
D. d B. power gain changes in a quantity.
C. CMRR B. Its values follow a logarithmic
4. This circuit is a setup for
D. supply voltage response curve.
C. It can be described with a finite
9. This circuit is a setup for
number of steps.
D. It has a continuous set of
values over a given range.
3. ASCII stands for:
A. an antilog amplifier A. American Serial
B. a constant-current source Communication Interface
C. an instrumentation amplifier B. Additive Signal Coupling
D. an isolation amplifier Interface
C. American Standard Code for
A. an antilog amplifier Information Interchange
B. a constant-current source D. none of the above
C. an instrumentation amplifier
D. an isolation amplifier 4. Which type of signal is represented by
discrete values?
5. 10. Circuits that shift the dc level of a A. noisy signal
signal are called B. nonlinear
A. limiters C. analog
B. clampers D. digital
C. peak detectors
D. dc converters 5. A data conversion system may be
used to interface a digital computer
11. The voltage gain of an OTA can be system to:
calculated using the formula A. an analog output device
B. a digital output device
A. C. an analog input device
Which circuit is known as a voltage-to- D. a digital printer
B.
current converter?
A. a
B. b C. NUMBER SYSTEMS AND
C. c CODES
D. d D.
6. The primary function of the oscillator 12. In the classic three-op-amp 1. Base 10 refers to which number
in an isolation amplifier is to instrumentation amplifier, the system?
A. convert dc to high-frequency differential voltage gain is usually A. binary coded decimal
ac produced by the B. decimal
B. convert dc to low-frequency ac A. first stage C. octal
C. rectify high-frequency ac to dc B. second stage D. hexadecimal
D. produce dual-polarity dc C. mismatched resistors 2. Convert the decimal number 151.75 to
voltages for the input to the D. output op-amp binary.
demodulator
A. 10000111.11
7. Refer to Figure 20-2. This circuit is a B. 11010011.01
setup for
ANALOG TO DIGITAL C. 00111100.00
D. 10010111.11
1. The two basic types of signals are
analog and: 3. Convert the binary number 1011010 to
A. digilog hexadecimal.
B. digital A. 5B
A. an antilog amplifier
C. vetilog B. 5F
B. a constant-current source
D. sine wave C. 5A
C. an instrumentation amplifier
D. 5C
D. an isolation amplifier
τµΩ INDIABIX ELECTRONICS PART 2
4. The number of bits used to store a B. 00110101 6. Exclusive-OR (XOR) logic gates can be
BCD digit is: C. 00110010 constructed from what other logic
A. 8 D. 00110001 gates?
B. 4 A. OR gates only
12. 3428 is the decimal value for which of
C. 1 B. AND gates and NOT gates
the following binary coded decimal
D. 2 C. AND gates, OR gates, and
(BCD) groupings?
NOT gates
5. Sample-and-hold circuits in ADCs are A. 11010001001000
D. OR gates and NOT gates
designed to: B. 11010000101000
A. sample and hold the output of C. 011010010000010 7. How many truth table entries are
the binary counter during the D. 110100001101010 necessary for a four-input circuit?
conversion process A. 4
13. What is the result when a decimal
B. stabilize the ADCs threshold B. 8
5238 is converted to base 16?
voltage during the conversion C. 12
A. 327.375
process D. 16
B. 12166
C. stabilize the input analog
C. 1388 8. A NAND gate has:
signal during the conversion
D. 1476 A. LOW inputs and a LOW output
process
B. HIGH inputs and a HIGH output
D. sample and hold the ADC
C. LOW inputs and a HIGH
staircase waveform during the LOGIC GATES output
conversion process
D. None of these
6. The weight of the LSB as a binary 1. The output will be a LOW for any case
when one or more inputs are zero in 9. The basic logic gate whose output is
number is:
a(n): the complement of the input is the:
A. 1
A. OR gate A. OR gate
B. 2
B. NOT gate B. AND gate
C. 3
C. AND gate C. INVERTER gate
D. 4
D. NAND gate D. comparator
7. What is the difference between binary
2. If a signal passing through a gate is 10. What input values will cause an AND
coding and binary coded decimal?
inhibited by sending a low into one of logic gate to produce a HIGH output?
A. Binary coding is pure binary.
the inputs, and the output is HIGH, the A. At least one input is HIGH.
B. BCD is pure binary.
gate is a(n): B. At least one input is LOW.
C. Binary coding has a decimal
A. AND C. All inputs are HIGH.
format.
B. NAND D. All inputs are LOW.
D. BCD has no decimal format.
C. NOR
8. Convert the binary number 1001.0010 D. OR
to decimal. LOGIC CIRCUIT
A. 125 3. A single transistor can be used to build SIMPLIFICATION
B. 12.5 which of the following digital logic
C. 90.125 gates? 1. Which statement below best describes
D. 9.125 A. AND gates a Karnaugh map?
B. OR gates A. It is simply a rearranged truth
9. Convert 110010012 (binary) to C. NOT gates
decimal. table.
D. NAND gates B. The Karnaugh map eliminates
A. 201
B. 2001 4. The logic gate that will have HIGH or the need for using NAND and
C. 20 "1" at its output when any one of its NOR gates.
D. 210 inputs is HIGH is a(n): C. Variable complements can be
A. OR gate eliminated by using Karnaugh
10. What is the decimal value of the B. AND gate maps.
hexadecimal number 777? C. NOR gate D. A Karnaugh map can be used to
A. 191 D. NOT gate replace Boolean rules.
B. 1911
C. 19 5. How many NAND circuits are 2. Which of the examples below
D. 19111 contained in a 7400 NAND IC? expresses the commutative law of
A. 1 multiplication?
11. What is the resultant binary of the B. 2 A. A+B=B+A
decimal problem 49 + 1 =? C. 4 B. A•B=B+A
A. 01010101 D. 8 C. A • (B • C) = (A • B) • C
τµΩ INDIABIX ELECTRONICS PART 2
D. A•B=B•A means that logically there is no A. 0.0 V to 0.4 V
3.The Boolean expression is difference between: B. 0.4 V to 0.8 V
logically equivalent to what single gate? A. a NAND gate and an AND gate C. 0.4 V to 1.8 V
A. NAND with a bubbled output D. 0.4 V to 2.4 V
B. NOR B. a NOR gate and an AND gate
4. When an IC has two rows of parallel
C. AND with a bubbled output
connecting pins, the device is referred to
D. OR C. a NOR gate and a NAND gate
as:
with a bubbled output
4. The observation that a bubbled input A. a QFP
D. a NAND gate and an OR gate
OR gate is interchangeable with a B. a DIP
with a bubbled output
bubbled output AND gate is referred to C. a phase splitter
as: 10. The commutative law of addition and D. CMOS
A. a Karnaugh map multiplication indicates that:
5. Which digital IC package type makes
B. DeMorgan's second theorem A. the way we OR or AND two
the most efficient use of printed circuit
C. the commutative law of variables is unimportant
board space?
addition because the result is the same
A. SMT
D. the associative law of B. we can group variables in an
B. TO can
multiplication AND or in an OR any way we
C. flat pack
want
5. The systematic reduction of logic D. DIP
C. an expression can be expanded
circuits is accomplished by: by multiplying term by term 6. The problem of interfacing IC logic
A. symbolic reduction just the same as in ordinary families that have different supply
B. TTL logic algebra voltages (VCCs) can be solved by using
C. using Boolean algebra D. the factoring of Boolean a:
D. using a truth table expressions requires the A. level-shifter
6. Logically, the output of a NOR gate multiplication of product terms B. tri-state shifter
would have the same Boolean that contain like variables C. translator
expression as a(n): D. level-shifter or translator
11. Which of the following expressions is
A. NAND gate immediately in the sum-of-products (SOP) form? 7. Ten TTL loads per TTL driver is known
followed by an INVERTER A. Y = (A + B)(C + D) as:
B. OR gate immediately followed B. Y = AB(CD) A. noise immunity
by an INVERTER B. power dissipation
C. AND gate immediately C. C. fanout
followed by an INVERTER D. propagation delay
D. NOR gate immediately D.
followed by an INVERTER 8. Which of the following summarizes
STANDARD LOGIC the important features of emitter-
7. Which of the examples below coupled logic (ECL)?
expresses the distributive law of Boolean
DEVICES (SLD) A. negative voltage operation,
algebra? high speed, and high power
A. A • (B • C) = (A • B) + C 1. A digital logic device used as a buffer consumption
B. A + (B + C) = (A • B) + (A • C) should have what input/output B. good noise immunity, negative
C. A • (B + C) = (A • B) + (A • C) characteristics? logic, high frequency capability,
D. (A + B) + C = A + (B + C) A. high input impedance and high low power dissipation, and
output impedance short propagation time
8. Which output expression might B. low input impedance and high C. slow propagation time, high
indicate a product-of-sums circuit output impedance frequency response, low power
construction? C. low input impedance and low consumption, and high output
output impedance voltage swings
A. D. high input impedance and low D. poor noise immunity, positive
output impedance supply voltage operation, good
B.
2. What is the standard TTL noise low-frequency operation, and
C. margin? low power
A. 5.0 V 9. What quantities must be compatible
D.
B. 0.2 V when interfacing two different logic
9. One of DeMorgan's theorems states C. 0.8 V families?
that . Simply stated, this D. 0.4 V A. only the currents
3. The range of a valid LOW input is:
τµΩ INDIABIX ELECTRONICS PART 2
B. both the voltages and the A. it cannot be reprogrammed. 3. A logic probe is placed on the output
currents B. its outputs are only active of a gate and the display indicator is dim.
C. only the voltages HIGHs A logic pulser is used on each of the
D. both the power dissipation and C. its outputs are only active input terminals, but the output
the impedance LOWs indication does not change. What is
D. its logic capacity is lost wrong?
10. CMOS logic is probably the best all-
A. The dim indication on the logic
around circuitry because of its: 4. The complex programmable logic
probe indicates that the supply
A. packing density device (CPLD) contains several PLD
voltage is probably low.
B. low power consumption blocks and:
B. The output of the gate
C. very high noise immunity A. field-programmable switches
appears to be open.
D. low power consumption and B. AND/OR arrays
C. The LOW indication is the result
very high noise immunity C. a global interconnection
of a bad ground connection on
matrix
11. Low power consumption achieved by the logic probe.
D. a language compiler
CMOS circuits is due to which D. The gate is a tri-state device.
construction characteristic? 5. PLAs, CPLDs, and FPGAs are all which
4. A +5 V PCB power source that has
A. complementary pairs type of device?
been "pulled down" to a +3.4 V level may
B. connecting pads A. SLD
be due to:
C. DIP packages B. PLD
A. a circuit open
D. small-scale integration C. EPROM
B. a faulty regulator
D. SRAM
12. A TTL totem pole circuit is designed C. the half-split method
so that the output transistors are: 6. The difference between a PLA and a D. a circuit short
A. always on together PAL is:
5. Measurement of pulse width should
B. providing phase splitting A. the PLA has a programmable
be taken at a 50% mean of the:
C. providing voltage regulation OR plane and a programmable
A. overshoot and undershoot
D. never on together AND plane, while the PAL
B. rise and fall
only has a programmable
13. The time needed for an output to C. damping and ringing
AND plane
change as the result of an input change D. leading and trailing amplitude
B. the PAL has a programmable
is known as:
OR plane and a programmable 6. Which test equipment best allows a
A. noise immunity
AND plane, while the PLA only comparison between input and output
B. fanout
has a programmable AND plane signals?
C. propagation delay
C. the PAL has more possible A. an oscilloscope
D. rise time
product terms than the PLA B. a logic probe
D. PALs and PLAs are the same C. a spectrum analyzer
thing. D. a multitrace oscilloscope
PROGRAMMABLE LOGIC
7. The duty cycle of a pulse is
DEVICES (PLD) determined by which formula?
TESTING AND
1. Which type of PLD should be used to TROUBLESHOOTING A. Duty Cycle =
program basic logic functions?
A. PLA 1. A series of gradually decreasing sine B. Duty Cycle =
B. PAL wave oscillations is called:
C. CPLD A. ringing C. Duty Cycle =
D. SLD B. slew
D. Duty Cycle =
C. overshooting
2. The content of a simple
D. undershooting 8. What is the next step after discovering
programmable logic device (PLD)
a faulty gate within an IC?
consists of: 2. The determination of a digital signal's
A. repair the gate
A. fuse-link arrays frequency and waveshape is best
B. resolder the tracks
B. thousands of basic logic gates accomplished with which test
C. replace the IC involved
C. advanced sequential logic equipment?
D. recheck the power source
functions A. an oscilloscope
D. thousands of basic logic gates B. a multimeter 9. The use of a multimeter with digital
and advanced sequential logic C. a spectrum analyzer circuits allows the measurement of:
functions D. a frequency generator A. pulse width
3. Once a PAL has been programmed:
τµΩ INDIABIX ELECTRONICS PART 2
B. voltage or resistance that occur during the 11. A basic multiplexer principle can be
C. current transmission of codes from one demonstrated through the use of a:
D. pulse trains location to another. A. single-pole relay
10. The use of triggered sweep when C. Parity checking is not suitable B. DPDT switch
using an oscilloscope provides more for detecting single-bit errors in C. rotary switch
accuracy in which area? transmitted codes. D. linear stepper
A. frequency D. Parity checking is capable of
12. In a BCD-to-seven-segment
B. amplitude detecting and correcting errors
converter, why must a code converter be
C. graticule activity in transmitted codes.
utilized?
D. timing
5. A multiplexed display: A. No conversion is necessary.
11. The time needed for a pulse to A. accepts data inputs from one B. to convert the 4-bit BCD into
increase from 10% to 90% of its line and passes this data to gray code
amplitude defines: multiple output lines C. to convert the 4-bit BCD into
A. pulse width B. uses one display to present 10-bit code
B. propagation delay two or more pieces of D. to convert the 4-bit BCD into
C. rise time information 7-bit code
D. duty cycle C. accepts data inputs from
multiple lines and passes this
12. Which device would best aid in FLIP FLOPS AND TIMERS
data to multiple output lines
shorted track detection?
D. accepts data inputs from
A. multimeter
several lines and multiplexes 1. Which of the following is correct for a
B. current tracer
this input data to four BCD lines gated D-type flip-flop?
C. logic pulser
D. oscilloscope 6. When two or more inputs are active A. The Q output is either SET or
simultaneously, the process is called: RESET as soon as the D input
A. first-in, first-out processing goes HIGH or LOW.
COMBINATIONAL LOGIC B. priority encoding B. The output complement follows
the input when enabled.
CIRCUITS C. ripple blanking
D. priority decoding C. Only one of the inputs can be
HIGH at a time.
1. How many inputs are required for a 1- 7. Which type of decoder will select one D. The output toggles if one of the
of-10 BCD decoder? of sixteen outputs, depending on the 4- inputs is held HIGH.
A. 4 bit binary input value?
B. 8 A. hexadecimal 2. When both inputs of a J-K flip-flop
C. 10 B. dual octal outputs cycle, the output will:
D. 1 C. binary-to-hexadecimal A. be invalid
D. hexadecimal-to-binary B. not change
2. Most demultiplexers facilitate which
C. change
of the following? 8. A magnitude comparator determines: D. toggle
A. decimal to hexadecimal A. A ≠ B and if A α B or A >> B
B. single input, multiple outputs B. A ≈ B and if A > B or A < b 3. Latches constructed with NOR and
C. ac to dc C. A = B and if A > B or A < b NAND gates tend to remain in the
D. odd parity to even parity D. A B and if A < b or a > B latched condition due to which
configuration feature?
3. One application of a digital 9. A circuit that responds to a specific set A. asynchronous operation
multiplexer is to facilitate: of signals to produce a related digital B. low input voltages
A. code conversion signal output is called a(n): C. gate impedance
B. parity checking A. BCD matrix D. cross coupling
C. parallel-to-serial data B. display driver
conversion C. encoder 4. The 555 timer can be used in which of
D. data generation D. decoder the following configurations?
A. astable, monostable
4. Select one of the following 10. Which digital system translates B. monostable, bistable
statements that best describes the coded characters into a more intelligible C. astable, toggled
parity method of error detection: form? D. bistable, tristable
A. Parity checking is best suited A. encoder
for detecting single-bit errors B. display 5. A basic S-R flip-flop can be
in transmitted codes. C. counter constructed by cross-coupling which
B. Parity checking is best suited D. decoder basic logic gates?
for detecting double-bit errors A. AND or OR gates
τµΩ INDIABIX ELECTRONICS PART 2
B. XOR or XNOR gates A. There is no known significance A. PIPO
C. NOR or NAND gates in their designations. B. SISO
D. AND or NOR gates B. The J represents "jump," which C. SIPO
is how the Q output reacts D. PISO
6. One example of the use of an S-R flip- whenever the clock goes HIGH
4. Synchronous counters eliminate the
flop is as a(n): and the J input is also HIGH.
delay problems encountered with
A. transition pulse generator C. The letters represent the initials
asynchronous (ripple) counters because
B. astable oscillator of Johnson and King, the co-
the:
C. racer inventors of the J-K flip-flop.
A. input clock pulses are applied
D. switch debouncer D. All of the other letters of the
only to the first and last
alphabet are already in use.
7. If both inputs of an S-R NAND latch stages
are LOW, what will happen to the 13. Which of the following describes the B. input clock pulses are applied
output? operation of a positive edge-triggered only to the last stage
A. The output would become D-type flip-flop? C. input clock pulses are not used
unpredictable. A. If both inputs are HIGH, the to activate any of the
B. The output will toggle. output will toggle. counter stages
C. The output will reset. B. The output will follow the D. input clock pulses are
D. No change will occur in the input on the leading edge of applied simultaneously to
output. the clock. each stage
C. When both inputs are LOW, an
8. The equation for the output frequency 5. One of the major drawbacks to the
invalid state exists.
of a 555 timer operating in the astable use of asynchronous counters is that:
D. The input is toggled into the
A. low-frequency applications
flip-flop on the leading edge of
mode is: are limited because of
the clock and is passed to the
What value of C1 will be required if R1 = 1 internal propagation delays
output on the trailing edge of
kΩ , R2 = 1 kΩ, and f = 1 kHz? B. high-frequency applications
the clock.
A. 0.33 µF are limited because of
B. 0.48 µF 14. What is one disadvantage of an S-R internal propagation delays
C. 480 µF flip-flop? C. Asynchronous counters do
D. 33 nF A. It has no Enable input. not have major
B. It has a RACE condition. drawbacks and are
9. An astable multivibrator is a circuit
C. It has no clock input. suitable for use in high- and
that:
D. It has only a single output. low-frequency counting
A. has two stable states
applications.
B. is free-running
D. Asynchronous counters do
C. produces a continuous output SEQUENTIAL LOGIC not have propagation
signal
D. is free-running and produces a CIRCUITS delays, which limits their use
in high- frequency
continuous output signal
applications.
10. What is another name for a one- 1. A ripple counter's speed is limited by
the propagation delay of: 6. Which type of device may be used to
shot?
A. each flip-flop interface a parallel data format with
A. monostable
B. all flip-flops and gates external equipment's serial format?
B. bistable
C. the flip-flops only with gates A. key matrix
C. astable
D. only circuit gates B. UART
D. tristable
C. memory chip
11. The truth table for an S-R flip-flop 2. To operate correctly, starting a ring D. serial-in, parallel-out
has how many VALID entries? counter requires:
A. clearing all the flip-flops 7. When the output of a tri-state shift
A. 3
B. presetting one flip-flop and register is disabled, the output level is
B. 1
clearing all the others placed in a:
C. 4
C. clearing one flip-flop and A. float state
D. 2
presetting all the others B. LOW state
12. What is the significance of the J and D. presetting all the flip-flops C. high impedance state
K terminals on the J-K flip-flop? D. float state and a high
3. What type of register would shift a impedance state
complete binary number in one bit at a
time and shift all the stored bits out one 8. A comparison between ring and
bit at a time? johnson counters indicates that:
τµΩ INDIABIX ELECTRONICS PART 2
A. a ring counter has fewer flip- OPERATIONS AND 8. Use the two's complement system to
flops but requires more add the signed numbers 11110010 and
decoding circuitry CIRCUITS 11110011. Determine, in decimal, the
B. a ring counter has an inverted sign and value of each number and their
feedback path 1. When 1100010 is divided by 0101, sum.
C. a johnson counter has more what will be the decimal remainder? A. –14 and –13; –27
flip-flops but less decoding A. 2 B. –113 and –114; 227
circuitry B. 3 C. –27 and –13; 40
D. a johnson counter has an C. 4 D. –11 and –16; –27
inverted feedback path D. 6
9. The selector inputs to an arithmetic-
9. A sequence of equally spaced timing 2. What are the two types of basic adder logic unit (ALU) determine the:
pulses may be easily generated by which circuits? A. selection of the IC
type of counter circuit? A. half adder and full adder B. arithmetic or logic function
A. shift register sequencer B. half adder and parallel adder C. data word selection
B. clock C. asynchronous and D. clock frequency to be used
C. johnson synchronous
D. one's complement and two's 10. Adding in binary, the decimal values
D. binary
complement 26 + 27 will produce a sum of:
10. What is meant by parallel-loading A. 111010
the register? 3. Adding the two's complement of –11 B. 110110
A. Shifting the data in all flip- + (–2) will yield which two's complement C. 110101
flops simultaneously answer? D. 101011
B. Loading data in two of the A. 1110 1101
B. 1111 1001 11. Binary subtraction of a decimal 15
flip-flops from 43 will utilize which two's
C. Loading data in all four flip- C. 1111 0011
D. 1110 1001 complement?
flops at the same time A. 101011
D. Momentarily disabling the 4. The two's complement system is to B. 110000
synchronous SET and RESET be used to add the signed numbers C. 011100
inputs 11110010 and 11110011. Determine, in D. 110001
11. What is a shift register that will decimal, the sign and value of each
number and their sum. 12. When multiplying in binary the
accept a parallel input and can shift data decimal values 13 × 11, what is the third
left or right called? A. –14 and –13; –27
B. –113 and –114; 227 partial product?
A. tri-state A. 100000
B. end around C. –27 and –13; 40
D. –11 and –16; –27 B. 100001
C. bidirectional universal C. 0000
D. conversion 5. The fast carry or look-ahead carry D. 1011
12. What happens to the parallel output circuits found in most 4-bit parallel-
adder circuits: 13. The range of an 8-bit two's
word in an asynchronous binary down complement word is from:
counter whenever a clock pulse occurs? A. increase ripple delay
B. add a 1 to complemented A. +12810 to –12810
A. The output word decreases B. –12810 to +12710
by 1. inputs
C. reduce propagation delay C. +12810 to –12710
B. The output word decreases by D. +12710 to –12710
2. D. determine sign and magnitude
C. The output word increases by 6. How many basic binary subtraction
1. operations are possible? SEMICONDUCTOR
D. The output word increases by A. 4 MEMORY
2. B. 3
13. Mod-6 and mod-12 counters are C. 2
1. A computerized self-diagnostic for a
most commonly used in: D. 1
ROM test uses:
A. frequency counters 7. How many basic binary subtraction A. the check-sum method
B. multiplexed displays combinations are possible? B. a ROM listing
C. digital clocks A. 4 C. ROM comparisons
D. power consumption B. 3 D. a checkerboard test
C. 2 2. How many storage locations are
ARITHMETIC D. 1 available when a memory device has
twelve address lines?
τµΩ INDIABIX ELECTRONICS PART 2
A. 144 D. the EEPROM can erase and A. reduced memory access time
B. 512 reprogram individual words B. reduced requirement for
C. 2048 without removal from the constant refreshing of the
D. 4096 circuit memory contents
C. reduced pin count and
3. Which of the following memories uses 8. Which of the following RAM timing
decrease in package size
a MOSFET and a capacitor as its parameters determine(s) its operating
D. no requirement for a chip-
memory cell? speed?
select input line, thereby
A. SRAM A. tacc
reducing the pin count
B. DRAM B. taa and tacs
C. ROM C. t1 and t3
D. DROM D. trc and twc ANALOG AND DIGITAL
4. Which of the following best describes 9. Memory that loses its contents when CONVERTERS
nonvolatile memory? power is lost is:
A. memory that retains stored A. nonvolatile
information when electrical B. volatile 1. Which of the following is a type of
power is removed C. random error associated with digital-to-analog
B. memory that loses stored D. static converters (DACs)?
information when electrical A. nonmonotonic error
10. Select the best description of the B. incorrect output codes
power is removed
fusible-link PROM. C. offset error
C. magnetic memory
A. user programmable, one- D. nonmonotonic and offset
D. nonmagnetic memory
time programmable error
5. The access time (tacc) of a memory IC B. manufacturer programmable,
is governed by the IC's: one-time programmable 2. A 4-bit R/2R digital-to-analog (DAC)
A. internal address buffer C. user programmable, converter has a reference of 5 volts.
B. internal address decoder reprogrammable What is the analog output for the input
C. volatility D. manufacturer programmable, code 0101.
D. internal address decoder and reprogrammable A. 0.3125 V
volatility B. 3.125 V
11. A nonvolatile type of memory that C. 0.78125 V
6. Select the best description of read- can be programmed and erased in D. –3.125 V
only memory (ROM). sectors, rather than one byte at a time is:
A. nonvolatile, used to store A. flash memory 3. A binary-weighted digital-to-analog
information that changes B. EPROM converter has an input resistor of 100
during system operation C. EEPROM . If the resistor is connected to a 5 V
B. nonvolatile, used to store D. MPROM source, the current through the resistor
information that does not is:
12. Which of the following best
change during system A. 50 A
describes static memory devices?
operation B. 5 mA
A. memory devices that are
C. volatile, used to store C. 500 A
magnetic in nature and do not
information that changes D. 50 mA
require constant refreshing
during system operation
B. semiconductor memory 4. What is the resolution of a digital-to-
D. volatile, used to store
devices in which stored data analog converter (DAC)?
information that does not
is retained as long as power A. It is the comparison between
change during system
is applied the actual output of the
operation
C. memory devices that are converter and its expected
7. Advantage(s) of an EEPROM over an magnetic in nature and output.
EPROM is (are): require constant refreshing B. It is the deviation between the
A. the EPROM can be erased D. semiconductor memory ideal straight-line output and
with ultraviolet light in much devices in which stored data the actual output of the
less time than an EEPROM will not be retained with the converter.
B. the EEPROM can be erased power applied unless C. It is the smallest analog
and reprogrammed without constantly refreshed output change that can occur
removal from the circuit as a result of an increment in
13. What is the principal advantage of
C. the EEPROM has the ability to the digital input.
using address multiplexing with DRAM
erase and reprogram D. It is its ability to resolve
memory?
individual words between forward and reverse
τµΩ INDIABIX ELECTRONICS PART 2
steps when sequenced over its 10. The resolution of a 0–5 V 6-bit mnemonic codes are in
entire range. digital-to-analog converter (DAC) is: shorthand English.
A. 63% C. Machine codes are in
5. The practical use of binary-weighted
B. 64% shorthand English, mnemonic
digital-to-analog converters is limited
C. 1.56% codes are in binary.
to:
D. 15.6% D. Machine codes are in
A. R/2R ladder D/A converters
shorthand English, mnemonic
B. 4-bit D/A converters 11. In a flash analog-to-digital converter,
codes are a high-level
C. 8-bit D/A converters the output of each comparator is
language.
D. op-amp comparators educing connected to an input of a:
the pin count A. decoder 3. Which bus is bidirectional?
B. priority encoder A. data bus
6. The difference between analog
C. multiplexer B. control bus
voltage represented by two adjacent
D. demultiplexer C. address bus
digital codes, or the analog step size, is
D. multiplexed bus
the: 12. Which is not an analog-to-digital
A. quantization (ADC) conversion error? 4. The software used to drive
B. accuracy A. differential nonlinearity microprocessor-based systems is called:
C. resolution B. missing code A. assembly language
D. monotonicity C. incorrect code programs
D. offset B. firmware
7. The primary disadvantage of the flash
C. BASIC interpreter instructions
analog-to digital converter (ADC) is that: 13. Sample-and-hold circuits in analog-
D. flowchart instructions
A. it requires the input voltage to to digital converters (ADCs) are
be applied to the inputs designed to: 5. A microprocessor unit, a memory
simultaneously A. sample and hold the output of unit, and an input/output unit form a:
B. a long conversion time is the binary counter during the A. CPU
required conversion process B. compiler
C. a large number of output lines B. stabilize the comparator's C. microcomputer
is required to simultaneously threshold voltage during the D. ALU
decode the input voltage conversion process
6. How many buses are connected as
D. a large number of C. stabilize the input analog
part of the 8085 microprocessor?
comparators is required to signal during the conversion
A. 2
represent a reasonable process
B. 3
sized binary number D. sample and hold the D/A
C. 5
converter staircase waveform
8. A binary-weighted digital-to-analog D. 8
during the conversion process
converter has a feedback resistor, Rf, of
12 k . If 50 A of current is through 7. Which of the following is not a
the resistor, the voltage out of the circuit computer bus?
is:
COMPUTER HARDWARE A. data bus
A. 0.6 V AND SOFTWARE B. timer bus
B. –0.6 V C. control bus
C. 0.1 V D. address bus
1. When referring to instruction words, a
D. –0.1 V mnemonic is: 8. The technique of assigning a memory
9. What is the major advantage of the A. a short abbreviation for the address to each I/O device in the SAM
R/2R ladder digital-to-analog (DAC), as operand address system is called:
compared to a binary-weighted digital- B. a short abbreviation for the A. wired I/O
to-analog DAC converter? operation to be performed B. I/O mapping
A. It only uses two different C. a short abbreviation for the C. dedicated I/O
resistor values. data word stored at the D. memory-mapped I/O
B. It has fewer parts for the same operand address
9. How many bits are used in the data
number of inputs. D. shorthand for machine
bus?
C. Its operation is much easier to language
A. 7
analyze. 2. What is the difference between B. 8
D. The virtual ground is mnemonic codes and machine codes? C. 9
eliminated and the circuit is A. There is no difference. D. 16
therefore easier to understand B. Machine codes are in binary,
and troubleshoot. 10. A port can be:
τµΩ INDIABIX ELECTRONICS PART 2
A. strictly for input 4. The generic array logic (GAL) device is B. several digital signals are sent
B. strictly for output ________. on each conductor.
C. bidirectional A. one-time programmable C. both binary and hexadecimal
D. all the above B. reprogrammable can be used.
C. a CMOS device D. no clock is needed.
11. Which of the following is not a basic
D. reprogrammable and a CMOS
element within the microprocessor? 12. A decoder converts ________.
device
A. microcontroller A. noncoded information into
B. arithmetic-logic unit (ALU) 5. The range of voltages between VL(max) coded form
C. temporary register and VH(min) are ________. B. coded information into
D. accumulator A. unknown noncoded form
B. unnecessary C. HIGHs to LOWs
12. How many bits are used in the
C. unacceptable D. LOWs to HIGHs
address bus?
D. between 2 V and 5 V
A. 7 13. A DAC changes ________.
B. 8 6. What is a digital-to-analog converter? A. an analog signal into digital
C. 9 A. It takes the digital data
D. 16 information from an B. digital data into an analog
audio CD and converts it to signal
13. Exceptions to the 8085
a usable form. C. digital data into an amplified
microprocessor normal operation are
B. It allows the use of cheaper signal
called:
analog techniques, which are D. none of the above
A. jump instructions
always simpler.
B. decoding 14. The output of a NOT gate is HIGH
C. It stores digital data on a hard
C. interrupts when ________.
drive.
D. jump instructions or A. the input is LOW
D. It converts direct current to
interrupts B. the input is HIGH
alternating current.
C. the input changes from LOW to
7. What are the symbols used to
HIGH
DIGITAL CONCEPTS represent digits in the binary number
D. voltage is removed from the
system?
gate
A. 0,1
1. Any number with an exponent of zero B. 0,1,2 15. The output of an OR gate is LOW
is equal to: C. 0 through 8 when ________.
A. zero D. 1,2
B. one A. all inputs are LOW
C. that number 8. A full subtracter circuit requires____.
B. any input is LOW
D. ten A. two inputs and two outputs
C. any input is HIGH
B. two inputs and three outputs
2. In the decimal numbering system, D. all inputs are HIGH
C. three inputs and one output
what is the MSD? D. three inputs and two 16. Which of the following is not an
A. The middle digit of a stream of outputs analog device?
numbers A. Thermocouple
B. The digit to the right of the 9. The output of an AND gate is LOW
B. Current flow in a circuit
decimal point _____.
C. Light switch
C. The last digit on the right A. all the time
D. Audio microphone
D. The digit with the most B. when any input is LOW
weight C. when any input is HIGH 17. A demultiplexer has ________.
D. when all inputs are HIGH A. one data input and a number
3. Which of the following statements of selection inputs, and they
does NOT describe an advantage of 10. Give the decimal value of binary
have several outputs
digital technology? 10010.
B. one input and one output
A. The values may vary over a A. 610
C. several inputs and several
continuous range. B. 910
outputs
B. The circuits are less affected C. 1810
D. several inputs and one output
by noise. D. 2010
C. The operation can be 18. A flip-flop has ________.
11. Parallel format means that:
programmed. A. one stable state
A. each digital signal has its
D. Information storage is easy. B. no stable states
own conductor.
C. two stable states
D. none of the above
τµΩ INDIABIX ELECTRONICS PART 2
receiver as there are data C. It allows the use of digital
19. Digital signals transmitted on a
bits. signals in everyday life.
single conductor (and a ground) must be
D. is less expensive than the serial D. It stores information on a CD.
transmitted in:
method of data transmission.
A. slow speed. 33. A multiplexer has ________.
B. parallel. 26. Convert the fractional decimal A. one input and several outputs
C. analog. number 6.75 to binary.O B. one input and one output
D. serial. A. 0111.1100 C. several inputs and several
B. 0110.1010 outputs
20. In a certain digital waveform, the
C. 0110.1100 D. several inputs and one
period is four times the pulse width. The
D. 0110.0110 output
duty cycle is ________.
3
A. 0% 27. What is one relative disadvantage of 34. What is the decimal value of 2 ?
B. 25% serial transfer? A. 2
C. 50% A. It requires too many B. 4
D. 100% conductors. C. 6
B. Its interconnect system is D. 8
21. In positive logic, ________.
complex.
A. a HIGH = 1, a LOW = 0 35. An encoder converts ________.
C. It is slow.
B. a LOW = 1, a HIGH = 0 A. noncoded information into
D. It can only be used over very
C. only HIGHs are present coded form
short distances.
D. only LOWs are present B. coded information into
28. Which format requires fewer noncoded form
22. Convert the fractional binary number
conductors? C. HIGHs to LOWs
0000.1010 to decimal.
A. Parallel D. LOWs to HIGHs
A. 0.625
B. Serial
B. 0.50 36. What kind of logic device or circuit is
C. Both are the same
C. 0.55 used to store information?
D. Cannot tell
D. 0.10 A. Counter
B. Register
23. Digital representations of numerical 29. A pulse has a period of 15 ms. Its
C. Inverter
values of quantities may BEST be frequency is ________.
D. Buffer
described as having characteristics: A. 6.66 Hz
A. that are difficult to interpret B. 66.66 Hz 37. PLCC packages have leads on ____.
because they are continuously C. 666.66 Hz A. one side
changing. D. 15 Hz B. two sides
B. that vary constantly over a C. three sides
30. Give the decimal value of binary
continuous range of values. D. four sides
10000110.
C. that vary in constant and direct
A. 13410 38. What is the typical invalid voltage for
proportion to the
B. 14410 a binary signal?
values they represent.
C. 11010 A. 0.7–2.8 volts
D. that vary in discrete steps in
D. 12610 B. 0.8–3 volts
proportion to the values they
C. 0.8–2 volts
represent. 31. The rise time is the time it takes a
D. 0.7–2.5 volts
pulse to go from ________.
24. A common instrument used in
A. the base line to the maximum 39. Convert the fractional binary number
troubleshooting a digital circuit is a(n)
HIGH voltage 0001.0010 to decimal.
_____.
B. 10% of the pulse amplitude to A. 1.40
A. logic probe
the maximum HIGH voltage B. 1.125
B. oscilloscope
C. the base line to 90% of the C. 1.20
C. pulser
pulse amplitude D. 1.80
D. all of the above
D. 10% of the pulse amplitude
40. Convert the fractional binary number
25. The parallel transmission of digital to 90% of the pulse
10010.0100 to decimal.
data: amplitude
A. 24.50
A. is much slower than the serial
32. What is an analog-to-digital B. 18.25
transmission of data.
converter? C. 18.40
B. requires only one signal line
A. It makes digital signals. D. 16.25
between sender and receiver.
B. It takes analog signals and
C. requires as many signal lines 41. How many binary bits are necessary
puts them in digital format.
between sender and to represent 748 different numbers?
τµΩ INDIABIX ELECTRONICS PART 2
A. 9 49. A type of digital circuit technology transmission of codes from one
B. 7 that uses bipolar junction transistors is location to another.
C. 10 ________. B. Parity checking is not suitable
D. 8 A. TTL for detecting single-bit errors in
B. CMOS transmitted codes.
42. A periodic digital waveform has a
C. LSI C. Parity checking is best suited
pulse width (tw) of 6 ms and a period (T)
D. NMOS for detecting single-bit errors
of 18 ms. The duty cycle is ______.
in transmitted codes.
A. 3.3% 50. How many unique symbols are used
D. Parity checking is capable of
B. 33.3% in the decimal number system?
detecting and correcting errors
C. 6% A. One
in transmitted codes.
D. 18% B. Nine
C. Ten 2. A logic circuit that provides a HIGH
43. Any number with an exponent of one
D. Unlimited output for both inputs HIGH or both
is equal to:
inputs LOW is a(n):
A. zero. 51. A classification of ICs with
A. Ex-NOR gate
B. one. complexities of 12 to 100 equivalent
B. OR gate
C. two. gates on a chip is known as ________.
C. Ex-OR gate
D. that number. A. SSI
D. NAND gate
B. MSI
44. Serial format means digital signals
C. LSI 3. A logic circuit that provides a HIGH
are:
D. VLSI output if one input or the other input,
A. sent over many conductors
but not both, is HIGH, is a(n):
simultaneously. 52. Which of the following is a
A. Ex-NOR gate
B. sent over one conductor semiconductor memory?
B. OR gate
sequentially. A. RAM
C. Ex-OR gate
C. sent in groups of eight signals. B. MAR
D. NAND gate
D. sent in binary coded decimal. C. CD-ROM
–1 D. CD 4. Identify the type of gate below from
45. What is the decimal value of 2 ?
A. 0.5 53. The holes through a PC board are the equation
B. 0.25 ________. A. Ex-NOR gate
C. 0.05 A. smaller with SMT than with B. OR gate
D. 0.1 through-hole mounting C. Ex-OR gate
B. larger with SMT than with D. NAND gate
46. Which format can send several bits
through-hole mounting 5. How is odd parity generated
of information faster?
C. the same size as with differently from even parity?
A. Parallel
through-hole mounting A. The first output is inverted.
B. Serial
D. usually unnecessary B. The last output is inverted.
C. Both are the same
D. Cannot tell 54. A classification of ICs with 6. Parity systems are defined as
complexities of 100 to 10,000 equivalent either________ or ________ and will add
47. The frequency of a pulse train is 2
gates per chip is known as ______. an extra ________ to the digital
kHz. The pulse period is ________.
A. SSI information being transmitted.
A. 5 ms
B. MSI A. positive, negative, byte
B. 50 ms
C. LSI B. odd, even, bit
C. 500 s
D. VLSI C. upper, lower, digit
D. 2 s
D. on, off, decimal
48. What has happened to the advances
in digital technologies over the past EX-OR AND EX-NOR 7. Which type of gate can be used to add
three decades? two bits?
GATES A. Ex-OR
A. Slowed down considerably
B. Continued to increase, but at a B. Ex-NOR
decreasing rate 1. Select the statement that best C. Ex-NAND
C. Made excellent progress describes the parity method of error D. NOR
D. Nothing short of detection: 8. Why is an exclusive-NOR gate also
phenomenal A. Parity checking is best suited called an equality gate?
for detecting double-bit errors A. The output is false if the inputs
that occur during the are equal.
τµΩ INDIABIX ELECTRONICS PART 2
B. The output is true if the inputs B. OR operation. C. c
are opposite. C. NOT operation. D. d
C. The output is true if the inputs D. AND operation.
8. In VHDL, the mode of a port does not
are equal.
4. For a three-input OR gate, with the define:
9. Show from the truth table how an input waveforms as shown below, which A. an input.
exclusive-OR gate can be used to invert output waveform is correct? B. an output.
the data on one input if the other input is C. both an input and an output.
a special control function. D. the TYPE of the bit.
A. Using A as the control, when A
9. Which of the following equations
= 0, X is the same as B. When A
would accurately describe a 4-input OR
= 1, X is the same as B.
gate when A = 1, B = 1, C = 0, and D = 0?
B. Using A as the control, when A
A. 1+1+0+0=1
= 0, X is the same as B. When
A. a B. 1 + 1 + 0 + 0 = 01
A = 1, X is the inverse of B.
B. b C. 1+1+0+0=0
C. Using A as the control, when A
C. c D. 1 + 1 + 0 + 0 = 00
= 0, X is the inverse of B. When
A = 1, X is the same as B. D. d 10. Which of the examples below
D. Using A as the control, when A 5. Which of the figures given expresses the distributive law?
= 0, X is the inverse of B. When below represents a NOR gate? A. (A + B) + C = A + (B + C)
A = 1, X is the inverse of B. B. A(B + C) = AB + AC
C. A + (B + C) = AB + AC
10. Determine odd parity for each of the
D. A(BC) = (AB) + C
following data words:
A. a
1011101 11110111 1001101 11. Which of the examples below
B. b
A. P = 1, P = 1, P = 0 expresses the associative law of
C. c
B. P = 0, P = 0, P = 0 addition:
D. d
C. P = 1, P = 1, P = 1 A. A + (B + C) = (A + B) + C
D. P = 0, P = 0, P = 1 6. Which of the figures (a to d) is the B. A + (B + C) = A + (BC)
DeMorgan equivalent of Figure (e)? C. A(BC) = (AB) + C
11. The Ex-NOR is sometimes
D. ABC = A + B + C
called the ________.
A. parity gate 12. How are the statements between
B. equality gate A. a BEGIN and END not evaluated in VHDL?
C. inverted OR B. b A. Constantly
D. parity gate or the equality gate C. c B. Simultaneously
D. d C. Concurrently
D. Sequentially
7. Which of the figures in figure (a to d) is
DESCRIBING LOGIC equivalent to figure (e)? 13. Which logic gate does this truth table
CIRCUITS describe?

1. The format used to present the logic


output for the various combinations of
logic inputs to a gate is called a(n):
A. truth table.
B. input logic function. A. AND
C. Boolean constant. B. OR
D. Boolean variable. C. NAND
D. NOR
2. What is the basic difference between
AHDL and VHDL? 14. For a 3-input NAND gate, with the
A. ADHL is used in all PLD's. input waveforms as shown below, which
B. VHDL is used in all PLD's. output waveform is correct?
C. ADHL is proprietary.
D. VHDL is proprietary.
A. a
3. A small circle on the output of a logic
B. b
gate is used to represent the:
A. Comparator operation.
τµΩ INDIABIX ELECTRONICS PART 2
A. a D.
B. b
27. Which step in this reduction process
C. c
is using DeMorgan's theorem?
D. d
20. Which of the following is a form of
DeMorgan's theorem?
A.
A. a
B.
B. b
C. c C.
D. d D.
15. Which of the figures given below 21. The logic gate that will have HIGH or
represents a NAND gate? "1" at its output when any one of its A. STEP 1
inputs is HIGH is a(n): B. STEP 2
A. NOR gate C. STEP 3
B. OR gate D. STEP 4
A. a C. AND gate 28. Simplify the expression using
B. b D. NOT operation DeMorgan's theorems.
C. c
D. d 22. Which of the symbols shown below A.
represents an AND gate? B.
16. Which timing diagram shown below
is correct for an inverter? C.
D.
A. a 29. For a three-input NOR gate, with the
B. b input waveforms as shown below, which
C. c output waveform is correct?
D. d
23. For a three-input AND gate, with the
input waveforms as shown below, which
A. a output waveform is correct?
B. b A. a
C. c B. b
D. d C. c
17. A NOR gate with one HIGH input and D. d
one LOW input: 24. An OR gate with inverted inputs A. a
A. will output a HIGH functions as: B. b
B. functions as an AND A. an AND gate. C. c
C. will not function B. a NAND gate. D. d
D. will output a LOW C. a NOR gate.
18. A NAND gate has: D. an inverter. LOGIC GATES
A. active-LOW inputs and an 25. The special software application that
active-HIGH output. translates from HDL into a grid of 1's and 1. The output of an AND gate with three
B. active-LOW inputs and an 0's, which can be loaded into a PLD, is inputs, A, B, and C, is HIGH when
active-LOW output. called a: _______.
C. active-HIGH inputs and an A. formatter. A. A = 1, B = 1, C = 0
active-HIGH output. B. compiler. B. A = 0, B = 0, C = 0
D. active-HIGH inputs and an C. programmable wiring. C. A = 1, B = 1, C = 1
active-LOW output. D. CPU. D. A = 1, B = 0, C = 1
19. Which of the figures given below 26. The Boolean equation for a NOR 2. If a 3-input NOR gate has eight input
represents an OR gate? function is: possibilities, how many of those
A. possibilities will result in a HIGH output?
A. 1
B. B. 2
C. C. 7
τµΩ INDIABIX ELECTRONICS PART 2
D. 8 used in digital control and sequencing A logic probe is again applied to the pins
circuits? of a 7421 IC with the following results. Is
3. If a signal passing through a gate is
A. basic gates, a clock oscillator, there a problem with the circuit and if
inhibited by sending a LOW into one of
and a repetitive waveform so, what is the problem?
the inputs, and the output is HIGH, the
generator
gate is a(n):
B. basic gates, a clock oscillator, A. Pin 6 should be ON.
A. AND
and a Johnson shift counter B. Pin 8 should be ON.
B. NAND
C. basic gates, a clock oscillator, C. Pin 8 should be pulsing.
C. NOR
and a DeMorgan pulse D. no problem
D. OR
generator
17. If a 3-input AND gate has eight input
4. A device used to display one or more D. basic gates, a clock oscillator, a
possibilities, how many of those
digital signals so that they can be repetitive waveform generator,
possibilities will result in a HIGH output?
compared to expected timing diagrams and a Johnson shift counter
A. 1
for the signals is a:
11. TTL operates from a ________. B. 2
A. DMM
A. 9-volt supply C. 7
B. spectrum analyzer
B. 3-volt supply D. 8
C. logic analyzer
C. 12-volt supply
D. frequency counter 18. The Boolean expression for a 3-input
D. 5-volt supply
AND gate is ________.
5. When used with an IC, what does the
12. The output of a NOR gate is HIGH if A. X = AB
term "QUAD" indicate?
_____. B. X = ABC
A. 2 circuits
A. all inputs are HIGH C. X=A+B+C
B. 4 circuits
B. any input is HIGH D. X = AB + C
C. 6 circuits
C. any input is LOW
D. 8 circuits 19. A CMOS IC operating from a 3-volt
D. all inputs are LOW
supply will consume ________.
6. The output of an OR gate with three
13. The switching speed of CMOS is A. less power than a TTL IC
inputs, A, B, and C, is LOW when ____.
now ________. B. more power than a TTL IC
A. A = 0, B = 0, C = 0
A. competitive with TTL C. the same power as a TTL IC
B. A = 0, B = 0, C = 1
B. three times that of TTL D. no power at all
C. A = 0, B = 1, C = 1
D. all of the above C. slower than TTL 20. What does the small bubble on the
D. twice that of TTL output of the NAND gate logic symbol
7. Which of the following logical
14. The format used to present the logic mean?
operations is represented by the + sign
output for the various combinations of A. open collector output
in Boolean algebra?
logic inputs to a gate is called a(n): B. tristate
A. inversion
A. Boolean constant C. The output is inverted.
B. AND
B. Boolean variable D. none of the above
C. OR
D. complementation C. truth table 21. What are the pin numbers of the
8. Output will be a LOW for any case D. input logic function outputs of the gates in a 7432 IC?
when one or more inputs are zero for 15. The power dissipation, PD, of a logic A. 3, 6, 10, and 13
a(n): gate is the product of the ________. B. 1, 4, 10, and 13
A. OR gate A. dc supply voltage and the peak C. 3, 6, 8, and 11
B. NOT gate current D. 1, 4, 8, and 11
C. AND gate B. dc supply voltage and the 22. The output of a NOT gate is HIGH
D. NOR gate average supply current when ________.
9. How many pins does the 4049 IC C. ac supply voltage and the peak A. the input is LOW
have? current B. the input is HIGH
A. 14 D. ac supply voltage and the C. power is applied to the gate's IC
B. 16 average supply current D. power is removed from the
C. 18 16. gate's IC
D. 20
23. If the input to a NOT gate is A and
the output is X, then ________.
10. Which of the following choices meets
A. X=A
the minimum requirement needed to
create specialized waveforms that are B.
C. X=0
D. none of the above
τµΩ INDIABIX ELECTRONICS PART 2
B. The output of the gate 35. The AND function can be used to ___
24. A logic probe is used to test the pins
appears to be open. and the OR function can be used to ___ .
of a 7411 IC with the following results. Is
C. The dim indication is the result A. enable, disable
there a problem with the chip and if so,
of a bad ground connection on B. disable, enable
what is the problem?
the logic probe. C. enable or disable, enable or
D. The gate is a tristate device. disable
D. detect, invert
29. What is the Boolean expression for a
three-input AND gate? 36. One advantage TTL has over CMOS
A. X=A+B+C is that TTL is ________.
B. X=A·B·C A. less expensive
C. A–B–C B. not sensitive to electrostatic
A. Pin 6 should be ON.
D. A$B$C discharge
B. Pin 6 should be pulsing.
C. faster
C. Pin 8 should be ON. 30. Which of the following gates
D. more widely available
D. no problem has the exact inverse output of the OR
gate for all possible input combinations? 37. A 2-input NOR gate is equivalent to a
25. How many inputs of a four-input
A. NOR ______.
AND gate must be HIGH in order for the
B. NOT A. negative-OR gate
output of the logic gate to go HIGH?
C. NAND B. negative-AND gate
D. AND C. negative-NAND gate
A. any one of the inputs
D. none of the above
B. any two of the inputs 31. What is the difference between a
C. any three of the inputs 7400 and a 7411 IC? 38. If a 3-input OR gate has eight input
D. all four inputs A. 7400 has two four-input NAND possibilities, how many of those
gates; 7411 has three three- possibilities will result in a HIGH output?
26. If the output of a three-input AND
input AND gates A. 1
gate must be a logic LOW, what must
B. 7400 has four two-input B. 2
the condition of the inputs be?
NAND gates; 7411 has three C. 7
A. All inputs must be LOW.
three- input AND gates D. 8
B. All inputs must be HIGH.
C. 7400 has two four-input AND
C. At least one input must be 39. Fan-out is specified in terms of ____.
gates; 7411 has three three-
LOW. A. voltage
input NAND gates
D. At least one input must be B. current
D. 7400 has four two-input AND
HIGH. C. wattage
gates; 7411 has three three-
D. unit loads
27. Logically, the output of a NOR gate input NAND gates
would have the same Boolean 40. How many input combinations
32. Write the Boolean expression for an
expression as a(n): would a truth table have for a six-input
inverter logic gate with input C and
A. NAND gate immediately AND gate?
output Y.
followed by an inverter A. 32
A. Y=C
B. OR gate immediately followed B. 48
by an inverter B. Y= C. 64
C. AND gate immediately D. 128
33. The output of an exclusive-OR gate is
followed by an inverter 41. What is the circuit number of the IC
HIGH if ________.
D. NOR gate immediately that contains four two-input AND gates
A. all inputs are LOW
followed by an inverter in standard TTL?
B. all inputs are HIGH
28. A logic probe is placed on the output C. the inputs are unequal A. 7402
of a gate and the display indicator is dim. D. none of the above B. 7404
A pulser is used on each of the input C. 7408
34. A clock signal with a period of 1 µs is D. 7432
terminals, but the output indication does
applied to the input of an enable gate.
not change. What is wrong? 42. The terms "low speed" and "high
The output must contain six pulses. How
A. The dim indication on the logic speed," applied to logic circuits, refer to
long must the enable pulse be active?
probe indicates that the supply the ________.
A. Enable must be active for 0µs.
voltage is probably low. A. rise time
B. Enable must be active for 3µ s.
C. Enable must be active for 6µs. B. fall time
D. Enable must be active for 12 µs. C. propagation delay time
D. clock speed
τµΩ INDIABIX ELECTRONICS PART 2
43. The NOR logic gate is the same as A. the inputs are equal 58. Which of the following gates is
the operation of the ________ gate with B. one input is HIGH, and the described by the expression ?
an inverter connected to the output. other input is LOW A. OR
A. OR C. the inputs are unequal B. AND
B. AND D. none of the above C. NOR
C. NAND D. NAND
51. How many AND gates are
D. none of the above
found in a 7411 IC? 59. What is the Boolean expression for a
44. The logic expression for a NOR A. 1 four-input OR gate?
gate is _______. B. 2 A. Y=A+B+C+D
A. C. 3 B. Y = A· B · C · D
D. 4 C. Y=A–B–C–D
B.
D. Y=A$B$C$D
52. Which of the following equations
C.
would accurately describe a four-input 60. How many truth table entries are
D. OR gate when A = 1, B = 1, C = 0, and D = necessary for a four-input circuit?
45. With regard to an AND gate, which 0? A. 4
statement is true? A. 1 + 1 + 0 + 0 = 01 B. 8
A. An AND gate has two inputs B. 1+1+0+0=1 C. 12
and one output. C. 1+1+0+0=0 D. 16
B. An AND gate has two or more D. 1 + 1 + 0 + 0 = 00
61. How many entries would a truth
inputs and two outputs. 53. What is the name of a digital circuit table for a four-input NAND gate have?
C. If one input to a 2-input AND that produces several repetitive digital A. 2
gate is HIGH, the output waveforms? B. 8
reflects the other input. A. an inverter C. 16
D. A 2-input AND gate has eight B. an OR gate D. 32
input possibilities. C. a Johnson shift counter 62. The Boolean expression for a 3-input
46. The term "hex inverter" refers to: D. an AND gate OR gate is ________.
A. an inverter that has six inputs A. X=A+B
54. The basic types of programmable
B. six inverters in a single B. X=A+B+C
arrays are made up of ________.
package C. X = ABC
A. AND gates
C. a six-input symbolic logic device D. X = A + BC
B. OR gates
D. an inverter that has a history of C. NAND and NOR gates 63. From the truth table for a three-input
failure D. AND gates and OR gates NOR gate, what is the only condition of
47. How many inputs are on the logic inputs A, B, and C that will make the
55. The logic gate that will have HIGH or
gates of a 74HC21 IC? output X high?
"1" at its output when any one (or more)
A. 1 A. A = 1, B = 1, C = 1
of its inputs is HIGH is a(n):
B. 2 B. A = 1, B = 0, C = 0
A. OR gate
C. 3 C. A = 0, B = 0, C = 1
B. AND gate
D. 4 D. A = 0, B = 0, C = 0
C. NOR gate
48. The basic logic gate whose output is D. NOT operation 64. The logic gate that will have a LOW
the complement of the input is the: output when any one of its inputs is
56. CMOS IC packages are available in
A. OR gate HIGH is the:
______.
B. AND gate A. NAND gate
A. DIP configuration
C. inverter B. AND gate
B. SOIC configuration
D. comparator C. NOR gate
C. DIP and SOIC configurations
D. OR gate
49. When reading a Boolean expression, D. neither DIP nor SOIC
what does the word "NOT" indicate? configurations 65. The output of a NAND gate is LOW if
A. the same as ______.
57. Which of the following is not a basic
B. inversion A. all inputs are LOW
Boolean operation?
C. high B. all inputs are HIGH
A. OR
D. low C. any input is LOW
B. NOT
D. any input is HIGH
50. The output of an exclusive-NOR gate C. AND
is HIGH if ________. D. FOR
τµΩ INDIABIX ELECTRONICS PART 2
NUMBER SYSTEMS AND C. 57
9. Which of the following is the most
D. 15
CODES widely used alphanumeric code for
computer input and output? 18. Convert the following binary number
A. Gray to octal.
1. Convert hexadecimal value 16 to B. ASCII 0101111002
decimal. C. Parity A. 1728
A. 2210 D. EBCDIC B. 2728
B. 1610 C. 1748
C. 1010 10. If a typical PC uses a 20-bit address
D. 2748
D. 2010 code, how much memory can the CPU
address? 19. How many binary digits are required
2. Convert the following decimal number A. 20 MB to count to 10010?
to 8-bit binary. B. 10 MB A. 7
187 C. 1 MB B. 2
A. 101110112 D. 580 MB C. 3
B. 110111012 D. 100
C. 101111012 11. Convert 59.7210 to BCD.
D. 101111002 20. The BCD number for decimal 347 is
A. 111011 ________.
3. Convert binary 111111110010 to B. 01011001.01110010 A. 1100 1011 1000
hexadecimal. C. 1110.11 B. 0011 0100 0111
A. EE216 D. 0101100101110010 C. 0011 0100 0001
B. FF216 D. 1100 1011 0110
C. 2FE16 12. Convert 8B3F16 to binary.
D. FD216 A. 35647 21. The binary number for octal 458 is
B. 011010 ________.
4. Convert the following binary number C. 1011001111100011 A. 100010
to decimal. D. 1000101100111111 B. 100101
010112 C. 110101
A. 11 13. Which is typically the longest: bit,
D. 100100
B. 35 byte, nibble, word?
C. 15 A. Bit 22. The sum of 11101 + 10111 equals
D. 10 B. Byte ________.
C. Nibble A. 110011
5. Convert the binary number 1001.00102 D. Word B. 100001
to decimal. C. 110100
A. 90.125 14. Assign the proper odd parity bit to
D. 100100
B. 9.125 the code 111001.
C. 125 A. 1111011 23. Convert the following binary number
D. 12.5 B. 1111001 to decimal.
C. 0111111 100110102
6. Decode the following ASCII message. D. 0011111 A. 154
1010011101010010101011000100101100 B. 155
1010000010010001000001101001010001 15. Convert decimal 64 to binary.
C. 153
00 A. 01010010
D. 157
A. STUDYHARD B. 01000000
B. STUDY HARD C. 00110110 24. The decimal number 188 is equal to
C. stydyhard D. 01001000 the binary number ________.
D. study hard A. 10111100
16. Convert hexadecimal value C1 to
B. 0111000
7. The voltages in digital electronics are binary.
C. 1100011
continuously variable. A. 11000001
D. 1111000
A. True B. 1000111
B. False C. 111000100 25. Convert the following binary number
D. 111000001 to octal.
8. One hex digit is sometimes referred to 0011010112
as a(n): 17. Convert the following octal number
A. 1538
A. byte to decimal.
B. 3518
B. nibble 178
C. 2538
C. grouping A. 51
D. 3528
D. instruction B. 82
τµΩ INDIABIX ELECTRONICS PART 2
26. How many bits are in an ASCII D. 14 43. Hexadecimal letters A through F are
character? used for decimal equivalent values from:
35. Convert the following octal number
A. 16 A. 1 through 6
to binary.
B. 8 B. 9 through 14
768
C. 7 C. 10 through 15
A. 1101112
D. 4 D. 11 through 17
B. 1111102
27. A binary number's value changes C. 1111002 44. Convert the following decimal
most drastically when the ________ is D. 1001112 number to 8-bit binary.
changed. 35
36. Convert 11001010001101012 to
A. MSB A. 000100102
hexadecimal.
B. frequency B. 000100112
A. 121035
C. LSB C. 001000112
B. CA35
D. duty cycle D. 001000102
C. 53AC1
28. Convert decimal 213 to binary. D. 530121 45. Convert the following hexadecimal
A. 11001101 number to binary.
37. Convert the following decimal
B. 11010101 C916
number to octal.
C. 01111001
281
D. 11100011 A. 101110012
A. 1348
B. 101110112
29. The decimal number for octal 748 is B. 4318
C. 100111002
________. C. 3318
D. 110010012
A. 74 D. 1338
B. 60 46. Convert the following decimal
38. When using even parity, where is the
C. 22 number to hexadecimal.
parity bit placed?
D. 62 125
A. Before the MSB
A. 7D16
30. The sum of the two BCD numbers, B. After the LSB
B. D716
0011 + 0011, is ________. C. In the parity word
C. 7C16
A. 0110 D. After the odd parity bit
D. C716
B. 0111
39. Convert the following octal number
C. 0011 47. A decimal 11 in BCD is ________.
to decimal.
D. 1100 A. 00001011
358
B. 00001100
31. Convert binary 01001110 to decimal. A. 71
C. 00010001
A. 4E B. 17
D. 00010010
B. 78 C. 92
C. 76 D. 29 48. What is the resultant binary of the
D. 116 decimal problem 49 + 01 = ?
40. Convert binary 11001111 to
A. 01010101
32. Which is not a word size? hexadecimal.
B. 00110101
A. 64 A. 8F16
C. 00110010
B. 28 B. CE16
D. 00110001
C. 16 C. DF16
D. 8 D. CF16 49. The difference of 111 – 001 equals
________.
41. Convert 17318 to decimal.
33. The octal numbering system: A. 100
A. 216.4
A. simplifies tasks B. 111
B. 985
B. groups binary numbers in C. 001
C. 3D9
groups of 4 D. 110
D. 1123
C. saves time
50. Convert the binary number 1100 to
D. simplifies tasks and saves 42. An analog signal has a range from 0
Gray code.
time V to 5 V. What is the total number of
A. 0011
analog possibilities within this range?
B. 1010
34. The binary number 1110 is equal to
C. 1100
the decimal number ________. A. 5
D. 1001
A. 3 B. 50
B. 1 C. 250
C. 7 D. infinite
τµΩ INDIABIX ELECTRONICS PART 2
51. The binary number 59. An informational signal that makes D. ASCII code
11101011000111010 can be written in use of binary digits is considered to be:
68. The decimal number 18 is equal to
hexadecimal as ________. A. solid state
the binary number ________.
A. DD63A16 B. digital
A. 11110
B. 1D63A16 C. analog
B. 10001
C. 1D33A16 D. non-oscillating
C. 10010
D. 1D63116
60. The 1's complement of 10011101 is D. 1111000
52. Which of the following is an invalid ________.
69. The 2's complement of 11100111 is
BCD code? A. 01100010
_____.
A. 0011 B. 10011110
A. 11100110
B. 1101 C. 01100001
B. 00011001
C. 0101 D. 01100011
C. 00011000
D. 1001
61. The binary number 101110101111010 D. 00011010
5
53. What decimal number does 2 can be written in octal as ________.
70. Convert the following decimal
represent? A. 515628
number to BCD.469
A. 10 B. 565778
A. 100101101000
B. 31 C. 656278
B. 010001101001
C. 25 D. 565728
C. 100001101001
D. 32
62. Convert 45710 to hexadecimal. D. 100101100100
54. Convert the Gray code 1011 to A. 711
71. Express the decimal number –37 as
binary. B. 2C7
an 8-bit number in sign-magnitude.
A. 1011 C. 811
A. 10100101
B. 1010 D. 1C9
B. 00100101
C. 0100
63. Convert the decimal number 151.75 C. 11011000
D. 1101
to binary. D. 11010001
55. Determine the decimal equivalent of A. 10000111.11
72. Convert the following BCD number
the signed binary number 11110100 in 1's B. 11010011.01
to decimal. 010101101001bcd
complement. C. 00111100.00
A. 539
A. 116 D. 10010111.11
B. 2551
B. –12
64. Convert the following octal number C. 569
C. 11
to binary.1048 D. 1552
D. 128
A. 0010001002
73. The binary number 11001110 is equal
56. What is the difference between B. 1000000012
to the decimal number ______.
binary coding and binary-coded C. 00101002
A. 12
decimal? D. 10000012
B. 206
A. BCD is pure binary. 1 0
65. 3 × 10 + 7 × 10 is equal to ________. C. 127
B. Binary coding has a decimal
A. 3.7 D. 66
format.
B. 37
C. BCD has no decimal format. 74. The binary number for F3A16 is ___.
C. 10
D. Binary coding is pure binary. A. 111100111010
D. 370
B. 111100111110
57. Convert the following decimal
66. 3428 is the decimal value for which C. 000000111010
number to BCD. 127
of the following binary-coded decimal D. 000011000100
A. 011100100001
(BCD) groupings?
B. 111010001 75. Convert the following BCD number
A. 11010001001000
C. 001010111 to decimal. 100000000011bcd
B. 11010000101000
D. 000100100111 A. 8003
C. 011010010000010
B. 803
58. Digital electronics is based on the D. 110100001101010
C. 1003
________ numbering system.
67. The binary-coded decimal (BCD) D. 103
A. decimal
system can be used to represent each of
B. octal 76. Convert the following hexadecimal
the 10 decimal digits as a(n):
C. binary number to binary.
A. 4-bit binary code
D. hexadecimal 14B16
B. 8-bit binary code
A. 1011010000012
C. 16-bit binary code
B. 0001010010112
τµΩ INDIABIX ELECTRONICS PART 2
C. 0001010011012 B. 001101000111
86. Convert 110010012 (binary) to
D. 1101010000012 C. 010100100111
decimal.
D. 011100100101
77. What is the result when a decimal A. 201
5238 is converted to base 16? B. 2001 93. Convert 5278 to binary.
A. 327.375 C. 20 A. 011100111
B. 12.166 D. 210 B. 101010111
C. 1388 C. 343
87. Convert the following decimal
D. 1476 D. 111010101
number to octal.39
78. The octal number for binary A. 638 94. The base of the hexadecimal system
1101110101110110 is ________. B. 368 is:
A. 6545218 C. 478 A. eight.
B. 5565618 D. 748 B. sixteen.
C. 1566568 C. ten.
88. The American Standard Code for
D. 1565668 D. two.
Information Interchange (ASCII) uses
79. Convert the following hexadecimal how many individual pulses for any 95. Assign the proper even parity bit to
number to decimal. 1CF16 given character? the code 1100001.
A. 463 A. 1 A. 11100001
B. 4033 B. 2 B. 1100001
C. 479 C. 7 C. 01100001
D. 4049 D. 8 D. 01110101
80. Convert the binary number 1011010 89. Convert the following hexadecimal 96. Select one of the following
to hexadecimal. number to decimal. B516 statements that best describes the
A. 5B A. 212 parity method of error detection.
B. 5F B. 197 A. Parity checking is best
C. 5A C. 165 suited for detecting single-
D. 5C D. 181 bit errors in transmitted
codes.
81. Convert the following decimal 90. The BCD number for decimal 16 is
B. Parity checking is not suitable
number to hexadecimal.74 ______.
for detecting single-bit errors
A. A416 A. 00010110
in transmitted codes.
B. B416 B. 00010000
C. Parity checking is capable of
C. 4A16 C. 00010010
detecting and correcting
D. 4B16 D. 11100000
errors in transmitted codes.
82. Convert hexadecimal C0B to binary. 91. Alphanumeric codes should include D. Parity checking is best suited
A. 110000001011 as a minimum: for detecting double-bit errors
B. 110000001001 A. the capacity to represent the that occur during the
C. 110000001100 alphabet upper- and transmission of codes from
D. 110100001011 lowercase characters one location to another.
and the decimal numbers in
83. Convert binary 1001 to hexadecimal. 97. Which of the following is the primary
a straight binary format.
A. 916 advantage of using the BCD code
B. the capacity to code all
B. 1116 instead of straight binary coding?
possible decimal numbers in a
C. 10116 A. Fewer bits are required to
direct octal representation of
D. 1016 represent a decimal number
BCD codes.
with the BCD code.
84. Convert 73116 to decimal. C. the alphabet upper- and
B. The relative ease of
A. 216.4 lowercase letters, the
converting to and from
B. 985 decimal digits, the seven
decimal.
C. 3D9 punctuation marks, and other
C. BCD codes are easily
D. 1841 characters or symbols.
converted to hexadecimal
D. the ability to represent
85. What is the decimal value of the codes.
decimal numbers greater than
hexadecimal number 777? 10 D. BCD codes are easily
128 in a straight
A. 191 converted to straight binary
binary format..
B. 1911 codes.
C. 19 92. Convert 52716 to binary.
D. 19111 A. 343
τµΩ INDIABIX ELECTRONICS PART 2
98. How many BCD code bits and how 10. Which output expression might
many straight binary bits would be indicate a product-of-sums circuit
required to represent the decimal construction?
number 643?
A.
A. 12 BCD, 12 binary A.
B. 12 BCD, 10 binary B.
C. 12 BCD, 9 binary B.
D. 16 BCD, 9 binary C.
C. D.
99. When using the repeated division by
2 method of converting from decimal to D. 11. An AND gate with schematic
binary, one must write the first 5. From the truth table below, determine "bubbles" on its inputs performs the
remainder as the: the standard SOP expression. same function as a(n)________ gate.
A. MSB A. NOT
B. MSB, provided the following B. OR
sequence of remainders are C. NOR
written in descending order D. NAND
until the final remainder is
achieved. 12.For the SOP expression
C. LSB , how many 1s
D. LSB, provided the final are in the truth table's output column?
A.
remainder is used to replace A. 1
B.
the original LSB, which is then B. 2
moved to the MSB position. C. C. 3
D. D. 5

BOOLEAN AND LOGIC 6. One of De Morgan's theorems states 13. A truth table for the SOP expression
has how many input
SIMPLIFICATION that . Simply stated, this
combinations?
means that logically there is no
difference between: A. 1
A. a NOR and an AND gate with B. 2
1. Convert the following SOP expression
inverted inputs C. 4
to an equivalent POS expression.
B. a NAND and an OR gate with D. 8

A. inverted inputs 14. How many gates would be required


C. an AND and a NOR gate with to implement the following Boolean
B. inverted inputs expression before simplification? XY +
C. D. a NOR and a NAND gate with X(X + Z) + Y(X + Z)
D. inverted inputs A. 1
7. The commutative law of Boolean B. 2
2. Determine the values of A, B, C, and D addition states that A + B = A × B. C. 4
that make the sum term A. True D. 5
equal to zero. B. False 15. Determine the values of A, B, C, and
A. A = 1, B = 0, C = 0, D = 0 D that make the product term
8. Applying DeMorgan's theorem to the
B. A = 1, B = 0, C = 1, D = 0 equal to 1.
C. A = 0, B = 1, C = 0, D = 0 expression , we get ________.
A. A = 0, B = 1, C = 0, D = 1
D. A = 1, B = 0, C = 1, D = 1 A. B. A = 0, B = 0, C = 0, D = 1
B. C. A = 1, B = 1, C = 1, D = 1
3. Which of the following expressions is D. A = 0, B = 0, C = 1, D = 0
in the sum-of-products (SOP) form? C.
A. (A + B)(C + D) D. 16. What is the primary motivation for
B. (A)B(CD) using Boolean algebra to simplify logic
9. The systematic reduction of logic expressions?
C. AB(CD)
circuits is accomplished by: A. It may make it easier to
D. AB + CD
A. using Boolean algebra understand the overall
4. Derive the Boolean expression for the B. symbolic reduction function of the
logic circuit shown below: C. TTL logic circuit.
D. using a truth table
τµΩ INDIABIX ELECTRONICS PART 2
B. It may reduce the number of B. F = CD + AD 30. Applying the distributive law to the
gates. C. F = BC + AB expression , we get
C. It may reduce the number of D. F = AC + AD ________.
inputs required.
24. Occasionally, a particular logic
D. all of the above A.
expression will be of no consequence in
17. How many gates would be required the operation of a circuit, such as a BCD- B.
to implement the following Boolean to-decimal converter. These result in C.
expression after simplification? XY + X(X ________terms in the K-map and can be
+ Z) + Y(X + Z) treated as either ________ or ________, D.
A. 1 in order to ________ the resulting term. 31. Mapping the SOP expression
B. 2 A. don't care, 1s, 0s, simplify , we get
C. 4 B. spurious, ANDs, ORs, ________.
D. 5 eliminate
C. duplicate, 1s, 0s, verify
18. AC + ABC = AC
D. spurious, 1s, 0s, simplify
A. True
B. False 25. The NAND or NOR gates are referred
to as "universal" gates because either:
19. When are the inputs to a A. can be found in almost all
NAND gate, according to De Morgan's digital circuits
theorem, the output expression could B. can be used to build all the
be: other types of gates
A. X=A+B C. are used in all countries of the
world
B. D. were the first gates to be
C. X = (A)(B) integrated
D.
26. The truth table for the SOP A. (A)
20. Which Boolean algebra property expression has how many B. (B)
allows us to group operands in an input combinations? C. (C)
expression in any order without A. 1 D. (D)
affecting the results of the operation [for B. 2 32. Derive the Boolean expression for
example, A + B = B + A]? C. 4 the logic circuit shown below:
A. associative D. 8
B. commutative
C. Boolean 27. Converting the Boolean expression
D. distributive LM + M(NO + PQ) to SOP form, we get
________.
21. Applying DeMorgan's theorem to the A. LM + MNOPQ A.
expression , we get ___ B. L + MNO + MPQ B.
C. LM + M + NO + MPQ
A. D. LM + MNO + MPQ C.
B. D.
28. A Karnaugh map is a systematic way
C. of reducing which type of expression? 33. Which is the correct logic function for
A. product-of-sums this PAL diagram?
D.
B. exclusive NOR
22. When grouping cells within a K-map, C. sum-of-products
the cells must be combined in groups of D. those with overbars
________.
29. The Boolean expression
A. 2s
B. 1, 2, 4, 8, etc. is logically equivalent
C. 4s to what single gate?
D. 3s A. NAND
B. NOR A.
23. Use Boolean algebra to find the most C. AND
simplified SOP expression for B.
D. OR
F = ABD + CD + ACD + ABC + ABCD. C.
A. F = ABD + ABC + CD
D.
τµΩ INDIABIX ELECTRONICS PART 2
simplifying Boolean B. AB = B + A
34. For the SOP expression , expressions. C. AB = BA
how many 0s are in the truth table's D. AB = A × B
output column? 37. Applying DeMorgan's theorem to the
expression , we get 43. Determine the binary values of the
A. zero ________. variables for which the following
B. 1 standard POS expression is equal to 0.
A.
C. 4
D. 5 B. A. (0 + 1 + 0)(1 + 0 + 1)
C. B. (1 + 1 + 1)(0 + 0 + 0)
35. Mapping the standard SOP
expression D. C. (0 + 0 + 0)(1 + 0 + 1)
D. (1 + 1 + 0)(1 + 0 + 0)
38. Which of the examples below
, we get 44. The expression W(X + YZ) can be
expresses the distributive law of Boolean
algebra? converted to SOP form by applying
which law?
A. (A + B) + C = A + (B + C) A. associative law
B. A(B + C) = AB + AC B. commutative law
C. A + (B + C) = AB + AC C. distributive law
D. A(BC) = (AB) + C D. none of the above

39. Applying DeMorgan's theorem to the 45. The commutative law of addition
expression , we get and multiplication indicates that:
________. A. we can group variables in an
AND or in an OR any way we
A. want
B. B. an expression can be
expanded by multiplying term
C. by term just the same as in
D. ordinary algebra
C. the way we OR or AND two
40. Which of the following is an variables is unimportant
important feature of the sum-of- because the result is the same
products (SOP) form of expression? D. the factoring of Boolean
A. All logic circuits are reduced expressions requires the
to nothing more than multiplication of product
simple AND and OR terms that contain like
gates. variables
B. The delay times are greatly
reduced over other forms. 46. Which of the following combinations
C. No signal must pass through cannot be combined into K-map groups?
more than two gates, not A. corners in the same row
A. (A) including inverters. B. corners in the same column
B. (B) D. The maximum number of gates C. diagonal
C. (C) that any signal must pass D. overlapping combinations
D. (D) through is reduced by a factor
36. Which statement below best of two.
COMBINATIONAL LOGIC
describes a Karnaugh map? 41. An OR gate with schematic "bubbles"
A. A Karnaugh map can be used on its inputs performs the same
ANALYSIS
to replace Boolean rules. functions as a(n)________ gate.
B. The Karnaugh map eliminates A. NOR 1. Referring to the GAL diagram, which
the need for using NAND and B. OR is the correct logic function?
NOR gates. C. NOT
C. Variable complements can be D. NAND
eliminated by using Karnaugh 42. Which of the examples below
maps. expresses the commutative law of
D. Karnaugh maps provide a multiplication?
cookbook approach to A. A+B=B+A
τµΩ INDIABIX ELECTRONICS PART 2
D. None of these

10. The following waveform pattern is


for a(n) ________.

A. 2-input AND gate


A. ̅̅ ̅ ̅ B. 2-input OR gate
A. (A)
B. ̅ ̅̅ ̅ C. Exclusive-OR gate
B. (B)
C. ̅̅ ̅ ̅ D. None of the above
C. (C)
D. ̅̅ ̅ ̅ ̅
D. (D)
11. To implement the expression
2. The output of an exclusive-NOR gate 6. Before an SOP implementation, the ̅ ̅ ̅ , it takes one
is 1. Which input combination is correct? expression ̅ would OR gate and ________.
A. A = 1, B = 0 require a total of how many gates? A. three AND gates and three
B. A = 0, B = 1 A. 1 inverters
C. A = 0, B = 0 B. 2 B. three AND gates and four
D. none of the above C. 4 inverters
D. 5 C. three AND gates
3. The Boolean SOP expression obtained D. one AND gate
from the truth table below is ________. 7. The following waveform pattern is for
a(n) ________. 12. One positive pulse with tw = 75 µs is
applied to one of the inputs of an
exclusive-OR circuit. A second positive
pulse with tw = 15 µs is applied to the
other input beginning 20 µs after the
leading edge of the first pulse. Which
A. 2-input AND gate
statement describes the output in
B. 2-input OR gate
relation to the inputs?
C. Exclusive-OR gate
A. A. The exclusive-OR output is a 20
D. None of the above
B. ̅ ̅ µs pulse followed by a 40 s
C. ̅̅ ̅ pulse, with a separation of 15
8. Implementing the expression
D. None of these µs between the pulses.
̅̅ with NOR logic, B. The exclusive-OR output is a 20
we get: µs pulse followed by a 15 µs
4. The 8-input XOR circuit shown has an
output of Y = 1. Which input pulse, with a separation of 40
combination below (ordered A – H) is µs between the pulses.
correct? C. The exclusive-OR output is a 15
µs pulse followed by a 40 µs
pulse.
D. *The exclusive-OR output is a
20 µs pulse followed by a 15 µs
pulse, followed by a 40 µs
A. (A) pulse.
B. (B) 13. How many AND gates are required to
C. (C) implement the Boolean expression,
D. (D) ̅ ̅ ̅ ?
A. 10111100 A. 1
9. A 4-variable AND-OR-Invert circuit B. 2
B. 10111000
produces a 0 at its Y output. Which C. 3
C. 11100111
combination of inputs is correct? D. 4
D. 00011101 ̅ ̅
A.
5. Implementing the expression AB + ̅̅ ̅̅ 14. How many NOT gates are required to
B.
CDE using NAND logic, we get: ̅ ̅ implement the Boolean expression,
C.
̅ ̅ ?
τµΩ INDIABIX ELECTRONICS PART 2
A. 1 19. Implementing the expression 24. A logic circuit with an output
B. 2 ̅ ̅ using NAND logic, we get: ̅ ̅ consists of ________.
C. 4 A. two AND gates, two OR gates,
D. 5 two inverters
B. three AND gates, two OR gates,
15. The inverter can be produced with one inverter
how many NAND gates? C. two AND gates, one OR gate,
A. 1 two inverters
B. 2 D. two AND gates, one OR gate
C. 3
D. 4
A. (A)
B. (B)
16. A 4-variable AND-OR circuit
C. (C)
MEASUREMENT,
produces a 0 at its Y output. Which CONVERSION AND
D. (D)
combination of inputs is correct?
A. A = 0, B = 0, C = 1, D = 1 CONTROL
20. The following waveform pattern is
B. A = 1, B = 1, C = 0, D = 0
for a(n) ________. 1. What device is similar to an RTD but
C. A = 1, B = 1, C = 1, D = 1
D. A = 1, B = 0, C = 1, D = 0 has a negative temperature coefficient?
A. Strain gauge
17. A 4-variable AND-OR circuit B. Thermistor
produces a 1 at its Y output. Which C. Negative-type RTD
combination of inputs is correct? D. Thermocouple
A. A = 0, B = 0, C = 0, D = 0 2. The resistive change of a strain gauge
A. 2-input AND gate
B. A = 0, B = 1, C = 1, D = 0 B. 2-input OR gate A. is based on the weight placed
C. A = 1, B = 1, C = 0, D = 0 C. Exclusive-OR gate upon it, but can be many
D. A = 1, B = 0, C = 0, D = 0 D. None of the above thousands of ohms
B. is usually no more than 100 Ω
18. Implementing the expression 21. Implementation of the Boolean C. is based on the gauge factor,
̅ ̅ using NAND logic, we get: expression ̅ results but is typically less than an
in ________. ohm
A. three AND gates, one OR gate D. has a positive temperature
B. three AND gates, one NOT coefficient
gate, one OR gate
3. The silicon-controlled rectifier can be
C. three AND gates, one NOT
turned off
gate, three OR gates
A. by a negative gate pulse
D. three AND gates, three OR
B. by forced commutation
gates
C. with the off switch
D. when the breakover voltage is
22. One possible output expression for
exceeded
an AND-OR-Invert circuit having one
AND gate with inputs A, B, and C and 4. The output voltage of a typical
one AND gate with inputs D and E is thermocouple is
________. A. less than 100 mV
A. B. greater than 1 V
B. ̅ ̅ ̅ ̅ ̅ C. Thermocouples vary resistance,
C. ̅ ̅ ̅ ̅ ̅ not voltage.
D. ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ D. None of the above
5. The connections to a thermocouple
23. How many 2-input NOR gates does it A. can produce an unwanted
take to produce a 2-input NAND gate? thermocouple effect, which
A. 1 must be compensated for
B. 2 B. produce an extra desirable
A. (A) C. 3 thermocouple effect
B. (B) D. 4 C. must be protected, since high
C. (C) voltages are present
D. (D)
τµΩ INDIABIX ELECTRONICS PART 2
D. produce an extra desirable A. the minimum current required C. orange, white, red, gold
thermocouple effect and must for turn-off D. orange, green, orange, silver
be protected, since high B. the current required before an
7. What resistor type is found in SIPs and
voltages are present SCR will turn on
DIPs?
C. the amount of current
6. What is the zero-voltage switch used A. metal film
required to maintain
for? B. wirewound
conduction
A. To reduce radiation of high C. metal oxide
D. the gate current required to
frequencies during turn-on of D. thick film
maintain conduction
a high current to a load
8. Ohm's law is not:
B. To control low-voltage circuits 13. What is the moving part of a linear
A. V = IR
C. To provide power to a circuit variable differential transformer?
B. I = V/R
when power is lost
C. R = IV
D. For extremely low-voltage A. Primary
D. R = V/I
applications B. Secondary
C. Diaphragm 9. What are the two major categories
7. Temperature sensing can be achieved D. Core for resistors?
by the use of A. low and high ohmic value
A. thermocouples B. commercial and industrial
B. RTDs RESISTANCE AND POWER C. low and high power value
C. thermistors D. fixed and variable
D. All of the above 1. The resistivity of copper is:
A. 9.9 Ω 10. How many connections does a
8. The purpose of compensation for a B. 10.7 Ω potentiometer have?
thermocouple is C. 16.7 Ω A. 1
A. to decrease temperature D. 17.0 Ω B. 2
sensitivity C. 3
B. to increase voltage output 2. How do fixed resistors usually fail? D. 4
C. to cancel unwanted voltage A. slowly over time
B. by increasing their value 11. What current is flowing in the circuit?
output of a thermocouple
D. used for high-temperature C. by becoming an open circuit
circuits D. by increasing their value and
becoming an open circuit
9. The change in value of an analog
signal during the conversion process 3. With Ohm's law, if voltage increases
produces what is called the A. 288 kA
and resistance stays the same: B. 2 kA
A. current remains the same C. 50 mA
A. quantization error
B. resolution error B. power decreases D. 500 µa
C. Nyquist error C. current increases 12. The six basic forms of energy are:
D. sampling error D. resistance decreases A. light, sun, magnetic, chemical,
10. Which of the following performance electrical, and mechanical
4. Which formula shows a direct
specifications applies to a sample-and- B. electrical, mechanical, light,
proportionality between power and
hold circuit? heat, magnetic, and chemical
voltage?
A. Aperture time C. electrical, mechanical, sun,
A. V = IR
B. Aperture droop heat, chemical, and light
B. P = VI
C. Feedback D. potential, sun, light, chemical,
C. P = IR
D. Acquisition jitter electrical, and mechanical
D. I = V/R
11. RTDs are typically connected with 13. How much energy is stored if 6.24 x
5. With 1 mA of current, what wattage 18
other fixed resistors 10 electrons are stored in 4 volts?
rating should a 470 ohm resistor have?
A. in a pi configuration A. 4 joules
A. 1/4 watt 18
B. in a bridge configuration B. 1.56 x 10 electrons
B. 1/2 watt
C. and variable resistors C. 1.56 coulombs
C. 1 watt 19
D. and capacitors in a filter-type D. 2.496 x 10 electrons
D. 2 watts
circuit 14. With Ohm's law:
6. How is a 3.9 k Ω resistor color-coded?
A. current is inversely
12. Holding current for an SCR is best A. red, white, red, gold
proportional to resistance
described as B. red, green, orange, silver
τµΩ INDIABIX ELECTRONICS PART 2
B. resistance is directly A. scratchy noise A. use the highest possible scale
proportional to voltage B. lack of bass response B. keep test leads short
C. voltage is indirectly C. variable volume C. zero the meter before using
proportional to power D. too much treble response D. remove power from the circuit
D. current is directly proportional
22. A color code of orange, orange, 30. Components designed to oppose the
to resistance orange is for what ohmic value? flow of current are called:
15. Power is defined as: A. 22 kilohms A. insulators
A. the rate at which energy is B. 3300 ohms B. conductors
used C. 44000 ohms C. resistors
B. watts D. 33 kilohms D. heat exchangers
C. energy 23. A conductor's cross-sectional area in 31. How many amps are used by a 100
D. the rate at which energy is circular mils for 1/2 inch is: watt, 120 volt light bulb?
generated A. 1.2 amps
16. What is the most commonly used A. 500 cmils B. 12000 amps
conductor in electronics? B. 100,000 cmils C. 830 mA
A. aluminum C. 1,000,000 cmils D. 12 amps
B. copper D. 500,000,000 cmils
32. The source is 24 volts and the load
C. gold 24. If a variable resistor's resistance resistance is 100 Ω. What is the load
D. silver varies in a nonuniform manner as the current?
17. With Ohm's law, no change in shaft is moved, it is considered to be: A. 2.4 A
resistance means that current and A. linear B. 240 mA
voltage will be: B. defective C. 24 mA
A. directly proportional C. not wirewound D. 2.4 mA
B. unable to produce energy D. tapered
33. Resistors are identified as to wattage
C. the same 25. Power is measured in units of: by:
D. inversely proportional A. joules x charge A. size
18. A potentiometer has how many B. joules/work B. color code
leads? C. joules x voltage C. types of materials
A. 1 D. joules/time D. internal construction
B. 2 26. How many basic types of resistors 34. What type of resistors have a
C. 3 exist? tolerance rating of 5% or greater?
D. 4 A. 1 A. precision
B. 2 B. SIP
19. What is the ratio of 13 to 47 C. 3 C. general-purpose
expressed in percent? D. 4 D. wirewound
A. 2.76%
B. 27.7% 27. With a complex circuit, a supply 35. Resistor tolerance is either printed on
C. 3.60% source senses: the component, or is provided by:
D. 36.1% A. open circuit components A. keyed containers
B. when voltages need to be B. size
20. What happens to current and increased C. color code
resistance if the voltage doubles? C. only a single resistive D. ohmmeter reading
A. Current doubles and resistance connection
36. How many connections does a
doubles. D. when complex currents are
rheostat have?
B. Current doubles and resistance needed
A. 1
is halved. 28. How many ohms of resistance allows B. 2
C. Current remains the same and a current of 720 µA to flow when 3.6 kV C. 3
resistance doubles. is applied? D. 4
A. 200 n Ω
D. Current doubles and 37. What are the parts of a rheostat?
B. 5kΩ
resistance remains the A. wiper and resistor track
C. 200 k Ω
same. B. solenoid and armature
D. 5MΩ
21. One problem with mechanically C. contact and wire wound
variable resistors is noticeable in audio 29. Which is the most important step D. center tape and wiper
circuits as: utilized when measuring resistors?
τµΩ INDIABIX ELECTRONICS PART 2
38. The load resistance increases. How 46. A 22-gauge wire will have a diameter 54. A 33 kΩ resistor with a 20% tolerance
will the load current change? in mils of: checks out as ok with which of the
A. vary A. 10.03 following ohmmeter readings?
B. remain constant B. 22.35 A. 26400 ohms
C. increase C. 45.26 B. 24183 ohms
D. decrease D. 71.96 C. 6600 ohms
D. 39970 ohms
39. What is the power dissipated by a 1.2 47. The word work means that:
2
k Ω resistor with 12 volts across it? A. energy has been transferred 55. For P = V /R, a decrease in resistance
A. 12 W B. it is inversely related to energy should produce:
B. 1.2 W C. no energy has been transferred A. a decrease in power
C. .12 W D. work and energy are not related B. an increase in ohms
D. 12 mW C. an increase in power
48. A good fuse will have:
40. How many joules of energy will a 10 D. a decrease in current
A. zero ohms resistance
W lamp dissipate in one minute?
B. a medium resistance 56. After a lamp is turned on, its filament
A. 10 joules
C. a high resistance resistance will change to become:
B. 60 joules
D. an infinite resistance A. less resistive
C. 600 joules
B. cooler
D. 3600 joules 49. What property does an incandescent
C. brighter
lamp possess?
D. more resistive
41. Which type of test equipment is used A. cold resistance
to measure resistors? B. hot resistance 57. Wirewound resistors are usually used
A. ohmmeter C. ballast resistance in circuits that have:
B. ammeter D. both cold and hot resistance A. high current
C. voltmeter B. negative temperature
50. One advantage of a carbon film
D. watt meter coefficients
resistor over a carbon composition
C. low power
42. Resistance is: resistor is:
D. high voltage
A. the opposition to current flow A. less circuit noise
accompanied by the B. smaller size 58. How is power dissipated in a resistor?
dissipation of heat C. higher wattage A. by resistance
B. symbolized by R, measured in D. poor tolerance B. by voltage
ohms, and directly proportional C. by current
51. If a metallic conductor has a positive
to conductance D. by heat
temperature coefficient of resistance,
C. directly proportional to current
then: 59. Resistance in a circuit is:
and voltage
A. as temperature increases, A. opposition to current
D. represented by the flow of fluid
resistance decreases B. opposition to voltage
in the fluid circuit
B. as current increases, resistance C. the same as current
43. Electrical equipment is protected decreases D. the same as voltage
against excessive current by a(n): C. as voltage increases, current
60. The unit designator for resistance
A. fusible wire link increases
value is the:
B. insulated glass container D. as temperature increases,
A. ampere
C. metal ended coil resistance increases
B. ohm
D. circuit opener
52. What value of a ±5% 1.3 k Ω resistor C. volt
44. If resistance decreases, then current as measured by a digital voltmeter D. watt
will: would be considered within tolerance?
61. One ampere of current flowing
A. decrease A. 1234 Ω
through one ohm of resistance is equal
B. increase B. 1235 Ω
to:
C. remain the same C. 1366 Ω
A. 1 horsepower
D. double D. 1367 Ω
B. 1 Btu
45. A wire with a smaller cross-sectional 53. If a calculator display was "0.00263," C. 1 watt
area will produce: what would this answer be in percent? D. 1 joule
A. less heat A. 0.026%
62. Good insulators:
B. more conductance B. 0.26%
A. have few electrons in their
C. less resistance C. 2.63%
outer shells
D. more heat D. 26.3%
τµΩ INDIABIX ELECTRONICS PART 2
B. have a large dielectric B. 16 ms C. in both directions at the same
strength C. 4 ms time
C. have a small breakdown voltage D. 20 ms D. 50% of the time clockwise and
D. have many electrons in the 50% of the time
8. Test equipment selection enables the
nucleus counterclockwise
technician to both generate signals and:
A. change circuit conditions 15. What does the CRT oscilloscope
ALTERNATING CURRENT B. inject signals display?
C. sense circuit conditions A. voltage and period
VS DIRECT CURRENT
D. change signal frequencies B. current and frequency
C. rms voltage and current
1. What are the two main applications 9. Why is ac current transfer more D. frequency and voltage
for ac? effective than dc current transfer over
A. direct, pulsating long distances? 16. Power companies supply ac, not dc,
B. electric, magnetic A. due to the height of power lines because:
C. power, information B. due to the use of ac generators A. it is easier to transmit ac
D. static, dynamic C. due to step-up and step-down B. there is no longer a need for dc
2. The distance that a signal's energy can transformers reducing I2R C. dc is more dangerous
travel in the time it takes for one cycle to losses D. there are not enough batteries
occur is called the signal's: D. due to very high voltages 17. If a waveform period is determined to
A. amplitude
10. A sine wave reaches maximum be 10 microseconds in duration, what is
B. frequency
positive voltage at: the frequency of the signal?
C. wavelength
A. 90° A. 100 Hz
D. period
B. 0° B. 1000 Hz
3. One oscilloscope selector knob that C. –90° C. 10 kHz
allows the major and minor divisions of D. 360° D. 100 kHz
the graticule to be used to determine a
11. Which percentages of full-amplitude 18. The phase difference between sine
signal amplitude value is called the:
rise time are used for a pulse wave? waves of different frequencies is:
A. time/cm control
A. 0 to 50 percent A. equal to their frequency
B. position control
B. 0 to 100 percent differences
C. intensity control
C. 5 to 95 percent B. the difference in their fixed
D. volts/cm control
D. 10 to 90 percent time displacement
4. If current varies periodically from zero C. the same throughout time
to a maximum, back to zero, and then 12. What is the average value of a 12 V D. constantly changing
repeats, the signal is: peak wave?
A. 3.82 V 19. If a sine wave signal is 100 mV peak-
A. direct
B. 4.24 V to-peak, how many volts would be
B. alternating
C. 7.64 V measured by a voltmeter?
C. pulsating
D. 9.42 V A. 14.14 mV
D. repetitive
B. 35.4 mV
5. What voltage will an ac voltmeter 13. A test equipment item that has the C. 63.7 mV
display? ability to produce either square, D. 70.7 mV
A. rms triangular, or sawtooth waveforms is
called: 20. What term expresses the frequency
B. average
A. a function generator of a rectangular wave?
C. peak
D. peak-to-peak B. a radio frequency generator
C. an audio frequency generator A. Hz
6. What is the peak value of a household D. a frequency meter or counter B. period
appliance that uses a 230 V ac source? C. PRF
A. 163 V 14. The current is flowing in what D. PRT
B. 230 V direction?
21. AC effective voltage is named:
C. 325 V
D. 480 V
A. average
7. What is the waveform period B. peak
difference between the 60 Hz electricity C. peak-to-peak
used in this country and the 50 Hz used A. clockwise D. root mean square
in Europe? B. counterclockwise
A. 3 ms
τµΩ INDIABIX ELECTRONICS PART 2
22. If a voltmeter measures a sine wave D. radio frequency generator 37. A sine wave has:
as 500 mV, what would be its average A. four quadrants
30. Which control should be moved
value? B. two alternations
to display more cycles of a signal on an
A. 159.0 mV C. one period
oscilloscope?
B. 318.5 mV D. all of the above
A. horizontal position to left or
C. 353.5 mV
right 38. What is the peak-to peak voltage of a
D. 451.0 mv
B. volts/cm to a smaller number 56 Vrms ac voltage?
23. One adjustable knob on the C. vertical position to top or A. 158 V
oscilloscope that allows the trace to be bottom B. 164 V
aligned with a reference graticule is D. time/cm to a higher setting C. 82 V
called the: D. 79 V
31. What is the name of a device that
A. position control
converts sound waves to electrical 39. One oscilloscope selector knob that
B. focus control
waves? allows the major and minor divisions of
C. intensity control
A. an amplifier the graticule to be used to determine a
D. volts/cm control
B. an antenna waveform period is called a:
24. Signal comparisons may be most C. a filter
easily seen when using which item of D. a microphone A. focus control
test equipment? B. time/cm control
32. If the frequency of a radio wave is
A. spectrum analyzer C. intensity control
increased, then its wavelength will:
B. multimeter D. volts/cm control
A. increase
C. function generator
B. decrease 40. What is the period of a 16 MHz sine
D. dual trace oscilloscope
C. remain the same wave?
25. The magnitude that an alternation D. cannot tell A. 196 ns
varies from zero is called its: B. 62.5 ns
33. What is the rms voltage value of an
A. altitude C. 31.25 ns
ac signal whose peak oscilloscope
B. amplitude D. 19.9 ns
display uses 3 major divisions above the
C. attitude
zero setting? (V/cm = 5)
D. polarity
A. 5.3 V SEMICONDUCTOR
26. The power that is distributed from a B. 10.6 V
power plant to your home is: C. 15.0 V PRINCIPLE
A. high voltage to high voltage D. 21.2 V
B. low voltage to high voltage 1. Intrinsic semiconductor material is
34. What is the peak-to-peak current
C. high voltage to low voltage characterized by a valence shell of how
value when an ammeter measures a 20
D. low voltage to low voltage many electrons?
mA value?
27. A rectangular wave that has a duty A. 14 mA A. 1
cycle of 50 percent could be called a: B. 28 mA B. 2
A. c wave C. 40 mA C. 4
B. sawtooth wave D. 57 mA D. 6
C. square wave 2. Ionization within a P-N junction
35. How long would it take to transmit
D. triangle wave causes a layer on each side of the barrier
an electromagnetic wave to a receiving
28. A triangle wave consists of antenna 1,000 miles away? called the:
repeating: A. 5.38 ms A. junction
A. positive ramps only B. 10.8 ms B. depletion region
B. negative ramps only C. 53.8 ms C. barrier voltage
C. positive and negative ramps of D. 108 ms D. forward voltage
equal value
36. What is the waveform period of a 3. What is the most significant
D. positive and negative ramps of
square wave signal that horizontally development in electronics since World
unequal value
covers 3 major divisions per cycle? War II?
29. What is the name of a device used to (time/cm = 50 ms) A. the development of color TV
directly measure the frequency of a A. 50 ms B. the development of the diode
periodic wave? B. 100 ms C. the development of the
A. oscilloscope C. 150 ms transistor
B. frequency meter or counter D. 200 ms D. the development of the
C. audio frequency generator TRIAC
τµΩ INDIABIX ELECTRONICS PART 2
A. magnetism 20. Electron pair bonding occurs when
4. What causes the depletion region? B. temperature atoms:
A. doping C. pressure A. lack electrons
B. diffusion D. all of the above B. share holes
C. barrier potential C. lack holes
D. ions 13. When an electron jumps from the D. share electrons
valence shell to the conduction band, it
5. What is an energy gap? 21. How many valence electrons are in
leaves a gap. What is this gap called?
A. the space between two orbital every semiconductor material?
A. energy gap
shells A. 1
B. hole
B. the energy equal to the energy B. 2
C. electron-hole pair
acquired by an electron passing C. 3
D. recombination
a 1 V electric field D. 4
C. the energy band in which 14. Forward bias of a silicon P-N junction
22. What is a type of doping material?
electrons can move freely will produce a barrier voltage of
A. extrinsic semiconductor
D. an energy level at which an approximately how many volts?
material
electron can exist A. 0.2
B. pentavalent material
B. 0.3
6. Silicon atoms combine into an orderly C. n-type semiconductor
C. 0.7
pattern called a: D. majority carriers
D. 0.8
A. covalent bond
23. Minority carriers are many times
B. crystal 15. Which semiconductor material is
activated by:
C. semiconductor made from coal ash?
A. heat
D. valence orbit A. germanium
B. pressure
B. silicon
7. In "n" type material, majority carriers C. dopants
C. tin
would be: D. forward bias
D. carbon
A. holes
24. What is the voltage across R1 if the
B. dopants 16. When and who discovered that more
P-N junction is made of silicon?
C. slower than one transistor could be constructed
D. electrons on a single piece of semiconductor
material:
8. Elements with 1, 2, or 3 valence
A. 1949, William Schockley
electrons usually make excellent:
B. 1955, Walter Bratten
A. conductors
C. 1959, Robert Noyce
B. semiconductors
D. 1960, John Bardeen A. 12 V
C. insulators
D. neutral 17. When is a P-N junction formed? B. 11.7 V
A. in a depletion region C. 11.3 V
9. A commonly used pentavalent D. 0V
B. in a large reverse biased region
material is:
C. the point at which two 25. If conductance increases as
A. arsenic
opposite doped temperature increases, this is known as
B. boron
materials come together a:
C. gallium
D. whenever there is a forward A. positive coefficient
D. neon
voltage drop B. negative current flow
10. Which material may also be C. negative coefficient
18. A P-N junction mimics a closed
considered a semiconductor element? D. positive resistance
switch when it:
A. carbon
A. has a low junction resistance 26. Which of the following cannot
B. ceramic
B. is reverse biased actually move?
C. mica
C. cannot overcome its barrier
D. argon
voltage A. majority carriers
11. In "p" type material, minority carriers D. has a wide depletion region B. ions
would be: C. holes
19. Solid state devices were first
A. holes D. free electrons
manufactured during:
B. dopants
A. World War 2 27. What electrical characteristic of
C. slower
B. 1904 intrinsic semiconductor material is
D. electrons
C. 1907 controlled by the addition of impurities?
12. What can a semiconductor sense? D. 1960 A. conductivity
τµΩ INDIABIX ELECTRONICS PART 2
B. resistance D. a Q point that is stable and C. IB/IE
C. power easily varies with changes in the D. IE/IB
D. all of the above transistor’s current gain
16. A collector characteristic curve is a
8. To operate properly, a transistor's graph showing:
BIPOLAR JUNTION base-emitter junction must be forward A. emitter current (IE) versus
TRANSISTORS (BJT) biased with reverse bias applied to which collector-emitter voltage (VCE)
junction? with (VBB) base bias voltage
1. When transistors are used in digital A. collector-emitter held constant
circuits they usually operate in the: B. base-collector B. collector current (IC) versus
A. active region C. base-emitter collector-emitter voltage (VCE)
B. breakdown region D. collector-base with (VBB) base bias voltage
C. saturation and cutoff regions held constant
9. The ends of a load line drawn on a
D. linear region C. collector current (IC) versus
family of curves determine:
collector-emitter voltage (VC)
2. Three different Q points are shown on A. saturation and cutoff
with (VBB) base bias voltage
a dc load line. The upper Q point B. the operating point
held constant
represents the: C. the power curve
D. collector current (IC) versus
A. minimum current gain D. the amplification factor
collector-emitter voltage (VCC)
B. intermediate current gain 10. If VCC = +18 V, voltage-divider with (VBB) base bias voltage
C. maximum current gain resistor R1 is 4.7 kΩ, and R2 is 1500 Ω, held constant
D. cutoff point what is the base bias voltage?
17. With low-power transistor packages,
3. A transistor has a of 250 and a A. 8.70 V
the base terminal is usually the:
base current, IB, of 20 µA. The collector B. 4.35 V
A. tab end
current, IC, equals: C. 2.90 V
B. middle
A. 500 µA D. 0.7 V
C. right end
B. 5 mA 11. The C-B configuration is used to D. stud mount
C. 50 mA provide which type of gain?
D. 5A 18. When a silicon diode is forward
A. voltage
biased, what is VBE for a C-E
4. A current ratio of IC/IE is usually less B. current
configuration?
than one and is called: C. resistance
A. voltage-divider bias
A. beta D. power
B. 0.4 V
B. theta 12. The Q point on a load line may be C. 0.7 V
C. alpha used to determine: D. emitter voltage
D. omega A. VC
19. What is the current gain for a
5. With the positive probe on an NPN B. VCC
common-base configuration where IE =
base, an ohmmeter reading between the C. VB
4.2 mA and IC = 4.0 mA?
other transistor terminals should be: D. IC
A. 16.80
A. open 13. A transistor may be used as a B. 1.05
B. infinite switching device or as a: C. 0.20
C. low resistance A. fixed resistor D. 0.95
D. high resistance B. tuning device
20. With a PNP circuit, the most positive
6. In a C-E configuration, an emitter C. rectifier
voltage is probably:
resistor is used for: D. variable resistor
A. ground
A. stabilization 14. If an input signal ranges from 20–40 B. VC
B. ac signal bypass µA (microamps), with an output signal C. VBE
C. collector bias ranging from .5–1.5 mA (milliamps), D. VCC
D. higher gain what is the ac beta?
21. If a 2 mV signal produces a 2 V
7. Voltage-divider bias provides: A. 0.05
output, what is the voltage gain?
A. an unstable Q point B. 20
A. 0.001
B. a stable Q point C. 50
B. 0.004
C. a Q point that easily varies with D. 500
C. 100
changes in the transistor's 15. Which is beta's current ratio? D. 1000
current gain A. IC/IB
22. The symbol hfe is the same as:
B. IC/IE
A.
τµΩ INDIABIX ELECTRONICS PART 2
B. A. off the load line A. gate
C. hi-fi B. nowhere B. block
D. C. up C. drain
D. down D. heat sink
23. Most of the electrons in the base of
an NPN transistor flow: 30. Which is the higher gain provided by 6. When testing an n-channel D-
A. out of the base lead a C-E configuration? MOSFET, resistance G to D = ∞,
B. into the collector A. voltage resistance G to S =∞ , resistance D to SS
C. into the emitter B. current = ∞ and 500 Ω, depending on the
D. into the base supply C. resistance polarity of the ohmmeter, and resistance
D. power D to S = 500 Ω. What is wrong?
24. In a transistor, collector current is
A. short D to S
controlled by: 31. What is the collector current for a C-E
B. open G to D
A. collector voltage configuration with a beta of 100 and a
C. open D to SS
B. base current base current of 30 µA?
D. nothing
C. collector resistance A. 30 µA
D. all of the above B. .3 µA 7. In the constant-current region, how
C. 3 mA will the IDS change in an n-channel JFET?
25. Total emitter current is: D. 3 MA A. As VGS decreases ID decreases.
A. IE – IC B. As VGS increases ID increases.
B. IC + IE C. As VGS decreases ID remains
FIELD EFFECT
C. IB + IC constant.
D. IB – IC TRANSISTORS (FET) D. As VGS increases ID remains
constant
26. Often a common-collector will be 1. Junction Field Effect Transistors
(JFET) contain how many diodes? 8. A MOSFET has how many terminals?
the last stage before the load; the main
A. 4 A. 2 or 3
function(s) of this stage is to:
B. 3 B. 3
A. provide voltage gain
C. 2 C. 4
B. provide phase inversion
D. 1 D. 3 or 4
C. provide a high-frequency path
to improve the frequency 2. When an input delta of 2 V produces a 9. IDSS can be defined as:
response transconductance of 1.5 mS, what is the A. the minimum possible drain
D. buffer the voltage amplifiers drain current delta? current
from the low-resistance load A. 666 mA B. the maximum possible current
and provide impedance B. 3 mA with VGS held at –4 V
matching for maximum power C. 0.75 mA C. the maximum possible current
transfer D. 0.5 mA with VGS held at 0 V
D. the maximum drain current
27. For a C-C configuration to operate 3. When not in use, MOSFET pins are with the source shorted
properly, the collector-base junction
kept at the same potential through the
should be reverse biased, while forward 10. What is the input impedance of a
bias should be applied to which use of: common-gate configured JFET?
junction? A. shipping foil A. very low
A. collector-emitter B. nonconductive foam B. low
B. base-emitter C. conductive foam C. high
C. collector-base D. a wrist strap D. very high
D. cathode-anode
11. JFET terminal "legs" are connections
4. D-MOSFETs are sometimes used in
28. The input/output relationship of the to the drain, the gate, and the:
series to construct a cascode high-
common-collector and common-base A. channel
frequency amplifier to overcome the loss
amplifiers is: B. source
of:
C. substrate
A. low output impedance
A. 270 degrees D. cathode
B. capacitive reactance
B. 180 degrees
C. high input impedance 12. A very simple bias for a D-MOSFET is
C. 90 degrees
D. inductive reactance called:
D. 0 degrees
A. self biasing
29. If a transistor operates at the middle 5. A "U" shaped, opposite-polarity
B. gate biasing
of the dc load line, a decrease in the material built near a JFET-channel
C. zero biasing
current gain will move the Q point: center is called the:
D. voltage-divider biasing
τµΩ INDIABIX ELECTRONICS PART 2
A. breakdown region
13. With the E-MOSFET, when gate
B. depletion region
input voltage is zero, drain current is:
C. saturation point
A. at saturation
D. pinch-off region
B. zero
C. IDSS 22. With a JFET, a ratio of output current
D. widening the channel change against an input voltage change
is called:
14. With a 30-volt VDD, and an 8-kilohm
A. transconductance
drain resistor, what is the E-MOSFET Q
B. siemens
point voltage, with ID = 3 mA?
C. resistivity
A. 6V
D. gain A. 5.2 V
B. 10 V
B. 4.2 V
C. 24 V 23. Which type of JFET bias requires a
C. 3.2 V
D. 30 V negative supply voltage?
D. 2.2 V
A. feedback
15. When an input signal reduces the
B. source 29. The overall input capacitance of a
channel size, the process is called:
C. gate dual-gate D-MOSFET is lower because
A. enhancement
D. voltage divider the devices are usually connected:
B. substrate connecting
A. in parallel
C. gate charge 24. How will a D-MOSFET input
B. with separate insulation
D. depletion impedance change with signal
C. with separate inputs
frequency?
16. Which JFET configuration would D. in series
A. As frequency increases input
connect a high-resistance signal source
impedance increases. 30. What is the transconductance of an
to a low-resistance load?
B. As frequency increases input FET when ∆ID = 1 mA and ∆VGS = 1 V?
A. source follower
impedance is constant. A. 1 kS
B. common-source
C. As frequency decreases input B. 1 mS
C. common-drain
impedance increases. C. 1kΩ
D. common-gate
D. As frequency decreases input D. 1mΩ
17. How will electrons flow through a p- impedance is constant.
31. Which component is considered to
channel JFET?
25. The type of bias most often used be an "OFF" device?
A. from source to drain
with E-MOSFET circuits is: A. transistor
B. from source to gate
A. constant current B. JFET
C. from drain to gate
B. drain-feedback C. D-MOSFET
D. from drain to source
C. voltage-divider D. E-MOSFET
18. When VGS = 0 V, a JFET is: D. zero biasing
32. In an n-channel JFET, what will
A. saturated
26. The transconductance curve of a happen at the pinch-off voltage?
B. an analog device
JFET is a graph of: A. the value of VDS at which
C. an open switch
A. IS versus VDS further increases in VDS will
D. cut off
B. IC versus VCE cause no further increase in ID
19. When applied input voltage varies C. ID versus VGS B. the value of VGS at which further
the resistance of a channel, the result is D. ID × RDS decreases in VGS will cause no
called: further increases in ID
27. The common-source JFET amplifier
A. saturization C. the value of VDG at which
has:
B. polarization further decreases in VDG will
A. a very high input impedance
C. cutoff cause no further increases in ID
and a relatively low voltage
D. field effect D. the value of VDS at which further
gain
increases in VGS will cause no
20. When is a vertical channel E- B. a high input impedance and a
further increases in ID
MOSFET used? very high voltage gain
A. for high frequencies C. a high input impedance and a
voltage gain less than 1 THYRISTORS AND
B. for high voltages
C. for high currents
D. no voltage gain TRANSDUCERS
D. for high resistances 28. Using voltage-divider biasing, what
is the voltage at the gate VGS? 1. A TRIAC:
21. When the JFET is no longer able to A. can trigger only on positive gate
control the current, this point is called voltages
the:
τµΩ INDIABIX ELECTRONICS PART 2
B. can trigger only on negative D. one emitter lead and two base A. maximum forward current
gate voltages leads B. maximum forward gate current
C. cannot be triggered with gate C. holding current
7. The only way to close an SCR is with:
voltages D. reverse gate leakage current
D. can be triggered by either a
A. a trigger input applied to the 12. Once a DIAC is conducting, the only
positive or a negative gate
gate way to turn it off is with:
voltage
B. forward breakover voltage A. a positive gate voltage
2. When checking a good SCR or TRIAC C. low-current dropout B. a negative gate voltage
with an ohmmeter it will: D. valley voltage C. low-current dropout
A. show high resistance in both D. breakover
8. What is an SCR?
directions
A. a PNPN thyristor with 3 13. Which is the TRIAC?
B. show low resistance with
terminals
positive on anode and negative
B. a PNPN thyristor with 4
on cathode, and high resistance
terminals
when reversed
C. a PNP thyristor with 3 terminals A.
C. show high resistance with
D. an NPN thyristor with 3
negative on anode and positive
terminals
on cathode, and low resistance
when reversed 9. What type of application would use a
B.
D. show low resistance in both photovoltaic cell?
directions A. an automobile horn
B. a TI 92 calculator
3. What does a hall effect sensor sense? C.
C. a magnetic field detector
A. temperature D. a remote power source
B. moisture
10. Which is the seven-segment display?
C. magnetic fields
D. pressure D.
14. The DIAC is a:
4. What causes the piezoelectric effect?
A. transistor
A. heat or dissimilar metals
B. unidirectional device
B. pressure on a crystal
C. three-layer device
C. water running on iron
D. bidirectional device
D. a magnetic field
15. What type of application would use
5. Which is the DIAC?
an injection laser diode?
A. A. a 10BASE-T Ethernet
B. a liquid crystal display
C. a fiber optic transmission line
A. D. a good flashlight
16. The PUT (programmable unijunction
B.
transistor) is actually a type of:
B. A. UJT thyristor
B. FET device
C. TRIAC
C. D. SCR
C.
17. A transducer's function is to:
A. transmit electrical energy
B. convert energy
D. C. produce mechanical energy
6. A UJT has: D. prevent current flow
D.
A. two base leads 11. The smallest amount of current that
B. one emitter lead the cathode-anode can have, and still
C. two emitter leads and one base sustain conduction of an SCR is called
lead the: