Alternative MOS Transistor

Structures and Substrate Materials

Indo German Winter Academy-2007

Krishna Teja Malladi

IIT Kanpur
Contents
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
Introduction
„ New requirements of electronics industry for faster, smaller, low
power and reliable ICs
„ Moore’s Law-Scaling down transistor lateral dimensions-rock
bottom?
„ Options:
‰ High performance, low
operating power circuit
‰ design
‰ Alternative transistor
structures and new
materials
MOS Scaling Constraints & Alternatives
„ Fundamental physics constraints on MOSFET:
‰ Quantum-mechanical tunneling of carriers via the thin gate oxide
‰ From source to drain, and from drain to the body
‰ Short Channel Effects (SCE) /Finite subthreshold slope –biggest
problem
„ DIBL (Halo/Pocket Implants)
„ Hot Carriers (Lightly Doped Drain)
„ Punch through (High Doping/ Buffer junctions)
„ Vt roll off
„ S-D series resistance

„ Manufacturing issues:
‰ Lithography constraints
‰ Control of the density and location of dopant atoms in the channel, S/D
„ Alternative paths to maintain Moore’s Law
„ New transistor structures like SOI, SON, FinFETs, Vertical
„ New substrate materials like Ge, SiGe, Strained Silicon
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
Silicon on Insulator (SOI)
„ MOSFET with a Buried Oxide (BOX)
„ Better lateral isolation - no CMOS Latchup
„ Lesser Csb, Cdb due to elimination of bulk junction (Frequency response)
„ Body couples to Gate - High Ion/Ioff – Dynamic MOSFET
„ Reduced junction leakage
„ Better short channel effects
„ 3D integration possible
„ Faster speeds - 20-50%
„ Simpler fabrication process - number of masking steps reduced by 30%
Partially Depleted (PD) SOI
ƒ Body thicker than channel depletion width
ƒ Floating body voltage
ƒ Kink effect changing Vt (Charge Accumulation)
ƒ Similar to bulk CMOS
ƒ Problematic SCE
Fully Depleted (FD) SOI
„ Body thinner than channel depletion width
„ No kink effect
„ Lesser SCE
„ No floating body
„ Thin body makes this very hard to manufacture
„ Self heating and early breakdown
SOI Problems

„ Not being actively used in the current day

„ Substrate costs
„ Low thermal conductivity (buried oxide) - heating problem
„ Floating body electrical effects
SOI Fabrication

ƒ SOI materials/technologies for fabrication:

‰ SOS (Silicon-On-Sapphire)

‰ SIMOX (Separation by IMplantation of OXygen)

‰ ZMR SOI (Zone Melting and Recrystallization)

‰ WB (Wafer Bonding) or BESOI (Bond and Etch back)

‰ UNIBOND (Smart Cut technology)

 SIMOX (Separation by IMplantation of
OXygen)
„ Si substrate
„ O2 implantation
„ Annealing at 1300°C (problematic - capping layer to avoid Si evaporation)
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon and SiGe
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
Silicon on Nothing (SON)
„ Buried oxide only under gate and spacers
„ Air tunnel between gate oxide and substrate
„ Ultra-thin silicon: 5-20 nm & thin buried dielectric: 10-30 nm
„ Extremely shallow and highly doped extensions
„ Highly doped drain (HDD) junctions deep-smaller junction surface -
less leakage and parasitics
SON Fabrication
Selective etching buried SiGe layer
Key features

„ High Ion/Ioff
„ Ideal sub threshold slope (~65mV/dec)
„ Suppression of SCE and DIBL due to:
‰ ultra-thin silicon: 5-20 nm
‰ thin buried dielectric: 10-30 nm
„ Low S/D series resistance
„ Lower heat dissipation
„ Additional steps (epitaxy)
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon and SiGe
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
DGFET-A Multi Gated Approach
„ Multi gates to suppress drain effects (DIBL, subthreshold slope)
„ Lower doped channel possible (mobility, drain to body leakage)
„ SCE series resistance paradox
„ Issue of gate allignment (parasitics)
„ Si planar technology not compatible
FinFET Basics
„ It is a 3D device structure
„ The Si fin forms the channel
„ Gate wraps around the fin to form
very small channel
„ The Si fin has insulator on the top
and gate on either sides
„ Current flows parallel to the device
surface
Advantages
„ Short channel effects reduced. Body need not be doped heavily
„ Very low leakage current
„ Raised S/D contacts minimize series resistance
„ Flexibility of using multiple fins for better performance
„ Compatibility with current manufacturing processes
„ Scalability to sub-10 nm
Challenges
„ Fabrication
‰ Formation of thin Si fins (for DIBL supression)

‰ Limitations of lithography

„ S/D resistance
„ Simulators needed to model 3D quantum effects
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
Why Vertical Transistors?
„ High throughput lithography (e-, ion, optical) for sub 50m very
challenging
„ Vertical MOSFETs offer lithography-independent channel length while
reducing the transistor area
„ Feasibility to have double gates - higher Ion, lesser DIBL
(made better with channel thinning)
„ Higher drive current per unit area
„ SOI like parasitic capacitances
 Principles of Vertical Transistors
„ Channel enclosed by double gate and channel current along both surfaces
„ The thickness of a deposited film to precisely define the gate length
„ Silicon pillar grown through a multilayer sandwich
„ The center layer is removed and replaced by the gate
„ Upper and lower layers provide dopants for the S/D extensions
„ Self-aligned source/drain extensions
Salient Features
„ Higher density (4X or greater)
„ Higher Ion / lower subthreshold slope / lesser SCE
„ Shorter L (70 -50 %) ~ 10 nm
„ 3D Integration by stacking
„ Manufacture with existing methods, materials and lithography
„ Self-aligned S/D extensions (parasitics)
„ Replacement-gate enables alternative gate stacks
Performance Improvement over Planar
Problems

„ High overlap capacitance in older vertical MOSFETS

„ Risk due to layout and process changes in VRG
„ Epitaxially grown channels complicate integration
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
Importance
„ Channel doping increasing to contain SCE, control Vt
„ Increase the channel doping degrades mobility by introducing more
charged impurity scattering sites
„ High-K gate dielectric for control of gate leakage also degrades
channel mobility
„ MOSFET drive current also depends on the mobility of charge
carriers in the channel of the device
„ Mobility enhancement in the channel can offset the negative aspects
of managing SCE and gate leakage
 Surface and Channel orientation
„ Exploitation of the mobility anisotropy of Si to improve on the mobility
and current drive capabilities of Si
„ Si substrate’s wafer orientation decides carrier mobility (effective mass)
„ Electron mobility highest for a (100) surface with a <110> channel
„ Hole mobility highest for (110) surface with a <110> channel
„ Hybrid substrate configuration proposed to allow for the ultimate mobility
configuration for each carrier
Surface and Channel Orientation
Hybrid Orientation Technology (HOT)
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
Strained Silicon Engineering
„ Channel doping increasing for SCE affecting mobility
„ Improve mobility by straining or stretching Si crystal lattice
„ Ease of fabrication over high mobility Ge, GaAs, INGaAs, InP
„ Biaxial tensile stress- 6 fold degeneracy lifted
„ Thin layer of epitaxial silicon on a material with a slightly larger
lattice constant, such as relaxed SiGe (SixGe1-x)
Performance Enhancement
Growth of SiGe layer by
step grade approach -
by UHVCVD
Critical Review
„ Advantages:
‰ Higher carrier mobility

‰ Increased Ion/Ioff ratio between 20-30% (due to high mobility)

„ Problems
‰ Processing of strained layers

‰ Lesser Band gap-higher leakage current

‰ Lower thermal conduction of SiGe-channel heat-up

‰ Material defects
SOI with Strained Silicon

„ Benefits of SOI with enhanced mobility (reduced parasitics, scalable

channel length, dynamic floating body effect )
„ Strained Si on a relaxed SiGe layer on Insulator (SGOI)
„ Wafer bonding, layer transfer, Oxygen implantation (SIMOX)
„ Similar mobility enhancements
for p, n MOSFETs
„ Combine orientation dependence,
strained silicon, SOI for better devices
„ SGOI grown on <110> Si surface by SIMOX
process offers excellent features
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon and SiGe
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
Background: Advantages of Ge

Ge Si

μn (cm2/V·s) 3900 1500

μp (cm2/V·s) 1900 450
Eg (eV) 0.66 1.12

„ Bulk Ge has higher electron (2.5×) and hole (4×) mobility

than Si
„ Compatible with high-κ gate dielectrics
 Disadvantages and Performance
„ Native GeO2 cannot be used as gate dielectric
‰ Thermally desorbs above 420°C

‰ Soluble in water

„ Requires surface passivation for good interface with high-κ

dielectrics
„ Smaller energy bandgap
„ Increased subthreshold leakage current
„ Favorable only to p-channel MOSFET
Device and Manufacturing Issues
„ GeOxNy best known dielectric for Ge channel
„ Metal gate electrode instead of poly Si (low MP of Ge)
„ Diffusion enhanced for Boron & suppresses for As, P, Sb
„ 3 embodiments of Ge substrate technology:
‰ Bulk Ge substrates

‰ Ge layers transferred to oxidized Si handle wafers

(Ge-on-insulator)
‰ Epitaxial deposition of Ge thin films on Si substrates

ƒ Bulk Ge substrates grown via the Czochralski method-difficult to

fabricate (Lower mechanical strength of Ge)
ƒ Epitaxial Ge technology promising for strained Ge channels
Ge on Si Fabrication
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon and SiGe
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
Carbon Nanotubes FETs (CNFETs)
„ Carbon nanotube based channel
„ Exhibit higher mobility, minimal mobility degradation when
integrated with high-k dielectrics, adjustable bandgap, and low
contact resistance
„ Atomically smooth surfaces - reduced electronic states at the
dielectric interface-ballistic transport and higher on-currents than Si
„ Precise modeling of carrier transport, SCE still in research
„ Fabrication challenges - making contacts, lithography
III-V Compounds
„ III-V based compounds as substrate materials
„ High speed, high frequency, lesser loss
„ GaAs, InSb, GaN
„ Problem of gate dielectrics (Ga2O3)
„ Problem of integration on Si
„ Introduction
„ Silicon on Insulator (SOI)
„ Silicon on Nothing (SON)
„ Multiple-gate or Fin FETs
„ Vertical Transistors
„ Orientation Dependent Mobility
„ Strained Silicon and SiGe
„ Ge Channel
„ Other Alternatives
„ Conclusions & Future Outlook
Future Outlook
„ To endure Moore’s law SCE have to be countered
„ Combination of discussed alternatives
„ Fundamental - optimize each of gate stack, S/D, channel and MOS
Structure
„ Strained FinFET technology
„ Single electron transistor
„ Quantum dots
„ Resonant Tunneling Diodes
„ Carbon nano tubes
„ DNA computing
Thank You!