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6, JUNE 2017 779

AlGaN/GaN MOS-HEMT Device Fabricated

Using a High Quality PECVD
Passivation Process
Ahmed Chakroun, Abdelatif Jaouad, Ali Soltani, Osvaldo Arenas, Vincent Aimez,
Richard Arès, and Hassan Maher

Abstract — In this letter, an AlGaN/GaN MOS-HEMT was challenge, as the device performance is very sensitive to the
demonstrated using a 5-nm-thick SiOx dielectric layer dielectric/semiconductor interface quality. The interface state
deposited by plasma enhanced chemical vapor deposi- density (Dit ), typically reported for MOS-HEMTs devices,
tion (PECVD) as a gate insulator. The fabricated device is in the range of 1012 -1013 eV−1 · cm−2 [1]–[7], which
exhibits a maximum IDS current of 570 mA/mm at could lead to threshold voltage (VTH ) instability [5], [6], large
VGS =+ 3 V, an ON-state resistance (Rbioscon ) of 7.3 · mm,
hysteresis [2]–[7] and significant current collapse [9].
a maximum transconductance peak of 180 mS/mm, and a
gate leakage current below 1 nA/mm at a gate voltage of In this work we report on the achievement of extremely
+/− 3 V. Moreover, a very low pinchoff voltage (Vp ) shift low hysteresis on a MOS-HEMT device fabricated using
was observed during the IDS –VGS hysteresis measurements an improved gate passivation process. It is based on the
giving an estimated interface state density (Dit ) as low as optimized chemical pre-treatment and the Plasma Enhanced
3.9 × 1011 cm−2 eV−1 . These results demonstrate the high Chemical Vapor Deposition (PECVD) technique previously
quality of the SiOx /AlGaN interface and the efficiency of the reported in [13]. The fabricated 1.5 μm gate length device,
passivation process. To the best of our knowledge, this is exhibits stable characteristics, with a maximum IDS current
the lowest reported Dit on an AlGaN/GaN MOS-HEMT device of 570 mA/mm, a gm peak of 180 mS/mm, a maximum
using a PECVD deposition technique. hysteresis of 113 mV and a gate leakage current below
Index Terms — Gallium nitride, HEMTs, MOSHFETs, 1 nA/mm, leading to an ION /IOFF ratio of about 109. Based
power transistors, interface states, hysteresis. on the hysteresis measurements, the extracted Dit is as low as
3.9 × 1011 cm−2 eV−1 . These values showcase the efficiency
I. I NTRODUCTION of the improved passivation process and the high quality of
the PECVD-SiOx /AlGaN interface.
T HANKS to its superior fundamental properties,
Gallium Nitride (GaN) has received extensive
attention for high power and high frequency applications.
AlGaN/GaN High Electron Mobility Transistors (HEMTs) AlGaN/GaN MOS-HEMT devices were fabricated on com-
have demonstrated tremendous potential due to their high mercial HEMT wafers (supplied by EpiGaN) grown by Metal-
sheet carrier density and two-dimensional electron gas (2DEG) Organic Chemical Vapor Deposition (MOCVD) on Si (111)
mobility. Standard AlGaN/GaN HEMT structures have a substrates. The epitaxial structure consists of a 1.8 μm thick
negative threshold voltage (VTH ), producing a “normally-on” Al0.18 Ga0.82 N back-barrier layer, a 150 nm thick undoped
operation mode. One of the major challenges for GaN-HEMTs GaN channel layer and a thin 4 nm Al0.45 Ga0.55 N top barrier
power devices is the achievement of an enhancement-mode layer. The epitaxial structure was capped with a 50 nm thick
device (normally-off), enabling simpler drive circuitry and in-situ SiN layer. A sheet carrier density of 1.08 ×
safer operation [1]. Since the gate is forward-biased, a Metal- 1013 cm−2 and an electron mobility of 1810 cm2 /V· s were
Oxide-Semiconductor (MOS) gate structure is required to obtained by Hall effect measurements.
reduce the gate leakage current [2]–[9], with the corresponding The 50 nm thick, in-situ dielectric layer was dry-etched
improvement of the device breakdown voltage [10]. However, before the e-beam evaporation of the (Ti/Al/Ni/Au) ohmic con-
the insertion of a gate dielectric layer adds another great tact. Rapid thermal annealing was then performed at 875 °C
for 30 sec in an N2 ambient. The typical contact resistance,
Manuscript received March 23, 2017; revised March 29, 2017 and obtained by transmission line measurements (TLM), was
April 12, 2017; accepted April 16, 2017. Date of publication April 24, 0.35 · mm. Device isolation was achieved by nitrogen ion
2017; date of current version May 22, 2017. This work was supported implantation. For the gate electrode, the 50 nm SiN cap layer
in part by the Natural Sciences and Engineering Research Council of was first etched using a very low power SF6 -based plasma
Canada, in part by le Regroupement Québécois sur les Matériaux de
Pointe, and in part by NanoQuébec. The review of this letter was arranged (5 W with a DC-bias of 36 V). The wafer was then cleaned
by Editor D.-H. Kim. and annealed at 420 °C for 20 min under an N2 ambient to
The authors are with the Laboratoire Nanotechnologies Nanosys- desorb the remaining fluorine ions at the AlGaN surface [11].
tèmes, CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Tech- Due to the extremely thin AlGaN barrier (4 nm), the removal
nologique, Université de Sherbrooke, Sherbrooke, QC J1K OA5, Canada
of the SiN (in-situ) underneath the gate electrode partially
Color versions of one or more of the figures in this letter are available depletes the 2DEG channel [12]. Prior to the gate dielectric
online at layer deposition, the sample was treated using a KOH solution,
Digital Object Identifier 10.1109/LED.2017.2696946 followed by an HCl immersion for 2 min. To avoid AlGaN
0741-3106 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See for more information.

Fig. 1. (a) Schematics and (b) SEM image of the fabricated MOS-HEMT

surface recontamination, special precautions were taken during

surface cleaning process and samples were transferred into
the PECVD deposition chamber immediately following the Fig. 2. DC output IDS -VDS characteristic for the fabricated MOS-HEMT
device. VGS stepping from −1 V to +3 V with +0.5 V step.
chemical pretreatment. A 5 nm thick silicon dioxide (SiO2 )
layer was then deposited at 300 °C. Silane (SiH4 ) and
nitrous oxide (N2 O) were used as silicon and oxygen sources,
respectively. The pressure in the deposition chamber was
maintained at 900 mTorr and the platen power at 30 W [13].
A Ni/Au (40/600 nm) gate metal stack was then deposited
by e-beam evaporation followed by a final stabilization anneal
at 420 °C for 20 min in an N2 ambient. Figs. 1 (a) and (b)
illustrate a schematic view and a SEM image of the fabricated
MOS-HEMT device. Electrical characterization was per-
formed using a Keithley 4200SCS analyzer. Breakdown volt-
age measurements were performed using a Keysight B1505A
power device analyzer.

III. R ESULTS AND D ISCUSSIONS Fig. 3. (a) Linear and (b) semi-logarithmic transfer characteristics
IDS -VGS for the fabricated MOS-HEMT device.
Fig. 2 shows the DC output characteristics for the fabricated
MOS-HEMT device with a 1.5 μm gate length, a 15 μm TABLE I
gate-to-drain distance. The device demonstrates a maximum S URFACE S TATE D ENSITY (Di t ) C OMPARED TO
drain current density of 570 mA/mm at VGS = +3 V and an P REVIOUSLY R EPORTED R ESULTS
on-state resistance (RON ) of 7.3 · mm.
Fig. 3 shows the device transfer characteristics (IDS -VGS )
at VDS equal to 10 V. The measurement was performed under
gate bias, which was swept from −3 V to +3 V and back
from +3 V to −3 V. The pinch-off voltage (V p ), obtained
by linear extrapolation at the maximum transconductance (gm )
peak is −0.25 V. The maximum gm peak is about 180 mS/mm
at VGS = +1.3 V. The threshold voltage (VTH ) measured at
IDS =1 mA/mm is equal to −0.9 V as can be seen in Fig. 3 (b). with low hysteresis (Fig. 4 (a)). The maximum hysteresis
A very low hysteresis was observed on IDS -VGS curves and value, extracted from this measurement is about 70 mV, which
the maximum VTH shift is below 113 mV. corresponds to a Dit value of 2.4 × 1011 eV−1 cm−2 . The field
Using the equation: Dit = C M O S · VT H / q[2,8], effect mobility (μFE ), extracted from the IDS -VDS curves at a
the extracted surface state density is as low as 3.9 × VDS bias of +0.1 V, reaches 300 cm2 /V· s, as can be seen
1011 cm−2 eV−1 , which is to the authors’ knowledge, the in Fig. 4 (b).
lowest Dit value ever reported using PECVD for the gate oxide Furthermore, constant voltage stress (CVS) measure-
deposition of MOS-HEMT devices [6], [14]–[18]. Table 1 ments [19] were also performed on fabricated devices under
shows a comparison with relevant reported results in the positive and negative bias. Figure 5 shows IDS -VGS measure-
literature. ments performed during a 100-cycles stress test. Each stress
The high quality of the 5 nm PECVD-SiOx gate insulator cycle consists of an IDS -VGS hysteresis sweep, followed by a
gives the device a low gate leakage current at reverse and continuous stress at constant gate bias (VGS ) during 100 secs.
forward bias conditions. For the whole measurement range, The stress cycle were repeated 100 times, giving a total stress
the maximum gate leakage current (IGS ) is below 1 nA/mm. time of 10 000 secs. Tests were performed at a constant gate
In addition, the off-state drain leakage current is also below bias of VGS = −3 V (Fig. 5 (a)) and VGS = +3 V (Fig. 5 (b)).
1 nA/mm, which gives an ION /IOFF ratio of about 109. The positive gate voltage stress bias was limited to +4 V,
The sub-threshold slope (SS) extracted from the transfer char- which corresponds to the maximum voltage that could be
acteristics is 103 mV/dec as can be seen in fig. 3 (b). The hys- supported by the dielectric layer before a large increase in gate
teresis capacitance-voltage CGS -VGS measurement performed leakage current was observed. The VGS was kept below +3 V,
on the gate electrode shows good surface potential modulation which is considered as the safe operation area (SOA) of our

Fig. 4. (a) 1 MHz hysteresis capacitance-voltage (CGS -VGS ) measure-

ments performed on the gate electrode and (b) extracted field effect
mobility for the fabricated MOS-HEMT device. Fig. 7. Breakdown voltage measured on MOS-HEMT with LGD = 15 µm.
inset: VBD for MOS-HEMTs with different LGD .

were characterized under a drain-bias stress of up to +40 V

(limit of the equipment) with a pulse width and period of
500 ns and 1 ms respectively, giving a corresponding duty
cycle of 0.05 %. The maximum extracted gate-lag was about
5 % and the maximum drain-lag remained below 8 %,
even under a drain-bias stress of 40 V. Using a B1505A
power device analyzer, off-state breakdown voltage (VBD )
measurements were performed at VGS = −3V. For the
fabricated device with a 15 μm gate-to-drain distance, the
Fig. 5. IDS -VGS hysteresis measurements for 100 cycles at a constant IDS leakage current measured at VDS =500 V was about
voltage stress of (a) VGS = −3 V and (b) VGS =+3 V. 75 μA/mm as shown in Fig. 7. Hard breakdown occurred
at a drain voltage of 573 V and completely destroyed the
device. From this measurement, it appears clearly that the
drain leakage current is dominated by the buffer leakage,
as we did not see increases in gate leakage current until
the hard breakdown occurred. The Poweron/Power OFF ratio,
calculated for a VDS(on) = 2 V; IDS(on) = 260 mA/mm
and VDS(off) = 400 V; IDS(off) = 1.1 μA/mm, is 1180.
The VBD trend as a function of L GD is illustrated in the
inset of Fig. 7. The VBD increased with increasing gate-to-
drain distance from 156 V for L GD of 4 μm up to 451 V
for 8 μm. For larger gate-to-drain gaps, the VBD increased
Fig. 6. IDS -VGS hysteresis measurement before and after 10 hours slightly and was no longer highly dependent on L GD . This
continuous stress at a constant gate bias of (a) VGS = −3 V and
(b) VGS =+3 V. observation is consistent with previously reported results in the
literature [20]. In our case, the breakdown mechanism seems to
be limited by the buffer thickness, which could be improved
devices. Under this condition, the corresponding electrical field by using a thicker GaN buffer stack and by optimizing the
in the silicon oxide gate dielectric layer is about 6.4 MV/cm. back barrier structure [20], [21].
As can be seen in figure 5, neither a major VTH drift nor
any hysteresis degradation were noticed at VGS = −3 V
and VGS = +3 V. The maximum VTH shift, after the total IV. C ONCLUSION
10 000 sec cumulative stress, remained lower than 90 mV. In summary, an extremely low hysteresis was demonstrated
Moreover, devices were also subjected to 10 hours of continu- on a MOS-HEMT device by using an optimized PECVD
ous stress under the same conditions, with a constant gate bias deposition process for the gate dielectric layer. The electrical
at VGS = −3 V and VGS = +3 V. Gate leakage measurements characterizations showed a pinch-off voltage (V p ) of −0.25 V,
did not show any significant increase. IGS remained below the a threshold voltage of −0.9 V at IDS = 1 mA/mm, a max-
precision limit of the equipment (< 20 pA) and no dielectric imum drain current of 570 mA/mm and a gate and drain
degradation was observed, as can be seen in figure 6. IDS -VGS leakage current below 1 nA/mm. The device also shows an
hysteresis measurements, performed before and after 10 hours ION /IOFF ratio of about 109 and a sub-threshold slope of
of continuous stress, did not show any significant degradation 103 mV/dec. From IDS -VGS hysteresis measurements, a Dit
on device performance. The maximum threshold voltage (VTH ) value as low as 3.9 × 1011 cm−2 eV−1 has been extracted.
shift was kept below 150 mV at VGS = −3V and 20 mV All these results confirm the high quality of the PECVD-
at VGS = +3V. SiOx /GaN interface and the effectiveness of the developed
In order to characterize the trapping effects in the fabri- passivation process. This approach can be integrated into
cated devices, IDS -VDS pulsed measurements were conducted existing fabrication processes in order to further improve the
using a Keithley 4225-PMU. The fabricated MOS-HEMTs performance of AlGaN/GaN MOS-HEMT devices.

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