Beruflich Dokumente
Kultur Dokumente
220 VAC
UBAT IPM
PGND UDCM-
UCDM
IP
T Temperature
EPP
DRIVER Sensor
UB
ADC
PWM
PWM
ADC
ADC
ADC
I/O
dsPIC33FJ16GS504
DRIVER
FAULT/SD
SYS_FLT
FLT_CLR
S3 A2 (Mains Relay)
ACI1M
S4
R Power Grid
PGND L C
ACI2M
S5 I
FAULT/SD
FLT_CLR
SYS_FLT
S6 ACO1M ACO2M
Load
DRIVER
PWM
PWM
ADC
PWM
PWM
ACO
I/O
I/O
I/O
KF(1)
I/O
ADC
I/O
dsPIC33FJ16GS504 ACI
ADC KG(1)
Note 1: KF and KG are feedback gain circuits. Refer to Appendix D: “Schematics and Board Layout” for details.
K3(1)
PGND
Flyback
PGND transformer UFEEDBACK
+15V
K4(1)
PI
45V
TOPSWITCH
ENABLE
EFB
UB
ADC
- IB
IFEEDBACK ADC
IERROR
PI PWM
IREF
I/O
dsPIC33FJ16GS504
Analog Controller
Note 1: K1 and K2 are feedback gain circuits. Refer to Appendix D: “Schematics and Board Layout” for details.
D2 VOUT
+ +
VIN -
-
D3 Q
EQUATION 1:
N2
Vout Vin d
N1
T1 D1
+ VOUT
L1
+ +
+
C2
+ VIN 0V
+ +
D2
+
C1
Q1 Q2
0V
+VIN
L1
+ T1 D1
C1 Q1
+ +VOUT
+
+ C3
0V
+
+
C2
Q2 D2
0V
EQUATION 3:
N2
Vout Vin d
N1
where:
d is the duty cycle of the transistors and 0 < d < 0.5
N2/N1 is the secondary-to-primary turns ratio of
the transformer
+VIN
L1
T1 D1
Q1 Q3
+ +VOUT
+
+ C2
+ 0V
C1 +
Q2 Q4 D2
0V
T1 D1
+VIN +VOUT
+
+
C2
+ +
C1 0V
Q1
0V
EQUATION 5:
N2 d
Vout Vin
N1 1 d
ii
+ S+ D+
VI 2 C+
- io
a +
VI + VO
-
N -
+
VI 2 C-
- S- D-
ii
S1+ D1+ S2+ D2+
io
a +
+
VI + VI C+ VO
- b
- -
AC Input
R1
DC Output
Charge
Power Supply Control
Power Output
Rectifier Transformer Battery
Switch Filter
AC Input
DC Output
Power Supply
Current Control
Logic
Ferroresonant
Rectifier
Transformer
Battery
Charge
Control
AC Input DC Output
Power Supply
Diode Current
Transformer Rectifier SCR Limiter Battery
AC Input
DC Output
3x12V Batteries
Relay Logic
dsPIC® DSC
USB
LCD Controller
Controller
PIC18F2420
PIC18F2450
The dsPIC DSC device is the heart of the Offline UPS. These peripheral modules include features that ease
It controls all critical operations of the system as well as the control of any switch-mode power supply with high
the housekeeping operations. The functions of the resolution PWM, flexible ADC triggering, and
dsPIC DSC can be broadly classified into the following comparator fault handling.
categories: In addition to the intelligent power peripherals, the
• All power conversion algorithms dsPIC DSC also provides built-in peripherals for digital
• UPS state machine for the different modes of communications including I2C™, SPI and UART that
operation can be used for power management and housekeeping
• Auxiliary tasks including true RMS calculations, functions.
soft start routines and user interface routines. Note: For device details, refer to the dsPIC33F
The dsPIC DSC device offers “intelligent power periph- “GS” series device data sheets. For more
erals” specifically designed for power conversion appli- information on the peripherals, refer to the
cations. These intelligent power Peripherals include corresponding SMPS sections in the
the High-Speed PWM, High-Speed 10-bit ADC, and “dsPIC33F Family Reference Manual”.
High-Speed Analog Comparator modules.
Priority: Medium
Execution Rate: Medium
Priority: High
Execution Rate: High
System M
D AIN
Startup BA C_LI S_O
TT N K K
ER _ O &
M Y_ K &
DC AIN LO
(BATTERY_OK || BATTERY_LOW)
_ S _ W
BA LIN O
TT K _ K &
ER OK
Y_ &
OK
DC_LINK_OK &
MAINS_OK &
MAINS_NOT_OK &
DC_LINK_OK &
BATTERY_OK
M
D AIN
BA C_LI S_O
T T NK K
ER _O &
Y_ K &
LO
BATTERY_OVERVOLTAGE
DC_LINK_OVERVOLTAGE
DC_LINK_UNDERVOLTAGE
MA W
DC IN
BA _LINS_O
TT K _ K &
ER O K
MAINS_OK &
MAINS_NOT_OK
Y_ &
MAINS_OK &
OK
Battery
Inverter Mode Charger
Mode
MA
IN
DC_ S_NOT
BAT LINK_ _OK &
TER OK &
Y_
OK E
& TAG
_ OK OL
O T RV E
BA M
TT AIN _N DE AG
ER S_ I NS _UN O LT
E
Y_ N O MAERY ER
V
AG
BA UN T _ LT
TT DE OK A TT _OV O
ER
Y_ RV & B
ER
Y RV GE
DC OV OL
TT DE TA
_L
INK ER TA
GE BA _ UN V OL
DC _U VOL K R
IN VE
_L
INK
ND TA _L _O
_O
ER
VO
GE System Error DC IN
K
VE LT _L
RV AG DC
OL E
TA
GE
D
C
BATT
_L
DC_
IN
BATTERY_OVERVOLTAGE
K_
ERY_
O
LINK
VE
R
UND
VO
_U
LT
NDE
E
AG
RVO
E
RVO
A GE LT
L TAG
E
System Startup
When the Offline UPS is turned ON, the state of the
system is unknown. Therefore, the state machine first
monitors all system variables and determines the
starting state of the UPS.
During this time, the state machine also monitors for
fault conditions and ensures that all system variables
are within specification so that the UPS can switch to
normal operation.
0.1A
Priority: High
Set Relay flag =
NOT_READY_TO_SWITCH
Battery
Charger
Mode
Quantizer
+K
Duty Cycle
Charging Current
Reference 0
-1
-K z
Measured Charging Current
Priority: High
No Set Maximum
Charging Current
Set Minimum
No
AC Mains Detection Charging Current
FIGURE 26: dsPIC® DSC DEVICE RESOURCE ALLOCATION FOR BATTERY CHARGER
VBAT
AC Input
+
Note 1
GND
kA(2) kB(2)
dsPIC33FJ16GS504
Note 1: The AC mains input is rectified by the body diodes of the IGBTs to provide a DC voltage to the battery charger.
2: KA and KB are feedback gain circuits. Refer to Appendix D: “Schematics and Board Layout” for details.
Inverter
Priority: Medium Mode
Priority: High
Increment push-pull
reference
Battery Voltage and Current
Measurement No Is Push-pull converter
(ADC Interrupt) reference = final setpoint?
Yes
Priority: Medium
Increment delay
counter
Yes
Priority: Medium
Inverter
Mode
Inverter Initialization
Push-pull control loop
Priority: Medium
(ADC Interrupt)
Priority: High
AC Mains Detection
(ADC Interrupt)
Inverter
Mode
Priority: Medium
1:16
Voltage Control Duty
VREF Error Output Cycle + VOUT
X PID
Vin
PWM +
+-
1001010111
Voltage Feedback
ADC S&H
Current
Sinusoidal Reference Reference Current Duty
Voltage Control AC Out
Error Cycle
Error Output
X PI X P
PWM
+ -
+ -
Output Filter
Current
Feedback
S&H
1011010011
1001010111
Voltage Feedback
ADC
S&H
FIGURE 32: dsPIC® DSC DEVICE RESOURCE ALLOCATION FOR PUSH-PULL CONVERTER
VDC
Push-Pull Converter
VBAT +
GND
GND
FET FET
Driver Driver kD kC
VOUT+
VOUT-
GND
ADC
dsPIC33FJ16GS504
ADC
AC
Mains
Inverter
Inverter turned
OFF
Inverter
Frequency
Modified
Mains Failure
detected
Push-pull Soft-start
Routine Completed
Mains Failure
Occurred Inverter turned ON
at the last measured
mains voltage
UPS
Output
Battery
Charger
Mode (AC Inverter Mode
Mains
Present)
DC
Link
Voltage
AC
Load
Input Voltage
Output Voltage
Input Current
Q1 Q2
C1
UB T1
+
(A) Full-Bridge Inverter
Q3 Q4
Q1 C1
C2
Q3
T1
UB +
Q Q
L1
D3 D4
T1
(B) Full-Bridge Rectifier
C1 R1
D1 D2
FIGURE 41: CONTROL SIGNALS FOR The output voltage is calculated by Equation 6, where
PUSH-PULL INVERTER N2 N1 is the transformer windings ratio, and d is the
duty cycle of the PWM signal. The duty cycle must be
limited to the given boundary. In a real application, the
duty cycle must be limited to 0.1 < d < 0.42. This is
done due to the switching behavior of the MOSFETs
and transformer. Due to allowed oscillation and losses
in the system, the calculation using Equation 6 is not
exact. When no load is applied to the push-pull boost
stage, the controller has to switch into Burst mode, and
when heavy load is applied, the duty cycle must be
increased to compensate for various losses.
EQUATION 6:
N2
For the secondary, a full-bridge rectifier was chosen for U DC = U BAT ------ 2d
N1
the following reasons:
where:
• Reducing the leakage inductance by using only d is the duty cycle of the transistors and 0 < d < 0.5
one secondary winding on the transformer
N2/N1 is the secondary-to-primary turns ratio of
• Reducing cost of transformer the transformer
• Rectifier diodes can be rated lower in reverse
breakdown voltage, such diodes have better
forward and switching characteristics.
• Synchronous rectification is not required due to
high-voltage and low current operation.
EQUATION 8:
1000 1000
-----------
d
- -----------
2.68
-
Pl 150
B max = ---------------------------c = -------------------------------------------------
1.64
= 1339G
a -----------
f 100000
1000- 0.036 -----------------
1000
-
EQUATION 9: BMAX
8
10 P omax
W a A c = -------------------------------
K t B f J B
B
H
ΔB in Equation 9 is equal to 2Bmax due to bidirectional
core excitation as seen in Figure 42. Current density of
B
a winding is estimated to be 500A/cm2, and maximum
output power Pomax is 2000W. Therefore, the calculated
area product is shown in Equation 10. BMAX
EQUATION 10:
8 BSAT
10 2000 4
W a A c = ------------------------------------------------------------------ = 5.9cm
0.254 2678 100000 500
EQUATION 11:
2 2
10 V imin --- Dmax 10 30 ------------------ 0.42
8 8
f 100000
NP = --------------------------------------------------------- = -------------------------------------------------------------- = 3.4
B AC 2678 2.8
NS
NP
NP NP
NS
Bobbin CORE Insulation and Shield
NP
NP NP
NS
EQUATION 14: U DC N 2
d
VBRDSS 2VBAT 2 U bat N1
2 45V 1.3 117V
When we use a transformer with windings ratio of 16
the peak current is that of Equation 18:
Continuous Current
To calculate the current rating of the devices, peak and EQUATION 18:
average currents have to be estimated. The peak and
average currents can be estimated from the power rat- 2000W
ings and input voltage. The average current is calcu- I pm 160.3 A
30V 0.416
lated using Equation 15, where PC is the continuous
power and UBAT is the battery voltage.
Therefore, we have to design the MOSFETs for contin-
uous drain current of 16.67A and peak drain current of
EQUATION 15:
160.3A. Because the waveform shape will not be an
exact sawtooth, these calculations are only an esti-
I a Pc / U bat mate. To be on the safe side, these numbers are
increased by 30%.
The highest current will flow at the lowest battery Package Thermal Performance
voltage so the continuous current is:
To design the thermal performance, the rms current
I = 1000W 30V = 33.34A. And per leg, the continuous
value must be calculated. If the waveform shape and
drain current is half of this: ID = 16.67A.
peak current are known, the rms can be calculated
using Equation 19.
EQUATION 19:
d
I rms I pc
3
EQUATION 20:
2
I rms 80.15 .416 42.13 A
3
EQUATION 22:
WL
Poff f SW
4
EQUATION 23:
i2 L
WL
2
EQUATION 24:
1.6e3
Poff 100e3 40W
4
L1
D3 D4
T1
C1 R1
(A) D3 and D2 Conduct
D1 D2
L1
D3 D4
T1
(B) D1 and D4 Conduct C1 R1
D1 D2
i[A] tfr t
u[V]
i
PDon PDoff
t1 t2 t3 t[s]
Diode switching loss can be estimated using Total power loss is estimated by adding conduction
Equation 28. losses and switching losses, as shown in Equation 29.
Package Thermal Performance The estimation shows that the power losses are within
For diodes, an isolated TO-220-2 package is used. the set criteria.
Continuous working junction temperature should not
exceed 130°C at a heat sink temperature of 60°C. Typ-
Output Inductor
ical thermal junction-to-heat sink resistance of the junc- This inductor is optional and is not required. Its use
tion-isolated TO-220-2 package is Rt = 3.5°C/W. depends on the transformer construction and control of
Therefore, the maximum allowed power dissipation per DC-link voltage, and the inductor value that must be
part is PMAX = 70 3.5 = 20W. used. This section describes the design of a 50 µH
The STTH1210DI from STMicroelectronics meets the output inductor.
voltage and current requirements. Power loss calcula- The design of the output inductor uses the area product
tion can now be done looking at the diode data sheet. approach with the following conditions:
• Inductance: L = 50 μH
• Peak DC current: Ip = 13A
• Operating flux density: Bm = 300 mT
• Current density: J = 500A/cm2
• Window utilization: Ku = 0.4
First, the energy handling capability must be calculated
by Equation 30.
L I p2 50 106 132
LIp
E 0.0043Ws Bnew 308mT
2 2 N Ac
Then, to select the appropriate size of ferrite core, the The 3C81 material has a saturation point at 320 mT
area product calculation must be done, as shown in (100oC).
Equation 31. If the criteria are not fulfilled, different material, air gap,
number of turns, or even a bigger core must be
EQUATION 31: selected.
The cross-section of a wire is calculated by
2 E 104 Equation 35, where RMS current through the inductor
Wa Ac 1.43cm 4
Bm J K u is calculated from primary RMS current of push-pull
transformer and turns ratio. This current is twice as
large as primary because for half of a switching period,
The selected core was the P36/22 pot core from FER- the first primary winding is conducting and in the other
ROXCUBE due to its small size and shape, which pro- half, the second primary winding.
duces less interference into surrounding components.
The area product of this core is 1.46 cm4 and can be EQUATION 35:
calculated from the data in the manufacturer’s data
sheet. NP
2 I Prms
The number of turns required to get the desired I rms NS
inductance of the coil is calculated by Equation 32. The Acu 0.82mm2
Core cross section Ac = 172 mm2 is obtained from the
J J
manufacturer’s data sheet. The calculated value is the minimum cross-section of a
wire (100 kHz litz wire must be used).
EQUATION 32:
Next, the fill factor must be calculated by Equation 36.
LIp This provides an estimation of whether the winding fits
N 12.6 into the bobbin. The fill factor must be 0.4 or less.
Ac Bm Wb is the bobbin winding area and is 72.4 mm2, and
can be found in the core data sheet.
The calculated number of turns is then rounded to the
nearest integer value, which is 13. EQUATION 36:
To get the desired inductance, 3C81 material with an N Acu
air gap was selected to control the flux density. If an air Ku 0.15
gap is distributed into the magnetic path of the core, the Wb
effective permeability of material changes and induc-
tance factor AL. From the AL value and number of turns,
the inductance is calculated by Equation 33. The AL Output Capacitors
value is obtained from the material data sheet and is
When choosing DC-link capacitors, the following must
315 nH at 0.97 mm air gap.
be considered:
Snubbers are used to dampen high frequency oscilla- To design the snubbers for the rectifier diodes, the
tion and reduce ringing losses on diodes. Snubbers on capacitance of the rectifier diode must be known. The
the primary side are placed across the primary wind- simplified high frequency circuit is shown in Figure 47.
ings and are not used to handle voltage spikes at turn-
off of the MOSFETs. They only reduce ringing and FIGURE 47: HIGH-FREQUENCY CIRCUIT
transformer in-rush current.
To design the snubber for the primary side, the CD1 L1
LSS
capacitance of the MOSFETs and leakage inductance
of the transformer must be known. Both parameters
can be measured; however, MOSFET capacitance is CD3
voltage dependent so only an estimate can be used. In
our case, the capacitance of three parallel MOSFETs is
approximately CDS = 7 nF, and leakage inductance of
the transformer is estimated at LS = 500 nH. A Here, the capacitor should be in the range from two to
simplified high frequency circuit is shown in Figure 46. five times the capacitance of the diode. The diode
capacitance can be found in the diode data sheet. For
FIGURE 46: HIGH-FREQUENCY CIRCUIT the selected diodes it is approximately CD = 70 pF.
Therefore, a good starting capacitance value for the
snubber is C = 150 pF. Here we will also limit the max-
imum waste power to 1% of the rated converter power
to keep the efficiency of the converter as high as possi-
RS ble. Thus, the resistor ratings will also be 4W. The
resistor value should be selected so that the main
switching voltage signal will produce as low as possible
LS
dissipation on the resistor. The dissipation is depen-
RC dent on the RC frequency characteristics, and selecting
.5 µH
lower resistance or lower capacitance will shift the
characteristic frequency of the RC circuit higher, which
CDS result in the 100 kHz switching voltage producing less
6.6 nF dissipation on the snubbers. However, damping of the
snubbers will also decrease. A good starting value for
the resistor is R = 1 k.
Q4
R6
D2 Q1 Q2 Q3
R1 R2 R3
S1 R4
+ V1
12V R5
C1
EQUATION 40:
EQUATION 45:
L I p2 250 106 17 2 The gap is chosen from the data sheet to be 3.5 mm.
E 0.036Ws The new AL value must be calculated for the new air
2 2 gap by Equation 47.
After that, to select the appropriate size of the core, the EQUATION 47:
area product calculation must be done, as shown in
Equation 43.
AL K1 s K 2 148nH
EQUATION 43:
EQUATION 55:
Now, the required wires for primary and secondary can The selected core needs to have a higher area product
be selected. We will design the flyback transformer to than what has been calculated. From the magnetics
run a current density of J = 4 A/mm2. Therefore, the side, ETD34 and above will be sufficient; however,
required copper area for the primary and secondary there needs to be enough space to fit the windings. For
can be calculated with Equation 56 (litz wire for this in iterations for different cores, the number of turns
132 kHz must be used). and from this the window utilization and fill factor has to
be calculated. If the window utilization is higher than
EQUATION 56: 90% or a fill factor higher than 0.4, the windings will not
fit. The transformer construction winding diagram and
I Prms mechanical diagram are shown in Figure 50.
ACuP 0.375mm 2
J
I
ACuS Srms 0.8mm 2
J
A winding factor of K = 0.2 is selected for the trans-
former and N87 material for the core. The maximum
core flux density is set to B = 130 mT. To select the
core, the area product has to be calculated with
Equation 55.
EQUATION 57:
100 PO max
Wa Ac 0.65cm 4
Kt 2 B f J
Primary
NP Secondary
Primary
NS
Bobbin CORE Insulation and Shield
NP
Primary
Secondary
Primary
For the windings, litz wire is used to grant low copper EQUATION 60:
losses at high frequency. For switching frequency f =
132 kHz, a litz wire made of AWG38 wires is used to 25
eliminate skin and proximity effect. The required num- N tP 25 25
ber of parallel wires is calculated with Equation 58. DP
25
EQUATION 58: N tS 16.7 16
DS
ACuP
nwP 47.7
ACuw EQUATION 61:
ACuP NP
nwS 101.8 N lP 2.32 3
ACuw N tP
For both, we have to select standard litz wires. So, for NS
N lS 1.875 2
the primary, 45xAWG38 is selected and for the second- N tS
ary, 105xAWG38 is selected. The diameter of selected
wires with silk isolation is DP = 1 mm and DS = 1.5 mm.
The window utilization is shown in Equation 62 and fill
For the used ETD39 core with an air gap, the required factor in Equation 63.
number of turns can now be calculated from the
required primary inductance, turns ratio, and core data. EQUATION 62:
Primary turns are calculated with Equation 59.
EQUATION 59:
Wu ( DP N lP DS N lS ) / Wa 86%
104 LP I Ppeek
NP 58.1 58
2 B Ae EQUATION 63:
NP
NS 30.5 30 K u ACuP N P ACuS N S / Wa 0.25
N PS
Now, the window utilization and fill factor can be calcu- According to this the windings fit to the selected core.
lated for the selected core and wires. The bobbin win- The required air gap can be calculated from the core
dow is 25x7 mm. From this we can calculated how data sheet. To calculate the required air gap the AL
many turns for the primary and secondary value of the core has to be calculated. The AL value is
(Equation 60) and the number of required layers air gap dependent. From knowing the primary induc-
(Equation 61). tance and number of winding turns, the required AL
value can be calculated with Equation 64.
EQUATION 66:
N2 28
VBR ( rect ) Vin 2 Vbat 2 VF ( IGBTD ) 260 2 45 2 1.3 240.4V
N1 52
1:16
Voltage Control Duty
VREF Error Output Cycle + VOUT
X PID
VIN
PWM +
+ –
1001010111
Voltage Feedback
ADC S&H
VO
D
VIN D
VIN.D L_C VO1
390 VO*
VIN1 Voltage
VO*1 Digital iLoad IL
Control System Buck Modulation1
540 L_C Circuit1 Scope1
VIN1
Out1 In1
ADC
VO ILOAD x
Full-Bridge Inverter Compensator rent reference value. The measured current value is
subtracted from the reference and the difference is
Current mode control has been implemented for the passed to the current error compensator (P). The out-
Inverter using two control algorithms: PI and P. put of the compensator is used to control the PWM out-
In current mode control, the current as well as the volt- puts. Current mode control is the preferred method as
age is measured. The inverter output is generated by it has better transient response and stability of the out-
varying the input voltage reference using a sinusoidal put. However, current mode control is usually harder to
lookup table. The difference is passed through the volt- implement as there are two control algorithms instead
age error compensator (PI) and the output is the cur- of just one as in voltage mode control.
Current
Sinusoidal Reference Reference Current Duty
Voltage Control AC Out
Cycle
Error Error Output
X PI X P
PWM
+ -
+ -
Output Filter
Current
Feedback
S&H
1011010011
1001010111
Voltage Feedback
ADC
S&H
Out1 In1 ++
Out2 In2 ++
Out1
Fractional format allows easy migration of code from In theory, the Q15 voltage V/VN is first multiplied by
one design to another with completely different ratings VN, and then gain (G), and then the IREF that is
with most changes only in the coefficients defined in the obtained is divided by IN to get current in the cor-
header file. rect format. Since VN and IN are constants, the gain
G is scaled as: G * VN / IN. This value can be used
To completely use the 16 bits available in the in software to act on voltage quantity and give out a
processor, the Q15 format is most convenient as it current quantity.
allows signed operations and full utilization of the
available bits (maximum resolution). Other formats are The input quantity should be in fractional format (this
also possible, but resolution is lost in the process. Q15 has to be ensured in code). Then, the output current
allows us to use the fractional multiply MAC operation quantity will automatically be in the correct fractional
of the dsPIC DSC effectively. quantity. This essentially solves the objective of
scaling. The same logic applies to any control block.
The feedback signal (typically voltage or current) is
usually from a 10-bit ADC. Based on the potential By considering the input and output units and scale of
divider/amplifier in the feedback circuitry, actual voltage each block to be implemented in software, the proper
and currents are scaled. scaled values can be arrived at.
90
85
80
Percentage (%)
75
70
65
60
10 25 50 60 70 80 90 100
% Load
FIGURE C-4: OUTPUT VOLTAGE AND OUTPUT CURRENT – 500 VA REACTIVE LOAD
Imax=2.5A
Vmax=48V
D25
R96
Udc W2 STTH8R06D Uch Ubat
T2 0.33e 5W
R97
C82
0.22uF 630V C84 C85
P4 6k8 4W C83 R98 C86 100uF 100V
12V
R108 3
+
1206 R101 1
Q12
390k 3k3 U7B 4
BC817 R103 -
8 LM358
2
R109 6.8k 1%
TP14 6
1206 7 R106
R104 B
7
2
390k 5 GND
3k3
1k5 1%
D
4
1
C R105
IC4
C143 GND
R107 180e 100nF
S
X
F
TOP250YN (TO220-7) 6.8e D27
Ibatm+
Ibatm-
C88
4
3
5
DNP BAR43C PGND
100nF 100V C89
R114
BC817 GND
4k7 C93
R115 GND
EFB
1k5
47nF
OFFLINE UPS REFERENCE DESIGN SCHEMATIC (SHEET 1 OF 8)
GND
PGND
R202
2k2
GND
DS01279A-page 75
AN1279
FIGURE D-3:
DS01279A-page 76
12V
L10
P3 3V3 C25 C94
AN1279
P_FAN
dsVpp 1 2 4.7uH 1.5A C59
D29
3 4 dsICSPD GND C22 1
dsICSPC 5 6 1uF 100nF 10uF 25V 2
GND ES1B 1uF 25V
ICSP e10 FAN
No galvanic isolation!
Do not connect when UPS is connected to AC Line!
R116
EPP
EFB
Q15
PS
dsI CSPC
dsI CSPD
/SYS_FLT
Tb
Iref
3V3 100 IRLL2705
10k
3V3 AR1
44
43
42
41
40
39
38
37
36
35
34
U15 GND
R206 dsPIC33FJ16GS504
C95
Vss
VDD
RP6
RP5
RP8
DNP
AN9
RP15
RP24
RP23
1 GND
FLT_CLR PGC1
PWM4L
33
PWM4H
OSCO R11712pF
2 Y1 1M DNP
SS RP20
32
R207 OS CI C96
2
3 20MHz
SCLK RP21
10e 31 GND
AN8 T
4 12pF
SDO RP22
30
Vss
5 3V3 C97
SDI RP19
29
VDD
6
R15 R26 R127 R201 Vss 100nF
28
DNP DNP DNP DNPC140 10uF 6V Tant AN10 A1 C98
7
VDDCORE
100nF C139 27
AN11 ACi
8 1uF
S2 PWM3H
26
D30 S2 D33 D34 AN5 Ub GND
9
DNP DNP DNP S1 PWM3L
GND 25
AN4 Ib
DNP 10
S6 PWM2H
24
AN3 Udcm
GND 11
S5 PWM2L
23
AN2 IP
PWM 1H
PWM 1L
RP16
RP29
AVSS
AVDD
MCLR
RP2 7
RP2 8
AN0
AN1
12
13
14
15
16
17
18
19
20
21
22
I
ACo
A2
S4
S3
TX
RX
FAULT/SD
3V3
BR4 3V3A R118
C141
0e 10k
1uF
AGND GND dsVpp
OFFLINE UPS REFERENCE DESIGN SCHEMATIC (SHEET 2 OF 8)
C99
C142
100nFAGND 100pF
GND
220e 10k
C100
100nF
P5
1 2
3 4 A0
GND
E1 5 6 E2
5V
DB0 7 8 DB1
Vpp 1 2
GND
3 4 ICSP D
ICSP C 5 6
GND
ICSP
No galvanic isolation!
Do not connect when UP S is connected to AC L ine!
5V
5V U8
2 21
DB6 RA0/AN0 RB0/INT0 DB0
R136 3 22
DB7 RA1/AN1 RB1/INT1 DB1
10k 4 23 R124 R125 R204 R126
A0 RA2/AN2/VREF- RB2/INT2 DB2
5 24 DNP DNP DNP DNP
E1 RA3/AN3/VREF+ RB3/CCP2 DB3 5V
6 25
E2 RA4/T0CKI RB4 DB4
7 26
RA5/AN4/SS/LVDIN RB5/PGM DB5
10 27
OSC2/CLKO/RA6 RB6/PGC ICSP C
9 28
OSC1/CLKI RB7/PGD ICSP D
Y2
7.3728MHz 5V 11 P_BZ R128
RC0/T1OSO/T1CKI LED1
2 1 12 SS
RC1/T1OSI/CCP2 LED2 1 0R
13
R130 RC2/CCP1 2 R129
14
10k RC3/SCK/SCL SCLK
R131 15 0R
RC4/SDI/SDA
1M 1 16 R132
VPP MCLR/VPP RC5/SDO
17 SDO
RC6/TX/CK BTN 0R
C102 C103 18
RC7/RX/DT R133
33pF 33pF
OFFLINE UPS REFERENCE DESIGN SCHEMATIC (SHEET 3 OF 8)
8 5V
VSS R134 SDI
19 20 0R
VSS VDD
GND GND 4k7
GND C104
D31 R203 R135
PIC18F2420-E/SO 100nF
DNP DNP
GND
GND
DS01279A-page 77
AN1279
S6 S3
R41 R42
S5 S4
4k7 4k7
FIGURE D-5:
R43 R44
4k7 4k7
DS01279A-page 78
GND GND
AN1279
GND GND K1
3V3 3V3
Phoenix Contact DP DT MR...21- 21
UDC
FLT_CLR DSH2
R45 47e 12V D15
R46 R47 HOP2
D13 D14
4k7 4k7 R48 12e
HON2
R49 1N4148 Q6
/SYS_FLT R51 1k Q7 Q8 R50
4k7 SDDH2 BC817
EGP10J EGP10J A1
GND STGP14NC60KD STGP14NC60KD 3k3
FAULT/SD DSH1
R53 47e R52
HOP1 10k
R54 12e
U3 HON1 R55 C34 R56
12V R57 1k 10k 3.3nF 25V 10k
S6 HIN DSH DSH2 SDDH1 C33 GND
S5 LIN Vb
3.3nF 25V R40
FLT_CLR FLT_CLR N.C. C35 L2
/SYS_FLT /SYS_FLT HOP HOP2 250uH ETD54
1uF 25V DSL2 100e 4W
FAULT/SD /FAULT/SD HON HON2 R58 47e L1 L2
Vss Vs LOP2
D16 D17
SDDL2 SSDL SSDH SDDH2 R59 12e
L2
GND LON2
COM N.C. R60 1k Q9
LON2 LON N.C. SDDL2 Q10
EGP10J EGP10J
1
3
5
7
2
4
6
8
EGP10J
9
12
11
10
L1
4n7 AGND AGND
A Ci1 m
A Ci2 m
No t on PCB
1e 1206 GND 33e 12V
C42 1206
A Co2m
EGP10J
A Co1m
J3 J4
OFFLINE UPS REFERENCE DESIGN SCHEMATIC (SHEET 4 OF 8)
Not on P CB 470pF
PACin ACOutN ACOutL
C43
2
Q11 10uF 25V
3 A2
BC817
1 R69 R70
R71 R72
100e 3k3
Plug AC Male 10k 12e
GND D20
GND
K2
Phoenix Contact DP DT MR...21- 21 1N4148
R138
2k 1%
2k2 1% 5VA 3V3
5VA 3V3 R139 R140 R141 C107
R142 R143 R144 R145 Udcm-
C108
8
ACi1m 56k 1% 56k 1% 56k 1%
1206 1206 1206 100nF U9A
8
82k 1% 82k 1% 82k 1% 82k 1%
100nF U10A 2 AGND MCP6022 D12
1206 1206 1206 1206
2 AGND MCP6022 D35 1 R146 BAR43S
R147 BAR43S R148 R149 R150 A Udcm
1 3 1k69 1%
R151 R152 R153 R154 A ACi Udcm+
3 R155
ACi2m 1k69 1% 56k 1% 56k 1% 56k 1%
R156 1206 1206 1206 R157 C109 C110
82k 1% 82k 1% 82k 1% 82k 1%
4
4.7nF 3k3 1% 4.7nF 3V3 2k 1%
2k2 1% AGND AGND AGND AGND
2V5A AGND AGND AGND AGND
D36 C113
AGND
C114 R159 BAR43S 4.7nF
4.7nF Im I
1k69 1% R160
R162 R161
C115 2k2 1%
2k2 1% 3V3
3k3 1% 4.7nF R163
3V3
R164 R165 R166 R167 Ubm-
8
8
82k 1% 82k 1% 82k 1% 82k 1%
U10B 6 MCP6022 D37
1206 1206 1206 1206
6 MCP6022 D38 7 R168 BAR43S
R169 BAR43S R170 B Ub
7 5 1k69 1%
R171 R172 R173 R174 B ACo Ubm+
5 R175 C117
ACo2m 1k69 1% 33k 1%
R176 1206 R177 C116
82k 1% 82k 1% 82k 1% 82k 1%
4
1206 1206 1206 1206 R178 C118 C119 4.7nF 3k3 1% 4.7nF
4
4.7nF 3k3 1% 4.7nF 2k2 1%
2k2 1% AGND AGND AGND AGND
2V5A AGND AGND AGND
C120
4.7nF
AGND
2V5A R179
100k 1%
5VA R180
5VA 3V3
5VA C121 R181 C122 2k2 1%
Ibatm-
8
8
100nF U11A 33k 1%
1206 100nF U12A 3V3
R182 2 AGND MCP6022 D39
2 AGND MCP6022
1 R183 BAR43S
A 1
8
2k2 1% 3 R184 A Ib
3 U12B
Ibatm+ 1k69 1%
R185 6 MCP6022 D40
R186 33k 1% R187 BAR43S
4
C123 1206 R188 C124 C125 7
4
B IP
4.7nF 4.7nF 3k3 1% 4.7nF 5 1k69 1%
2k2 1% IPm
100k 1% R189 C126
AGND
AGND AGND AGND AGND R190
4
2 Tb
8
3
U11B C128 R195
1k
6 MCP6022 D42 Bat Temp AGND 100nF
7 R196 BAR43S 100k
R197 B T
5 1k69 1% AGND
Tm+
R198 AGND AGND
3k3 1%
C129
4
C130 3k3 1% 100nF
100nF
AGND AGND AGND
AGND
DS01279A-page 79
AN1279
Udc Ubat
P1
W1 12V 1 2 12V
R73 C44 C45 C46
2-position header 5V 3 4 5VA
FIGURE D-7:
1206 external ON/OFF switch F1 0.33uF 100V 0.33uF 100V 470nF 25V
SMD075F/60 3V3 5 6 3V3A
150k D21
(on enclosure) GND 7 8 AGND
DS01279A-page 80
BAV99
R76 GND GND C47 power
AN1279
1206 R77
150k IC1 12V
100k L3
C48 220nF 25V
R79 1uF 25V 3 1 47uH 2.6A
VIN VCC
1206 2 16 C49
/SD BST
150k GND 4 14 D22 330pF C50 C51 C52 D44
SYNC SW
8 15 ES3B C53
RAMP PRE BZX85C16
R80 BC856 R74 10 13 1uF 25V 68uF 25V 68uF 25V 68uF 25V
SS IS
1206 Q13 10k 7 R81 LowESR LowESR LowESR
RT
150k 5 11 10e R82 GND
COMP OUT
6 1206
FB 10k
R84 R75 9 12
AGND PGND
1206 47k C54 GND
150k R78 1uF 25V R85 GND
C55 12K PAGND1 LM5575 GND R86 R83
68k
R87 P10 680pF 25V 3k3 1k2
4k7 S3
2
1206 SW-PB
1
PAGND1
GND TEST R88
PAGND1 24k
C56
GND 1nF 25V L6
0e
GND PAGND1 Needs heatsink on P CB
VR1 5V 5VA
L8
VIN VOUT
0805 C68
GND R220 C72
C73 BLM21PG221
C75 2k2 2.2uF 10V 68uF 25V
LM2904S-5.0
2.2uF 10V 68uF 25V LowESR
LowESR AGND
GND
D46
GND
GND
GND PGND
EGND EGND EGND EGND
S2
S1
P9A
EPP
2.4k 3W 2.4k 3W
R2 R5 ETD54 L1 DC+
DNP C2D05120 Udc
FIGURE D-8:
C2D05120
T1
R3 DNP Ubat C1 C4 Udcm+
4k7 C23 200H
Ubm+ R16 C2 C3
150pF 1kV 150pF 1kV C5 C7
R6 e15 e15
4k7 10R 3W 0.01uF
.1uF 630V .1uF 630V
100V Udcm-
J1 Fext 470uF 400V HT 105×C
DC- PGND
BR1
C13 C14
4
3
2
1
0e 2x20A e5 e5 P9B
BAT+ Slow Blow (on enclosure) T3 DNP
U2 C11 C12 1uF 100V CT 1:1000 Tr
GND
I N_B
I N_A
100V 100V 1uF 100V
ENB_A
10k DNP
BAT- PGND PGND C24 R7 R9
1000uF 100V HT 105×C R17
12V 10R 3W PGND 2.4k 3W ref1
2.4k 3W
OUT_ B
VDD
OUT_ A
ENB_ B
12V D3 D28
0.01uF
100V
5
6
7
8
C6 C8 R12 R13
C2D05120 C2D05120 C17
R10
DNP DNP DNP
150pF 1kV 150pF 1kV
1k
C15 C16 current sense GND
Q18 12V
1uF 25V 68uF 25V BAS21
BC817 Tr
LowESR D4
DNP
D8 R25
R11
4.7e R19A
4.7e R19B
4.7e R19C
D24
100V FDP2532 FDP2532 FDP2532
BAR43S
D10
R19 PGND BAS21 GND
10k
4.7e R22A
4.7e R22B
4.7e R22C
R37
TP6 LM393 10k
C28 2k2 C29 KTY81/122
Vvercurrent shutdown to driver
100pF DNP DNP
GND DNP
TP7 3V3 IPm
OFFLINE UPS REFERENCE DESIGN SCHEMATIC (SHEET 7 OF 8)
R39 U1B
DNP
33e(CT)
10k DNP 5
1k / 33e(CT)
7
PS
6
ref2
Cycle-by-cycle Current-Limit to dsPIC C30
68pF DNP GND
GND
DS01279A-page 81
AN1279
FIGURE D-9:
DS01279A-page 82
AN1279
P8 5VUSB
UVpp 1 2
3 4 UICSP D
UICSP C 5 6
GNDUSB
ICSP
3V3 5VUSB
C131 C136
100nF 100nF
U13
1 8
GND Vcc1 Vcc2 GNDUSB
2 7
RX Out A In A
3 6
TX In B Out B
4 5
GND 1 GND2
U14
R199
10k
1 28
UVpp MCLR/VPP/RE3 RB7/KBI3/PGD UICSP D
2 27
RA0/AN0 RB6/KBI2/PGC UICSP C
3 26
RA1/AN1 RB5/KBI1/PGM
4 25
RA2/AN2/VREF- RB4/AN11/KBI0
5 24
RA3/AN3/VREF+ RB3/AN9/VPO
C133 6 23 5VUSB
RA4/T0CKI/RCV RB2/AN8/INT2/VMO
7 22
GNDUSB RA5/AN4/HLVDIN RB1/AN10/INT1
8 21
2
Vss RB0/AN12/INT0
12pF 9 20 C134 0805
OSC1/CLKI VDD
R200 Y3 10 19 100nF BLM21PG221
OSC2/CLKO/RA6 VSS
C135 1M 11 18 5VUSB L9 J7
1
RC0/T1OSO/T1CKI RC7/RX/CK
12 17 1
GNDUSB RC1/T1OSI/UOE RC6/TX/CK VBUS
20MHz 13 16 2
RC2/CCP1 RC5/D+/VP D-
12pF 14 15 C137 3
VUSB RC4/D-/VM D+
1uF 25V 4
GND
C138
1nF GNDUSB
USB B 1-1470156- 1
GNDUSB PIC18F2450 GNDUSB
GNDUSB
OFFLINE UPS REFERENCE DESIGN SCHEMATIC (SHEET 8 OF 8)
EGND
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
03/26/09