Chin. Phys. B Vol. 22, No.

4 (2013) 048501

Dual-gate lateral double-diffused metal oxide semiconductor

with ultra-low specific on-resistance∗
Fan Jie(范 杰)† , Wang Zhi-Gang(汪志刚), Zhang Bo(张 波), and Luo Xiao-Rong(罗小蓉)
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

(Received 9 April 2012; revised manuscript received 13 September 2012)

A new high voltage trench lateral double-diffused metal–oxide semiconductor (LDMOS) with ultra-low specific on-
resistance (Ron,sp ) is proposed. The structure features a dual gate (DG LDMOS): a planar gate and a trench gate inset in
the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce Ron,sp dramatically. Secondly,
the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain
comparable breakdown voltage (BV). Simulation results show that the cell pitch of the DG LDMOS can be reduced by
50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, Ron,sp of the DG LDMOS can be
reduced by 67% due to the smaller cell pitch and the dual gate.

Keywords: breakdown voltage, specific on-resistance, dual gate, oxide trench

PACS: 85.30.De, 85.30.Tv, 84.70.+p DOI: 10.1088/1674-1056/22/4/048501

1. Introduction
In recent years, the breakdown voltage (BV) has been
the focus of power lateral double-diffused metal–oxide semi-
conductor (LDMOS) field-effect transistors.[1–6] However, the
long drift region, which is essential to sustaining high volt-
age in power lateral metal–oxide semiconductor field-effect
transistors (MOSFETs), limits the improvement in the spe-
cific on-resistance (Ron,sp ). In order to reduce the Ron,sp and
increase the current density while maintaining a high break-
down voltage, numerous structures and technologies were
proposed.[7–14] The Ron,sp can be reduced by introducing a su-
perjunction into the power MOSFET structure.[11] Besides, a
secondary drift region, which is placed under the drift region,
is utilized to further improve the Ron,sp and BV for CLAVER
LDMOS structure.[12] In these cases, Ron,sp is reduced by op-
timizing the drift region of the device. On the other hand,
the combination of planar and trench gate structure has been
investigated.[13,14] In contrast, the Ron,sp of power LDMOS can
be further reduced when the resistances of the channel region
and the drift region are improved simultaneously.
Here, we propose a novel trench LDMOS with dual gate
(DG LDMOS) and an oxide trench in the drift region. A
planar gate and a trench gate integrated in this novel struc-
ture can form a dual gate. This dual gate not only can pro-
vide an additional conduction channel to mitigate the resis-
tance of the channel region, but also can fold the drift region
and reduce the cell pitch but still maintain comparable BV.
∗ Projectsupported by the National Natural Science Foundation of China (Grant No. 61176069), the National Key Laboratory of Analog Integrated Circuit,
China (Grant No. 9140C090304110C0905), and the Innovation Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices,
China (Grant No. CXJJ201004).
† Corresponding author. E-mail: fan576@163.com
These two aspects can lead to low Ron,sp compared with that
by the optimized conventional LDMOS (C-LDMOS) and pla-
nar gate trench-type LDMOS (PG LDMOS) with a similar BV.
MEDICI TCAD simulator is used to help analyze the electrical
characteristics of the proposed dual-gate structure.
2. Device structure
The schematic cross section view of the proposed DG
LDMOS is shown in Fig. 1. In the drift region, an oxide trench
is located in a region between the drain and the source. An ad-
ditional trench gate is introduced in this oxide trench. The
dual gate is formed by the trench gate and the planar gate. On
the one hand, in the ON-state, dual conduction channels are
formed, and thus, the current can flow through both the sur-
face channel and the vertical channel (along the oxide trench
sidewall). The lower Ron,sp can be obviously obtained. On
the other hand, in the OFF-state of the DG LDMOS, the oxide
trench folds the drift region in the vertical direction, thereby
increasing the effective drift region length. In comparison with
the conventional LDMOS, the proposed DG LDMOS con-
sumes small cell pitch at the comparable breakdown voltage
(BV). To fabricate the oxide trench and trench gate structure,
many fabrication methods are reported.[15–17] Based on these
fabrication methods, the proposed DG LDMOS can be fabri-
cated only by employing an extra planar gate. In Fig. 1, wT and
tT are the width and depth of the oxide trench, respectively; tS
and Nd are the thickness and the doping concentration of the

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048501-1
 Chin. Phys. B Vol. 22, No. 4 (2013) 048501
n-type silicon layer, respectively; Psub is the doping concentra- pects can lead to the fact that the electron concentrations in the
tion of the p-type substrate. Thickness tS = 7 µm is used in inversion layers of the two channels are similar to each other
this paper. Furthermore, Nd is optimized in order to obtain the as illustrated in the inset of Fig. 2(b). From this figure, similar
maximum BV for each device. electron distributions in the inversion layer can be observed
along the two channels when Vgs = 1.5 V.
halfcell pitch
60
D GT S GP S GT D (a)
Vgs= 2.5 V

Drain current/mASmm-1
turn on dual gates
n+ x n+ p+ n+ n+ p+ n+ n+
40
tT pwell pwell

A A′ planar oxide
y gate
wT trench trench tS
gate 20 turn on trench gate only
B B′
Ndrift region
turn on planar gate only
0
psub 0 3 6 9 12
Drain voltage/V

Electron concentration/cm-3
40 1017
Fig. 1. Schematic cross section of DG LDMOS. Vgs= 1.5 V Vds= 5 V
1016
Drain current/mASmm-1

planar channel

ls
30 1015

ne
an
3. Simulation results and discussion vertical channel

ch
1014

al
0 0.6 1.2
el

du
In the ON-state, the inversion channel can be formed at 20 Distance along channel/mm nn
cha
the sidewall of the trench gate and under the planar gate. Com- na
r
pla el
pared with single channel device in C-LDMOS, and PG LD- 10 nn
l cha
a
MOS, the proposed dual-gate LDMOS offers a large conduc- tic
ver (b)
tion current region, resulting in a reduced Ron,sp . The forward 0
1.2 1.4 1.6 1.8 2.0 2.2
Ids –Vds characteristics of the proposed dual-gate LDMOS are
Gate voltage/V
shown in Fig. 2(a) for three different combinations of the two
Fig. 2. Forward characteristic curves of (a) Ids –Vds and (b) Ids –Vgs
gate voltages (GT and GP ). As shown in this figure, the drain for the proposed dual-gate LDMOS. The inset in panel (b) shows the
current can be independently controlled by the planar gate (GP corresponding electron distributions along the dual channels. (tS =
7 µm, tT = 4 µm, wT = 3.5 µm, Nd = 4.5 × 1015 cm−3 , Psub =
contact) and the trench gate (GT contact), but in single-channel 3.5 × 1015 cm−3 , half-cell pitch = 9.5 µm.)
operation, the DG LDMOS exhibits a relatively low satura-
tion current: 9 mA/mm with the biased planar gate only, and Figure 3 shows the current flowline contours for DG LD-
24 mA/mm with the biased trench gate only. When the dual MOS (see Fig. 3(a)), PG LDMOS (see Fig. 3(b)) and C-
gate is biased at the same time, a larger saturation current of LDMOS (see Fig. 3(c)) at Vgs = 5 V, Vds = 1 V. Comparing
51 mA/mm is obtained, attributing to two current paths. Thus, Fig. 3(a) with Fig. 3(b), it can be seen that an additional ver-
it is evident that the dual gates of the DG LDMOS should be tical channel is formed along the oxide trench sidewall for
biased simultaneously in order to reduce Ron,sp . Figure 2(b) DG LDMOS. As a result, the drain current of 16 mA/mm
illustrates the current flowing through the vertical channel, the flows through the vertical channel and the planar channel at
planar channel and the dual channels when the dual gate is the same time. The drain currents of PG LDMOS and C-
biased simultaneously. It indicates that the threshold voltage LDMOS are limited by the single channel compared with
of the vertical channel is almost the same as that of the pla- the drain current of DG LDMOS. The drain current thus de-
nar channel. This can be explained from the following two creases to 8.4 mA/mm for the PG LDMOS, and it reduces
aspects: the trench gate shields the influence of the electric to 10.7 mA/mm for the C-LDMOS. So the drain current de-
field in the oxide trench on the dual channels; the similar dif- creases to 53% for the PG LDMOS, and it reduces to 66.9%
fused impurity concentration distributions and the same thick- for the C-LDMOS in comparison with that of the DG LD-
ness values of gate oxide for the dual channels. These two as- MOS.

048501-2
 Chin. Phys. B Vol. 22, No. 4 (2013) 048501
D G S G D S G D G S
0 0 0

y/mm
y/mm

y/mm
4 4 4

8 8 (b) 8 (c)
(a)
0 4 8 0 4 8 0 8 16
x/mm x/mm x/mm

Fig. 3. (color online) Current flowline contours for (a) DG LDMOS (Nd = 4.5×1015 cm−3 , Ids = 16 mA/mm), (b) PG LDMOS
(Nd = 4.3×1015 cm−3 , Ids = 8.4 mA/mm), and (c) C-LDMOS (Nd = 2.1×1015 cm−3 , Ids = 10.7 mA/mm). (tT = 4 µm, wT = 3.5 µm
and half-cell pitch = 9.5 µm for DG and PG LDMOS. Half-cell pitch = 19 µm for C-LDMOS in order to obtain the comparable BV.
tS = 7 µm, Psub = 3.5×1015 cm−3 . 2 mA·mm−1 /contour)

100 Vgs=5 V (a) that of PG LDMOS, the Ron,sp of C-LDMOS is higher due to
Drain current/mASmm-1

Vgs=4 V DG LDMOS its larger cell pitch at the equivalent BV. The transconductance
80
(Gm , Gm = Ids /Vgs ) as a function of Vgs is shown in Fig. 4(b).
60 It is obvious that the Gm of DG LDMOS is much higher than
40 CLDMOS
that of PG LDMOS and also that of C-LDMOS in the same
bias conditions. The peak Gm of 5.8 mS/mm is obtained at
20 PG LDMOS
Vds = 1 V and Vgs = 2.1 V for DG LDMOS. However, the val-
0
0 1 2 3 4 5 6 7
ues of Gm for PG LDMOS and C-LDMOS are both less than
Drain voltage/V 3 mS/mm when Vds = 1 V.
30 In the OFF-state, BV is improved by the oxide trenches
DG LDMOS PG LDMOS CLDMOS

10 V (b) of DG LDMOS and PG LDMOS, which results in a smaller

Vds=10 V
7V Vds=7 V
cell pitch at the equivalent BV. Figures 5(a) and 5(b) show the
Gm/mSSmm-1

20 Vds=5 V
5V
lateral electric fields along the line of surface (see Fig. 5(a))
Vds=3 V
Vds=1 V 10 V and y = 2.2 µm (AA0 line in Fig. 1) (see Fig. 5(c)) for DG LD-
3V 7V
10
MOS, PG LDMOS, and C-LDMOS. Since an oxide trench is
5V
inserted between the source and the drain, the effective drift
3V
region length for DG LDMOS is increased and also is for PG
Vds=1 V
Vds=1 V
0 LDMOS. This helps to achieve smaller half-cell pitch with the
1 3 51 3 51 3 5
Gate voltage/V same BV. In other words, the surface electric field between the

Fig. 4. Transfer characteristic curves of (a) Ids –Vds and (b) Gm at the
source and the drain is enhanced by the oxide trench and thus
comparable BV, with the same structure parameters as those in Fig. 3. the half-cell pitch is reduced at the comparable BV. As shown
in Fig. 5(a), the electric field strength near the drain region de-
The output characteristics of DG LDMOS, PG LDMOS,
creases from 1×106 V/cm for DG LDMOS to 0.5×106 V/cm
and C-LDMOS are compared in Fig. 4(a) at the equivalent BV
(221 V∼ 228 V). For DG LDMOS and PG LDMOS, the oxide for C-LDMOS due to the absence of the oxide trench. There-
trench folds the drift region, and thus, the cell pitch decreases fore, the half-cell pitch of C-LDMOS needs to be lengthened
but can still hold the high BV. The cell pitch of C-LDMOS is from 9.5 µm for DG LDMOS and PG LDMOS to 19 µm
increased in order to obtain the comparable BV. Owing to the in order to obtain the comparable BV. The smaller cell pitch
contribution of the dual-gate, DG LDMOS exhibits the largest helps to reduce Ron,sp . Furthermore, the BV of DG LDMOS
drain current in Fig. 4(a). The drain current of 16 mA/mm is nearly the same as that of PG LDMOS, although the trench
is obtained for DG LDMOS at Vds = 1 V and Vgs = 5 V, gate is placed in the oxide trench (the surface field strength in
which is larger than that of PG LDMOS (8.4 mA/mm) and the trench gate is zero). This can be explained by the fact that
also larger than that of C-LDMOS (10.7 mA/mm). Therefore, the electric field distribution in the oxide trench is modulated
the low Ron,sp of 5.9 mΩ·cm2 is obtained for DG LDMOS at by the trench gate. Especially under the trench gate as illus-
Vgs = 5 V, while that of PG LDMOS is 11.3 mΩ·cm2 . Note trated by Fig. 5(b), the field strength is much higher than that
that although the drain current of C-LDMOS is higher than of PG LDMOS.
048501-3
 Chin. Phys. B Vol. 22, No. 4 (2013) 048501
12 halfcell pitch=9.5 mm
DG LDMOS halfcell pitch=9.5 mm
15 DG LDMOS
8 BV=226 V BV=226 V
10
Electric field/105 VScm-1

Electric field/105 VScm-1

4 oxide
5
trench oxide
0 trench
0
12 halfcell pitch=9.5 mm PG LDMOS 15 halfcell pitch=9.5 mm PG LDMOS
8 BV=228 V oxide BV=228 V
10 trench
4 oxide 5
trench
0 0
12 halfcell pitch=19 mm 15 halfcell pitch=19 mm
CLDMOS
8 (a) 10 CLDMOS
BV=221 V
4 BV=221 V
5 (b)
0 0
0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18
x/mm x/mm

Fig. 5. Field distributions along (a) surface and (b) AA0 line in Fig. 1. The structure parameters are the same as those in Fig. 3.

D G S G D S G D G S
0 0 0

4 4 4

y/mm
y/mm
y/mm

8 8 8

12 12 12 (c)
(a) (b)

0 4 8 0 4 8 0 8 16
x/mm x/mm x/mm

Fig. 6. Equipotential contours at breakdown voltage for (a) DG LDMOS (226 V), (b) PG LDMOS (228 V), and (c) C-LDMOS
(221 V). The same structure parameters are used as those in Fig. 3. 10 V/contour.

Figure 6 shows the equipotential contours for DG LD- low (tT = 3 µm in Fig. 7), the average electric field is small
MOS, PG LDMOS, and C-LDMOS. Comparing Figs. 6(a)– in region II. However, the oxide trench cannot be too deep
6(c), the enhancement and modulation effects for the oxide (tT = 6 µm in Fig. 7), otherwise the average electric field of
trench and trench gate on the field distribution can be ob- region I will be lowered. As a result, the new field peak P2
served, respectively. It is clearly obtained from Figs. 6(a) and will lead to a uniform electric field distribution in the drift re-
6(b) that the voltage drop from the drain to the source in the gion. This indicates that the maximum of BV will be obtained
drift region is equal to that in the oxide trench, implying that at tT = 4 µm.
the drift region is folded by the oxide trench in the vertical di-
rection. The effective drift region length is thus increased by 6
Q tT=3 mm tT=4 mm
the oxide trench. So in order to achieve the equivalent BV, the tT=6 mm
Electric field/105 VScm-1

5
half-cell pitch of C-LDMOS increases from 9.5 µm for DG
II
LDMOS and PG LDMOS up to 19 µm. The values of Ron,sp 4 P1 P2 P3
are thus reduced for DG LDMOS and PG LDMOS. Compar-
Q′
ing Fig. 6(a) with Fig. 6(b), it can be seen that the BV is barely 3

affected by the trench gate.

2
Figure 7 illustrates the electric field distribution along AB I
line in Fig. 1 under breakdown condition. In the OFF-state, 1 n+ n- psub
the electric field peaks Q and Q0 are generated at the n+/n-
0 1 2 3 4 5 6 7
junction and the n-/p-sub junction, respectively. Owing to the y/mm
oxide trench, new electric field peaks P1 , P2 , and P3 are gen-
Fig. 7. Electric field distributions along AB line (x = 2 µm) in Fig. 1.
erated at B point in Fig. 1. The new field peak enhances the (wT = 3.5 µm, tS = 7 µm, half-cell pitch = 9.5 µm, Psub = 3.5 ×
electric field of the drift region. When the oxide trench is shal- 1015 cm−3 . Nd is optimized to obtain the maximum BV for each tT .)

048501-4
 Chin. Phys. B Vol. 22, No. 4 (2013) 048501
Psub= 3.5T1015 cm-3 12 The reduced Ron,sp results in a far higher figure-of-merit
wT=3.5 mm
220 10 (FOM) (FOM=BV2 /Ron,sp in this paper)[18] value for DG LD-
Breakdown voltage/V

BV

Ron,sp/mWScm2
Ron,sp 8 MOS. Figure 8 shows the influences of tT , wT , and Psub on
200 tT/mm
2 4 6 6 BV, Ron,sp , and FOM. Owing to the electric field distributions
9 8.7

FOM/MWScm-2
180
4
shown in Fig. 7, BV first increases from 171 V to 226 V with
7
tT increasing from 2.5 µm to 4 µm. After that, as shown in
5 2
160 (a)
3
Fig. 8(a), BV decreases to 201 V with tT further increasing.
0
2 3 4 5 6 Due to the narrow conduction path in the drift region under
tT/mm
240
the oxide trench, the Ron,sp of DG LDMOS increases from
Psub= 3.5T1015 cm-3
tT=4 mm 10 5.9 mΩ·cm2 to 11.8 mΩ·cm2 with tT increasing. In Fig. 8(b),
Breakdown voltage/V

BV
the increasing of wT results in an increased BV and Ron,sp .
200 8

Ron,sp/mWScm2
Moreover, the BV is saturated when wT > 3.5 µm because
wT/mm 6
1 3 5
8.7
it is limited by the vertical BV. The simulation results indi-
FOM/MWScm-2

160 8 4
Ron,sp cate that the vertical electric field distribution and the optimal
(b)
6 2 Nd are influenced by Psub . So as shown in Fig. 8(c), the BV
120 4
0 and Ron,sp are affected by Psub . As illustrated in the insets of
1 2 3 4 5 6
wT/mm Figs. 8(a)–8(c), the optimal FOM of 8.7 MW/cm2 is extracted
9 8.7
at tT = 4 µm, wT = 3.5 µm, and Psub = 3.5×1015 cm−3 .
260 wT=3.5 mm 11
FOM/MWScm-2

tT=4 mm Table 1 summarizes the optimal results for these struc-

Breakdown voltage/V

7 10
tures. The half-cell pitches of DG LDMOS and PG LDMOS
Ron,sp/mWScm2

240
5 9
0 2 4 6
are reduced by 50% at the equivalent BV compared with that
Psub/1015 cm-3 8
Ron,sp of C-LDMOS due to the oxide trench. Moreover, the optimal
220
7 Nd for C-LDMOS is approximately half of those for DG LD-
BV

200 (c) 6 MOS and PG LDMOS. The smaller half-cell pitch and higher
0 1 2 3 4 5 6 Nd both lead to that the Ron,sp of PG LDMOS is reduced by
Psub/1015 cm-3 37% compared with that of C-LDMOS. As for DG LDMOS,
Fig. 8. Dependences of BV, Ron,sp , and FOM on tT , wT , and Psub for DG the further reduced Ron,sp of 5.9 mΩ·cm2 is obtained due to
LDMOS. (a) tT (wT = 3.5 µm, Psub = 3.5×1015 cm−3 ), (b) wT (tT = 4 µm,
the dual-gate, while that of C-LDMOS is 17.8 mΩ·cm2 . As a
Psub = 3.5×1015 cm−3 ), and (c) Psub (tT = 4 µm, wT = 3.5 µm). (tS = 7 µm
and half-cell pitch = 9.5 µm for panels (a)–(c).) result, the FOM of DG LDMOS is the highest in Table 1.

Table 1. Optimal results for each device.

Device parameters DG LDMOS PG LDMOS C-LDMOS
Half-cell pitch/µm 9.5 9.5 19
Thickness of n-type silicon layer, tS /µm 7 7 7
Width of the oxide trench, wT /µm 3.5 3.5 –
Depth of the oxide trench, tT /µm 4 4 –
Doping concentration of n-type silicon layer, Nd /1015 cm−3 4.5 4.3 2.1
Doping concentration of p-type substrate, Psub /1015 cm−3 3.5 3.5 3.5
Breakdown voltage, BV/V 226 228 221
Specific on-resistance, Ron,sp /mΩ·cm2 5.9 11.3 17.8
Figure-of-merit, FOM/MW·cm−2 8.7 4.6 2.7

4. Conclusion shorten the cell pitch at the comparable BV. The dual con-
duction channel and the shortened cell pitch both result in a
A novel high voltage trench LDMOS with dual-gate
structure is proposed and investigated by simulation. The dual dramatically reduced Ron,sp . The half-cell pitch and Ron,sp are
gate provides dual conduction channel for reducing Ron,sp . The reduced by 50% and 67% for DG LDMOS, respectively, com-
oxide trench lengthens the effective drift region in order to pared with those for C-LDMOS at the equivalent BV.
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 Chin. Phys. B Vol. 22, No. 4 (2013) 048501
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