Title: Study of CMOS, NMOS, and PMOS

Objective: To calculate the value of VTH for NMOS and PMOS. Study the ID Vs. VDS characteristics of
NMOS and PMOS at different values of VGS.

1.) Breadboard snapshot

ID Vs. VGD characteristics for NMOS

As we can easily conclude that VTH = 1.6 V.

 3

2.5

1.5
ID

0.5

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
VDS

Calculations:

V = 1.6 V
TH

R2= 4.7 k 𝛀, R3 = 1 k 𝛀;

V = 12*R3/ (R2+R3);
GS

Current passing through the circuit is given by the equation I = 12 - V / R1;

D DS

ID vs. VDS characteristics of NMOS at different value of VGS

Breadboard snapshot:
VGS = 2.105 v

0.0003

0.00025

0.0002

0.00015
ID

0.0001

0.00005

0
0 2 4 6 8 10 12
VDS

VGS = 1.0909 v

0.000014

0.000012

0.00001

0.000008
ID

0.000006

0.000004

0.000002

0
0 2 4 6 8 10 12 14
VDS

VGS = 2.790 v
 0.001

0.0009

0.0008

0.0007

0.0006

0.0005
ID

0.0004

0.0003

0.0002

0.0001

0
0 1 2 3 4 5 6 7 8 9 10
VDS

Results:

(I) When VGS < VTH then voltages across the R1 becomes almost zero i.e. current flowing
through the circuit is almost zero. Therefore we can say that circuit behaves as an open
circuit.
(II) when VGS > VTH then initially as the value of VDS increases a value of ID increases sharply
then after some time it becomes constant current. therefore we can say that circuit is in the
saturation mode.

3.) ID vs. VSG characteristics for PMOS

Breadboard snapshot:
As we can easily conclude that VTH = 1.0 V

0.003

0.0025

0.002

0.0015
ID

0.001

0.0005

0
0 0.5 1 1.5 2 2.5 3 3.5 4
VSG

Calculations:

VSG = 12(R3/R2+R3);

R3 = 1k Ω

Current flowing out of the drain ID = (12 – VSD) / R1

R2= 560 Ω VSG = 7.69 V

 0.0035

0.003

0.0025

0.002

0.0015

0.001

0.0005

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4

R2= 1k Ω VSG = 6 V

0.0035

0.003

0.0025

0.002
ID

0.0015

0.001

0.0005

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VSD

R2 = 3.3k Ω VSG = 2.79 V

 0.001
0.0009
0.0008
0.0007
0.0006
0.0005
ID

0.0004
0.0003
0.0002
0.0001
0
0 1 2 3 4 5 6 7 8 9 10
VSD

R2 =4.7 k Ω VSG = 2.10 V

0.00035

0.0003

0.00025

0.0002
ID

0.00015

0.0001

0.00005

0
0 2 4 6 8 10 12
VSD

R2= 10 k Ω, VSG = 1.09 V

 1.4E-07

1.2E-07

0.0000001

8E-08
ID

6E-08

4E-08

2E-08

0
11.997 11.9975 11.998 11.9985 11.999 11.9995 12 12.0005
VSD

Results:

(I) When VSG < VTH the circuit behaves as an open circuit, the current flowing through the circuit
becomes almost zero. i.e. (VSD = 12 V and VR1 = 0 V )
(II) When VSG > VTH initially as the value of VSD increases current ID increases drastically then after
some time it almost become constant and therefore we can say that device gets into the
saturation region.

4.)

Objective: To study the characteristics of CMOS inverter at a different frequency by applying different
voltages to the gate and observing the output voltages at the drain.

Breadboard snapshot:
Input-output response at low frequency f = 10 k Hz

Input-output response at high frequency f = 1M Hz

Result: At the higher frequency, before charging completes CMOS starts to discharge and before
discharging completes again charging starts and none of the phenomena get completed that's why
output wave degraded to the sine wave due to exponential nature of charging and discharging of MOS
capacitor.