TON DUC THANG UNIVERSITY

FACULTY OF ELECTRICAL AND ELECTRONICS

ENGINEERING

402088
MOS VLSI DESIGN
Chapter 1: INTRODUCTION

Nguyen Huu Khanh Nhan, PhD.

 OBJECTIVES

 Understand and Experience VLSI Design Flow

 Learn Transistor-Level CMOS Logic Design
 Understand VLSI Fabrication and Experience
CMOS Physical Design
 Be aware about the trends in semiconductor
technology, and how it impacts scaling and
performance.
 Study High-Level Digital Functional Blocks
 Visualize CMOS Digital Chip Design

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 CONTENTS

1.1. A Brief History

1.2. MOS transistor

1.3. CMOS logic gates

1.4. CMOS design process

1.5. Layout design and fabrication

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 1.1.A BRIEF HISTORY

 1958: First integrated circuit

– Flip-flop using two transistors
– Built by Jack Kilby at Texas
Instruments
 2010 Courtesy Texas Instruments

– Intel Core i7 mprocessor

• 2.3 billion transistors
– 64 Gb Flash memory
• > 16 billion transistors
[Trinh09]
© 2009 IEEE

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 1.1. A BRIEF HISTORY

 53% compound annual growth rate over 50 years

– No other technology has grown so fast so long
 Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society

[Moore65]
Electronics Magazine

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 1.1. A BRIEF HISTORY

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 1.1. A BRIEF HISTORY

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 1.1. A BRIEF HISTORY

Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates

Pentium 4 Processor
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 1.2. nMOS TRANSISTOR

 Four terminals: gate, source, drain, body

 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor Source Gate Drain
Polysilicon
– Even though gate is SiO2
no longer made of metal*
n+ n+
Body
p bulk Si
* Metal gates are returning today!

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 1.2. nMOS TRANSISTOR

 Body is usually tied to ground (0 V)

 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

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 nMOS OPERATION CONT.

 When the gate is at a high voltage:

– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

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 pMOS TRANSISTOR

 Similar, but doping and voltages reversed

– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

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 POWER SUPPLY VOLTAGE

 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny
transistors
– Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

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 1.3. CMOS LOGIC GATES

 We can view MOS transistors as electrically

controlled switches
 Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

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 1.3. CMOS LOGIC GATES

 Complementary CMOS logic gates

– nMOS pull-down network pMOS

– pMOS pull-up network pull-up

network
inputs
– a.k.a. static CMOS output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

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 1.3.1. BASIC GATES

 CMOS Inverter
VDD
A Y
0 1 OFF
ON
0
1
1 0 A Y
ON
OFF

A Y
GND
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 1.3.1. BASIC GATES

 CMOS NAND Gate

A B Y
0 0 1 ON
OFF
OFF
ON OFF
ON
0 1 1
1
0 Y
1 0 1 ON
OFF
1 1 0 A
0
1
1
0 OFF
ON
ON
OFF
B

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 1.3.1. BASIC GATES

A B Y  CMOS NOR Gate

0 0 1
A
0 1 0
1 0 0 B
1 1 0
Y

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 1.3.2.COMPOUND GATES

 Compound gates can do any inverting function

 Ex: Y  A B  C D (AND-AND-OR-INVERT, AOI22)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)

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 EXAMPLE: O3AI

 Y   A B  C D

A
B
C D
Y
D
A B C

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 1.3.3.TRANSMISSION GATES
 Transistors can be used as switches

g=0 Input g = 1 Output

g
s d 0 strong 0
s d g=1 g=1
s d 1 degraded 1

g=0 Input Output

g=0
g s d 0 degraded 0

s d g=1
g=0
s d 1 strong 1

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 1.3.3.TRANSMISSION GATES

 Pass transistors produce degraded outputs

 Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

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 TRISTATES

 Tristate buffer produces Z when not enabled

EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y

EN

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 TRISTATE INVERTER

 Tristate inverter produces restored output

– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

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 MULTIPLEXERS

 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1

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 TRANSMISSION GATE MUX

 Nonrestoring mux uses two transmission gates

– Only 4 transistors
S

D0
S Y
D1

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 D LATCH

 When CLK = 1, latch is transparent

– D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
– Q holds its old value independent of D
 a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q

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 D LATCH DESIGN

 Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

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 D LATCH OPERATION

Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

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 D FLIP-FLOP

 When CLK rises, D is copied to Q

 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop

CLK
CLK
D
Flop

D Q
Q

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 D FLIP-FLOP DESIGN

 Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

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 D FLIP-FLOP OPERATION
QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

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 1.4. CMOS DESIGN PROCESS

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 1.4. CMOS DESIGN PROCESS

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 1.5. LAYOUT DESIGN AND
FABRICATION
 CMOS transistors are fabricated on silicon
wafer
 Lithography process similar to printing press
 On each step, different materials are
deposited or etched
 Easiest to understand by viewing both top
and cross-section of wafer in a simplified
manufacturing process

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 INVERTER CROSS-SECTION

 Typically use p-type substrate for nMOS transistors

 Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

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 WELL AND SUBSTRATE TAPS

 Substrate must be tied to GND and n-well to VDD

 Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
 Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

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 INVERTER MASK SET

 Transistors and wires are defined by masks

 Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

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 DETAILED MASK VIEWS

 Six masks n well

– n-well
– Polysilicon
Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

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 1.5.1. DESIGN RULES

 Chips are specified with set of masks

 Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
 Feature size f = distance between source and drain
– Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design
rules
 Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process

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 1.5.1. DESIGN RULES

 Conservative rules to get you started

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 WIRING TRACKS

 A wiring track is the space required for a wire

– 4 l width, 4 l spacing from neighbor = 8 l pitch
 Transistors also consume one wiring track

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 WELL SPACING

 Wells must surround transistors by 6 l

– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track

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 INVERTER LAYOUT

 Transistor dimensions specified as Width / Length

– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm
long

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 1.5.2.STICK DIAGRAMS

 Layout can be very time consuming

– Design gates to fit together nicely
– Build a library of standard cells
 Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

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 1.5.2.STICK DIAGRAMS

 Stick diagrams help plan layout quickly

– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3

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 AREA ESTIMATION

 Estimate area by counting wiring tracks

– Multiply by 8 to express in l

40 l

32 l

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 EXAMPLE: O3AI

 Sketch a stick diagram for O3AI and estimate area

– Y   A B  C D

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 SUMMARY

 MOS transistors are stacks of gate, oxide,

silicon
 Act as electrically controlled switches
 Build logic gates out of switches
 Draw masks to specify layout of transistors
 Now you know everything necessary to start
designing schematics and layout for a simple
chip!

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 HOMEWORKS

 Reading: [1]: 7-22

 Solving Problems: [1] 63-65

 Referring to: [2]: 13-52; [3]: 31-34

[4]: 5.1-5.25; [5]: 534-556

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 CONTACT TO ELEARNING

51 CMOS
Chapter
VLSI Design 4th Ed.
1: Introduction 9/2/2016