PCIe Layered Architecture

Features of PCIe Physical Layer (Logical Sub-block)

• Encoding for 2.5 GT/s and 5 GT/s (Gen1 and Gen 2) (Sec 4.2.1)
➢ 8b/10b decoding
➢ Symbol encoding
➢ Serialization and De-serialization of data
➢ Special symbols for framing and link management
➢ 8b/10b decoding (Error detection)
➢ Framing and application of symbols to lanes (Single Lane and Multiple
Lanes)
➢ Data scrambling
• Encoding for 8GT/s and 16GT/s (Gen3 and Gen4)
➢ Lane level encoding
➢ Ordered set blocks
o Block alignment
➢ Data blocks
o Framing tokens
o Transmitter framing requirement (For single and multiple
lanes)
o Receiver framing requirement (For single and multiple lanes)
o Recovery from framing error
• Link Training and Status State Machine
• Clock recovery mechanism at the receiver
• Clock tolerance and compensation at the receiver
• Compliance pattern in 8b/10b encoding
 • Modified compliance pattern in 8b/10b encoding
• Compliance pattern in 128/130b encoding
• Modified Compliance pattern in 128/130b encoding
• M-phy logical sub block

What is PIPE?
• PIPE means Physical Interface for PCIe, SATA, USB PHY’s
• A standard interface between a PHY layer and a MAC and Data Link
Layer ASIC proposed by INTEL.

Why PIPE?
• Details about the interaction between MAC and Physical Layer were not
given in the PCIe base specification.
• PIPE specification provides the information about the interaction
between MAC and PHY layer for various LTSSM states, link states, other
states through PIPE interface.

Partitioning diagram for PHY layer

 Diagram showing MAC/PHY interface

Diagram showing MAC,PCS,PMA layers

What is LTSSM ?
• Link Training Status State Machine is a hardware-based (not software)
process controlled by the physical layer.
• This process configures and processes and initializes a device’s link and
port so that normal packet proceeds on the link
 Diagram showing LTSSM
• Each state internally has its own sub state machine.(Refer PCIe Base
specification)

Block Diagram Showing Synopsis PCIe VIP

Features of Physical Layer supported inside Smart DV PCIe VIP

• Supports PCIe(Gen1,2,3,4 spec)
• Supports mPCIe
 • Supports PIPE,Serial,PCS/PMA and serdes interface
• Supports full link speed and link width negotiation up to 32 lanes
• Automated error injections
• Supports full LTSSM
• Supports SERDES model with digital clock recovery
• Supports upconfigure,polarity inversion and lane to lane deskew
• Gen 1 and 2 PCS ,8b/10b encoding
• Gen 3 and 4 PCS ,128b/130b encoding

Features Implemented in our VIP

• Encoding for 2.5 GT/s (Gen1 single lane)
➢ 8/10 encoding
➢ Serialization and De-serialization of data
➢ 8b/10b decoding
➢ Special symbols for framing and link management
➢ Framing and application of symbols to lanes (Single Lane)
• Encoding for 8GT/s (Gen3)
➢ Lane level encoding
➢ Ordered set blocks
o Block alignment
➢ Data blocks
o Framing tokens
o Transmitter framing requirement (For single lane)
o Receiver framing requirement (For single lane)

Pending Features
• 2.5 GT/s and 5 GT/s (Gen1 and Gen 2)
➢ Serialization and De-serialization of data(For 5GT/s )
➢ Special symbols for framing and link management
➢ 8b/10b decoding (Error detection)
➢ Framing and application of symbols to lanes (For Gen1 Multi lane and
For Gen 2 Single Lane and Multi lane)
➢ Data scrambling (Gen 1nad Gen2 to be implemented inside MAC)
• Encoding for 8GT/s and 16GT/s (Gen3 and Gen4)
➢ Lane level encoding
➢ Ordered set blocks
o Block alignment
 ➢ Data blocks
o Framing tokens
o Transmitter framing requirement (For multi lane)
o Receiver framing requirement (For multi lane)
o Recovery from framing error
• Link Training and Status State Machine
• Clock tolerance and compensation
• Compliance pattern in 8b/10b encoding
• Modified compliance pattern in 8b/10b encoding
• Compliance pattern in 128/130b encoding
• Modified Compliance pattern in 128/130b encoding
• MAC implementation using PIPE interface
• M-phy logical sub block

Dependencies on MAC Implementation through PIPE Interface

• LTSSM implementation inside MAC
• Clock recovery at the receiver expects TS1 and TS2 ordered sets in
the polling state of LTSSM inside the MAC
• Inorder to do clock tolerance and compensation at the receiver we
need an elastic buffer whose Writing clock frequency of the elastic
buffer need to be obtained through the recovered clock
• Higher operating speeds (5GT/s,8 GT/s,16 GT/s) or speed change can
be obtained through LTSSM inside the MAC
• Configuring the link for multiple lanes, power management, testing,
initial training of the link can be done only through LTSSM inside the
MAC.
• Scrambling/Descrambling the data to avoid EMI noise should be done
inside the MAC.
• Lane-to-lane De-skew for multi-lane can be done inside MAC.