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4.75 to 35 V
29876DS
DABIC-5 8-Channel Source Driver
UDN2987x-6 with Overcurrent Protection
Selection Guide
Part Number Pb-free* Packing Package
UDN2987A-6-T Yes 18 pieces/tube 20-pin DIP
UDN2987LW-6-T Yes 37 pieces/tube
20-pin SOIC, wide body
UDN2987LWTR-6-T Yes 1000 pieces/13-in. reel
*Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production
but have been determined to be LAST TIME BUY. This classification indicates that sale of this device is cur-
rently restricted to existing customer applications. The variants should not be purchased for new design applica-
tions because obsolescence in the near future is probable. Samples are no longer available. Status change:
October 31, 2006. Deadline for receipt fo LAST TIME BUY orders: April 27, 2007. These variants include:
UDN2987A-6, UDN2987LW-6, and UDN2987LWTR-6.
VS
Thermal
Shut Down
OE/R¯ FAULT
+
–
R S
Q
IN1
OUT1
Driver 1 of 8 drivers
IN8 OUT8
GND
Pin-Out Diagram
Terminal List Table
Number Name Description
IN1 1 20 OUT1 1 IN1 Logic input 1
2 IN2 Logic input 2
2 19 OUT2
IN2
3 IN3 Logic input 3
IN3 3 18 OUT3 4 IN4 Logic input 4
5 IN5 Logic input 5
4 17 OUT4
IN4
6 IN6 Logic input 6
IN5 5 16 OUT5 7 IN7 Logic input 7
8 IN8 Logic input 8
IN6 6 15 OUT6
9 FAULT Fault output
IN7 7 14 OUT7 10 OE/ R̄¯ Logic input for Output Enable and Reset
11 VS Supply voltage
IN8 8 13 OUT8
12 GND Supply ground
x8
FAULT 9
OE
OEN
12 GND 13 OUT8 Output 8 to load
10 FF SENSE N
14 OUT7 Output 7 to load
OE/R 11 VS
15 OUT6 Output 6 to load
Dwg. PP-067
16 OUT5 Output 5 to load
17 OUT4 Output 4 to load
Package A (DIP) shown. Package LW 18 OUT3 Output 3 to load
(SOIC-W) is electrically identical and has 19 OUT2 Output 2 to load
the same terminal number assignment. 20 OUT1 Output 1 to load
THERMAL CHARACTERISTICS
Characteristics Symbol Test Conditions Rating Unit
Package A, on 4-layer board based on JEDEC standard 32 °C/W
Package Thermal Resistance* RθJA
Package LW, on 4-layer board based on JEDEC standard 48 °C/W
*Additional thermal information is available on the Allegro Web site.
3.5
3.0
P a QJA
(R
ck =
ag 32
2.5
e ºC
A
Pa
PD (W)
(R cka
g
= e LW
/
QJ
W
2.0 A
)
48
ºC
/W
)
1.5
1.0
0.5
0
25 50 75 100 125 150
TA (°C)
Characteristic Performance
VIN(A) = VIN(B)
tPLH tPHL
— tRTB
OE/R
Output (A) shorted
ISH
IOUT(A)
tBLANK
IM
IOUT(B)
Momentary fault or capacitive charging (<1μs)
400 400
Quantity of outputs conducting simultaneously Quantity of outputs conducting simultaneously
8 7 6 5 4 3 8 7 6 5 4 3 2
350 350
Collector Current (mA)
300 300
250 250
200 200
150 150
100 100
50 50
0 0
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Duty Cycle (%) Duty Cycle (%)
As with all power integrated circuits, the UDN2987A-6 and pared to the voltage drop across a reference resistor with
UDN2987LW-6 have a maximum allowable output current a constant current. The two resistors are matched to elimi-
rating. The 500 mA rating does not imply that operation at nate errors due to manufacturing tolerances or tempera-
that value is permitted or even obtainable. The channel out- ture effects. Each channel includes a comparator and its
put current trip point is specified as –370 mA, minimum; own latch. An overcurrent fault (VSENSE > VREF) will set
therefore, attempted operation at current levels greater the affected latch and shut down only that channel. All
than –370 mA may cause a fault indication and channel other channels will continue to operate normally. The
shut down. The device is tested at a maximum of –350 mA latch includes a 1 μs blanking delay, t BLANK, to prevent
and that is the recommended maximum output current unwanted triggering due to crossover currents generated
per driver. It provides protection for current overloads or when switching inductive loads. For an abrupt short circuit,
shorted loads up to 30 V. the blanking and output switching times will allow a brief,
¯ input high. permissable current in excess of the trip current before the
All outputs are enabled by pulling the OE/R
¯ is low or allowed to float (internal pull-down), output driver is turned off.
When OE/R
all outputs are inhibited and the latches are reset. Note that A common thermal shut down disables all outputs if the
the reset pulse duration (OE/R¯ low) should be at least 1 μs. chip temperature exceeds 165°C. At thermal shut down,
This will ensure safe operation under attempted reset condi- all latches are reset. The outputs are disabled until the chip
tions with a shorted load. The latches are also reset during cools down to approximately 150°C (thermal hysteresis).
power-up, regardless of the state of the OE/R ¯ input.
In the event of an overcurrent condition on any channel, or
The load current causes a small voltage drop across the chip thermal shut down, the FAULT open-collector output
internal low-value sense resistor. This voltage is com- is pulled low (turned on).
+ +
Matched
VREF VSENSE
– –
To Fault Latch – SENSE
+
REF
ILOAD
IREF
1.060 26.92
A .014 0.36
0.980 24.89
B .008 0.20
20
.430 10.92
.280 7.11 .300 .7.62
Preliminary dimensions, for reference only MAX
.240 6.10
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only A
(reference JEDEC MS-001 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions 1 2
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
.195 4.95 C
.115 2.92 SEATING
PLANE
.015 2.92
MIN
.005 0.13
MIN .100 .2.54 .150 3.81
.115 2.92
.070 1.78
.045 1.14
.022 .056
24X
.014 .036
.010 [0.25] M C
1 2
0.25 .010
0.51 .020
20X 2.65 .104
0.31 .012
2.35 .093
0.25 [.010] M C A B
1.27 .050 0.30 .012
0.10 .004
The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889;
5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright©2006, Allegro MicroSystems, Inc.